Frame header synchronization method based on CPM constant envelope spread spectrum sequence

Abstract

The invention provides a frame header synchronization method based on a CPM constant envelope spread spectrum sequence, and belongs to the technical field of satellite-borne satellite communication. A traditional recursive feedback type structure based on a phase-locked loop (PLL) is optimized, and a matched filter, a resampling module and a delay locked tracking loop (DLL) module are added after frame header pulse detection and frequency offset estimation are completed by utilizing the differential self-correlation characteristic of a synchronous sequence. The single symbol rate timing error estimation result serves as negative feedback and is fed back to the matched filter for resampling operation, the optimal resampling point is continuously adjusted, the symbol synchronization establishment time is greatly shortened, and then frame header synchronization of LINK20 received signals is achieved. The method has the advantages of being easy to implement, low in complexity and high in real-time performance and synchronization precision.

Description

Technical Field

[0001] The present invention relates to the field of onboard satellite communication technology, and in particular to a frame header synchronization method based on a CPM constant envelope spread spectrum sequence. Background Art

[0002] From the perspective of the development of global maritime communications, the E-Navigation strategy promoted by the International Maritime Organization (IMO) will drive the upgrading of global maritime communication systems, and also bring a golden opportunity to the development of my country's maritime communication technology. VDES (VHF Data Exchange System) is the core content of the E-Navigation strategy. The VDES satellite payload is a key link in building a new generation of integrated "sky-sea-shore" communication network. Countries around the world attach great importance to the research of VDES satellite payloads and have carried out a large number of technical research and tests. my country will also build its own VDES satellite network in the future construction of low-orbit satellite constellations to occupy the commanding heights of the construction and application of the third-generation maritime communication network, and provide strong support for my country to achieve technological breakthroughs and industrial upgrades in the field of maritime communications.

[0003] The ITU RM.2092-1 standard defines the satellite uplink data confirmation signaling channel (DSCH) and uplink random access channel (RAC) for resource requests, paging responses and short messages. The physical layer frame format of Link_ID 20 must be used for data communication. The physical layer frame format of Link_ID 20 uses a CPM constant envelope spread spectrum waveform to spread the QPSK modulated signal 16 times, so that the data remains phase-continuous during the transition from one symbol to the next. This improves the power utilization of the system without sacrificing the bandwidth utilization.

[0004] The traditional frame header synchronization method uses a recursive feedback structure based on a phase-locked loop (PLL). This structure of the PLL not only takes a long time to capture but is also difficult to debug. For CPM constant envelope spread spectrum modulation sequences, due to different signal characteristics, the Gardner algorithm cannot be used. Symbol synchronization is completed by relying on the sampling error of the symbol transition zero point. The LS channel estimation algorithm is usually used, and the pilot is used for channel estimation. Channel equalization is used to eliminate or weaken the inter-symbol interference caused by transmission delay and Doppler frequency deviation. This method has a large amount of calculation, takes a long time to synchronize the frame header, and is easily affected by noise and interference. Summary of the invention

[0005] According to the technical problems mentioned in the above background technology, a frame header synchronization method based on CPM constant envelope spread spectrum sequence is provided. The present invention mainly utilizes the differential autocorrelation characteristics of the synchronization sequence, and considers that the receiver can still have good demodulation performance when the signal-to-noise ratio is low, and uses a closed-loop feedback method to achieve frame header synchronization.

[0006] The technical means adopted by the present invention are as follows:

[0007] A frame header synchronization method based on a CPM constant envelope spread spectrum sequence comprises the following steps:

[0008] Step 1: Obtain a received signal from a receiver, and perform analog-to-digital conversion on the received signal to obtain an analog-to-digital sampling signal;

[0009] Step 2: performing a down-conversion operation on the analog-to-digital sampling signal, removing the carrier frequency, and obtaining a co-directional output signal and an orthogonal output signal;

[0010] Step 3: Perform CIC extraction filtering on the co-directional output signal and the quadrature output signal, and reduce the data rate after sampling to 4 times the spread spectrum code rate for output, so as to ensure the real-time requirements of the subsequent frame header synchronization algorithm;

[0011] Step 4: Cache the signal output by CIC extraction and filtering, and output it after the delay channel is completed after the frame header pulse detection and frequency offset estimation are completed;

[0012] Step 5: Perform differential detection design, local sequence conjugate correlation design and peak detection on the direct signal output by the CIC extraction filter, and output the captured pulse;

[0013] Step 6: Perform matched filtering on the delayed signal output by the CIC extraction filter, and resample the matched filtered signal from 4 times the chip rate to 2 times the chip rate;

[0014] Step 7: The output signal is symbol synchronized through a delay lock tracking loop DLL, and the early code, the middle code and the late code are despread respectively to extract the timing error signal;

[0015] Step 8: The timing error signal is used as negative feedback and input into a matched filter for resampling operation, and the optimal resampling point is adjusted to achieve frame header synchronization of the LINK_20 received signal.

[0016] Furthermore, the differential detection is designed as follows: the direct signal output by the CIC extraction filter is used as input, the data rate is 4 times the spread spectrum code rate, that is, there are 4 sampling points in one code chip time, and the delay Ts needs to delay the sampled data by 4 sampling points; after the delay of 4 sampling points, the delayed signal and the received data are conjugate multiplied, and the differential operation result after the conjugate multiplication is output.

[0017] Furthermore, the local sequence conjugate correlation is designed as follows: the synchronization sequence is 48 symbols, and the sequence after modulation, CPM constant envelope spread spectrum and differential operation is used as the local differential synchronization sequence, and conjugate correlation is performed with the differential operation result of the CIC extraction filter output direct signal; since the synchronization sequence has excellent autocorrelation characteristics after the differential operation, a maximum correlation peak will appear at the completely overlapping position, and the position of the correlation peak is the position of the last symbol of the received signal synchronization header sequence, and the phase of the correlation peak is the frequency deviation.

[0018] Furthermore, the step 7 comprises the following steps:

[0019] Firstly, the double chip rate data output by the matched filter is used to generate early, middle and late codes in a format with a difference of half a chip period;

[0020] Secondly, the early, middle and late codes are conjugate-correlated with the spreading sequence of twice the chip rate to complete despreading;

[0021] Finally, the timing error of the single symbol rate is calculated through envelope detection and loop filter, and the single symbol rate data after medium code despreading and integration is demodulated.

[0022] Furthermore, the peak detection is performed by finding the angle of the maximum correlation peak to obtain the phase of the correlation peak, and using the CORDIC algorithm to calculate the angle of the correlation value corresponding to the frame header to obtain a coarse frequency offset estimation value.

[0023] Furthermore, the calculation formula of the coarse frequency offset estimation value is:

[0024]

[0025] Then the phase control word M is calculated by the formula;

[0026] M=f*2 32 / f sys ;

[0027] Among them, phase represents the phase difference, Rs represents the symbol rate, and fsys represents the sampling rate.

[0028] DDS generates sine and cosine waves with a frequency equal to the rough frequency deviation estimate, and then multiplies the complex number composed of the received IQ complex signal and the sine and cosine to compensate for the rough frequency deviation mixed in the signal.

[0029] Compared with the prior art, the present invention has the following advantages:

[0030] The present invention provides a frame header synchronization method based on a CPM constant envelope spread spectrum sequence, which combines a matching filter, resampling and a delay lock tracking loop DLL, optimizes the traditional recursive feedback structure based on a phase-locked loop (PLL), and uses the differential autocorrelation characteristics of the synchronization sequence. After the frame header pulse detection and frequency offset estimation are completed, a matching filter, a resampling module and a delay lock tracking loop DLL module are added. The single symbol rate timing error estimation result is used as negative feedback and fed back to the matching filter for resampling operation, and the optimal resampling point is continuously adjusted, which greatly shortens the symbol synchronization establishment time, thereby realizing the frame header synchronization of the LINK_20 received signal. The improved loop structure can effectively reduce the timing jitter error caused by the system self-noise during the synchronization process. BRIEF DESCRIPTION OF THE DRAWINGS

[0031] In order to more clearly illustrate the embodiments of the present invention or the technical solutions in the prior art, the drawings required for use in the embodiments or the description of the prior art will be briefly introduced below. Obviously, the drawings described below are some embodiments of the present invention. For ordinary technicians in this field, other drawings can be obtained based on these drawings without paying creative labor.

[0032] Figure 1 It is a schematic diagram of the overall process of the present invention.

[0033] Figure 2 The principle block diagram of the present invention is shown in FIG. Figure 1 ; (b) is the principle frame Figure 2 . DETAILED DESCRIPTION

[0034] In order to enable those skilled in the art to better understand the scheme of the present invention, the technical scheme in the embodiments of the present invention will be clearly and completely described below in conjunction with the drawings in the embodiments of the present invention. Obviously, the described embodiments are only part of the embodiments of the present invention, not all of the embodiments. Based on the embodiments of the present invention, all other embodiments obtained by ordinary technicians in this field without creative work should fall within the scope of protection of the present invention.

[0035] It should be noted that the terms "first", "second", etc. in the specification and claims of the present invention and the above-mentioned drawings are used to distinguish similar objects, and are not necessarily used to describe a specific order or sequence. It should be understood that the data used in this way can be interchanged where appropriate, so that the embodiments of the present invention described herein can be implemented in an order other than those illustrated or described herein. In addition, the terms "including" and "having" and any variations thereof are intended to cover non-exclusive inclusions, for example, a process, method, system, product or device that includes a series of steps or units is not necessarily limited to those steps or units that are clearly listed, but may include other steps or units that are not clearly listed or inherent to these processes, methods, products or devices.

[0036] like Figure 1-2 As shown, the present invention provides a frame header synchronization method based on a CPM constant envelope spread spectrum sequence, comprising the following steps:

[0037] Step 1: Obtain a received signal from a receiver, and perform analog-to-digital conversion (A / D) on the received signal to obtain an analog-to-digital sampling signal;

[0038] Step 2: Down-convert the analog-to-digital sampling signal, and the carrier NCO uses the Link_ID 20 channel frequency as the frequency control word to generate a local orthogonal carrier, which is multiplied with the (A / D) sampling signal, and the carrier frequency is removed to obtain a co-directional output signal and an orthogonal output signal;

[0039] Step 3: Since the data rate obtained by AD sampling is too high, resulting in insufficient subsequent signal processing speed, it is necessary to reduce the data speed after AD sampling to meet the real-time requirements of the frame header synchronization algorithm. CIC extraction and filtering are performed on the co-directional output signal and the orthogonal output signal, and the data rate after sampling is reduced to 4 times the spread spectrum code rate for output (i.e., 134.4kHz) to ensure the real-time requirements of the subsequent frame header synchronization algorithm;

[0040] Step 4: The signal output by the CIC extraction filter is cached under the input clock drive. The delay channel is output after the frame header pulse detection and frequency offset estimation are completed. The calculation formula for the cache data length (dly_len) is as follows:

[0041] dly_len=sync_word_length*chip_rate*4+14;

[0042] Among them, sync_word_length is the synchronization word length, chip_rate is the spreading factor;

[0043] Step 5: Perform differential detection design, local sequence conjugate correlation design and peak detection on the direct signal output by CIC extraction and filtering, and output the captured pulse; first, complete the differential operation of the direct channel signal by delaying it by four points, then convolve the differential signal with the local differential synchronization sequence, and finally complete the peak detection by modulo-calculating the IQ two-way data after conjugate correlation. The specific implementation is as follows:

[0044] Assume that the signal model can be expressed as:

[0045] r(k)=s(k)e j(2πfdkTs+φ) ;

[0046] Among them, r(k) represents the received signal of the receiver, s(k) represents the sent signal of the transmitter, fd and φ represent the carrier frequency deviation and carrier initial phase introduced by the communication channel respectively, and Ts represents the sampling period.

[0047] Assume that the original modulation sequence corresponding to the known synchronization sequence (i.e., the local synchronization sequence) is c(k), k = 1, 2, ..., L0 (L0 is the length of the synchronization sequence), and multiply the local synchronization sequence c(k) by c*(k-1) (* indicates conjugation) which is delayed by one symbol period Tb to obtain the difference value c(k)c*(k-1) of the local synchronization sequence. Perform differential processing on the received signal r(k) to obtain the difference value of the received signal:

[0048]

[0049] It can be seen from the formula that after the received signal is differentially processed, the initial phase φ of the carrier introduced by the communication channel is offset and the carrier frequency deviation is converted to a fixed phase.

[0050] After differential detection, the 4-times oversampled local differential synchronization sequence replica generated by the synchronization sequence is conjugate correlated with the differential operation result. The correlation value of differential detection is obtained:

[0051]

[0052] If there is a frame header, the sequence will have a peak that is significantly higher than other places.

[0053] The angle of the maximum correlation peak is calculated to obtain the phase of the correlation peak, and the angle of the correlation value corresponding to the frame header is calculated using the CORDIC algorithm. According to the formula, the rough frequency offset estimation value can be obtained. The specific RTL implementation is as follows:

[0054] The CORDIC algorithm is implemented in the RTL code using the CORDIC IP core, which is configured to output normalized phase. After the IQ value of the correlation peak is input, the phase value divided by 2π can be obtained.

[0055] Step 6: Perform matched filtering on the delayed signal output by the CIC extraction filter, and resample the matched filtered signal from 4 times the chip rate to 2 times the chip rate; perform coarse frequency offset compensation on the delayed signal output by the CIC extraction filter, and use DDS to generate two orthogonal waveforms to compensate the data for frequency offset. DDS requires the input of a phase control word, which has a 32-bit phase control word bit number and is calculated from the received phase value. The frequency offset estimate is obtained by the formula

[0056]

[0057] The phase control word M is then calculated using the formula.

[0058] M=f*2 32 / f sys ;

[0059] Among them, phase represents the phase difference, Rs represents the symbol rate, and fsys represents the sampling rate;

[0060] DDS generates sine and cosine waves with a frequency equal to the rough frequency deviation estimation value, and then multiplies the complex number composed of sine and cosine by the received IQ complex signal to compensate for the rough frequency deviation mixed in the signal;

[0061] Since the pulse shaping filter of the transmitter of Link_ID 20 physical layer frame format adopts a root raised cosine filter with a roll-off factor of 0.25, the receiver should also use the same root raised cosine filter to match filter the delayed signal after coarse frequency offset compensation. This can not only make the signal-to-noise ratio at the sampling time the highest (that is, complete the role of the matched filter), but also prevent the introduction of inter-symbol interference in a certain band-limited flat channel (satisfy the Nyquist no inter-symbol interference criterion). The design length of the matched filter is 8 symbols, and each symbol is oversampled 128 times, that is, the total coefficient length is 1024;

[0062] The timing error is used as feedback (single symbol rate) and then superimposed with the reference frequency word and sent to the NCO accumulator as the frequency control word. The accumulator overflow pulse is used as the resampling clock.

[0063] Under the control of the resampling clock, 32 data of the input signal in the current circular buffer are read continuously; the 32 input signal data and the filter coefficients are multiplied and accumulated in series, and the final accumulation result is the matched filter output result; the double chip rate data output by the matched filter is delayed by 3 times the half chip period, so as to extract the early, middle and late codes;

[0064] Step 7: The above output signal is synchronized with the delay lock tracking loop DLL, and the early code, medium code and late code are despread respectively to extract the timing error signal; the early, medium and late codes are conjugate correlated with the local pseudo code of twice the chip rate (i.e., CPA and CPE local spread spectrum sequences) to complete the despreading, and then the timing error of the single symbol rate is calculated through envelope detection and loop filter, and the single symbol rate data after the despreading and integration of the medium code is sent for demodulation processing. The specific implementation is as follows:

[0065] Since the phase error between the local pseudo code generated by the receiver (ie, the CPA and CPE local spread spectrum sequences) and the received pseudo code is less than one chip, the receiver should switch to the tracking state to perform precise phase tracking.

[0066] First, the local pseudo code generated by the receiver (i.e., the CPA and CPE local spreading sequences) is correlated with the early, middle, and late codes of the received signal. The pseudo code sent to the early correlator is p(t+Tc / 2), the pseudo code sent to the late correlator is p(t-Tc / 2), the pseudo code sent to the middle correlator is p(t), and the received signal sent to the two correlators is

[0067] s(t)=Ag(t)F(t-τ)cos(ω c t-θ);

[0068] Where A represents the amplitude of the received signal; g(t) = ±1, represents the baseband digital signal; p(t-τ) represents the local pseudo code; ω c represents the residual frequency deviation; θ represents the carrier phase.

[0069] Secondly, the received signal is multiplied by two local pseudo codes (i.e., CPA and CPE local spread spectrum sequences) and then processed by envelope detection. Considering that envelope detection is equivalent to taking the absolute value of the signal amplitude, and the role of the low-pass filter in the envelope detector is similar to finding the average value, the output of the envelope detector is the absolute value of the autocorrelation function of the pseudo code, so the detector input is

[0070] E{|Ag(t)p(t-τ)·p(t=T c / 1)|};

[0071] Wherein, E{·} indicates finding the average value.

[0072] Ignoring the constant factor A and considering that |g(t)| = ⊥, the above formula is the absolute value of the correlation function between the received pseudocode and the local pseudocode:

[0073] Delayed related branches:

[0074] |R(τ-T c / 2)|=E{|p(t-τ)·p(tTc / 2)|};

[0075] Early related branches:

[0076] |R(τ-T c / 2)|=E{|p(t-τ)·p(tT c / 2)|};

[0077] Finally, the absolute value of the autocorrelation function of the late code and the early code is subtracted by the adder, and the obtained timing error is fed back to the matched filter through loop filtering, so as to adjust the optimal sampling point and achieve frame header synchronization. The purpose of the loop filter is to eliminate the timing error jitter caused by noise interference on the received signal and filter out the high-frequency component of the timing error, significantly shortening the locking time, thereby improving the timing error detection accuracy.

[0078] Step 8: The timing error signal is used as negative feedback and input into a matched filter for resampling operation, and the optimal resampling point is adjusted to achieve frame header synchronization of the LINK_20 received signal.

[0079] The serial numbers of the above embodiments of the present invention are only for description and do not represent the advantages or disadvantages of the embodiments.

[0080] In the above embodiments of the present invention, the description of each embodiment has its own emphasis. For parts that are not described in detail in a certain embodiment, reference can be made to the relevant descriptions of other embodiments.

[0081] In the several embodiments provided in this application, it should be understood that the disclosed technical content can be implemented in other ways. Among them, the device embodiments described above are only schematic. For example, the division of the units can be a logical function division. There may be other division methods in actual implementation. For example, multiple units or components can be combined or integrated into another system, or some features can be ignored or not executed. Another point is that the mutual coupling or direct coupling or communication connection shown or discussed can be through some interfaces, indirect coupling or communication connection of units or modules, which can be electrical or other forms.

[0082] The units described as separate components may or may not be physically separated, and the components shown as units may or may not be physical units, that is, they may be located in one place or distributed on multiple units. Some or all of the units may be selected according to actual needs to achieve the purpose of the present embodiment.

[0083] In addition, each functional unit in each embodiment of the present invention may be integrated into one processing unit, or each unit may exist physically separately, or two or more units may be integrated into one unit. The above-mentioned integrated unit may be implemented in the form of hardware or in the form of software functional units.

[0084] If the integrated unit is implemented in the form of a software functional unit and sold or used as an independent product, it can be stored in a computer-readable storage medium. Based on this understanding, the technical solution of the present invention, in essence, or the part that contributes to the prior art, or all or part of the technical solution can be embodied in the form of a software product, and the computer software product is stored in a storage medium, including a number of instructions for a computer device (which can be a personal computer, a server or a network device, etc.) to perform all or part of the steps of the method described in each embodiment of the present invention. The aforementioned storage medium includes: U disk, read-only memory (ROM, Read-Only Memory), random access memory (RAM, Random Access Memory), mobile hard disk, magnetic disk or optical disk and other media that can store program codes.

[0085] Finally, it should be noted that the above embodiments are only used to illustrate the technical solutions of the present invention, rather than to limit it. Although the present invention has been described in detail with reference to the aforementioned embodiments, those skilled in the art should understand that they can still modify the technical solutions described in the aforementioned embodiments, or replace some or all of the technical features therein with equivalents. However, these modifications or replacements do not cause the essence of the corresponding technical solutions to deviate from the scope of the technical solutions of the embodiments of the present invention.

Claims

1. A frame header synchronization method based on CPM constant envelope spread spectrum sequence, characterized in that: The following steps are involved: Step 1: Obtain a received signal from a receiver, and perform analog-to-digital conversion on the received signal to obtain an analog-to-digital sampling signal; Step 2: performing a down-conversion operation on the analog-to-digital sampling signal, removing the carrier frequency, and obtaining a co-directional output signal and an orthogonal output signal; Step 3: Perform CIC extraction filtering on the co-directional output signal and the quadrature output signal, and reduce the data rate after sampling to 4 times the spread spectrum code rate for output, so as to ensure the real-time requirements of the subsequent frame header synchronization algorithm; Step 4: Cache the through signal output by the CIC extraction filter, and output the delayed channel to the complex down-conversion module after the frame header pulse detection and frequency offset estimation are completed; Step 5: Perform differential detection design, local sequence conjugate correlation design and peak detection on the direct signal output by the CIC extraction filter, and output the capture pulse; Step 6: Perform coarse frequency offset compensation on the delayed signal output by the CIC extraction filter, and then perform matched filtering to resample the matched filtered signal from 4 times the chip rate to 2 times the chip rate; Step 7: The output signal of step 6 is symbol synchronized through a delay lock tracking loop DLL, and the early code, the middle code and the late code are despread respectively to extract the timing error signal; Step 8: The timing error signal is used as negative feedback and input into a matched filter for resampling operation, and the optimal resampling point is adjusted to achieve frame header synchronization of the LINK_20 received signal.

2. A frame header synchronization method based on CPM constant envelope spread spectrum sequence according to claim 1, characterized in that: The differential detection is designed as follows: the direct signal output by the CIC extraction filter is used as input, the data rate is 4 times the spread spectrum code rate, that is, there are 4 sampling points in one code chip time, and the delay Ts needs to delay the sampled data by 4 sampling points; after the delay of 4 sampling points, the delayed signal and the received data are conjugate multiplied, and the differential operation result after the conjugate multiplication is output.

3. A frame header synchronization method based on CPM constant envelope spread spectrum sequence according to claim 1, characterized in that: The local sequence conjugate correlation is designed as follows: the synchronization sequence is a sequence of 48 symbols, which is modulated, CPM constant envelope spread spectrum and differential operation, and is used as a local differential synchronization sequence, and is conjugate correlated with the differential operation result of the CIC extraction filter output direct signal; since the synchronization sequence has excellent autocorrelation characteristics after the differential operation, a maximum correlation peak will appear at the completely overlapping position, and the position of the correlation peak is the position of the last symbol of the received signal synchronization header sequence, and the phase of the correlation peak is the frequency deviation.

4. The frame header synchronization method based on CPM constant envelope spread spectrum sequence according to claim 1, characterized in that: The step 7 comprises the following steps: Firstly, the double chip rate data output by the matched filter is used to generate early, middle and late codes in a format with a difference of half a chip period; Secondly, the early, middle and late codes are conjugate-correlated with the spreading sequence of twice the chip rate to complete despreading; Finally, the timing error of the single symbol rate is calculated through envelope detection and loop filter, and the single symbol rate data after medium code despreading and integration is demodulated.

5. The frame header synchronization method based on CPM constant envelope spread spectrum sequence according to claim 1, characterized in that: The peak detection is performed by finding the angle of the maximum correlation peak to obtain the phase of the correlation peak, and using the CORDIC algorithm to calculate the angle of the correlation value corresponding to the frame header to obtain a coarse frequency offset estimation value.

6. A frame header synchronization method based on CPM constant envelope spread spectrum sequence according to claim 5, characterized in that: The calculation formula of the coarse frequency offset estimation value is: Then the phase control word M is calculated by the formula; M=f*2 32 / f sys ; Among them, phase represents the phase difference, Rs represents the symbol rate, and fsys represents the sampling rate; The DDS generates sine and cosine waves with a frequency equal to the coarse frequency deviation estimate, and then multiplies the received IQ complex signal by the complex number composed of sine and cosine to compensate for the coarse frequency deviation mixed in the signal.

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