Data transmission method and device

Abstract

The present invention provides a data transmission method and apparatus, the method comprising: in the case of single-link transmission between a first processor and a second device, in response to a first instruction, controlling a first core in a first processor and a first core in a second processor in a second device to transmit data using a transmission link; determining a data transmission and reception rate between the first core in the first processor and the first core in the second processor; controlling switching of cores used for data transmission in the first processor and / or the second processor, and repeating the above steps until the data transmission and reception rates between all cores are determined; determining a target core combination based on the data transmission and reception rates between different cores in the first processor and the second processor; and in response to a second instruction, controlling the target core combination to perform a transmission task of target data, where the target data is determined based on the second instruction. The data transmission method of the present invention can change the transmission rate to adapt to different transmission requirements and devices when single-link transmission is used between two devices.

Description

Technical Field

[0001] The present invention belongs to the field of computer technology, and in particular relates to a data transmission method and device. Background Art

[0002] The Transmission Control Protocol (TCP) is a transmission protocol designed to provide reliable end-to-end byte streams on unreliable Internet networks.

[0003] The application layer sends an 8-bit byte data stream to the TCP layer for transmission across the internet. TCP partitions the data stream into segments of appropriate length (usually limited by the Maximum Transmission Unit (MTU) of the data link layer of the network to which the computer is connected). TCP passes the resulting packet to the IP layer, which delivers the packet across the network to the receiving entity's TCP layer. To prevent packet loss, TCP assigns a sequence number to each packet, which also ensures that packets delivered to the receiving entity are received in order. The receiving entity sends back an acknowledgment (ACK) for successfully received packets. If the sending entity does not receive the acknowledgment within a reasonable round-trip time (RTT), the corresponding data packet is assumed to have been lost and will be retransmitted.

[0004] Every machine that supports TCP has a TCP transport entity. The TCP entity can be a library procedure, a user process, or part of the kernel.

[0005] Direct memory access (DMA) is a method of operation in which I / O transactions are performed entirely by hardware. In this method, the DMA controller completely takes over bus control from the CPU. Data exchange occurs directly between memory and I / O devices, bypassing the CPU. During DMA operation, the DMA controller sends address and control signals to memory, performs address modification, counts the number of transferred words, and reports the completion of the transfer operation to the CPU via an interrupt.

[0006] The purpose of using DMA is to reduce CPU overhead during large-scale data transmission. A dedicated DMA controller (DMAC) is used to generate memory access addresses and control the memory access process. The advantages are that all operations are implemented by hardware circuits, and the transmission speed is fast; the CPU basically does not intervene and is only involved during initialization and termination. The CPU and peripherals work in parallel, which is highly efficient.

[0007] RDMA is a technology that transfers data directly to the memory of the remote computer through DMA over the network, quickly moving data from one system to the memory of a remote system.

[0008] The working process of RDMA is as follows:

[0009] 1) When an application performs an RDMA read or write request, no data copying is performed. RDMA requests are sent from the application running in user space to the local NIC (network interface card) without any kernel memory involvement.

[0010] 2) The NIC reads the buffered contents and transmits them to the remote NIC over the network.

[0011] 3) The RDMA message transmitted over the network contains the target virtual address, the memory key, and the data itself. Request completion can be handled entirely in user space (by polling the user-level completion queue) or through kernel memory, where the application sleeps until the request completes. RDMA operations enable applications to read data from or write data to the memory of a remote application.

[0012] 4) The target NIC confirms the memory key and writes the data directly to the application cache. The remote virtual memory address used for the operation is included in the RDMA information.

[0013] The Internet, cloud platforms, big data, and communications fields often require large amounts of data to be transmitted from data carrier A to data carrier B using TCP or RDMA technology.

[0014] To achieve these goals, it is necessary to select and evaluate the hardware platform infrastructure, such as high-performance servers, routing and switching equipment, cabinets, and supporting equipment in the computer room. Next, the software platform must be selected, including the operating system, system software, application software, and development platform. Furthermore, efficient and appropriate programming languages, such as C, C++, Java, Python, and C#, must be selected to implement TCP and RDMA data transmission capabilities.

[0015] After selecting a programming language, in order to maximize the transmission rate, traditional solutions will increase the transmission rate as much as possible by increasing the CPU main frequency, increasing the memory main frequency, increasing the cache, etc.

[0016] Traditional solutions improve transmission efficiency by taking into account aspects such as programming languages ​​(Python, Java, C#, C++, C), operating systems, and server clock speeds. The main principles and methods are the efficiency of programming languages, operating systems, and hardware upgrades. Data transmission solutions for the Internet and cloud platforms are based on multiple TCP / RDMA connections, with clients distributed across different user devices, such as computers, mobile phones, and tablets. The server side primarily handles high concurrency and high traffic. High concurrency is reflected in the high randomness and large number of client connections, while high traffic is reflected in n clients sending and receiving data. Because the cardinality of n is large, the total size of the data packets is large.

[0017] Most existing solutions are to improve server performance and provide efficient TCP / RDMA transmission by using multiple CPUs and multiple cores. Existing technical solutions have outstanding performance in solving multi-connection and high-concurrency business scenarios, but they are not suitable for the following scenarios: Figure 1 In the application scenario, there is currently no mature solution to further increase the transmission rate. Figure 1 In a data transmission and processing scenario, due to business needs and customer data processing requirements, two servers A and B are only allowed to establish a single TCP or RDMA link to enable high-speed data transmission from server A to server B. Furthermore, server A's CPU is a domestically produced model with a clear CPU model and programming language, C. The data transfer unit is small (16KB or less). Under these constraints, traditional solutions using multiple connections, concurrency, and high throughput are clearly ineffective. Summary of the Invention

[0018] The technical problem to be solved by the present invention is to provide a data transmission method and apparatus that can change the transmission rate to adapt to different transmission requirements when a single-link transmission type is used between two devices.

[0019] The present invention includes a data transmission method, applied to a first device including a first processor, the method comprising:

[0020] In the case of single-link transmission with the second device, in response to the first instruction, controlling the first core of the first processor and the first core of the second processor of the second device to perform data transmission using the transmission link between the first device and the second device, where both the first processor and the second processor are multi-core processors;

[0021] determining a data transmission and reception rate between the first core in the first processor and the first core in the second processor;

[0022] Controlling switching of cores in the first processor and / or the second processor for data transmission, and repeating the above steps until each core in the first processor cooperates with each core in the second processor to perform the data transmission task and determines the corresponding data transmission and reception rates;

[0023] Determine a target core combination based on data transmission and reception rates between different cores in the first processor and the second processor, the target core combination including a target core in the first processor and a target core in the second processor;

[0024] In response to the second instruction, the target core combination is controlled to execute a transmission task of target data, where the target data is determined based on the second instruction.

[0025] In some embodiments, controlling the first core in the first processor and the first core of the second processor in the second device to transmit data using a transmission link between the first device and the second device includes:

[0026] Creating a first thread for executing the data transmission task on a first core of the first processor;

[0027] Sending an instruction to the second device to instruct the second device to create a second thread for executing the data transmission task for the first core of the second processor;

[0028] Test data is transmitted based on the first thread, the transmission link, and the second thread.

[0029] In some embodiments, determining a data transmission and reception rate between the first core in the first processor and the first core in the second processor includes:

[0030] Determine the testing period;

[0031] The timing starts when the first core executes the data transmission task and stops when the test duration is reached;

[0032] Counting the amount of test data sent by the first core during the test period and the amount of test data received by the second core during the test period;

[0033] The data transmission and reception rate is determined by calculation based on the test data transmission amount, the test data reception amount, and the test period.

[0034] In some embodiments, when the first core executes the first thread, the test data sending amount is recorded, and when the second core executes the second thread, the test data receiving amount is recorded;

[0035] The method further comprises:

[0036] Sending a start timing signal and an end timing signal to the second core of the second processor to control the second processor to start and stop receiving test data;

[0037] The test data reception amount fed back by the second core of the second processor is obtained.

[0038] In some embodiments, the test period is the duration of a test, and the method further includes:

[0039] In response to the end of the current test, instructing the first core of the first processor and the first core of the second processor to clear the recorded test data sending amount and test data receiving amount;

[0040] Recording the number of tests and data transmission and reception rates corresponding to the current test of the first core of the first processor and the first core of the second processor, where the number of tests is the cumulative number of tests;

[0041] The next test is initiated on the first core of the first processor and the first core of the second processor.

[0042] In some embodiments, the method further comprises:

[0043] Determine whether the current cumulative number of tests of the first core of the first processor and the first core of the second processor reaches a threshold; if not, continue to start the next test; if so, perform average processing on all data transmission and reception rates corresponding to the cumulative number of tests to obtain the average of the data transmission and reception rates corresponding to the first core of the first processor and the first core of the second processor.

[0044] In some embodiments, the method further comprises:

[0045] determining whether the current cumulative number of tests of the first core of the first processor and the first core of the second processor reaches a threshold; if not, continuing to start the next test; if so, clearing the cumulative number of tests to zero and notifying the second processor of the second device to switch the first core to the second core, so as to test the first core of the first processor and the second core of the second processor;

[0046] When the first core of the first processor and each core of the second processor have completed testing, the first processor is controlled to switch the first core to the second core, and at the same time, the second processor of the second device is notified to switch the core currently corresponding to the test to the first core, so as to test the second core of the first processor and the first core of the second processor.

[0047] In some embodiments, determining the target core combination based on data transmission and reception rates between different cores in the first processor and the second processor includes:

[0048] Determining an average of data transmission and reception rates between different cores in the first processor and the second processor;

[0049] Determining two target cores corresponding to the maximum average data receiving and sending rates based on average data receiving and sending rates between different cores in the first processor and the second processor, wherein the two target cores include the target core in the first processor and the target core in the second processor;

[0050] The target core combination is determined based on a target core in the first processor and a target core in the second processor.

[0051] In some embodiments, responding to the first instruction includes:

[0052] In response to a user input command to initiate a test; or

[0053] In response to obtaining a transmission task for data of a specified type; or

[0054] in response to the initiation of a designated program; or

[0055] When the result of the data transmission task performed by the first processor and the second processor in cooperation with two randomly selected cores is determined to not meet the preset transmission requirement, responding to an instruction generated by the determination result;

[0056] The responding to the second instruction includes:

[0057] In response to the transfer request of the target data, the target data is instruction type data, or is any type of data.

[0058] Another embodiment of the present invention also provides a data transmission apparatus, applied to a first device including a first processor, the apparatus comprising:

[0059] a first response module, configured to, in response to a first instruction, control the first core of the first processor and the first core of the second processor of the second device to perform data transmission using the transmission link between the first device and the second device, when single-link transmission is used with the second device, where both the first processor and the second processor are multi-core processors;

[0060] a first determining module, configured to determine a data transmission and reception rate between the first core in the first processor and the first core in the second processor;

[0061] a control module, configured to control switching of cores in the first processor and / or the second processor for data transmission, and repeatedly perform the above steps until each core in the first processor cooperates with each core in the second processor to perform the data transmission task and determines corresponding data transmission and reception rates;

[0062] a second determining module, configured to determine a target core combination according to a data transmission and reception rate between different cores in the first processor and the second processor, the target core combination comprising a target core in the first processor and a target core in the second processor;

[0063] The second response module is configured to control the target core combination to execute a target data transmission task in response to a second instruction, where the target data is determined based on the second instruction.

[0064] The beneficial effects of the present invention include achieving adjustable transmission efficiency and even optimal transmission rate for a device or computer system by optimally integrating computer software technology with computer hardware resources. This application solution mainly solves the problem of a single-link transmission service scenario, in which the system automatically selects the core by polling and measuring the data transmission and reception rate between different cores of two devices, making the communication rate adjustable and achieving optimal transmission performance. This not only maximizes the use of computer hardware resources, but also provides more flexible options for different forms of data transmission.

[0065] Other features and advantages of the present application will be described in the following description, and in part will become apparent from the description, or will be understood by practicing the present application. The purposes and other advantages of the present application can be realized and obtained by the structures particularly pointed out in the written description, claims, and drawings.

[0066] The technical solution of the present application is further described in detail below through the accompanying drawings and examples. BRIEF DESCRIPTION OF THE DRAWINGS

[0067] In order to more clearly illustrate the specific embodiments of the present invention or the technical solutions in the prior art, the following briefly introduces the drawings required for use in the specific embodiments or the description of the prior art. Obviously, the drawings described below are some embodiments of the present invention. For ordinary technicians in this field, other drawings can be obtained based on these drawings without paying any creative work.

[0068] Figure 1 This is a flow chart of the existing solution.

[0069] Figure 2 This is an application scenario diagram of the data transmission method according to an embodiment of the present invention.

[0070] Figure 3 Flowchart of a data transmission method according to an embodiment of the present invention.

[0071] Figure 4 FIG2 is a schematic diagram of an application flow of a data transmission method according to another embodiment of the present invention.

[0072] Figure 5 FIG2 is a schematic diagram of an application flow of a data transmission method according to another embodiment of the present invention.

[0073] Figure 6 FIG. 4 is a structural block diagram of a data transmission device according to an embodiment of the present invention. DETAILED DESCRIPTION

[0074] The specific embodiments of the present invention are described in detail below with reference to the accompanying drawings, but are not intended to limit the present invention.

[0075] It should be understood that various modifications may be made to the embodiments disclosed herein. Therefore, the following description should not be considered as limiting, but merely as an example of an embodiment. Other modifications within the scope of the present disclosure will occur to those skilled in the art.

[0076] The accompanying drawings, which are incorporated in and constitute a part of the specification, illustrate embodiments of the present disclosure and, together with the general description of the present disclosure given above and the detailed description of the embodiments given below, serve to explain the principles of the present disclosure.

[0077] These and other characteristics of the invention will become apparent from the following description of a preferred form of embodiment given as a non-limiting example with reference to the accompanying drawings.

[0078] It should also be understood that although the invention has been described with reference to certain specific examples, those skilled in the art will be able to realize many other equivalent forms of the invention that have the characteristics recited in the claims and are therefore within the scope of protection defined thereby.

[0079] The above and other aspects, features and advantages of the present disclosure will become more apparent from the following detailed description when taken in conjunction with the accompanying drawings.

[0080] Specific embodiments of the present disclosure will be described hereinafter with reference to the accompanying drawings; however, it should be understood that the disclosed embodiments are merely examples of the present disclosure, which may be implemented in a variety of ways. Well-known and / or repetitive functions and structures are not described in detail to avoid obscuring the present disclosure with unnecessary or redundant detail. Therefore, the specific structural and functional details disclosed herein are not intended to be limiting, but rather serve merely as a basis and representative basis for the claims to teach those skilled in the art to variously employ the present disclosure with substantially any suitable detailed structure.

[0081] This description may use the phrases "in one embodiment," "in another embodiment," "in a further embodiment," or "in other embodiments," each of which may refer to one or more of the same or different embodiments according to the present disclosure.

[0082] Hereinafter, embodiments of the present invention will be described in detail with reference to the accompanying drawings.

[0083] Existing technical solutions have outstanding performance in solving multi-connection and high-concurrency business scenarios, but in Figure 2 In the application scenario, there is currently no mature solution to further increase the transmission rate. Figure 2In a data transmission and processing business scenario, due to business needs and customer data processing requirements, two servers A and B are only allowed to establish one TCP or RDMA link to achieve high-speed data transmission from server A to server B. At the same time, the CPU model of server A is clear, the programming language is also clear as C language, and the data transmission unit is small (16KB and below). Under these constraints, the traditional method of using multi-connection technology, concurrency and high traffic is obviously ineffective. In order to solve this technical problem, Figure 3 As shown, an embodiment of the present invention provides a data transmission method, which is applied to a first device including a first processor, and the method includes:

[0084] S1: In a case where single-link transmission is used with a second device, in response to a first instruction, controlling a first core in the first processor and a first core in the second processor in the second device to perform data transmission using the transmission link between the first device and the second device, where both the first processor and the second processor are multi-core processors;

[0085] S2: Determine a data transmission and reception rate between the first core in the first processor and the first core in the second processor;

[0086] S3: Control switching of the cores used for data transmission in the first processor and / or the second processor, and repeat the above steps until each core in the first processor cooperates with each core in the second processor to perform the data transmission task and determines the corresponding data transmission and reception rates;

[0087] S4: Determine a target core combination based on data transmission and reception rates between different cores in the first processor and the second processor, where the target core combination includes a target core in the first processor and a target core in the second processor;

[0088] S5: In response to the second instruction, controlling the target core combination to execute a target data transmission task, where the target data is determined based on the second instruction.

[0089] The transmission link in this embodiment can be a TCP-TCP transmission type or an RDMA-RDMA transmission type, such as Figure 2 In the scenario shown, since the physical parameters of the devices are fixed, the transmission speed is determined by the server randomly selecting the processor core (referred to as the core) to handle the data transmission task. To enable the data transmission speed to be changed, this embodiment achieves this by selecting the core used to handle the data transmission task.

[0090] For example, the core of computer A is defined as A{Ac0, Ac1, Ac2…Aci}, and the core of computer B is defined as B{Bc0, Bc1, Bc2…Bci}, and data is sent from A to computer B via a TCP or RDMA type transmission link. Different CPU cores of the same server or computer have different core rates, and the phenomenon of inconsistent CPU core rates is mainly due to the different clock speeds of each core, which leads to differences in core performance. The clock speed of each core may be different due to a variety of reasons, including but not limited to heat dissipation problems, unstable voltage supply, slight differences in the manufacturing process, etc. This rate inconsistency may cause some cores to be faster or slower than other cores when processing tasks, thereby affecting the overall performance, including differences in transmission speed. Therefore, in order to adjust the transmission speed, this embodiment provides a method, specifically by selecting different cores to perform the current data transmission task, thereby changing the transmission speed.

[0091] When selecting a core, the method used in this embodiment includes responding to a first instruction that triggers the core selection process, controlling the first cores of the processors of the two devices to cooperate in executing the transmission of test data, determining their data transmission and reception rates, and then switching the cores of the processors, and continuing the test until each core in the two processors has been combined and tested. That is, each core in the first processor of the first device has been combined with each core in the second processor of the second device, and tested in cooperation, and the corresponding data transmission and reception speeds have been obtained. At this point, the system will determine a data transmission and reception speed that meets the requirements based on multiple data transmission and reception speeds, and then determine the corresponding two target cores based on the selected data transmission and reception speeds. Thereafter, in response to a second instruction, the system will select the two target cores to cooperate in executing the data transmission task.

[0092] The selected data transmission and reception speed can be the fastest speed or the second fastest speed, which is not fixed and can be freely selected according to actual transmission needs. As can be seen from the above content, this embodiment achieves adjustable transmission efficiency of a device or computer system and even achieves optimal transmission rate by optimally integrating computer software technology and computer hardware resources. The solution of this embodiment mainly solves the problem of single-link transmission business scenario, by polling and measuring the data transmission and reception rate between different cores of two devices, and automatically allowing the system to select the core, so that the communication rate is adjustable and the transmission performance can be optimized. It not only maximizes the use of computer hardware resources, but also provides more flexible options for different forms of data transmission.

[0093] In one embodiment, controlling the first core in the first processor and the first core of the second processor in the second device to transmit data using a transmission link between the first device and the second device includes:

[0094] S6: Creating a first thread for executing the data transmission task on the first core of the first processor;

[0095] S7: Sending an instruction to the second device to instruct the second device to create a second thread for executing the data transmission task for the first core of the second processor;

[0096] S8: Transmit test data based on the first thread, the transmission link, and the second thread.

[0097] Specifically, the first device locally creates a first thread for a data transmission task and then synchronously sends instructions to the second device, instructing the first core of the second processor to similarly create a related thread, known as the second thread. The processors of both devices then use the transmission link to transmit test data based on their respective threads. The first and second threads can include, but are not limited to, link initialization, data transmission or reception, and data volume statistics.

[0098] Furthermore, determining a data transmission and reception rate between the first core in the first processor and the first core in the second processor includes:

[0099] S9: Determine the test period;

[0100] S10: starting timing when the first core executes the data transmission task and stopping timing when the test duration is reached;

[0101] S11: Counting the amount of test data sent by the first core during the test period and the amount of test data received by the second core during the test period;

[0102] S12: Calculate and determine the data transmission and reception rate based on the test data transmission amount, the test data reception amount, and the test period.

[0103] In this embodiment, when the first core executes the first thread, it records the test data sending amount; when the second core executes the second thread, it records the test data receiving amount. That is, when the cores of different devices are tested, they each record the data sending amount and data receiving amount during the test period, and then send them to the first device for unified calculation by the first device.

[0104] The method further comprises:

[0105] S13: Sending a start timing signal and an end timing signal to the first core of the second processor to control the second processor to start and stop receiving test data;

[0106] S14: Obtain the test data reception amount fed back by the first core of the second processor.

[0107] That is, the start-up test and the end-test of the core in the second device are both controlled by the first device, and the second device specifically executes and ends the test by responding to the instruction or notification sent by the first device.

[0108] For example, the first processor of the first device first determines a test period, such as 1s, 2s, etc., which is not unique. After determining the test period, the first processor of the first device will start the timer when controlling the first core to execute the first thread, and notify the second processor of the second device to execute the second thread, such as sending a timestamp to implement the notification. When the timing ends and reaches the corresponding duration of the test period, the first processor of the first device will control the first core to end the execution of the first thread, and notify the second processor of the second device to stop executing the second thread, such as still notifying through a timestamp. At this time, the first processor and the second processor will respectively obtain their respective data sending and data receiving volumes. The second device can send the statistical data receiving volume to the first device, and the first device will calculate the data sending and data receiving volumes between the corresponding cores in combination with the test period to obtain the data sending and receiving rate between the corresponding cores.

[0109] In another embodiment, the test period is the duration of a test, and the method further includes:

[0110] S15: In response to the end of the current test, instruct the first core of the first processor and the first core of the second processor to clear the recorded test data sending amount and test data receiving amount;

[0111] S16: Record the number of tests and data receiving and sending rates corresponding to the current test of the first core of the first processor and the first core of the second processor, where the number of tests is the cumulative number of tests;

[0112] S17: Start the next test on the first core of the first processor and the first core of the second processor.

[0113] In this embodiment, Figure 4As shown, any two cores in the first device and the second device are tested multiple times, such as 50 times, 100 times, etc., with no specific limit. The duration of each test is a test period. When the current test ends, if it is necessary to continue testing the two cores currently under test, the first processor of the first device responds to the end of the current test by instructing the first core of the first processor and the first core of the second processor to clear the recorded test data sending volume and test data receiving volume, and at the same time records the number of tests and data transmission and reception rates corresponding to the current test of the first core of the first processor and the first core of the second processor, that is, matches the recorded core information, the corresponding data transmission and reception rate and the number of tests completed by the core, and the number of tests is the cumulative number of tests. Afterwards, the next test is started for the first core of the first processor and the first core of the second processor, and the specific process is the same as the previous test.

[0114] Further, combined Figure 5 As shown, the method further includes:

[0115] S18: Determine whether the current cumulative number of tests on the first core of the first processor and the first core of the second processor has reached a threshold; if not, continue to start the next test; if so, perform average processing on all data transmission and reception rates corresponding to the cumulative number of tests to obtain the average of the data transmission and reception rates corresponding to the first core of the first processor and the first core of the second processor.

[0116] Assume that the threshold value of the number of tests between every two cores is 100, or it can be other values, which are not specific. In response to the end of the current test, before starting the next test, the first processor of the first device will determine whether the cumulative number of tests of the two cores currently under test has reached the threshold. If not, the next test will be started, that is, the current two cores will continue to be tested. If the test threshold is reached, the average calculation will be performed based on the test results of all completed tests, that is, the average calculation will be performed based on the data transmission and reception speeds of all tests, and the average data transmission and reception rate that can characterize the actual data transmission and reception speed level of the two cores will be determined. When the speed comparison between different cores is subsequently performed, the data transmission and reception speed average is used for comparison to determine the target core.

[0117] Continue to combine Figure 5 As shown, the method further includes:

[0118] S19: Determine whether the current cumulative number of tests of the first core of the first processor and the first core of the second processor reaches a threshold; if not, continue to start the next test; if so, reset the cumulative number of tests to zero, and notify the second processor of the second device to switch the first core to the second core, so as to test the first core of the first processor and the second core of the second processor;

[0119] S20: After the first core of the first processor and each core of the second processor have completed testing, control the first processor to switch the first core to the second core, and at the same time notify the second processor of the second device to switch the core currently corresponding to the test to the first core, so as to test the second core of the first processor and the first core of the second processor.

[0120] For example, each core is tested for a set amount of time, where Count represents the number of seconds tested on that CPU core, for example, 100 seconds. The average rate for that core is calculated over 100 seconds. After testing Count times, the thread is set to move to a new CPU core and continue testing. After testing all cores on that computer, a command is sent to notify the other computer to switch to the new CPU core and repeat the test. Finally, by comparing the maximum rate V, the core number of the corresponding computer A or B is determined.

[0121] The determining the target core combination based on data transmission and reception rates between different cores in the first processor and the second processor includes:

[0122] S21: Determine an average of data transmission and reception rates between different cores in the first processor and the second processor;

[0123] S22: Determine two target cores corresponding to maximum average data receiving and sending rates based on average data receiving and sending rates between different cores in the first processor and the second processor, where the two target cores include a target core in the first processor and a target core in the second processor;

[0124] S23: Determine the target core combination based on the target core in the first processor and the target core in the second processor.

[0125] For example, when the sending thread (first thread) of the i core of the first device and the receiving thread (second thread) of the j core of the second device are executing the transmission of test data, the data transmission and reception rate is recorded as Vij{Vc0c0, Vc0c1, Vc0c2…Vcicj}, i∈{Ac0, Ac1, Ac2…Aci}, j∈{Bc0, Bc1, Bc2…Bci}. The scheme of this embodiment is used to calculate Vmax, that is, to calculate the maximum data transmission and reception speed. Among them, Vmax∈{Vc0c0, Vc0c1, Vc0c2…Vcicj}, that is, the core subscripts i and j of the computer kernel. In other words, this embodiment compares the average values ​​of the data transmission and reception speeds obtained after testing different core combinations, selects and determines the maximum value of the data transmission and reception speed, and then determines the core combination with the best performance, that is, the target core combination. Of course, cores with other speed averages can also be selected as the target core combination. The specific selection needs to be made according to actual needs and is flexible in use.

[0126] In this embodiment, the generation of the first instruction for triggering the first device to execute the test process may be, but is not limited to, the following scenarios, for example including:

[0127] S24: responding to a test start instruction input by a user; or

[0128] In response to obtaining a transmission task for data of a specified type; or

[0129] in response to the initiation of a designated program; or

[0130] When the result of the data transmission task performed by the first processor and the second processor in cooperation with two randomly selected cores is determined to not meet the preset transmission requirement, responding to an instruction generated by the determination result;

[0131] The responding to the second instruction includes:

[0132] S25: Responding to the transmission request of the target data, the target data is data of a specified type, or data of any type.

[0133] For example, the first instruction is an instruction input by the user, which is used to instruct the first device to perform a transmission speed test. Alternatively, in response to the startup of a specified program, the program can be a sharing program, a conference program, etc., which requires two devices to display data synchronously, etc. In this case, the first instruction can be an instruction generated based on the startup of the program. Alternatively, when the first device performs a data transmission task with a speed transmission requirement, if the core is first determined based on a random core selection method, if the predicted speed of data transmission based on the randomly selected core cannot meet the requirement, a first instruction is generated to start the test program to select and determine the core that can perform the data transmission task.

[0134] The second instruction is an instruction for transmitting new data, namely, target data. The data type can be a specified type of data, i.e., when transmitting data of the instruction type, a target core is selected to cooperate in executing the data transmission task, or it can be any type of data, i.e., when transmitting any data, the target core is used to execute the data transmission task. In addition, corresponding to different types of data, target cores with different transmission speeds can be determined to cooperate in executing the corresponding transmission task. Specifically, a relationship table can be pre-configured, and when applied, the target core selected for different types of data is directly determined based on the relationship table.

[0135] like Figure 6 As shown, another embodiment of the present invention also provides a data transmission device, which is applied to a first device including a first processor, and the device includes:

[0136] a first response module, configured to, in response to a first instruction, control the first core of the first processor and the first core of the second processor of the second device to perform data transmission using the transmission link between the first device and the second device, when single-link transmission is used with the second device, where both the first processor and the second processor are multi-core processors;

[0137] a first determining module, configured to determine a data transmission and reception rate between the first core in the first processor and the first core in the second processor;

[0138] a first control module, configured to control switching of cores in the first processor and / or the second processor for data transmission, and repeatedly perform the above steps until each core in the first processor cooperates with each core in the second processor to perform the data transmission task and determines corresponding data transmission and reception rates;

[0139] a second determining module, configured to determine a target core combination according to a data transmission and reception rate between different cores in the first processor and the second processor, the target core combination comprising a target core in the first processor and a target core in the second processor;

[0140] The second response module is configured to control the target core combination to execute a target data transmission task in response to a second instruction, where the target data is determined based on the second instruction.

[0141] In some embodiments, controlling the first core in the first processor and the first core of the second processor in the second device to transmit data using a transmission link between the first device and the second device includes:

[0142] Creating a first thread for executing the data transmission task on a first core of the first processor;

[0143] Sending an instruction to the second device to instruct the second device to create a second thread for executing the data transmission task for the first core of the second processor;

[0144] Test data is transmitted based on the first thread, the transmission link, and the second thread.

[0145] In some embodiments, determining a data transmission and reception rate between the first core in the first processor and the first core in the second processor includes:

[0146] Determine the testing period;

[0147] The timing starts when the first core executes the data transmission task and stops when the test duration is reached;

[0148] Counting the amount of test data sent by the first core during the test period and the amount of test data received by the second core during the test period;

[0149] The data transmission and reception rate is determined by calculation based on the test data transmission amount, the test data reception amount, and the test period.

[0150] In some embodiments, when the first core executes the first thread, the test data sending amount is recorded, and when the second core executes the second thread, the test data receiving amount is recorded;

[0151] The device further comprises:

[0152] a second control module, configured to send a start timing signal and an end timing signal to the second core of the second processor, so as to control the second processor to start or stop receiving test data;

[0153] An obtaining module is used to obtain the test data reception amount fed back by the second core of the second processor.

[0154] In some embodiments, the test period is the duration of a test, and the method further includes:

[0155] In response to the end of the current test, instructing the first core of the first processor and the first core of the second processor to clear the recorded test data sending amount and test data receiving amount;

[0156] Recording the number of tests and data transmission and reception rates corresponding to the current test of the first core of the first processor and the first core of the second processor, where the number of tests is the cumulative number of tests;

[0157] The next test is initiated on the first core of the first processor and the first core of the second processor.

[0158] In some embodiments, the apparatus further comprises:

[0159] Determine whether the current cumulative number of tests of the first core of the first processor and the first core of the second processor reaches a threshold; if not, continue to start the next test; if so, perform average processing on all data transmission and reception rates corresponding to the cumulative number of tests to obtain the average of the data transmission and reception rates corresponding to the first core of the first processor and the first core of the second processor.

[0160] In some embodiments, the apparatus further comprises:

[0161] a determination module, configured to determine whether a current cumulative number of tests of the first core of the first processor and the first core of the second processor has reached a threshold; if not, to proceed with initiating the next test; and if so, to reset the cumulative number of tests to zero and to notify the second processor of the second device to switch from the first core to the second core, so as to test the first core of the first processor and the second core of the second processor;

[0162] The third control module is used to control the first processor to switch the first core to the second core after the first core of the first processor and each core of the second processor have completed testing, and at the same time notify the second processor of the second device to switch the core currently corresponding to the test to the first core, so as to test the second core of the first processor and the first core of the second processor.

[0163] In some embodiments, determining the target core combination based on data transmission and reception rates between different cores in the first processor and the second processor includes:

[0164] Determining an average of data transmission and reception rates between different cores in the first processor and the second processor;

[0165] Determining two target cores corresponding to the maximum value of the average data receiving and sending rates based on the average data receiving and sending rates between different cores in the first processor and the second processor, wherein the two target cores include the target core in the first processor and the target core in the second processor;

[0166] The target core combination is determined based on a target core in the first processor and a target core in the second processor.

[0167] In some embodiments, responding to the first instruction includes:

[0168] In response to a user input command to initiate a test; or

[0169] In response to obtaining a transmission task for data of a specified type; or

[0170] in response to the initiation of a designated program; or

[0171] When the result of the data transmission task performed by the first processor and the second processor in cooperation with two randomly selected cores is determined to not meet the preset transmission requirement, responding to an instruction generated by the determination result;

[0172] The responding to the second instruction includes:

[0173] In response to the transfer request of the target data, the target data is instruction type data, or is any type of data.

[0174] Another embodiment of the present invention further provides an electronic device, comprising:

[0175] one or more processors;

[0176] a memory configured to store one or more programs;

[0177] When the one or more programs are executed by the one or more processors, the one or more processors implement the data transmission method as described in any one of the above embodiments.

[0178] Furthermore, an embodiment of the present invention further provides a storage medium having a computer program stored thereon, which, when executed by a processor, implements the data transmission method described above. It should be understood that each solution in this embodiment has the corresponding technical effects of the above method embodiments, and will not be further described here.

[0179] Furthermore, an embodiment of the present invention also provides a computer program product, which is tangibly stored on a computer-readable medium and includes computer-readable instructions. When the computer-executable instructions are executed, at least one processor executes the data transmission method in the embodiment described above.

[0180] It should be noted that the computer storage medium of the present invention may be a computer-readable signal medium or a computer-readable storage medium, or any combination thereof. Computer-readable media may, for example, be, but are not limited to, electrical, magnetic, optical, electromagnetic, infrared, or semiconductor systems, systems, or devices, or any combination thereof. More specific examples of computer-readable storage media may include, but are not limited to, an electrical connection having one or more wires, a portable computer disk, a hard disk, a random access memory (RAM), a read-only memory (ROM), an erasable programmable read-only memory (EPROM or flash memory), an optical fiber, a portable compact disk read-only memory (CD-ROM), an optical storage medium, a magnetic storage medium, or any suitable combination thereof. In the present invention, a computer-readable storage medium may be any tangible medium containing or storing a program that can be used by or in conjunction with an instruction execution system, system, or device. In the present invention, a computer-readable signal medium may include a data signal propagated in baseband or as part of a carrier wave, which carries computer-readable program code. This propagated data signal may take a variety of forms, including, but not limited to, electromagnetic signals, optical signals, or any suitable combination thereof. A computer-readable signal medium may also be any computer-readable medium other than a computer-readable storage medium that can transmit, propagate, or transport a program configured for use by or in conjunction with an instruction execution system, system, or device. Program code embodied on a computer-readable medium may be transmitted using any suitable medium, including but not limited to wireless, antenna, optical cable, RF, or any suitable combination thereof.

[0181] In addition, it will be understood by those skilled in the art that embodiments of the present invention may be provided as methods, systems, or computer program products. Thus, the present invention may take the form of a complete hardware embodiment, a complete software embodiment, or an embodiment combining software and hardware. Furthermore, the present invention may take the form of a computer program product implemented on one or more computer-usable storage media (including but not limited to magnetic disk storage and optical storage, etc.) containing computer-usable program code.

[0182] The present invention is described with reference to flowcharts and / or block diagrams of methods, devices (systems), and computer program products according to embodiments of the present invention. It should be understood that each process and / or block in the flowcharts and / or block diagrams, as well as combinations of processes and / or blocks in the flowcharts and / or block diagrams, can be implemented by computer program instructions. These computer program instructions can be provided to a processor of a general-purpose computer, a special-purpose computer, an embedded processor, or other programmable data processing device to produce a machine, so that the instructions executed by the processor of the computer or other programmable data processing device generate instructions for implementing the processes in the flowcharts and / or block diagrams. Figure 1a process or multiple processes and / or boxes Figure 1 A system that specifies the functions of a box or boxes.

[0183] These computer program instructions may also be stored in a computer-readable memory that can direct a computer or other programmable data processing device to work in a specific manner, so that the instructions stored in the computer-readable memory produce an article of manufacture including an instruction system that is implemented in the process. Figure 1 a process or multiple processes and / or boxes Figure 1 The function specified in one or more boxes.

[0184] Those skilled in the art should understand that the discussion of any of the above embodiments is merely illustrative and is not intended to imply that the scope of protection of the present application is limited to these examples. In line with the present application, the technical features in the above embodiments or different embodiments may be combined, the steps may be implemented in any order, and there are many other variations of different aspects of one or more embodiments of the present application as described above, which are not provided in detail for the sake of simplicity.

Claims

1. A data transmission method, applied to a first device including a first processor, characterized in that: The method comprises: In the case of single-link transmission with the second device, in response to the first instruction, controlling the first core of the first processor and the first core of the second processor of the second device to perform data transmission using the transmission link between the first device and the second device, where both the first processor and the second processor are multi-core processors; determining a data transmission and reception rate between the first core in the first processor and the first core in the second processor; Controlling switching of cores in the first processor and / or the second processor for data transmission, and repeating the above steps until each core in the first processor cooperates with each core in the second processor to perform the data transmission task and determines the corresponding data transmission and reception rates; Determine a target core combination based on data transmission and reception rates between different cores in the first processor and the second processor, the target core combination including a target core in the first processor and a target core in the second processor; In response to the second instruction, the target core combination is controlled to execute a transmission task of target data, where the target data is determined based on the second instruction.

2. The data transmission method according to claim 1, wherein: The controlling the first core in the first processor and the first core of the second processor in the second device to perform data transmission using a transmission link between the first device and the second device includes: Creating a first thread for executing the data transmission task on a first core of the first processor; Sending an instruction to the second device to instruct the second device to create a second thread for executing the data transmission task for the first core of the second processor; Test data is transmitted based on the first thread, the transmission link, and the second thread.

3. The data transmission method according to claim 2, wherein: The determining a data transmission and reception rate between the first core in the first processor and the first core in the second processor includes: Determine the testing period; The timing starts when the first core executes the data transmission task and stops when the test duration is reached; Counting the amount of test data sent by the first core during the test period and the amount of test data received by the second core during the test period; The data transmission and reception rate is determined by calculation based on the test data transmission amount, the test data reception amount, and the test period.

4. The data transmission method according to claim 3, wherein: When the first core executes the first thread, the test data sending amount is recorded; when the second core executes the second thread, the test data receiving amount is recorded; The method further comprises: Sending a start timing signal and an end timing signal to the first core of the second processor to control the second processor to start and stop receiving test data; The test data reception amount fed back by the first core of the second processor is obtained.

5. The data transmission method according to claim 3, wherein: The test period is the duration of a test, and the method further includes: In response to the end of the current test, instructing the first core of the first processor and the first core of the second processor to clear the recorded test data sending amount and test data receiving amount; Recording the number of tests and data transmission and reception rates corresponding to the current test of the first core of the first processor and the first core of the second processor, where the number of tests is the cumulative number of tests; The next test is initiated on the first core of the first processor and the first core of the second processor.

6. The data transmission method according to claim 5, characterized in that: The method further comprises: Determine whether the current cumulative number of tests of the first core of the first processor and the first core of the second processor reaches a threshold; if not, continue to start the next test; if so, perform average processing on all data transmission and reception rates corresponding to the cumulative number of tests to obtain the average of the data transmission and reception rates corresponding to the first core of the first processor and the first core of the second processor.

7. The data transmission method according to claim 5, characterized in that: The method further comprises: determining whether the current cumulative number of tests of the first core of the first processor and the first core of the second processor reaches a threshold; if not, continuing to start the next test; if so, clearing the cumulative number of tests to zero and notifying the second processor of the second device to switch the first core to the second core, so as to test the first core of the first processor and the second core of the second processor; When the first core of the first processor and each core of the second processor have completed testing, the first processor is controlled to switch the first core to the second core, and at the same time, the second processor of the second device is notified to switch the core currently corresponding to the test to the first core, so as to test the second core of the first processor and the first core of the second processor.

8. The data transmission method according to claim 6, wherein: The determining the target core combination based on data transmission and reception rates between different cores in the first processor and the second processor includes: Determining an average of data transmission and reception rates between different cores in the first processor and the second processor; Determining two target cores corresponding to the maximum value of the average data receiving and sending rates based on the average data receiving and sending rates between different cores in the first processor and the second processor, wherein the two target cores include the target core in the first processor and the target core in the second processor; The target core combination is determined based on a target core in the first processor and a target core in the second processor.

9. The data transmission method according to claim 1, wherein: The responding to the first instruction includes: In response to a user input command to initiate a test; or In response to obtaining a transmission task for data of a specified type; or in response to the initiation of a designated program; or When the result of the data transmission task performed by the first processor and the second processor in cooperation with two randomly selected cores is determined to not meet the preset transmission requirement, responding to an instruction generated by the determination result; The responding to the second instruction includes: In response to the transmission request of the target data, the target data is data of a specified type or data of any type.

10. A data transmission device, applied to a first device including a first processor, characterized in that: The device comprises: a first response module, configured to, in response to a first instruction, control the first core of the first processor and the first core of the second processor of the second device to perform data transmission using the transmission link between the first device and the second device, when single-link transmission is used with the second device, where both the first processor and the second processor are multi-core processors; a first determining module, configured to determine a data transmission and reception rate between the first core in the first processor and the first core in the second processor; a control module, configured to control switching of cores in the first processor and / or the second processor for data transmission, and repeatedly perform the above steps until each core in the first processor cooperates with each core in the second processor to perform the data transmission task and determines corresponding data transmission and reception rates; a second determining module, configured to determine a target core combination according to a data transmission and reception rate between different cores in the first processor and the second processor, the target core combination comprising a target core in the first processor and a target core in the second processor; The second response module is configured to control the target core combination to execute a target data transmission task in response to a second instruction, where the target data is determined based on the second instruction.

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