Method and device for measuring network delay by using message timestamp

Abstract

The invention discloses a method for measuring network time delay by using a message timestamp, which comprises the following steps of: connecting first equipment to be tested with first test equipment through a network cable, then connecting the first test equipment with second test equipment, and connecting the second test equipment with second equipment to be tested; after the second test equipment receives the data of the first test equipment, a processing unit of the second test equipment automatically reads timestamps and removes the timestamps, then the processing unit converts the timestamps into time information, the time information is compared with internal time to calculate a difference value of two times, and network delay can be measured in real time through the two timestamp processing equipment; high-precision time delay can be calculated by using the time provided by the time service receiver; measurement can be carried out under most conditions after being tamed by a crystal oscillator, and the measurement is not affected by the outside. The network time delay can be observed in real time through the man-machine interaction module of the device, the calculated network time delay error is small, and the device has real-time performance and can be applied to some environments with high requirements for the network time delay.

Description

Technical Field

[0001] The present invention relates to the field of communication technology, and in particular to a method and device for measuring network delay by using message timestamp. Background Art

[0002] At present, the industry's network delay measurement method is mainly through Ping (network detection): Ping is one of the most commonly used tools to measure network delay, by sending a small data packet to the destination address, and then checking the time to receive the response; Traceroute (path tracking): Traceroute is another network delay tool used to test delay. It also uses data packets, but more than that, it will also record the time it takes for the data packet to pass through the intermediate nodes from the source to the destination address; MTR (network diagnostic tool) MTR is a super combination of Ping and Traceroute. MTR provides a detailed report that lists the information of each network node required from one endpoint to another. This report usually includes various details. The previous methods can basically only roughly calculate the network delay. The network delay not only needs to consider the delay on the physical link, but also the impact caused by processing delay, routers, etc.

[0003] The traditional measurement method generally uses end A to send a small data packet to end B, and then end A Z receives the response data packet from end B, and calculates the network delay by calculating the time required to receive the response. This method not only calculates a large error in the network delay, but also does not have real-time performance and cannot be applied to some environments with high requirements for network delay. Summary of the invention

[0004] The purpose of the present invention is to overcome the deficiencies of the prior art and provide a method and device for measuring network delay using message timestamps.

[0005] The objective of the present invention is achieved through the following technical solutions: First invention, the present invention provides a method for measuring network delay using message timestamp, comprising the following steps: S1. At a first location, connect a first device under test to a first network port of a first test device through a network cable, then connect a second network port of the first test device to a first network port of a second test device, and connect a second network port of the second test device to a second device under test at a second location; S2. After the first device under test at the first location communicates normally with the second device under test at the second location, the first test device will detect its first network port. If there is data input on the first network port, the first test device will add a timestamp to the message through the processing unit inside the device, and then send it out from the second network port. S3. When the second network port of the second test device recognizes the data input, the second test device automatically packages the input data and sends it to the processing unit. After receiving the data, the processing unit automatically reads the timestamp and removes the timestamp. The processing unit then converts the timestamp into time information, compares it with the internal time, calculates the difference between the two times, and sends it through the third network port of the second test device, or directly observes the network delay from the first location to the second location through the human-computer interaction module of the device.

[0006] Based on the first aspect, step S1 also includes: placing the antennas at the first location and the second location in an open area, using antenna feeders to connect the satellite signals to the first test device and the second test device respectively, waiting for the human-computer interaction module display screen to show that the satellite time signal is valid, and then starting the network delay measurement, waiting for the human-computer interaction module lock indicator light up before disconnecting the satellite antenna, if the lock indicator light goes out and the timekeeping indicator light up after the satellite antenna is disconnected, then the internal time moment value is provided by the crystal oscillator.

[0007] Based on the first aspect, if the second location sends data to the first location, the network delay from the second location to the first location is measured.

[0008] In a second aspect, the present invention provides a device for measuring network delay using a message timestamp, which is used to implement any one of the above methods for measuring network delay using a message timestamp, including an L63111 circuit, a PLL phase-locked loop circuit, an FPGA processing circuit, an HPM6750 control circuit, a timekeeping circuit, a receiver and a power conversion circuit; The power conversion circuit includes an AC / DC power module and several DC-DCs and LDOs. The AC / DC power module is used to convert the external input 220V / 50hz alternating current into a DC12V voltage. The DC-DC is used to convert the voltage into the corresponding voltage according to the demand. The LDO is used to power the devices with high power accuracy and ripple requirements. The device outputs time information TOD to the HPM6750 control circuit through the receiver, and outputs 1PPS to the timekeeping and FPGA processing circuits. The timekeeping circuit includes a crystal oscillator circuit, which includes a GD32 series single-chip microcomputer, a voltage-controlled crystal oscillator and a TDC measurement circuit. When a valid 1PPS signal is input, the TDC measurement function will be triggered. TDC calculates the difference by comparing the 1PPS output by the crystal oscillator with the external valid 1PPS, and then feeds it back to the single-chip microcomputer. The single-chip microcomputer controls the voltage of the crystal oscillator according to the difference to achieve the purpose of taming the crystal oscillator. At the same time, the crystal oscillator will also output a 10M sine wave to the PLL circuit. The phase-locked loop chip will output different models to other modules according to the configuration information; The FPGA circuit receives and processes the 1PPS from the crystal oscillator and the receiver, and removes the 1PPS synchronization signal to each module. The XL63111 circuit is used to record and output the message information of the first network port and the second network port, send the message of the first network port to the HPM6750 control circuit in a mirroring manner, and send the received message of the HPM6750 control circuit to the second network port. When the HPM6750 control circuit receives the message of the XL63111 circuit, it will perform a timestamp determination on it. If the message does not contain a timestamp, a timestamp will be added to the message and then sent back to the XL63111 circuit. If there is a timestamp, the message will be divided into two parts, one part is the timestamp part and the other part is the original message part. The original message will be sent back to XL63111, and HPM6750 will process the remaining timestamp part, calculate the time information and compare it with the device time to calculate the time difference. This time difference is the network delay between the first location and the second location. After the network delay is calculated, it will be synchronized to the human-computer interaction module and output through the third network port.

[0009] The beneficial effects of the present invention are: 1) The network delay can be measured in real time through two timestamp processing devices, and the high-precision delay can be calculated using the time provided by the timing receiver; after being tamed by the crystal oscillator, it can be measured in most cases without being affected by the outside world. The calculated network delay has a small error and is real-time, so it can be applied to some environments with high requirements for network delay.

[0010] 2) Using the PLL phase-locked loop output frequency can reduce the error caused by inaccurate working frequency; using the XL63111 switching chip can simultaneously perform receiving timestamps and sending timestamps; the network delay can be observed in real time through the human-computer interaction module of the device. BRIEF DESCRIPTION OF THE DRAWINGS

[0011] Figure 1 A schematic flow chart of a method for measuring network delay using message timestamps according to an embodiment of the present invention; Figure 2 A schematic diagram of measuring network delay according to an embodiment of the present invention; Figure 3 An internal block diagram of a device for measuring network delay using a message timestamp according to an embodiment of the present invention; Figure 4 This is a diagram showing the long-distance relative synchronization accuracy test results of the high-precision navigation clock frequency module according to an embodiment of the present invention; Figure 5 This is a statistical chart of network delay test according to an embodiment of the present invention. DETAILED DESCRIPTION

[0012] The technical solution of the present invention will be clearly and completely described below in conjunction with the embodiments. Obviously, the described embodiments are only part of the embodiments of the present invention, rather than all of the embodiments. Based on the embodiments of the present invention, all other embodiments obtained by those skilled in the art without creative work are within the scope of protection of the present invention.

[0013] The present invention provides a method for measuring network delay using message timestamps, the flow chart of which is as follows: Figure 1 As shown, the following steps are included: S1. At a first location, connect a first device under test (device under test A) with a first network port of a first test device (device A) through a network cable, then connect a second network port of the first test device with a first network port of a second test device (device B), and connect a second network port of the second test device with a second device under test at a second location; S2. After the first device under test at the first location communicates normally with the second device under test (device B) at the second location, the first test device at the first location will detect the first network port. If there is data input on the first network port, the first test device will add a timestamp to the message through the processing unit inside the device, and then send it out from the second network port. S3. When the second network port of the second test device at the second location recognizes the data input, the second test device automatically packages the input data and sends it to the processing unit. After receiving the data, the processing unit automatically reads the timestamp and removes the timestamp. Then the processing unit converts the timestamp into time information, compares it with the internal time, calculates the difference between the two times, and sends it through the third network port of the second test device, or directly observes the network delay from the first location to the second location through the human-computer interaction module of the device. By adding a timestamp to each frame of the data packet at the sending end and then adding a timestamp at the receiving end, and by calculating the time difference between the timestamps at the receiving end and the sending end, it ensures that the network delay of each frame of the data packet can be accurately calculated, with high real-time and accuracy.

[0014] Exemplarily, step S1 also includes: placing the antennas at the first location and the second location in an open area, connecting the satellite signal to the first test device and the second test device respectively using antenna feeders, waiting for the display screen of the human-computer interaction module to show that the satellite time signal is valid, starting the network delay measurement, and waiting for the lock indicator light of the human-computer interaction module to light up before disconnecting the satellite antenna. If the lock indicator light goes out and the timekeeping indicator light up after disconnecting the satellite antenna, the internal time value is provided by the crystal oscillator. If the second location sends data to the first location, the network delay from the second location to the first location is measured. The schematic diagram of measuring the network delay is shown in FIG. Figure 2 Shown The present invention also provides a device for measuring network delay using message timestamps, the structural diagram of which is shown in FIG. Figure 3 As shown, it includes L63111 circuit, PLL phase-locked loop circuit, FPGA processing circuit, HPM6750 control circuit, timekeeping circuit, receiver and power conversion circuit; Specifically, the power conversion circuit includes an AC / DC power module and several DC-DCs and LDOs. The AC / DC power module is used to convert the external input 220V / 50hz alternating current into a DC12V voltage. The DC-DC is used to convert it into the corresponding voltage according to demand, such as 3.3V, 1.8V of FPGA, 2.5V of PHY, etc. The LDO is used to power devices with high power accuracy and ripple requirements, such as PLL, crystal oscillator, etc.

[0015] Specifically, the device outputs time information TOD to the HPM6750 control circuit through the receiver, and outputs 1PPS to the crystal oscillator circuit and FPGA processing circuit. The crystal oscillator circuit includes a GD32 series single-chip microcomputer, a voltage-controlled crystal oscillator and a TDC measurement circuit. When a valid 1PPS signal is input, the TDC measurement function will be triggered. The TDC calculates the difference by comparing the 1PPS output by the crystal oscillator with the external valid 1PPS, and then feeds it back to the single-chip microcomputer. The single-chip microcomputer controls the voltage of the crystal oscillator according to the difference to achieve the purpose of taming the crystal oscillator. At the same time, the crystal oscillator will also output a 10M sine wave to the PLL circuit. The phase-locked loop chip will output different models to other modules according to the configuration information. For example, the use of the NCS23345 phase-locked loop chip can support the simultaneous output of differential clock signals and LVTTL clock signals.

[0016] Specifically, the FPGA circuit receives and processes the 1PPS of the crystal oscillator and the receiver, and deletes the 1PPS synchronization signal to each module. The XL63111 circuit is used to record and output the message information of the first network port and the second network port, and sends the message of the first network port to the HPM6750 control circuit in a mirroring manner, and receives the message from the HPM6750 control circuit and sends it to the second network port. When the HPM6750 control circuit receives the message from the XL63111 circuit, it will perform a timestamp judgment on it. If the message contains If there is no timestamp, a timestamp will be added to the message and then sent back to the XL63111 circuit. If there is a timestamp, the message will be divided into two parts, one is the timestamp part and the other is the original message part. The original message will be sent back to XL63111. HPM6750 will process the remaining timestamp part, solve the time information and compare it with the device time to calculate the time difference. This time difference is the network delay between the first location and the second location. After the network delay is calculated, it will be synchronized to the human-computer interaction module and output through the third network port. The network delay test statistics are as follows Figure 4As shown, T1 represents the timestamp of the time when the message is sent, T2 represents the timestamp after the message is received, and offset ns represents the actual transmission delay unit ns.

[0017] Specifically, to ensure the accuracy of the timestamp, a PLL chip is used to simultaneously fan out multiple signals of different frequencies for use by each processing unit. In addition, in order to minimize the error of network delay measurement caused by its own factors, an XL63111 switching chip produced by Xiongli is also used. The switching function of the XL63111 chip is used to add a timestamp to the data in data transmission device A, and then the timestamp added by device A is read and deleted in device B. After device B reads the timestamp of device A, it is transmitted to the computing unit of device B to calculate the delay from the first location to the second location. Conversely, the delay from the second location to the first location can be measured. Considering that there may be differences in the timestamps of the two devices, the timing module and the timekeeping module are integrated inside device A and device B. The time is calculated by using the timing receiver and antenna to receive the timing satellite signal in space, and the time accuracy can reach 5ns. At the same time, the 1PPS second pulse output by the receiver is used to tame the crystal oscillator of the timekeeping module. After taming, the crystal oscillator can maintain the time accuracy of the us level for a long time. Combined with the time information inside the timing module, the measurement work can be continued during the interruption of the satellite signal. Considering that some messages may be very large, which requires a high computing speed of the processing unit, device A and device B also use an HPM6750 chip as the CPU of the computing unit. HPM6750 is a dual-core processor with a RISC-V architecture. The main frequency of 800M is sufficient to meet the processing of message timestamps in most cases, and can ensure that the measured delay is at the us level. The human-computer interaction module installed on the front panel of device A and device B allows users to set parameters and read real-time delays. The human-computer interaction module includes a display screen, a power indicator, a lock indicator, a timekeeping indicator, a 1PPS indicator, and a small keyboard. The result diagram of the present invention performing 100,000 message tests at a 100M network speed is shown in FIG. Figure 5 shown.

[0018] The above is only a preferred embodiment of the present invention. It should be understood that the present invention is not limited to the form disclosed herein, and should not be regarded as excluding other embodiments, but can be used in various other combinations, modifications and environments, and can be modified within the scope of the concept described herein through the above teachings or the technology or knowledge of the relevant field. The changes and modifications made by those skilled in the art shall not deviate from the spirit and scope of the present invention, and shall be within the scope of protection of the claims attached to the present invention.

Claims

1. A method for measuring network delay using message timestamps, characterized in that: The following steps are involved: S1. At a first location, connect a first device under test to a first network port of a first test device through a network cable, then connect a second network port of the first test device to a first network port of a second test device, and connect a second network port of the second test device to a second device under test at a second location; S2. After the first device under test at the first location communicates normally with the second device under test at the second location, the first test device will detect its first network port. If there is data input on the first network port, the first test device will add a timestamp to the message through the processing unit inside the device, and then send it out from the second network port. S3. When the second network port of the second test device recognizes the data input, the second test device automatically packages the input data and sends it to the processing unit. After receiving the data, the processing unit automatically reads the timestamp and removes the timestamp. The processing unit then converts the timestamp into time information, compares it with the internal time, calculates the difference between the two times, and sends it through the third network port of the second test device, or directly observes the network delay from the first location to the second location through the human-computer interaction module of the device.

2. A method for measuring network delay using message timestamp according to claim 1, characterized in that: The step S1 also includes: placing the antennas at the first location and the second location in an open area, connecting the satellite signals to the first test device and the second test device respectively using antenna feeders, waiting for the display screen of the human-computer interaction module to show that the satellite time signal is valid, starting the network delay measurement, and disconnecting the satellite antenna after the locking indicator light of the human-computer interaction module is on. If the locking indicator light goes out and the timekeeping indicator light comes on after the satellite antenna is disconnected, the internal time value is provided by the crystal oscillator.

3. The method for measuring network delay using message timestamp according to claim 1, characterized in that: If the second location sends data to the first location, the network delay from the second location to the first location is measured.

4. A device for measuring network delay using a message timestamp, used to implement a method for measuring network delay using a message timestamp according to any one of claims 1 to 3, characterized in that: It includes XL63111 circuit, PLL phase-locked loop circuit, FPGA processing circuit, HPM6750 control circuit, timekeeping circuit, receiver and power conversion circuit; The power conversion circuit includes an AC / DC power module and several DC-DCs and LDOs. The AC / DC power module is used to convert the external input 220V / 50hz alternating current into a DC12V voltage. The DC-DC is used to convert the voltage into the corresponding voltage according to the demand. The LDO is used to power the devices with high power accuracy and ripple requirements. The device outputs time information TOD to the HPM6750 control circuit through the receiver, and outputs 1PPS to the timekeeping and FPGA processing circuits. The timekeeping circuit includes a crystal oscillator circuit, which includes a GD32 series single-chip microcomputer, a voltage-controlled crystal oscillator and a TDC measurement circuit. When a valid 1PPS signal is input, the TDC measurement function will be triggered. The TDC calculates the difference by comparing the 1PPS output by the crystal oscillator with the external valid 1PPS, and then feeds it back to the single-chip microcomputer. The single-chip microcomputer controls the voltage of the crystal oscillator according to the difference to achieve the purpose of taming the crystal oscillator. At the same time, the crystal oscillator will also output a 10M sine wave to the PLL circuit. The phase-locked loop chip will output different models to other modules according to the configuration information; The FPGA circuit receives and processes the 1PPS from the crystal oscillator and the receiver, and removes the 1PPS synchronization signal to each module. The XL63111 circuit is used to record and output the message information of the first network port and the second network port, send the message of the first network port to the HPM6750 control circuit in a mirroring manner, and send the received message of the HPM6750 control circuit to the second network port. When the HPM6750 control circuit receives the message of the XL63111 circuit, it will perform a timestamp determination on it. If the message does not contain a timestamp, a timestamp will be added to the message and then sent back to the XL63111 circuit. If there is a timestamp, the message will be divided into two parts, one part is the timestamp part and the other part is the original message part. The original message will be sent back to XL63111, and HPM6750 will process the remaining timestamp part, calculate the time information and compare it with the device time to calculate the time difference. This time difference is the network delay between the first location and the second location. After the network delay is calculated, it will be synchronized to the human-computer interaction module and output through the third network port.

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