A dynamic load balancing message transceiving scheduling method and system

Abstract

The application relates to the technical field of load balancing scheduling, and discloses a dynamic load balancing message sending and receiving scheduling method and system. The method comprises the following steps: initializing and creating a sending end processing core structure body array and a receiving end processing core structure body array; randomly allocating messages of the sending end and / or the receiving end to corresponding processing cores, and recording the number of the randomly allocated processing cores in corresponding array nodes; judging whether the randomly allocated processing cores are idle, judging whether the number of the processing cores in the array nodes needs to be changed based on whether the randomly allocated processing cores are idle, and finally executing a packet sending or receiving task by using the core corresponding to the number of the core recorded in the data node. The application judges whether the processing core is idle to determine whether the processing core is used for the packet sending or receiving task. When the number of links is less than the number of cores, all the cores can be fully utilized; when the number of links is greater than the number of cores, load balancing can still be achieved, and the overall utilization rate of the processing core resources is improved.

Description

TECHNICAL FIELD

[0001] The present application relates to the technical field of load balancing scheduling, in particular to a dynamic load balancing message transceiving scheduling method and system. BACKGROUND

[0002] The core number of the packet sending end and the packet receiving end of the existing processor is limited. In the actual application scenario, the upper limit of the number of links established on the link may be in the order of millions. In order to ensure high-performance message transceiving, the packet sending process of a link of the packet sending end is allocated to a core, and the packet of a link of the packet receiving end is also allocated to the same core for processing. In this way, the order can be preserved and the pressure can be evenly distributed to each core. Since the scheduling position is fixed, when the number of links established by the packet sending end and the packet receiving end is less than the number of available processing cores, some processing cores are idle. At the same time, since only the middle part of the processing process of each message needs to preserve the order, the processing efficiency of load scheduling is not high, and the system processing resources are wasted. SUMMARY

[0003] Therefore, the present application provides a dynamic load balancing message transceiving scheduling method and system, which solves the problem of how to optimize load balancing scheduling and improve the overall utilization of processing core resources. When the number of links is less than the number of processing cores, all processing cores can be fully utilized. When the number of links is greater than the number of processing cores, load balancing can still be achieved.

[0004] In a first aspect, the present application provides a dynamic load balancing message transceiving scheduling method, which comprises:

[0005] Initializing to create a packet sending end processing core structure array and a packet receiving end processing core structure array;

[0006] Randomly allocating the messages of the packet sending end and / or the packet receiving end to the corresponding processing cores, and recording the number of the randomly allocated processing cores in the corresponding array nodes;

[0007] Judging whether the randomly allocated processing cores are idle, and based on whether the randomly allocated processing cores are idle, judging whether the number of the processing cores in the array nodes needs to be changed, and finally using the core corresponding to the number of the core recorded in the data node to perform the packet sending or packet receiving task.

[0008] The dynamic load balancing message transceiving scheduling method provided by the embodiment of the application can determine whether to use a processing core to send or receive a message by judging whether the processing core is idle, so that the processing core is allocated work only when it has the ability to process a new task, avoiding the allocation of a task to a busy processing core, thereby improving the overall utilization rate of the processing core resources. If the idle state of the processing core is not considered, the task may be accumulated on the busy processing core, and the idle processing core has no task to do. This not only causes the task processing delay, but also wastes the computing power of the idle processing core. The allocation method based on the idle state can effectively avoid the resource waste, so that each processing core can play a role at the appropriate time, so that all the processing cores can be fully utilized when the number of links is less than the number of processing cores, and load balancing can still be achieved when the number of links is greater than the number of processing cores, thereby improving the overall utilization rate of the processing core resources.

[0009] In an optional embodiment, the initialization of the sending-end processing core structure array and the receiving-end structure array comprises:

[0010] The available processing cores are divided into a sending-end processing core and a receiving-end processing core number range.

[0011] Based on the divided processing core number range, a sending-end structure array and a receiving-end processing core structure array are respectively initialized and constructed, and each array node contains a core number variable, and the initial value of the variable is equal to the array number.

[0012] The embodiment of the application can clearly define the role of each processing core in the data transmission task by explicitly dividing the number range of the sending-end processing core and the receiving-end processing core, which helps to avoid task confusion between the processing cores and improve the efficiency of overall task execution. Since the sending-end and receiving-end processing cores have their own independent structure arrays for management, parallel processing can be better achieved when performing tasks. The sending-end processing core can simultaneously perform multiple data sending preparation work, and the receiving-end processing core can also receive and process multiple data in parallel, fully utilizing the parallel processing capability of the multi-core processor and further improving the processing speed and efficiency of the system.

[0013] In an optional embodiment, the random allocation of the sending-end and / or receiving-end message to the corresponding processing core comprises:

[0014] The message link information of the sending-end and / or receiving-end is extracted, and a hash value is calculated based on the link information by using a preset hash algorithm; and the hash value or a value obtained by performing a preset algorithm on the hash value is used as the number corresponding to the randomly allocated processing core.

[0015] The embodiment of the present application can determine the processing core number by processing the message link information through a hash algorithm, so that different messages can be evenly distributed to each processing core. Because the hash function has good hash characteristics, different hash values will be generated for different link information, which can be mapped to different processing core numbers after processing, avoiding the situation that tasks are concentrated on a few processing cores, thereby achieving load balancing among processing cores. With the continuous change of message link information, the hash algorithm can automatically redistribute tasks to processing cores according to new information. When new links appear or the traffic of old links changes, the calculated hash values will also change accordingly, so that the task allocation of the processing core can dynamically adapt to such load changes and maintain a state of load balancing.

[0016] In an optional embodiment, whether the processing core based on random allocation is idle is judged to determine whether the number of the processing core in the array node needs to be changed, including:

[0017] Judging whether the processing core based on random allocation is idle;

[0018] If the processing core based on random allocation is in an idle state, the packet sending or receiving task is scheduled to the corresponding processing core;

[0019] If the processing core based on random allocation is in an occupied state, the next idle processing core is searched in the order of the array number, and the number of the idle processing core is updated to the corresponding array node. If all the processing cores are occupied, the number of the processing core in the array node remains unchanged.

[0020] The scheduling mode provided by the embodiment of the present application can quickly allocate tasks to idle processing cores, so that the processing core resources can be fully utilized. When there is a new packet sending or receiving task, the task can be immediately scheduled as long as there is an idle processing core, and the situation that the processing core is idle while the task is waiting will not occur, thereby improving the resource utilization of the whole system. By searching for the idle processing core in the order of the array number, the system can automatically dynamically allocate tasks according to the load of the processing core. When some processing cores are heavily loaded and other processing cores are idle, the new task will be preferentially allocated to the idle processing core, thereby achieving load balancing among the processing cores to a certain extent. If a processing core fails or is in a high load state for a long time, the system can continue to process the task by searching for other idle processing cores. This mechanism increases the fault tolerance of the system, so that the system can still normally perform the packet sending and receiving operation in the face of processing core abnormalities.

[0021] In a second aspect, the present application provides a dynamic load balancing message sending and receiving scheduling system, including:

[0022] a structure array construction module, configured to initialize creation of a sending-end processing core structure array and a receiving-end processing core structure array;

[0023] a processing core random allocation module, configured to randomly allocate messages of the sending end and / or the receiving end to corresponding processing cores, and record numbers of the randomly allocated processing cores in corresponding array nodes;

[0024] a scheduling module, configured to judge whether the randomly allocated processing cores are idle, and based on whether the randomly allocated processing cores are idle, judge whether it is necessary to change the numbers of the processing cores in the array nodes, and finally execute a sending packet or a receiving packet task by using a core corresponding to the number of the core recorded in the data node.

[0025] In an optional implementation, the structure array construction module comprises:

[0026] a processing core number division unit, configured to divide the available processing cores into a sending-end processing core number range and a receiving-end processing core number range;

[0027] a construction and initialization structure unit, configured to initialize construction of the sending-end processing core structure array and the receiving-end processing core structure array based on the divided processing core number ranges, and each array node contains a core number variable, and an initial value of the variable is equal to an array number.

[0028] In an optional implementation, the scheduling module comprises:

[0029] an idle state judgment unit, configured to judge whether the randomly allocated processing cores are idle;

[0030] a task scheduling unit, configured to if the randomly allocated processing cores are in an idle state, schedule a sending packet or a receiving packet task to a corresponding processing core, and if the randomly allocated processing cores are in an occupied state, traverse a next idle processing core in a number order of the array, and update a number of the idle processing core to a corresponding array node, and if all the processing cores are occupied, the number of the processing core in the array node is unchanged.

[0031] In a third aspect, the present application provides a computer device, comprising a memory and a processor, the memory and the processor are in communication connection with each other, the memory stores computer instructions, and the processor executes the computer instructions, thereby executing the dynamic load balancing packet transceiving scheduling method in the first aspect or any of the corresponding embodiments thereof.

[0032] In a fourth aspect, the present application provides a computer readable storage medium, the computer readable storage medium stores computer instructions, and the computer instructions are used to make a computer execute the dynamic load balancing packet transceiving scheduling method in the first aspect or any of the corresponding embodiments thereof.

[0033] In a fifth aspect, the present application provides a computer program product comprising computer instructions for causing a computer to perform the dynamic load balancing packet transceiving scheduling method according to the first aspect or any of the corresponding embodiments thereof. BRIEF DESCRIPTION OF DRAWINGS

[0034] In order to more clearly illustrate the specific embodiments of the present application or the technical solutions in the prior art, the following will briefly introduce the drawings needed to be used in the specific embodiments or prior art description. Obviously, the drawings described below are some embodiments of the present application, and for those skilled in the art, other drawings can also be obtained without creative labor on the basis of these drawings.

[0035] Figure 1 The schematic diagram for the part code of the linked packet sending process and the packet receiving process which needs to be ordered;

[0036] Figure 2 The flowchart of the dynamic load balancing packet transceiving scheduling method according to the embodiment of the present application;

[0037] Figure 3 The flowchart of another dynamic load balancing packet transceiving scheduling method according to the embodiment of the present application;

[0038] Figure 4 The flowchart of the dynamic load balancing packet transceiving scheduling process according to a specific example of the embodiment of the present application;

[0039] Figure 5 The dynamic load balancing packet transceiving scheduling process according to a specific example of the embodiment of the present application;

[0040] Figure 6 The structural block diagram of the dynamic load balancing packet transceiving scheduling system according to the embodiment of the present application;

[0041] Figure 7 The hardware structure schematic diagram of the computer device according to the embodiment of the present application. DETAILED DESCRIPTION

[0042] In order to make the purpose, technical solutions and advantages of the embodiments of the present application clearer, the technical solutions in the embodiments of the present application will be described clearly and completely below with reference to the drawings in the embodiments of the present application. Obviously, the described embodiments are some embodiments of the present application, but not all the embodiments. Based on the embodiments in the present application, all the other embodiments obtained by those skilled in the art without creative labor are within the protection scope of the present application.

[0043] The message in a link needs to be received and processed in order at the receiving end, such as a RoCE message (a network packet used to implement remote direct memory access (RDMA) in an Ethernet environment), which needs to be processed in order according to the packet sequence number (PSN) (a field in the RoCE message used to check whether the RoCE message arrives at the receiving end in order and whether there is a packet loss), otherwise, it will be wrongly judged that the message is out of order or even lost in the network. Similarly, the sending end also needs to be processed in order, and the PSN sequence number is added according to the order, as shown in Figure 1 The sending process and the receiving process of a link generally do not need to be completely in order, only part of the code in the process needs to be executed in order, and this part of the code in order generally needs to be locked.

[0044] In actual application scenarios, the upper limit of the number of links established on a link may be in the order of millions. In order to ensure high-performance message receiving and sending, a hash method is often used, and the sending process of a link at the sending end is hashed to a core, and the message of a link at the receiving end is also hashed to the same core for processing, so that the order is preserved and the pressure is evenly distributed to each core. However, when the number of links established by the sending end and the receiving end is less than 16, some cores are idle, and at the same time, because only the middle part of the processing process of each message needs to be in order, all idle cores can be utilized to obtain greater receiving and sending flow (when the frequency of the core is lower, it is more obvious).

[0045] According to the embodiment of the present application, a dynamic load balancing message receiving and sending scheduling method embodiment is provided. It should be noted that the steps shown in the flowchart of the accompanying drawings can be executed in a computer system such as a set of computer executable instructions, and although the logical order is shown in the flowchart, in some cases, the steps shown or described can be executed in an order different from that shown here.

[0046] In this embodiment, a dynamic load balancing message receiving and sending scheduling method is provided, Figure 2 is a flowchart of the dynamic load balancing message receiving and sending scheduling method according to the embodiment of the present application, as shown in Figure 2 The flowchart includes the following steps:

[0047] S101, initialize to create a message sending end processing core structure array and a message receiving end processing core structure array.

[0048] For example, when the RDMA engine is initialized, a global structure array is constructed, and the initialization is completed. The number of global structure arrays is consistent with the number of available processing cores.

[0049] The embodiment of the application divides available processing cores into a sending-end processing core number range and a receiving-end processing core number range; based on the divided processing core number ranges, a sending-end structure array and a receiving-end processing core structure array are respectively initialized, each array node containing a core number variable, and the initial value of the variable being equal to the array number. For example, there are 16 available processing cores, core0-core7 are sending-end processing cores, and core8-core15 are receiving-end processing cores. By explicitly dividing the number ranges of the sending-end processing cores and the receiving-end processing cores, the role of each processing core in the data transmission task can be clearly defined, which helps to avoid task confusion among the processing cores and improves the efficiency of overall task execution. Since the sending-end processing cores and the receiving-end processing cores have their own independent structure arrays for management, parallel processing can be better implemented when executing tasks. The sending-end processing cores can simultaneously perform multiple data sending preparation work, and the receiving-end processing cores can also parallelly receive and process multiple data, fully utilizing the parallel processing capability of the multi-core processor and further improving the processing speed and efficiency of the system.

[0050] S102, randomly allocating the messages of the sending end and / or the receiving end to corresponding processing cores, and recording the number of the randomly allocated processing cores in the corresponding array nodes.

[0051] Specifically, for example, a random number generator can be used to allocate a processing core for each message. For example, in a system with n processing cores, for each message, a random integer between 0 and n-1 is generated, and this integer represents the number of the processing core to be allocated; or a weight is allocated to each processing core according to the performance (such as computing power, cache size, etc.) or current load of the processing core, and the greater the weight, the higher the probability of being selected. The above random allocation process is only an example and is not limited thereto. In actual application, reasonable settings are made according to specific circumstances.

[0052] S103, judging whether the randomly allocated processing core is idle, and based on whether the randomly allocated processing core is idle, judging whether the number of the processing core in the array node needs to be changed, and finally executing the packet sending or receiving task using the core corresponding to the core number recorded in the data node.

[0053] The embodiment of the present application can ensure that the processing core is assigned work only when it has the ability to process new tasks, avoid assigning tasks to the processing core that is already busy, and thus improve the overall utilization of the processing core resources. If the idle state of the processing core is not considered, the tasks may be accumulated on the busy processing core, while the idle processing core has no task to do. This not only causes the task processing delay, but also wastes the computing power of the idle processing core. The allocation method based on the idle state can effectively avoid the resource waste, so that each processing core can play a role at the appropriate time. In the case of processing core failure or performance decline, the allocation method based on the idle state can automatically reassign the task to other normal idle processing core. This enhances the fault tolerance of the system, so that the system can still work normally when part of the processing core is problematic.

[0054] In an embodiment, as shown in Figure 3 In the embodiment, a dynamic load balancing message transceiving scheduling method is provided, Figure 3 According to the embodiment of the present application, the flow chart of the dynamic load balancing message transceiving scheduling method is shown in Figure 3 The flow chart includes the following steps:

[0055] S201, initialize to create the sending end processing core structure array and the receiving end processing core structure array.

[0056] The specific data and parameters are described in the above description of step S101, and will not be repeated here.

[0057] S202, randomly assign the messages of the sending end and / or the receiving end to the corresponding processing core, and record the number of the randomly assigned processing core in the corresponding array node. Specifically, the following steps are included:

[0058] S2021, extract the message link information of the sending end and / or the receiving end, and calculate the hash value based on the link information using the preset hash algorithm;

[0059] S2022, use the hash value or the value obtained by processing the hash value with the preset algorithm as the number corresponding to the randomly assigned processing core.

[0060] Specifically, the sending end extracts from the context, and the receiving end extracts from the message. For example, the source IP, the destination IP, the source MAC, the destination MAC, the send PSN (the field that needs to be carried by the BTH header of the ROC protocol message, the order is incremented), the ACK PSN, and other link information are stored in the ROC link qp1 context. By extracting these link information and using a hash algorithm (which can be selected, such as MD5, SHA-1, and SHA-256), it is assumed that SHA-256 is selected as the preset hash algorithm to calculate the extracted link information. Sometimes, it is not appropriate to directly use the hash value as the processing core number, for example, the range of the hash value may be too large or too small, and does not match the actual number of processing cores. At this time, the hash value can be processed by some preset algorithm, such as the hash value modulo operation on the number of array nodes.

[0061] The embodiment of the application determines the processing core number by processing the message link information by a hash algorithm, which can make different messages evenly distributed to each processing core. Because the hash function has good hash characteristics, different hash values are usually generated for different link information. These hash values can be mapped to different processing core numbers after processing, which avoids the situation that tasks are concentrated on a few processing cores, thereby achieving load balancing among processing cores. With the continuous change of message link information, the hash algorithm can automatically redistribute tasks to processing cores according to new information. When new links appear or the traffic of old links changes, the calculated hash values will also change accordingly, so that the task allocation of the processing core can dynamically adapt to such load changes and maintain a state of load balancing.

[0062] S203, determining whether the randomly allocated processing core is idle, and determining whether the number of the processing core in the array node needs to be changed based on whether the randomly allocated processing core is idle, and finally using the core corresponding to the core number recorded in the data node to execute the sending or receiving task. Specifically, the following steps are included:

[0063] S2031, determining whether the randomly allocated processing core is idle;

[0064] S2032, if the randomly allocated processing core is in an idle state, scheduling the sending or receiving task to the corresponding processing core;

[0065] S2033, if the randomly allocated processing core is in an occupied state, traversing the next idle processing core in the order of the array number, and updating the number of the idle processing core to the corresponding array node. If all the processing cores are occupied, the number of the processing core in the array node remains unchanged.

[0066] This scheduling method quickly allocates tasks to idle processing cores, ensuring full utilization of processing core resources. When a new packet sending or receiving task arrives, it can be scheduled immediately as long as an idle processing core is available, preventing situations where processing cores are idle while tasks wait. This improves the overall system resource utilization. By traversing the array in sequence to find idle processing cores, the system can automatically and dynamically allocate tasks based on the load of the processing cores. When some processing cores are heavily loaded while others are idle, new tasks will be preferentially assigned to idle processing cores, thus achieving load balancing among processing cores to a certain extent. If a processing core fails or remains under high load for an extended period, the system can continue processing tasks by finding other idle processing cores. This mechanism increases the system's fault tolerance, enabling it to continue packet sending and receiving operations normally even when processing cores malfunction.

[0067] In one example, such as Figure 4 As shown, the core number n is determined based on the hash value calculation result. The core number n is then used to look up the structure array, and the core number m is obtained from the array node. It is then determined whether the core with number m is idle. If this core is occupied, the next idle core is found (e.g., using a bitmap to quickly find an idle core), and the number is updated in the array node and assigned to m. If all cores are currently occupied, the value of m remains unchanged, and the packet sending / receiving tasks are scheduled to the core corresponding to m. This ensures load balancing with a large number of connections and maximizes sending and receiving performance with a small number of connections. It solves the problem of underutilization of computing resources when the number of connections is small.

[0068] In an application scenario, the roce links can be a few or tens of thousands, and the problem of reasonably scheduling the messages of the roce links to the arm core is faced. If the correspondence between the link and the core id is recorded, a large amount of memory will be occupied, the roce implementation is on the network card, the resources are limited, and such lookup is very performance-consuming, so only packet-based scheduling can be performed. If the sequential scheduling mode is used, a large number of roce link locks will occur (when the messages of a link are divided into multiple cores for processing), and therefore the hash scheduling can better guarantee the performance. However, when the number of roce links is less than the number of cores, for example, there is only one roce link, the hash scheduling will only occupy one core, and the maximum performance of the single roce link cannot be exerted (the packet receiving and sending process only has a part of the fragment locked, so the performance is higher when multiple cores are run), and the scheduling method provided by the embodiment of the application can make up for the part of the scene missed by the hash scheduling. If the message is scheduled by using the sequential scheduling mode to make up for the scene in which the number of roce links is less than the number of cores, it is assumed that there are 48 cores and 12 roce links, and the sequential scheduling mode will result in that the messages of each roce link are scattered to the 48 cores, and the messages of each roce link are locked between the processing. The scheduling method provided by the embodiment of the application will be that each roce link only occupies a few cores, so that the capability of the 48 cores for processing the roce messages is maximized, and the degree of lock is greatly reduced, and the scene in which the number of roce links is less than the number of cores can be better made up. When the number of roce links is greater than the number of cores and the hash polarization is serious, the current application can still fully utilize the computing power of all cores, and maximize the performance of the roce message receiving and sending.

[0069] In a specific embodiment, as Figure 5As shown, for example, the ROCe link QP1 of the sending end includes nodes WQE1-WQE8, assuming that each node sends a packet and needs to partially preserve order, each core has its own PC register, and when no packet is sent, PC==default, after receiving the packet sending instruction, PC is assigned to A, and after executing to B, the current packet sending is completed, and PC is assigned to default again. The action for preserving order for the code section that needs to preserve order is: when WQE1 arrives, the send PSN is taken from the QP1 context and filled into the packet, and then the add 1 write-back action is performed on the send PSN in the QP1 context; WQE2 executes to this code section and also needs to read the send PSN and perform a series of actions, and WQE3-WQE8 are the same. Locking the order preserving section mainly has the effect of fault tolerance, preventing the write-back action from being too long (which does not involve outside this section), causing WQE1 to arrive at this position before WQE2-WQE8. Since each core uses the same execution code and the same core execution frequency, the WQE m execution position will not exceed the WQE n execution position (m>n), so the order preservation can still be achieved, and the computing resources are also fully utilized.

[0070] In the embodiment, a dynamic load balancing message sending and receiving scheduling system is also provided, which is used to implement the above-mentioned embodiments and preferred embodiments, and will not be described again. As used below, the term "module" can be a combination of software and / or hardware that implements a predetermined function. Although the system described in the following embodiments is preferably implemented in software, hardware, or a combination of software and hardware is also possible and is contemplated.

[0071] The embodiment provides a dynamic load balancing message sending and receiving scheduling system, as shown by Figure 6 The system comprises:

[0072] The structure array construction module 601 is configured to initialize and create a sending end processing core structure array and a receiving end processing core structure array.

[0073] The processing core random allocation module 602 is configured to randomly allocate messages of the sending end and / or the receiving end to corresponding processing cores, and record the numbers of the randomly allocated processing cores in corresponding array nodes.

[0074] The scheduling module 603 is configured to judge whether the randomly allocated processing cores are idle, and based on whether the randomly allocated processing cores are idle, judge whether the numbers of the processing cores in the array nodes need to be changed, and finally use the numbers of the cores recorded in the data nodes to execute packet sending or receiving tasks.

[0075] In some optional embodiments, the structure array construction module 601 comprises:

[0076] The processing core number division unit is configured to divide the available processing cores into a sending-end processing core number range and a receiving-end processing core number range.

[0077] The structure body construction and initialization unit is configured to initialize a sending-end structure body array and a receiving-end processing core structure body array based on the divided processing core number ranges, and each array node contains a variable of a core number and an initial value of the variable equaling to an array number.

[0078] In some optional embodiments, the processing core random allocation module 602 comprises:

[0079] The hash value calculation unit is configured to extract message link information of the sending end and / or the receiving end, and calculate a hash value based on the link information by using a preset hash algorithm.

[0080] The random allocation unit is configured to use the hash value or a value obtained by performing a preset algorithm on the hash value as a number corresponding to the randomly allocated processing core.

[0081] In some optional embodiments, the scheduling module 603 comprises:

[0082] The idle state judgment unit is configured to judge whether the processing core allocated randomly is idle.

[0083] The task scheduling unit is configured to schedule a sending or receiving task to the corresponding processing core if the processing core allocated randomly is in an idle state, and to traverse a next idle processing core in a number order of the array and update the number of the idle processing core to the corresponding array node if the processing core allocated randomly is in an occupied state, and the number of the processing core in the array node is unchanged if all the processing cores are occupied.

[0084] Further function descriptions of the above-mentioned modules and units are the same as those of the corresponding embodiments, and will not be repeated here.

[0085] The dynamic load balancing message sending and receiving scheduling system in the embodiment is presented in the form of functional units, and the units refer to ASIC (Application Specific Integrated Circuit, special-purpose integrated circuit) circuits, processors and memories executing one or more software or fixed programs, and / or other devices capable of providing the above-mentioned functions.

[0086] The embodiment of the application further provides a computer device with the above-mentioned Figure 6 dynamic load balancing message sending and receiving scheduling system.

[0087] Please refer to Figure 7 ,Figure 7 This is a schematic diagram of the structure of a computer device provided in an optional embodiment of the present invention, such as... Figure 7 As shown, the computer device includes one or more processors 10, memory 20, and interfaces for connecting the components, including high-speed interfaces and low-speed interfaces. The components communicate with each other via different buses and can be mounted on a common motherboard or otherwise installed as needed. The processors can process instructions executed within the computer device, including instructions stored in or on memory to display graphical information of a GUI on external input / output devices (such as display devices coupled to the interfaces). In some alternative implementations, multiple processors and / or multiple buses can be used with multiple memories and multiple memory modules, if desired. Similarly, multiple computer devices can be connected, each providing some of the necessary operations (e.g., as a server array, a group of blade servers, or a multiprocessor system). Figure 7 Take a processor 10 as an example.

[0088] Processor 10 may be a central processing unit, a network processor, or a combination thereof. Processor 10 may further include a hardware chip. The hardware chip may be an application-specific integrated circuit (ASIC), a programmable logic device (PLD), or a combination thereof. The programmable logic device may be a complex programmable logic device (CAMP), a field-programmable gate array (FPGA), a general-purpose array logic (GDA), or any combination thereof.

[0089] The memory 20 stores instructions executable by at least one processor 10 to cause at least one processor 10 to perform the method shown in the above embodiments.

[0090] The memory 20 may include a program storage area and a data storage area. The program storage area may store the operating system and applications required for at least one function; the data storage area may store data created based on the use of the computer device. Furthermore, the memory 20 may include high-speed random access memory and may also include non-transitory memory, such as at least one disk storage device, flash memory device, or other non-transitory solid-state storage device. In some alternative embodiments, the memory 20 may optionally include memory remotely located relative to the processor 10, and these remote memories may be connected to the computer device via a network. Examples of such networks include, but are not limited to, the Internet, intranets, local area networks, mobile communication networks, and combinations thereof.

[0091] The memory 20 may include volatile memory, such as random access memory; the memory may also include non-volatile memory, such as flash memory, hard disk or solid-state drive; the memory 20 may also include a combination of the above types of memory.

[0092] The computer device also comprises a communication interface 30 for communication of the computer device with other devices or communication networks.

[0093] The embodiments of the present application further provide a computer readable storage medium, and the method according to the embodiments of the present application can be implemented in hardware, firmware, or recorded in a storage medium, or stored in a remote storage medium or a non-transitory machine readable storage medium and downloaded from a network and stored in a local storage medium, so that the method described herein can be processed by such software on a storage medium using a general purpose computer, a special purpose processor, or programmable or special hardware. The storage medium can be a magnetic disk, an optical disk, a read-only memory, a random access memory, a flash memory, a hard disk, or a solid state disk, etc. Further, the storage medium can also include a combination of the above-mentioned memories. It can be understood that the computer, the processor, the microprocessor central control system, or the programmable hardware includes a storage component that can store or receive software or computer code, when the software or computer code is accessed and executed by the computer, the processor, or the hardware, the method shown in the above embodiments is implemented.

[0094] Part of the present application can be applied as a computer program product, for example, computer program instructions, when executed by a computer, through the operation of the computer, the method and / or technical solutions according to the present application can be called or provided. Those skilled in the art should understand that the form of computer program instructions in a computer readable medium includes but is not limited to source files, executable files, installation package files, etc. Correspondingly, the way of computer program instructions executed by computer includes but is not limited to: the computer directly executes the instructions, or the computer compiles the instructions and then executes the corresponding compiled program, or the computer reads and executes the instructions, or the computer reads and installs the instructions and then executes the corresponding installed program. Here, the computer readable medium can be any available computer readable storage medium or communication medium accessible to the computer.

[0095] Although the embodiments of the present application are described in conjunction with the accompanying drawings, various modifications and changes can be made by those skilled in the art without departing from the spirit and scope of the present application, and such modifications and changes fall within the scope defined by the appended claims.

Claims

1. A dynamic load balancing message sending and receiving scheduling method, characterized in that, include: Initialize and create the sending end processing core structure array and the receiving end processing core structure array, including: The available processing cores are divided into sending-end processing cores and receiving-end processing core number ranges; Based on the divided processing core number range, the sending end structure array and the receiving end processing core structure array are initialized and constructed respectively. Each array node contains a variable of core number, and the initial value of the variable is equal to the array number. The messages from the sending end and / or receiving end are randomly assigned to the corresponding processing cores, and the number of the randomly assigned processing core is recorded in the corresponding array node; Determine whether the randomly assigned processing core is idle, and based on whether the randomly assigned processing core is idle, determine whether it is necessary to change the number of the processing core in the array node, and finally use the core corresponding to the core number recorded in the data node to execute the packet sending or receiving task; the step of determining whether it is necessary to change the number of the processing core in the array node based on whether the randomly assigned processing core is idle includes: Determine if the randomly assigned processing core is idle; If the randomly assigned processing core is idle, the packet sending or receiving task will be scheduled to the corresponding processing core. If the randomly assigned processing core is occupied, the next free processing core is traversed in the array number order, and the number of the free processing core is updated to the corresponding array node. If all processing cores are occupied, the number of the processing core in the array node remains unchanged.

2. The method according to claim 1, characterized in that, The step of randomly assigning messages from the sending end and / or receiving end to the corresponding processing core includes: Extract message link information from the sending end and / or receiving end, and calculate hash value based on the link information using a preset hash algorithm; The hash value or the value obtained by processing the hash value using a preset algorithm is used as the number corresponding to the randomly assigned processing core.

3. A dynamic load balancing message sending and receiving scheduling system, characterized in that, include: The structure array construction module is used to initialize and create the sending end processing core structure array and the receiving end processing core structure array, including: The processing core numbering division unit is used to divide the available processing cores into the numbering ranges of the sending end processing core and the receiving end processing core; Construct and initialize structure units to initialize and construct the sending end structure array and the receiving end processing core structure array respectively based on the divided processing core number range. Each array node contains a variable of core number, and the initial value of the variable is equal to the array number. The processing core random allocation module is used to randomly allocate messages from the sending end and / or receiving end to the corresponding processing cores, and record the number of the randomly allocated processing core in the corresponding array node; A scheduling module is used to determine whether a randomly assigned processing core is idle, and based on whether the randomly assigned processing core is idle, to determine whether the number of the processing core in the array node needs to be changed, and finally uses the core corresponding to the core number recorded in the data node to execute the packet sending or receiving task; the scheduling module includes: The idle state determination unit is used to determine whether the processing cores based on random allocation are idle; The task scheduling unit is used to schedule packet sending or receiving tasks to the corresponding processing core if the randomly assigned processing core is in an idle state; if the randomly assigned processing core is in an occupied state, it traverses the next idle processing core in the array number order and updates the number of the idle processing core to the corresponding array node; if all processing cores are currently occupied, the number of the processing core in the array node remains unchanged.

4. A computer device, characterized in that, include: The system includes a memory and a processor, which are communicatively connected to each other. The memory stores computer instructions, and the processor executes the computer instructions to perform the dynamic load balancing message sending and receiving scheduling method according to any one of claims 1-2.

5. A computer-readable storage medium, characterized in that, The computer-readable storage medium stores computer instructions, which are used to cause the computer to execute the dynamic load balancing message sending and receiving scheduling method according to any one of claims 1-2.

6. A computer program product, characterized in that, Includes computer instructions, which are used to cause a computer to execute the dynamic load balancing message sending and receiving scheduling method according to any one of claims 1-2.

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