Video coding method and device

By introducing an inter-frame compression module in video encoding, the feature representations of video frames are aggregated, which solves the problem of too long and redundant token sequences when inputting long videos, and realizes efficient video encoding and computing resources optimization.

CN119728985AActive Publication Date: 2025-03-28HUAWEI TECH CO LTD +1
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Patent Information

Application Number
CN202311292413.7
Authority / Receiving Office
CN · China
Patent Type
Applications(China)
Current Assignee / Owner
Filing Date
2023-09-28
Publication Date
2025-03-28
Estimated Expiration
2043-09-28

AI Technical Summary

Technical Problem

Long videos are divided into a large number of visual tokens when inputting the Video Transformer model, resulting in the input token sequence length being too long and has great redundancy, which damages the efficiency of video encoding and is not conducive to the model learning key semantic information.

Method used

By introducing an inter-frame compression module, the feature representations of multiple video frames are aggregated, reducing the number of feature representations that the model needs to process, thereby reducing computing power overhead. The specific method includes fusing the feature representations of similar video frames, and accurately selecting the objects to be fused through a selection algorithm based on the importance of visual tokens and a selection algorithm based on geometric information.

Benefits of technology

While improving computing efficiency, it ensures the quality and effect of video encoding, reduces the computational burden of feature encoding, and effectively reduces the resource consumption of video-related tasks.

✦ Generated by Eureka AI based on patent content.

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Abstract

The video coding method comprises the following steps: acquiring a plurality of video frames; processing the plurality of video frames through an encoder to obtain an encoding result; wherein the encoder comprises a first network layer; the first network layer comprises an inter-frame compression module, the plurality of video frames comprise M first video frames and N second video frames, and the inter-frame compression module is used for fusing feature representations of the M first video frames to feature representations of the N second video frames to obtain N feature representations; and executing video-related tasks according to the coding result to obtain a processing result. Wherein the inter-frame compression module can aggregate the feature representations of similar video frames, so that the number of the feature representations needing to be processed by the model is reduced, and the computing power overhead of the model is further reduced.
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Description

Technical Field

[0001] The present application relates to the field of artificial intelligence, and in particular to a video encoding method and device thereof. Background Art

[0002] Artificial Intelligence (AI) is the theory, method, technology and application system that uses digital computers or machines controlled by digital computers to simulate, extend and expand human intelligence, perceive the environment, acquire knowledge and use knowledge to obtain the best results. In other words, artificial intelligence is a branch of computer science that attempts to understand the essence of intelligence and produce a new intelligent machine that can respond in a similar way to human intelligence. Artificial intelligence is to study the design principles and implementation methods of various intelligent machines so that machines have the functions of perception, reasoning and decision-making.

[0003] The Video Transformer model applies the original Transformer model to the video field, encoding video features by modeling temporal and spatial information, and then used for downstream video understanding tasks such as video-text retrieval, video description generation, video question answering, etc. The Video Transformer model effectively adapts to large-scale pre-training and has now become the basic model architecture for video understanding.

[0004] When a long video is input into the Video Transformer model, it is divided into a large number of visual tokens, resulting in an input token sequence that is too long and has high redundancy; this impairs the efficiency of video encoding and is not conducive to the model learning key semantic information. For example, for a 96-frame video with a resolution of 224x224 per frame, the commonly used Video Transformer model cuts each frame into 16x16 patches, which will result in up to (224 / 16)x(224 / 16)x96=19K visual tokens, which brings a huge computational burden to the subsequent feature encoding.

[0005] Therefore, there is an urgent need for a video encoding method with low computing power overhead. Summary of the invention

[0006] In a first aspect, the present application provides a video encoding method, the method comprising: obtaining multiple video frames; processing the multiple video frames through an encoder to obtain an encoding result; wherein the encoder comprises a first network layer; the first network layer comprises an inter-frame compression module, the multiple video frames comprise M first video frames and N second video frames, the inter-frame compression module is used to fuse feature representations of the M first video frames into feature representations of the N second video frames to obtain N feature representations; according to the encoding result, perform video-related tasks to obtain a processing result.

[0007] Among them, the inter-frame compression module can aggregate the feature representations of similar video frames, thereby reducing the number of feature representations that the model needs to process, thereby reducing the computing power overhead of the model.

[0008] In a possible implementation, the video-related task is video retrieval, video question answering, or video description generation.

[0009] In a possible implementation, fusing the feature representations of the M first video frames into the feature representations of the N second video frames includes: fusing the feature representation of each first video frame in the M first video frames into the feature representation of the second video frame that is most similar to the N second video frames.

[0010] Among them, the inter-frame compression module can aggregate the feature representations of similar video frames, thereby reducing the number of feature representations that the model needs to process. By aggregating similar video frames, the embodiment of the present application ensures that important timing information in the video is fully preserved. Therefore, the method of the embodiment of the present application can still ensure the quality and effect of video encoding while improving the computational efficiency.

[0011] In a possible implementation, the M first video frames are M video frames having the lowest correlation with other video frames among the multiple video frames.

[0012] Regarding the selection of objects that need to be fused (for example, M first video frames), the embodiment of the present application proposes a selection algorithm based on the importance of visual tokens. By evaluating and ranking the importance of each token, tokens with higher importance are selected as representative tokens.

[0013] In a possible implementation, the first video frame and the second video frame are interlaced with each other in the multiple video frames.

[0014] The embodiment of the present application proposes a selection algorithm based on visual token geometric information, which selects tokens with reasonable spatial distribution as representative tokens by considering the position and distribution of tokens in space. The introduction of these selection algorithms makes the aggregation process more accurate and efficient, ensuring the quality and accuracy of the aggregation results.

[0015] In a possible implementation, the fusion is average pooling.

[0016] In a possible implementation, the encoder includes a second network layer; the first network layer and the second network layer are the same or different network layers, the second network layer includes an intra-frame compression module, the multiple video frames include a third video frame, the third video frame includes X first image blocks and Y second image blocks, and the intra-frame compression module is used to fuse feature representations of the X first image blocks into feature representations of the Y second image blocks to obtain Y feature representations.

[0017] Among them, the intra-frame compression module can aggregate the feature representations of similar image blocks, thereby reducing the number of feature representations that the model needs to process, thereby reducing the computing power overhead of the model.

[0018] In a possible implementation, fusing the feature representations of the X first image blocks into the feature representations of the Y second image blocks includes:

[0019] The feature representation of each first image block in the X first image blocks is fused to the feature representation of the second image block that is most similar to the Y second image blocks.

[0020] Among them, the inter-frame compression module can aggregate the feature representations of similar video frames, thereby reducing the number of feature representations that the model needs to process. By aggregating similar video frames, the embodiment of the present application ensures that important timing information in the video is fully preserved. Therefore, the method of the embodiment of the present application can still ensure the quality and effect of video encoding while improving the computational efficiency.

[0021] In a possible implementation, the X first image blocks are X image blocks having the lowest correlation with other image blocks among a plurality of image blocks included in the third video frame.

[0022] In a possible implementation, the first image block and the second image block are interlaced with each other in the third video frame.

[0023] In a second aspect, the present application provides a video encoding device, the device comprising:

[0024] An acquisition module, used for acquiring multiple video frames;

[0025] A processing module, configured to process the plurality of video frames through an encoder to obtain an encoding result; wherein the encoder includes a first network layer; the first network layer includes an inter-frame compression module, the plurality of video frames include M first video frames and N second video frames, and the inter-frame compression module is configured to fuse feature representations of the M first video frames into feature representations of the N second video frames to obtain N feature representations;

[0026] According to the encoding result, video-related tasks are performed to obtain a processing result.

[0027] In a possible implementation, the video-related task is video retrieval, video question answering, or video description generation.

[0028] In a possible implementation, the processing module is specifically configured to:

[0029] The feature representation of each of the M first video frames is fused to the feature representation of the second video frame that is most similar to the N second video frames.

[0030] In a possible implementation, the M first video frames are M video frames having the lowest correlation with other video frames among the multiple video frames.

[0031] In a possible implementation, the first video frame and the second video frame are interlaced with each other in the multiple video frames.

[0032] In a possible implementation, the fusion is average pooling.

[0033] In a possible implementation, the encoder includes a second network layer; the first network layer and the second network layer are the same or different network layers, the second network layer includes an intra-frame compression module, the multiple video frames include a third video frame, the third video frame includes X first image blocks and Y second image blocks, and the intra-frame compression module is used to fuse feature representations of the X first image blocks into feature representations of the Y second image blocks to obtain Y feature representations.

[0034] In a possible implementation, the processing module is specifically configured to:

[0035] The feature representation of each first image block in the X first image blocks is fused to the feature representation of the second image block that is most similar to the Y second image blocks.

[0036] In a possible implementation, the X first image blocks are X image blocks having the lowest correlation with other image blocks among a plurality of image blocks included in the third video frame.

[0037] In a possible implementation, the first image block and the second image block are interlaced with each other in the third video frame.

[0038] In a third aspect, an embodiment of the present application provides a data processing device, which may include a memory, a processor, and a bus system, wherein the memory is used to store programs, and the processor is used to execute the programs in the memory to perform the first aspect and any optional method thereof.

[0039] In a fourth aspect, an embodiment of the present application provides a computer-readable storage medium, in which a computer program is stored. When the computer-readable storage medium is run on a computer, the computer executes the above-mentioned first aspect and any optional method thereof.

[0040] In a fifth aspect, an embodiment of the present application provides a computer program, which, when executed on a computer, enables the computer to execute the above-mentioned first aspect and any optional method thereof.

[0041] In a sixth aspect, the present application provides a chip system, which includes a processor for supporting the execution of a data processing device to implement the functions involved in the above aspects, such as sending or processing the data involved in the above methods; or information. In one possible design, the chip system also includes a memory, which is used to store program instructions and data necessary for the execution device or training device. The chip system can be composed of chips, or it can include chips and other discrete devices. BRIEF DESCRIPTION OF THE DRAWINGS

[0042] Figure 1A A structural diagram of the main framework of artificial intelligence;

[0043] Figure 1B Hezhi Figure 1C It is a schematic diagram of the application system framework of the present invention;

[0044] Figure 1D A schematic diagram of an optional hardware structure of a terminal;

[0045] Figure 2 A schematic diagram of the structure of a server;

[0046] Figure 3 A system architecture diagram of the present application is shown below;

[0047] Figure 4 A process for a cloud service;

[0048] Figure 5 A flowchart of a data processing method provided in an embodiment of the present application;

[0049] Figure 6 A schematic diagram of a network structure of this application;

[0050] Figure 7 A flowchart of a data processing method provided in an embodiment of the present application;

[0051] Figure 8 A schematic diagram of a fusion method for this application;

[0052] Fig.9A A schematic diagram of a pre-training method for this application;

[0053] Fig. 9B A schematic diagram of a beneficial effect of the present application;

[0054] Fig.10 A schematic diagram of the structure of a data processing device provided in an embodiment of the present application;

[0055] Fig.11 A schematic diagram of the structure of an execution device provided in an embodiment of the present application;

[0056] Fig.12 A schematic diagram of the structure of a training device provided in an embodiment of the present application;

[0057] Fig.13 A schematic diagram of the structure of a chip provided in an embodiment of the present application. DETAILED DESCRIPTION

[0058] The embodiments of the present invention are described below in conjunction with the accompanying drawings in the embodiments of the present invention. The terms used in the implementation mode of the present invention are only used to explain the specific embodiments of the present invention, and are not intended to limit the present invention.

[0059] The embodiments of the present application are described below in conjunction with the accompanying drawings. Those skilled in the art will appreciate that, with the development of technology and the emergence of new scenarios, the technical solutions provided in the embodiments of the present application are also applicable to similar technical problems.

[0060] The terms "first", "second", etc. in the specification and claims of the present application and the above-mentioned drawings are used to distinguish similar objects, and need not be used to describe a specific order or sequential order. It should be understood that the terms used in this way can be interchangeable under appropriate circumstances, which is only to describe the distinction mode adopted by the objects of the same attributes when describing in the embodiments of the present application. In addition, the terms "including" and "having" and any of their variations are intended to cover non-exclusive inclusions, so that the process, method, system, product or equipment comprising a series of units need not be limited to those units, but may include other units that are not clearly listed or inherent to these processes, methods, products or equipment.

[0061] As used herein, the terms "substantially," "about," and the like are used as terms of approximation, not as terms of degree, and are intended to take into account the inherent deviations of measurements or calculations that one of ordinary skill in the art would know. In addition, the use of "may" when describing embodiments of the present invention means "possible one or more embodiments." As used herein, the terms "use," "using," and "used" may be considered synonymous with the terms "utilize," "utilizing," and "utilized," respectively. In addition, the term "exemplary" is intended to refer to an example or illustration.

[0062] First, the overall workflow of the artificial intelligence system is described. Figure 1A , Figure 1A The figure shows a structural diagram of the main framework of artificial intelligence. The following is an explanation of the above artificial intelligence theme framework from the two dimensions of "intelligent information chain" (horizontal axis) and "IT value chain" (vertical axis). Among them, the "intelligent information chain" reflects a series of processes from data acquisition to processing. For example, it can be a general process of intelligent information perception, intelligent information representation and formation, intelligent reasoning, intelligent decision-making, intelligent execution and output. In this process, the data has undergone a condensation process of "data-information-knowledge-wisdom". The "IT value chain" reflects the value that artificial intelligence brings to the information technology industry from the underlying infrastructure of human intelligence, information (providing and processing technology implementation) to the industrial ecology process of the system.

[0063] (1) Infrastructure

[0064] The infrastructure provides computing power support for the AI ​​system, enables communication with the outside world, and supports it through the basic platform. It communicates with the outside world through sensors; computing power is provided by smart chips (CPU, NPU, GPU, ASIC, FPGA and other hardware acceleration chips); the basic platform includes distributed computing frameworks and networks and other related platform guarantees and support, which can include cloud storage and computing, interconnected networks, etc. For example, sensors communicate with the outside world to obtain data, and these data are provided to the smart chips in the distributed computing system provided by the basic platform for calculation.

[0065] (2) Data

[0066] The data on the upper layer of the infrastructure is used to represent the data sources in the field of artificial intelligence. The data involves graphics, images, voice, text, and IoT data of traditional devices, including business data of existing systems and perception data such as force, displacement, liquid level, temperature, and humidity.

[0067] (3) Data processing

[0068] Data processing usually includes data training, machine learning, deep learning, search, reasoning, decision-making and other methods.

[0069] Among them, machine learning and deep learning can symbolize and formalize data for intelligent information modeling, extraction, preprocessing, and training.

[0070] Reasoning refers to the process of simulating human intelligent reasoning in computers or intelligent systems, using formalized information to perform machine thinking and solve problems based on reasoning control strategies. Typical functions are search and matching.

[0071] Decision-making refers to the process of making decisions after intelligent information is reasoned, usually providing functions such as classification, sorting, and prediction.

[0072] (4) General ability

[0073] After the data has undergone the data processing mentioned above, some general capabilities can be further formed based on the results of the data processing, such as an algorithm or a general system, for example, translation, text analysis, computer vision processing, speech recognition, image recognition, etc.

[0074] (5) Smart products and industry applications

[0075] Smart products and industry applications refer to the products and applications of artificial intelligence systems in various fields. They are the encapsulation of the overall artificial intelligence solution, which productizes intelligent information decision-making and realizes practical applications. Its application areas mainly include: smart terminals, smart transportation, smart medical care, autonomous driving, smart cities, etc.

[0076] The present application can be applied to the field of natural language processing in the field of artificial intelligence. Taking natural language processing as an example, multiple application scenarios of products will be introduced below.

[0077] First, the application scenarios of the present application are introduced. The present application can be applied to, but not limited to, applications with video understanding functions such as video (hereinafter referred to as video understanding applications) or cloud services provided by cloud-side servers, etc., which are introduced below:

[0078] 1. Video Understanding Applications

[0079] The product form of the embodiment of the present application may be a video understanding application program. The video understanding application program may be run on a terminal device or a server on the cloud side.

[0080] In a possible implementation, a video understanding application can implement video-related processing tasks and obtain processing results.

[0081] For example, a video understanding application may implement at least video understanding tasks including video classification tasks, video search tasks, video recommendation tasks, video positioning tasks, advertisement matching tasks, etc., but is not limited thereto.

[0082] In one possible implementation, a user can open a video understanding application installed on a terminal device and input a video (the video may be triggered by an instruction, not necessarily actively input by the user). The video understanding application can process the video using the method provided in an embodiment of the present application and present the processing results to the user (the presentation method may be but is not limited to display, saving, uploading to the cloud, etc.).

[0083] In one possible implementation, a user can open a video understanding application installed on a terminal device and input a video. The video understanding application can send the video to a server on the cloud side. The server on the cloud side processes the video using the method provided in an embodiment of the present application and transmits the processing result back to the terminal device. The terminal device can present the processing result to the user (the presentation method can be but is not limited to display, saving, uploading to the cloud side, etc.).

[0084] Next, the video understanding application in the embodiment of the present application is introduced from the functional architecture and the product architecture that implements the functions.

[0085] Reference Figure 1B , Figure 1B The functional architecture of the video understanding application in the embodiment of the present application is shown as follows:

[0086] In one possible implementation, Figure 1B As shown, a video understanding application 102 can receive input parameters 101 (e.g., including an image) and generate a processing result 103. The video understanding application 102 can be executed on (for example) at least one computer system, and includes computer codes, which, when executed by one or more computers, cause the computers to execute the method provided by the embodiments of the present application.

[0087] Reference Figure 1C , Figure 1C The following is a schematic diagram of the physical architecture for running a video understanding application in an embodiment of the present application:

[0088] See also Figure 1C , Figure 1C A schematic diagram of a system architecture is shown. The system may include a terminal 100 and a server 200. The server 200 may include one or more servers ( Figure 1CIn the example, a server is included, and the server 200 can provide a video understanding function for one or more terminals.

[0089] Among them, the terminal 100 can be installed with a video understanding application, or a web page related to the video understanding function can be opened. The above application and web page can provide an interface. The terminal 100 can receive relevant parameters entered by the user on the video understanding function interface and send the above parameters to the server 200. The server 200 can obtain processing results based on the received parameters and return the processing results to the terminal 100.

[0090] It should be understood that in some optional implementations, the terminal 100 can also complete the action of obtaining the processing result based on the received parameters by itself without the cooperation of the server, and the embodiments of the present application are not limited to this.

[0091] Next describe Figure 1C The product form of the mid-terminal 100;

[0092] The terminal 100 in the embodiment of the present application can be a mobile phone, a tablet computer, a wearable device, a vehicle-mounted device, an augmented reality (AR) / virtual reality (VR) device, a laptop computer, an ultra-mobile personal computer (UMPC), a netbook, a personal digital assistant (PDA), etc., and the embodiment of the present application does not impose any limitation on this.

[0093] Figure 1D An optional hardware structure diagram of the terminal 100 is shown.

[0094] refer to Figure 1D As shown, the terminal 100 may include a radio frequency unit 110, a memory 120, an input unit 130, a display unit 140, a camera 150 (optional), an audio circuit 160 (optional), a speaker 161 (optional), a microphone 162 (optional), a processor 170, an external interface 180, a power supply 190 and other components. Those skilled in the art will appreciate that Figure 1D These are merely examples of terminals or multi-function devices and do not constitute limitations on the terminals or multi-function devices, which may include more or fewer components than those shown in the figures, or combinations of certain components, or different components.

[0095] The input unit 130 can be used to receive input digital or character information, and generate key signal input related to the user settings and function control of the portable multifunctional device. Specifically, the input unit 130 may include a touch screen 131 (optional) and / or other input devices 132. The touch screen 131 can collect the user's touch operations on or near it (such as the user's operation on or near the touch screen using any suitable object such as fingers, joints, stylus, etc.), and drive the corresponding connection device according to a pre-set program. The touch screen can detect the user's touch action on the touch screen, convert the touch action into a touch signal and send it to the processor 170, and can receive and execute the command sent by the processor 170; the touch signal at least includes the touch point coordinate information. The touch screen 131 can provide an input interface and an output interface between the terminal 100 and the user. In addition, the touch screen can be implemented using multiple types such as resistive, capacitive, infrared and surface acoustic wave. In addition to the touch screen 131, the input unit 130 can also include other input devices. Specifically, other input devices 132 may include, but are not limited to, one or more of a physical keyboard, function keys (such as a volume control button 132 , a switch button 133 , etc.), a trackball, a mouse, a joystick, and the like.

[0096] The input device 132 can receive input video.

[0097] The display unit 140 may be used to display information input by the user or provided to the user, various menus of the terminal 100, interactive interfaces, file displays, and / or playback of any multimedia file. In an embodiment of the present application, the display unit 140 may be used to display the interface of a video understanding application, processing results, etc.

[0098] The memory 120 can be used to store instructions and data. The memory 120 can mainly include an instruction storage area and a data storage area. The data storage area can store various data, such as multimedia files, texts, etc.; the instruction storage area can store software units such as operating systems, applications, instructions required for at least one function, or their subsets and extensions. It can also include a non-volatile random access memory; provide the processor 170 with hardware, software and data resources including management of computing and processing equipment, and support control software and applications. It is also used for the storage of multimedia files, and the storage of running programs and applications.

[0099] The processor 170 is the control center of the terminal 100. It uses various interfaces and lines to connect various parts of the entire terminal 100. By running or executing instructions stored in the memory 120 and calling data stored in the memory 120, it executes various functions of the terminal 100 and processes data, thereby controlling the terminal device as a whole. Optionally, the processor 170 may include one or more processing units; preferably, the processor 170 may integrate an application processor and a modem processor, wherein the application processor mainly processes the operating system, user interface and application program, and the modem processor mainly processes wireless communication. It is understandable that the above-mentioned modem processor may not be integrated into the processor 170. In some embodiments, the processor and the memory may be implemented on a single chip, and in some embodiments, they may also be implemented separately on separate chips. The processor 170 may also be used to generate corresponding operation control signals, send them to corresponding components of the computing and processing device, read and process data in the software, especially read and process data and programs in the memory 120, so that each functional module therein performs corresponding functions, thereby controlling the corresponding components to act according to the requirements of the instructions.

[0100] Among them, the memory 120 can be used to store software codes related to the data processing method, the processor 170 can execute the steps of the chip data processing method, and can also schedule other units (such as the above-mentioned input unit 130 and display unit 140) to realize corresponding functions.

[0101] The radio frequency unit 110 (optional) can be used for receiving and sending information or receiving and sending signals during a call, for example, after receiving the downlink information of the base station, it is sent to the processor 170 for processing; in addition, the designed uplink data is sent to the base station. Generally, the RF circuit includes but is not limited to an antenna, at least one amplifier, a transceiver, a coupler, a low noise amplifier (Low Noise Amplifier, LNA), a duplexer, etc. In addition, the radio frequency unit 110 can also communicate with network devices and other devices through wireless communication. The wireless communication can use any communication standard or protocol, including but not limited to Global System of Mobile communication (Global System of Mobile communication, GSM), General Packet Radio Service (General Packet Radio Service, GPRS), Code Division Multiple Access (Code Division Multiple Access, CDMA), Wideband Code Division Multiple Access (Wideband Code Division Multiple Access, WCDMA), Long Term Evolution (Long Term Evolution, LTE), email, Short Messaging Service (SMS), etc.

[0102] In this embodiment of the present application, the RF unit 110 can send the video to the server 200 and receive the processing result sent by the server 200.

[0103] It should be understood that the radio frequency unit 110 is optional and can be replaced by other communication interfaces, such as a network port.

[0104] The terminal 100 also includes a power supply 190 (such as a battery) for supplying power to various components. Preferably, the power supply can be logically connected to the processor 170 through a power management system, so that the power management system can manage functions such as charging, discharging, and power consumption.

[0105] The terminal 100 further includes an external interface 180 , which may be a standard Micro USB interface or a multi-pin connector, and may be used to connect the terminal 100 to communicate with other devices, or to connect a charger to charge the terminal 100 .

[0106] Although not shown, the terminal 100 may also include a flashlight, a wireless fidelity (WiFi) module, a Bluetooth module, sensors with different functions, etc., which are not described in detail here. Some or all of the methods described below may be applied in the following embodiments. Figure 1D In the terminal 100 shown.

[0107] Next describe Figure 1C The product form of the server 200;

[0108] Figure 2 A structural diagram of a server 200 is provided, such as Figure 2 As shown, the server 200 includes a bus 201, a processor 202, a communication interface 203, and a memory 204. The processor 202, the memory 204, and the communication interface 203 communicate with each other via the bus 201.

[0109] The bus 201 may be a peripheral component interconnect (PCI) bus or an extended industry standard architecture (EISA) bus. The bus may be divided into an address bus, a data bus, a control bus, etc. For ease of representation, Figure 2 Only one thick line is used in the diagram, but this does not mean that there is only one bus or only one type of bus.

[0110] The processor 202 may be any one or more of a central processing unit (CPU), a graphics processing unit (GPU), a microprocessor (MP), or a digital signal processor (DSP).

[0111] The memory 204 may include a volatile memory, such as a random access memory (RAM). The memory 204 may also include a non-volatile memory, such as a read-only memory (ROM), a flash memory, a hard drive (HDD), or a solid state drive (SSD).

[0112] The memory 204 may be used to store software codes related to the data processing method, and the processor 202 may execute the steps of the data processing method of the chip, and may also schedule other units to implement corresponding functions.

[0113] It should be understood that the above-mentioned terminal 100 and server 200 can be centralized or distributed devices, and the processors in the above-mentioned terminal 100 and server 200 (such as processor 170 and processor 202) can be hardware circuits (such as application specific integrated circuit (ASIC), field-programmable gate array (FPGA), general-purpose processor, digital signal processor (DSP), microprocessor or microcontroller, etc.), or a combination of these hardware circuits. For example, the processor can be a hardware system with an instruction execution function, such as a CPU, DSP, etc., or a hardware system without an instruction execution function, such as an ASIC, FPGA, etc., or a combination of the above-mentioned hardware systems without an instruction execution function and hardware systems with an instruction execution function.

[0114] It should be understood that the steps related to the model reasoning process in the embodiments of the present application involve AI-related operations. When performing AI operations, the instruction execution architecture of the terminal device and the server is not limited to the processor combined with the memory architecture described above. Figure 3 The system architecture provided in the embodiments of the present application is introduced in detail.

[0115] Figure 3 This is a schematic diagram of the system architecture provided in the embodiment of the present application. Figure 3 As shown, the system architecture 500 includes an execution device 510 , a training device 520 , a database 530 , a client device 540 , a data storage system 550 , and a data collection system 560 .

[0116] The execution device 510 includes a calculation module 511, an I / O interface 512, a preprocessing module 513 and a preprocessing module 514. The calculation module 511 may include a target model / rule 501, and the preprocessing module 513 and the preprocessing module 514 are optional.

[0117] The execution device 510 may be a terminal device or a server that runs the above-mentioned video understanding application.

[0118] The data acquisition device 560 is used to collect training samples. The training samples can be videos, etc. After collecting the training samples, the data acquisition device 560 stores these training samples in the database 530.

[0119] The training device 520 can train the neural network (such as the model in the embodiment of the present application (such as including an image encoder, a text encoder, etc.)) to obtain the target model / rule 501 based on the training samples maintained in the database 530.

[0120] It should be understood that the training device 520 can perform a pre-training process on the neural network to be trained based on the training samples maintained in the database 530, or fine-tune the model based on the pre-training.

[0121] It should be noted that, in actual applications, the training samples maintained in the database 530 may not all come from the data acquisition device 560, but may also be received from other devices. It should also be noted that the training device 520 may not train the target model / rule 501 entirely based on the training samples maintained in the database 530, but may also obtain training samples from the cloud or other places for model training. The above description should not be used as a limitation on the embodiments of the present application.

[0122] The target model / rule 501 obtained by training the training device 520 can be applied to different systems or devices, such as Figure 3 The execution device 510 shown may be a terminal, such as a mobile phone terminal, a tablet computer, a laptop computer, an augmented reality (AR) / virtual reality (VR) device, a vehicle terminal, etc., or a server, etc.

[0123] Specifically, the training device 520 may transfer the trained model to the execution device 510 .

[0124] exist Figure 3 In the embodiment, the execution device 510 is configured with an input / output (I / O) interface 512 for data interaction with an external device, and a user can input data (such as a video in an embodiment of the present application) to the I / O interface 512 through a client device 540.

[0125] The preprocessing module 513 and the preprocessing module 514 are used to preprocess the input data received by the I / O interface 512. It should be understood that there may be no preprocessing module 513 and the preprocessing module 514 or only one preprocessing module. When there is no preprocessing module 513 and the preprocessing module 514, the computing module 511 may be directly used to process the input data.

[0126] When the execution device 510 preprocesses the input data, or when the computing module 511 of the execution device 510 performs calculations and other related processing, the execution device 510 can call the data, code, etc. in the data storage system 550 for corresponding processing, and can also store the data, instructions, etc. obtained from the corresponding processing into the data storage system 550.

[0127] Finally, the I / O interface 512 provides the processing results to the client device 540 and thus to the user.

[0128] exist Figure 3 In the case shown, the user can manually give input data, and the "manually given input data" can be operated through the interface provided by the I / O interface 512. In another case, the client device 540 can automatically send input data to the I / O interface 512. If the client device 540 is required to automatically send input data and needs to obtain the user's authorization, the user can set the corresponding authority in the client device 540. The user can view the results output by the execution device 510 on the client device 540, and the specific presentation form can be a specific method such as display, sound, action, etc. The client device 540 can also be used as a data acquisition terminal to collect the input data of the input I / O interface 512 and the output results of the output I / O interface 512 as shown in the figure as new sample data, and store them in the database 530. Of course, it is also possible not to collect through the client device 540, but the I / O interface 512 directly stores the input data of the input I / O interface 512 and the output results of the output I / O interface 512 as new sample data in the database 530.

[0129] It is worth noting that Figure 3 This is only a schematic diagram of a system architecture provided by an embodiment of the present application. The positional relationship between the devices, components, modules, etc. shown in the figure does not constitute any limitation. For example, in Figure 3 In the embodiment, the data storage system 550 is an external memory relative to the execution device 510. In other cases, the data storage system 550 may also be placed in the execution device 510. It should be understood that the execution device 510 may be deployed in the client device 540.

[0130] From the inference side of the model:

[0131] In the embodiment of the present application, the computing module 511 of the above-mentioned execution device 520 can obtain the code stored in the data storage system 550 to implement the steps related to the model reasoning process in the embodiment of the present application.

[0132] In an embodiment of the present application, the computing module 511 of the execution device 520 may include a hardware circuit (such as an application specific integrated circuit (ASIC), a field-programmable gate array (FPGA), a general-purpose processor, a digital signal processor (DSP), a microprocessor or a microcontroller, etc.), or a combination of these hardware circuits. For example, the training device 520 may be a hardware system with an instruction execution function, such as a CPU, DSP, etc., or a hardware system without an instruction execution function, such as an ASIC, FPGA, etc., or a combination of the above-mentioned hardware systems without an instruction execution function and hardware systems with an instruction execution function.

[0133] Specifically, the computing module 511 of the execution device 520 can be a hardware system with an execution instruction function, and the steps related to the model reasoning process provided in the embodiment of the present application can be software codes stored in the memory. The computing module 511 of the execution device 520 can obtain the software code from the memory and execute the obtained software code to implement the steps related to the model reasoning process provided in the embodiment of the present application.

[0134] It should be understood that the computing module 511 of the execution device 520 can be a combination of a hardware system that does not have the function of executing instructions and a hardware system that has the function of executing instructions. Some of the steps related to the model reasoning process provided in the embodiments of the present application can also be implemented by the hardware system that does not have the function of executing instructions in the computing module 511 of the execution device 520, which is not limited here.

[0135] From the training side of the model:

[0136] In the embodiment of the present application, the training device 520 can obtain the memory ( Figure 3 Not shown in the figure, the code stored in the training device 520 (or deployed separately from the training device 520) can be integrated into the training device 520 to implement the steps related to model training in the embodiments of the present application.

[0137] In an embodiment of the present application, the training device 520 may include a hardware circuit (such as an application specific integrated circuit (ASIC), a field-programmable gate array (FPGA), a general-purpose processor, a digital signal processor (DSP), a microprocessor or a microcontroller, etc.), or a combination of these hardware circuits. For example, the training device 520 may be a hardware system with an instruction execution function, such as a CPU, DSP, etc., or a hardware system without an instruction execution function, such as an ASIC, FPGA, etc., or a combination of the above-mentioned hardware systems without an instruction execution function and hardware systems with an instruction execution function.

[0138] It should be understood that the training device 520 can be a combination of a hardware system that does not have the function of executing instructions and a hardware system that has the function of executing instructions. Some of the steps related to model training provided in the embodiments of the present application can also be implemented by the hardware system that does not have the function of executing instructions in the training device 520, which is not limited here.

[0139] 2. Video understanding cloud services provided by the server:

[0140] In a possible implementation, the server may provide a video understanding function service to the terminal side through an application programming interface (API).

[0141] Among them, the terminal device can send relevant parameters (such as images, text and other data) to the server through the API provided by the cloud. The server can obtain processing results based on the received parameters, etc., and return the processing results to the terminal.

[0142] The description of the terminal and the server can be the same as that of the above embodiments, and will not be repeated here.

[0143] like Figure 4 The process of using a video understanding function cloud service provided by a cloud platform is shown.

[0144] 1. Activate and purchase content review service.

[0145] 2. Users can download the software development kit (SDK) corresponding to the content review service. Usually, the cloud platform provides multiple development versions of the SDK for users to choose according to the requirements of the development environment, such as JAVA version SDK, Python version SDK, PHP version SDK, Android version SDK, etc.

[0146] 3. After the user downloads the corresponding version of the SDK to the local computer according to the needs, the SDK project is imported into the local development environment, and configuration and debugging are performed in the local development environment. The local development environment can also be used to develop other functions, thus forming an application that integrates video understanding functional capabilities.

[0147] 4. When the video understanding function application is used, when the video understanding function is needed, the API call of the video understanding function can be triggered. When the application triggers the video understanding function, an API request is initiated to the running instance of the video understanding function service in the cloud environment. The API request carries an image, and the running instance in the cloud environment processes the image to obtain the processing result.

[0148] 5. The cloud environment returns the processing results to the application, thereby completing a video understanding function call.

[0149] Since the embodiments of the present application involve the application of a large number of neural networks, in order to facilitate understanding, the relevant terms and related concepts such as neural networks involved in the embodiments of the present application are first introduced below.

[0150] (1) Neural Network

[0151] A neural network may be composed of neural units, and a neural unit may refer to an operation unit that takes xs (i.e., input data) and intercept 1 as input, and the output of the operation unit may be:

[0152]

[0153] Where s=1, 2, ...n, n is a natural number greater than 1, Ws is the weight of xs, and b is the bias of the neural unit. f is the activation function of the neural unit, which is used to introduce nonlinear characteristics into the neural network to convert the input signal in the neural unit into the output signal. The output signal of the activation function can be used as the input of the next convolution layer, and the activation function can be a sigmoid function. A neural network is a network formed by connecting multiple single neural units mentioned above, that is, the output of one neural unit can be the input of another neural unit. The input of each neural unit can be connected to the local receptive field of the previous layer to extract the characteristics of the local receptive field. The local receptive field can be an area composed of several neural units.

[0154] (2) Transformer layer

[0155] The neural network includes an embedding layer and at least one transformer layer, and the at least one transformer layer can be N transformer layers (N is an integer greater than 0), wherein each transformer layer includes an attention layer, an add&norm layer, a feed forward layer and an add&norm layer that are adjacent in sequence. In the embedding layer, the current input is embedded to obtain multiple embedding vectors; in the attention layer, P input vectors are obtained from the previous layer of the first transformer layer, and the intermediate vector corresponding to the first input vector is obtained based on the correlation between each input vector within a preset attention window range and the first input vector, with any first input vector among the P input vectors as the center, so as to determine the P intermediate vectors corresponding to the P input vectors; in the pooling layer, the P intermediate vectors are merged into Q output vectors, wherein the multiple output vectors obtained by the last transformer layer in the transformer layer are used as the feature representation of the current input.

[0156] (3) Attention mechanism

[0157] The attention mechanism imitates the internal process of biological observation behavior, that is, a mechanism that aligns internal experience and external sensations to increase the observation precision of some areas, and can use limited attention resources to quickly filter out high-value information from a large amount of information. The attention mechanism can quickly extract important features of sparse data, and is therefore widely used in natural language processing tasks, especially machine translation. The self-attention mechanism is an improvement on the attention mechanism, which reduces dependence on external information and is better at capturing the internal correlation of data or features. The essential idea of ​​the attention mechanism can be rewritten as the following formula:

[0158] Among them, Lx=||Source|| represents the length of Source. The formula means that the elements in Source are imagined to be composed of a series of data pairs. At this time, given a certain element Query in the target Target, by calculating the similarity or correlation between Query and each Key, the weight coefficient of the Value corresponding to each Key is obtained, and then the Value is weighted and summed to obtain the final Attention value. Therefore, the Attention mechanism is essentially a weighted sum of the Value values ​​of the elements in Source, and Query and Key are used to calculate the weight coefficient of the corresponding Value. Conceptually, Attention can be understood as selectively filtering out a small amount of important information from a large amount of information and focusing on these important information, ignoring most of the unimportant information. The focusing process is reflected in the calculation of the weight coefficient. The larger the weight, the more focus is placed on its corresponding Value value, that is, the weight represents the importance of the information, and the Value is the corresponding information. The self-attention mechanism can be understood as internal Attention (intra attention). The Attention mechanism occurs between the Target element Query and all elements in the Source. The self-attention mechanism refers to the Attention mechanism that occurs between the internal elements of the Source or between the internal elements of the Target. It can also be understood as the attention calculation mechanism in the special case of Target = Source. The specific calculation process is the same, but the calculation object has changed.

[0159] (4) Natural language processing (NLP)

[0160] Natural language is human language, and natural language processing (NLP) is the processing of human language. Natural language processing is the process of systematically analyzing, understanding, and extracting information from text data in an intelligent and efficient way. By using NLP and its components, we can manage very large blocks of text data, or perform a large number of automated tasks, and solve a variety of problems, such as automatic summarization, machine translation (MT), named entity recognition (NER), relation extraction (RE), information extraction (IE), sentiment analysis, speech recognition, question answering, and topic segmentation, etc.

[0161] (5) Back propagation algorithm

[0162] Convolutional neural networks can use the error back propagation (BP) algorithm to correct the size of the parameters in the initial super-resolution model during the training process, so that the reconstruction error loss of the super-resolution model becomes smaller and smaller. Specifically, the forward transmission of the input signal to the output will generate error loss, and the error loss information is back-propagated to update the parameters in the initial super-resolution model, so that the error loss converges. The back propagation algorithm is a back propagation movement dominated by error loss, aiming to obtain the optimal parameters of the super-resolution model, such as the weight matrix.

[0163] (6) Loss Function

[0164] In the process of training a deep neural network, because we hope that the output of the deep neural network is as close as possible to the value we really want to predict, we can compare the predicted value of the current network with the target value we really want, and then update the weight vector of each layer of the neural network according to the difference between the two (of course, there is usually an initialization process before the first update, that is, pre-configuring parameters for each layer in the deep neural network). For example, if the predicted value of the network is high, adjust the weight vector to make it predict a lower value, and keep adjusting until the deep neural network can predict the target value we really want or a value very close to the target value we really want. Therefore, it is necessary to pre-define "how to compare the difference between the predicted value and the target value", which is the loss function or objective function, which are important equations used to measure the difference between the predicted value and the target value. Among them, taking the loss function as an example, the higher the output value (loss) of the loss function, the greater the difference, so the training of the deep neural network becomes a process of minimizing this loss as much as possible.

[0165] (7) Transformer: A network based on a multi-head attention mechanism that includes residual connections, layer normalization, and full connections and can process sequence data in parallel. It was originally used to encode text features.

[0166] (8) Video Transformer: A Transformer network modified for the video domain. It models temporal and spatial information through spatiotemporal attention and can be used to encode video features.

[0167] (9) Token: The smallest unit in the input sequence of the Video Transformer model. Like the Transformer, the Video Transformer accepts a sequence of Tokens as input. The video input is 3D, including the number of frames T, the width W, and the height H of each frame. In order to encode the video, the model generally divides the video into several smallest units (i.e., Tokens), and then inputs them as a sequence. The Token here can be 3D (i.e., a small cube Cube, obtained by directly dividing the 3D video) or 2D (i.e., a small square patch, obtained by dividing each frame of the picture). The Token in this technology corresponds to a 2D small square patch, i.e., Patch.

[0168] (10) Image patch: A 2D small square obtained by splitting each frame of the image in the Video Transformer. A picture (such as 224x224, 224 is the side length of the picture) is cut into several small squares of the same size (such as 16x16, 16 is the side length of the small square), namely a patch.

[0169] The Video Transformer model applies the original Transformer model to the video field, encoding video features by modeling temporal and spatial information, and then used for downstream video understanding tasks such as video-text retrieval, video description generation, video question answering, etc. The Video Transformer model effectively adapts to large-scale pre-training and has now become the basic model architecture for video understanding.

[0170] When a long video is input into the Video Transformer model, it is divided into a large number of visual tokens, resulting in an input token sequence that is too long and has high redundancy; this impairs the efficiency of video encoding and is not conducive to the model learning key semantic information. For example, for a 96-frame video with a resolution of 224x224 per frame, the commonly used Video Transformer model cuts each frame into 16x16 patches, which will result in up to (224 / 16)x(224 / 16)x96=19K visual tokens, which brings a huge computational burden to the subsequent feature encoding.

[0171] Therefore, there is an urgent need for a video encoding method with low computing power overhead.

[0172] In order to solve the above problems, the present application provides a data processing method. The data processing method of the present application is described in detail below with reference to the accompanying drawings.

[0173] Reference Figure 5 , Figure 5 A data processing method according to an embodiment of the present invention is shown in FIG. Figure 5 As shown, a data processing method provided in an embodiment of the present application may include steps 501 to 505, and these steps are described in detail below.

[0174] 501. Acquire multiple video frames;

[0175] In a possible implementation, the video including multiple video frames can be pre-stored locally in the terminal, or obtained by the terminal from the outside world (such as the Internet), or collected by the terminal in real time, for example, through a camera of the terminal.

[0176] The video can be a long video. Generally, a short video is defined as a video with a duration of less than 30 seconds, while a long video is defined as a video with a duration of more than 30 seconds. The average duration of long videos in many academic datasets is about 150 seconds, which is more than 5 times that of short videos. When the frame rate is constant, long videos naturally contain more input frames than short videos.

[0177] 502. Process the multiple video frames through an encoder to obtain an encoding result; wherein the encoder includes a first network layer; the first network layer includes an inter-frame compression module, the multiple video frames include M first video frames and N second video frames, and the inter-frame compression module is used to fuse the feature representations of the M first video frames into the feature representations of the N second video frames to obtain N feature representations.

[0178] In the current Video Transformer model, long videos are divided into a large number of visual tokens (the number of visual tokens is the number of frames * the number of patches per frame), which results in the input token sequence being too long and having a large redundancy. This situation has an adverse effect on the efficiency of video coding and brings a huge computational burden to the subsequent feature coding process. At the same time, due to the existence of redundancy, the input sequence may contain a large amount of similar or repeated visual information, which further increases the redundancy of the calculation. These problems together lead to a decrease in the efficiency of video coding, making the subsequent feature coding process face a huge computational burden and complexity. Therefore, the embodiments of the present application aim to solve these technical problems triggered when long videos are input, so as to improve the efficiency of video coding and reduce the computational burden of feature coding.

[0179] The encoder may include multiple network layers, each network layer may receive a feature representation output by an adjacent previous network layer, and perform feature extraction on the feature representation output by the adjacent previous network layer.

[0180] In a possible implementation, the encoder includes a first network layer, and the first network layer may include an inter-frame compression module. Specifically, the multiple video frames include M first video frames and N second video frames, and the inter-frame compression module is used to merge the feature representations of the M first video frames into the feature representations of the N second video frames to obtain N feature representations. That is, the inter-frame compression module can merge the feature representations of some video frames in the multiple video frames into the feature representations of another part of the video frames during encoding, thereby reducing the number of feature representations.

[0181] Among them, the feature representation can be expressed as a token, that is, the inter-frame compression module is used to convert the M tokens corresponding to the M first video frames (each first video frame corresponds to a token) to the N tokens corresponding to the N second video frames to obtain N tokens.

[0182] For example, see Figure 6 , Figure 6The video encoder block in the video encoder block can be the first network layer, the temporal aggregation in the video encoder block is an inter-frame compression module, and the input of the temporal aggregation is a feature of size T*L*D, wherein T is the number of video frames, L is the number of image blocks included in the video frame, and D is the dimension of the feature representation of each image block. Since the temporal aggregation fuses the feature representations of Rt video frames out of T video frames into the feature representation of (T-Rt) video frames, a feature representation of size (T-Rt)*L*D can be obtained.

[0183] Next, we will introduce how to determine the video frame that needs to be fused into the feature representation of other video frames:

[0184] In a possible implementation, the M first video frames are M video frames having the lowest correlation with other video frames among the multiple video frames.

[0185] Among them, the least important M first video frames among multiple video frames can be selected and divided into Set A, and the remaining N second video frames can be divided into Set B. The feature representations of the least important M first video frames can be fused into the feature representations of the N second video frames, which can reduce the information loss of the fusion.

[0186] Regarding the selection of objects that need to be fused (for example, M first video frames), the embodiment of the present application proposes a selection algorithm based on the importance of visual tokens. By evaluating and ranking the importance of each token, tokens with higher importance are selected as representative tokens.

[0187] In a possible implementation, a video frame with a lower correlation with other video frames may be considered to be a video frame with lower importance.

[0188] Optionally, the importance of a video frame is calculated as follows:

[0189]

[0190] Among them, A ji is from token x j (that is, the feature representation of the jth video frame) to token x i The attention score of the i-th video frame (i.e., the feature representation of the i-th video frame) can indicate the relevance between video frames. Q and K represent the query and key in the self-attention mechanism.

[0191] In a possible implementation, the first video frame and the second video frame are interlaced with each other in the multiple video frames.

[0192] Among them, adjacent video frames often have higher similarity, and they should be divided into different sets to encourage their fusion. Therefore, the adjacent first video frame and the second video frame can be divided into different sets, for example, the first video frame with an odd sequence number can be divided into Set A, and the second video frame with an even sequence number can be divided into Set B. The feature representation of the first video frame in Set A is fused to the feature representation of the second video frame in Set B.

[0193] The embodiment of the present application proposes a selection algorithm based on visual token geometric information, which selects tokens with reasonable spatial distribution as representative tokens by considering the position and distribution of tokens in space. The introduction of these selection algorithms makes the aggregation process more accurate and efficient, ensuring the quality and accuracy of the aggregation results.

[0194] In a possible implementation, each first video frame in the M first video frames may be fused to a feature representation of the most similar second video frame in the N second video frames.

[0195] Among them, the inter-frame compression module can aggregate the feature representations of similar video frames, thereby reducing the number of feature representations that the model needs to process. By aggregating similar video frames, the embodiment of the present application ensures that important timing information in the video is fully preserved. Therefore, the method of the embodiment of the present application can still ensure the quality and effect of video encoding while improving the computational efficiency.

[0196] In the time dimension, the embodiments of the present application can integrate multiple similar video frames into one frame for processing. To this end, a pseudo-token (proxy token) called a frame token can be defined to represent a frame. Optionally, the frame token can be obtained by average pooling the features of all patches in the frame. The similarity between frame tokens (such as cosine similarity) is calculated to determine which frames to aggregate. When two frames are aggregated, their corresponding patches will be aggregated one by one, that is, the L patches in the first frame and L patches in the second frame Will be aggregated separately to obtain L patches after aggregation Among them, optional, It is through and The feature representation is obtained by average pooling.

[0197] like Figure 7On the left, the initial input video contains 96 frames, which are reduced by 8 frames at each layer through aggregation, reducing to 52 frames by the 6th layer and to 8 frames by the 12th layer.

[0198] Taking the feature representation of each video frame as a token as an example, given L tokens, the embodiment of the present application reduces R tokens through each aggregation, so the basic strategy of the aggregation algorithm is: first select R tokens, and then merge them into the remaining LR tokens based on similarity. The process of the algorithm may include:

[0199] Divide the tokens in the input sequence into two parts, record them as Set A and Set B. For each token in Set A, find the most similar token in Set B and connect them. The similarity is calculated as follows: for two tokens x i and x j , respectively get the features K of their attention Key i and K j , and then use cosine similarity to calculate norm(K i )norm(K j ). Keep the R edges with the highest similarity and aggregate the tokens at both ends of the edge. The aggregation method is to average pool the features of the tokens at both ends. Put the remaining tokens in the two sets back into a sequence as the output sequence.

[0200] Reference Figure 8 , Figure 8 This is an illustration of a fusion process, which may include 8 tokens, each of which may correspond to a video frame, and divide adjacent frames into different sets (e.g. Figure 8 In the example, token1, token3, token5, and token7 are divided into setA, and token2, token4, token6, and token8 are divided into setB). Through similarity calculation, token1 and token2 are most similar, token3 and token2 are most similar, token5 and token6 are most similar, and token7 and token8 are most similar. Therefore, token1 and token3 can be merged into token2 to obtain token123, and token5 can be merged into token6 to obtain token56.

[0201] The above introduces the inter-frame fusion process, and the following introduces the intra-frame fusion process.

[0202] The encoder may include multiple network layers, each network layer may receive a feature representation output by an adjacent previous network layer, and perform feature extraction on the feature representation output by the adjacent previous network layer.

[0203] In a possible implementation, the encoder includes a second network layer; the first network layer and the second network layer are the same or different network layers, the second network layer includes an intra-frame compression module, the multiple video frames include a third video frame, the third video frame includes X first image blocks and Y second image blocks, and the intra-frame compression module is used to fuse feature representations of the X first image blocks into feature representations of the Y second image blocks to obtain Y feature representations.

[0204] The feature representation can be expressed as a token, that is, the intra-frame compression module is used to convert the X tokens corresponding to the X first image blocks (each first image block corresponds to a token) to the Y tokens corresponding to the Y second image blocks to obtain Y tokens.

[0205] For example, see Figure 6 , Figure 6 The video encoder block in the video encoder block can be the second network layer, the spatial aggregation in the video encoder block is an intra-frame compression module, and the input of the spatial aggregation is a feature of size (T-Rt)*L*D, wherein T-Rt is the number of video frames, L is the number of image blocks included in the video frame, and D is the dimension of the feature representation of each image block. Since the spatial aggregation fuses the feature representation of Rs image blocks in each video frame into the feature representation of (L-Rs) video frames, a feature representation of size (T-Rt)*(L-Rs)*D can be obtained.

[0206] Next, we will introduce how to determine the image blocks that need to be fused into the feature representation of other image blocks:

[0207] In a possible implementation, the X first image blocks are X image blocks having the lowest correlation with other image blocks among the multiple image blocks.

[0208] Among them, the least important X first image blocks among multiple image blocks can be selected and divided into Set A, and the remaining Y second image blocks can be divided into Set B. The feature representations of the least important X first image blocks are fused into the feature representations of the Y second image blocks, which can reduce the information loss of the fusion.

[0209] For the selection of objects to be fused (e.g., X first image blocks), the embodiment of the present application proposes a selection algorithm based on the importance of visual tokens, by evaluating and ranking the importance of each token, and selecting tokens with higher importance as representative tokens.

[0210] In a possible implementation, it can be considered that an image block with a lower correlation with other image blocks is an image block with lower importance.

[0211] Optionally, the importance of an image block is calculated as follows:

[0212]

[0213] Among them, A ji is from tokeY x j (that is, the feature representation of the jth image block) to tokeY x i The attention score of the i-th image block (i.e., the feature representation of the i-th image block) can indicate the relevance between image blocks. Q and K represent the query and key in the self-attention mechanism.

[0214] In a possible implementation, the first image block and the second image block are interlaced with each other in the multiple image blocks.

[0215] Among them, adjacent image blocks often have higher similarities, and they should be divided into different sets to encourage their fusion. Therefore, the adjacent first image blocks and the second image blocks can be divided into different sets, for example, the first image blocks with odd numbers can be divided into Set A, and the second image blocks with even numbers can be divided into Set B. The feature representation of the first image block in Set A is fused to the feature representation of the second image block in Set B.

[0216] The embodiment of the present application proposes a selection algorithm based on visual token geometric information, which selects tokens with reasonable spatial distribution as representative tokens by considering the position and distribution of tokens in space. The introduction of these selection algorithms makes the aggregation process more accurate and efficient, ensuring the quality and accuracy of the aggregation results.

[0217] In a possible implementation, the feature representation of each first image block among the X first image blocks may be fused to the feature representation of the second image block that is most similar to the Y second image blocks.

[0218] In the embodiment of the present application, semantically similar patches in each frame can be integrated into one patch for processing. Figure 7On the right, the initial video contains 196 patches per frame, which are reduced to 16 patches per layer through aggregation, down to 101 patches by the 6th layer, and down to 11 patches by the 12th layer.

[0219] The intra-frame compression module automatically aggregates similar patches in each frame and merges them into a larger patch, thereby further reducing the number of visual tokens. Aggregation of similar patches in each frame also ensures that important visual features and details are not lost. Therefore, the method of the embodiment of the present application can still ensure the quality and effect of video encoding while improving computational efficiency.

[0220] Next, Figure 6 Take an example to introduce a specific implementation of the embodiment of the present application:

[0221] Reference Figure 6 , the video encoder is a Video Transformer. In each layer of the video encoder, the embodiment of the present application introduces a temporal aggregation module (Temporal Aggregation) and a spatial aggregation module (Spatial Aggregation). The temporal aggregation module reduces the RT frame in each aggregation, and the spatial aggregation module reduces RS patches in each aggregation, where RT and RS are hyperparameters used to control the final acceleration ratio. In this way, the size of the video features is reduced layer by layer, reducing the computational overhead of subsequent layers. For example, for the Video Transformer in the figure, the input of its i-th layer is a video feature of size Ti*Li*D, where Ti is the number of frames, Li is the number of patches per frame, and D is the feature dimension of the token. After passing through the temporal aggregation module, the RT frame can be reduced by frame aggregation, so that the size of the video feature is reduced to (Ti-RT)*Li*D. After passing through the spatial aggregation module, RS patches can be reduced by patch aggregation in each frame, so that the size of the video feature is reduced to (Ti-RT)*(Li-RS)*D. After passing through the M layers of Video Transformer, the number of visual tokens will be reduced from T*L to (TM*RT)*(LM*RS). By setting appropriate hyperparameters RT and RS, a total of 75% of visual tokens can be reduced, speeding up video encoding by 1.7 times.

[0222] During reasoning, the method provided in the embodiment of the present application can achieve aggregation and reduction layer by layer and quantitatively according to the number of frames of the input video and the number of patches per frame. Specifically, in the aggregation process of each layer, the number of visual tokens reduced by aggregation can be controlled according to the set hyperparameters. In this way, as the network advances layer by layer, the number of visual tokens in the input sequence will gradually decrease, thereby achieving aggregation and reduction operations in the video encoding process.

[0223] 503. Perform video-related tasks according to the encoding result to obtain a processing result.

[0224] In a possible implementation, the video-related task is video retrieval, video question answering, or video description generation.

[0225] Based on the spatiotemporal aggregation algorithm of the visual token, refer to Fig.9A , Fig.9A A video-language pre-training model is shown, including 1 video encoder, 1 text encoder, 1 cross-modal encoder, and 1 text decoder. The 3 encoders and 1 decoder are all Transformer architectures.

[0226] Next, the beneficial effects of the embodiments of the present application are introduced in combination with experiments:

[0227] Fig. 9B The left side shows the effect of reducing the number of frames on GFlops and Recall. It can be seen that reducing 5 frames per layer can reduce GFlops by 800 with almost no loss in performance.

[0228] Fig. 9B The middle shows the effect of reducing the number of patches on GFlops and Recall. It can be seen that reducing 10 frames per layer can reduce GFlops by 800 with almost no performance loss.

[0229] Fig. 9B The right side shows the relationship between reducing the number of frames, the number of patches, and GFlops / Recall.

[0230] Table 1

[0231]

[0232] Referring to Table 1, the embodiment of the present application (TESTA) achieves the best results in Paragraph-to-Video Retrieval. Task description: Given a text query, find the (first K) videos with the closest semantics to it from the video database. The target datasets are: QuerYD, CondenseMovie; the automatic evaluation index is: Recall@K.

[0233] As shown in Table 1, for 32-frame video input, TESTA achieved R@1 of 77.0 and 21.5, respectively, surpassing SOTA by 7.3 and 3.1. At the same time, the computational overhead (GFLOPs) of TESTA is only 420, which is significantly less than Frozen and VINDLU. When using 96-frame video input, TESTA further improves R@1 to 83.4 and 24.9, demonstrating its good scalability.

[0234] Table 2

[0235]

[0236] As shown in Table 2, the results on the target datasets: DiDeMo and ActivityNet Caption are similar to those in the previous article. For 32-frame video input, TESTA achieved an R@1 of 56.6 on DiDeMo with only 5M pre-training data, surpassing methods that use more than 100M pre-training data. When using 96-frame video input, TESTA improves R@1 to 59.2 and 53.7, surpassing SOTA 2.7 and 2.6.

[0237] Table 3

[0238]

[0239] As shown in Table 3, the embodiment of the present application achieved the best results on Long-form VideoQA. Target dataset: ActivityNet-QA; Automatic evaluation index: Accuracy. Conclusion: TESTA achieved an accuracy of 45.0%, which is 3.2% higher than SOTA.

[0240] Table 4

[0241]

[0242] As shown in Table 4, the aggregation algorithm based on bipartite graph matching outperforms the pruning algorithm in terms of performance. In addition, geometry-based aggregation has the best performance.

[0243] Reference Fig.10 , Fig.10 A schematic diagram of the structure of a data processing device provided in an embodiment of the present application is shown in FIG. Fig.10 As shown, an embodiment of the present application provides a data processing device, the device 1000 includes:

[0244] An acquisition module 1001 is used to acquire multiple video frames;

[0245] For the specific description of the acquisition module 1001, reference may be made to the description of step 501 in the above embodiment, which will not be repeated here.

[0246] A processing module 1002 is used to process the multiple video frames through an encoder to obtain an encoding result; wherein the encoder includes a first network layer; the first network layer includes an inter-frame compression module, the multiple video frames include M first video frames and N second video frames, and the inter-frame compression module is used to merge the feature representations of the M first video frames into the feature representations of the N second video frames to obtain N feature representations;

[0247] According to the encoding result, video-related tasks are performed to obtain a processing result.

[0248] For the specific description of the processing module 1002, reference may be made to the description of step 502 to step 503 in the above embodiment, which will not be repeated here.

[0249] In a possible implementation, the video-related task is video retrieval, video question answering, or video description generation.

[0250] In a possible implementation, the processing module 1002 is specifically configured to:

[0251] The feature representation of each of the M first video frames is fused to the feature representation of the second video frame that is most similar to the N second video frames.

[0252] In a possible implementation, the M first video frames are M video frames having the lowest correlation with other video frames among the multiple video frames.

[0253] In a possible implementation, the first video frame and the second video frame are interlaced with each other in the multiple video frames.

[0254] In a possible implementation, the fusion is average pooling.

[0255] In a possible implementation, the encoder includes a second network layer; the first network layer and the second network layer are the same or different network layers, the second network layer includes an intra-frame compression module, the multiple video frames include a third video frame, the third video frame includes X first image blocks and Y second image blocks, and the intra-frame compression module is used to fuse feature representations of the X first image blocks into feature representations of the Y second image blocks to obtain Y feature representations.

[0256] In a possible implementation, the processing module 1002 is specifically configured to:

[0257] The feature representation of each first image block in the X first image blocks is fused to the feature representation of the second image block that is most similar to the Y second image blocks.

[0258] In a possible implementation, the X first image blocks are X image blocks having the lowest correlation with other image blocks among a plurality of image blocks included in the third video frame.

[0259] In a possible implementation, the first image block and the second image block are interlaced with each other in the third video frame.

[0260] In a possible implementation, the task network is used to implement at least one of the following tasks: a video retrieval task, a video classification task, a video positioning task, and a video generation task (such as video question answering and video title generation).

[0261] Next, an execution device provided by an embodiment of the present application is introduced. Fig.11 , Fig.11 A schematic diagram of the structure of the execution device provided in the embodiment of the present application, the execution device 1100 can be specifically manifested as a virtual reality VR device, a mobile phone, a tablet, a laptop, a smart wearable device, a monitoring data processing device or a server, etc., which is not limited here. Specifically, the execution device 1100 includes: a receiver 1101, a transmitter 1102, a processor 1103 and a memory 1104 (wherein the number of processors 1103 in the execution device 1100 can be one or more, Fig.11 In the example of FIG. 1 , the processor 1103 may include an application processor 11031 and a communication processor 11032. In some embodiments of the present application, the receiver 1101, the transmitter 1102, the processor 1103 and the memory 1104 may be connected via a bus or other means.

[0262] The memory 1104 may include a read-only memory and a random access memory, and provides instructions and data to the processor 1103. A portion of the memory 1104 may also include a non-volatile random access memory (NVRAM). The memory 1104 stores processor and operation instructions, executable modules or data structures, or subsets thereof, or extended sets thereof, wherein the operation instructions may include various operation instructions for implementing various operations.

[0263] The processor 1103 controls the operation of the execution device. In a specific application, the various components of the execution device are coupled together through a bus system, wherein the bus system includes not only a data bus but also a power bus, a control bus, and a status signal bus, etc. However, for the sake of clarity, various buses are referred to as bus systems in the figure.

[0264] The method disclosed in the above embodiment of the present application can be applied to the processor 1103, or implemented by the processor 1103. The processor 1103 can be an integrated circuit chip with signal processing capabilities. In the implementation process, each step of the above method can be completed by the hardware integrated logic circuit or software instructions in the processor 1103. The above processor 1103 can be a general processor, a digital signal processor (digital signal processing, DSP), a microprocessor or a microcontroller, and can further include an application specific integrated circuit (application specific integrated circuit, ASIC), a field programmable gate array (field-programmable gate array, FPGA) or other programmable logic devices, discrete gates or transistor logic devices, discrete hardware components. The processor 1103 can implement or execute the various methods, steps and logic block diagrams disclosed in the embodiments of the present application. The general processor can be a microprocessor or the processor can also be any conventional processor, etc. The steps of the method disclosed in the embodiment of the present application can be directly embodied as a hardware decoding processor to execute, or the hardware and software modules in the decoding processor can be combined and executed. The software module may be located in a storage medium mature in the art, such as a random access memory, a flash memory, a read-only memory, a programmable read-only memory, or an electrically erasable programmable memory, a register, etc. The storage medium is located in the memory 1104, and the processor 1103 reads the information in the memory 1104 and completes the steps of the above method involving the model reasoning process in combination with its hardware.

[0265] The receiver 1101 can be used to receive input digital or character information and generate signal input related to the relevant settings and function control of the execution device. The transmitter 1102 can be used to output digital or character information through the first interface; the transmitter 1102 can also be used to send instructions to the disk group through the first interface to modify the data in the disk group; the transmitter 1102 can also include a display device such as a display screen.

[0266] The present application also provides a training device. Fig.12 , Fig.12 It is a structural diagram of a training device provided in an embodiment of the present application. Specifically, the training device 1200 is implemented by one or more servers. The training device 1200 may have relatively large differences due to different configurations or performances, and may include one or more central processing units (CPU) 1212 (for example, one or more processors) and memory 1232, and one or more storage media 1230 (for example, one or more mass storage devices) storing application programs 1242 or data 1244. Among them, the memory 1232 and the storage medium 1230 can be short-term storage or permanent storage. The program stored in the storage medium 1230 may include one or more modules (not shown in the figure), and each module may include a series of instruction operations in the training device. Furthermore, the central processing unit 1212 can be configured to communicate with the storage medium 1230 to execute a series of instruction operations in the storage medium 1230 on the training device 1200.

[0267] The training device 1200 may also include one or more power supplies 1226, one or more wired or wireless network interfaces 1250, one or more input and output interfaces 1258; or, one or more operating systems 1241, such as Windows ServerTM, Mac OS XTM, UnixTM, LinuxTM, FreeBSDTM, etc.

[0268] In the embodiment of the present application, the central processing unit 1212 is used to execute actions related to model training in the above embodiment.

[0269] Also provided in an embodiment of the present application is a computer program product which, when executed on a computer, enables the computer to execute the steps executed by the aforementioned execution device, or enables the computer to execute the steps executed by the aforementioned training device.

[0270] A computer-readable storage medium is also provided in an embodiment of the present application, which stores a program for signal processing. When the computer-readable storage medium is run on a computer, it enables the computer to execute the steps executed by the aforementioned execution device, or enables the computer to execute the steps executed by the aforementioned training device.

[0271] The execution device, training device or terminal device provided in the embodiments of the present application may specifically be a chip, and the chip includes: a processing unit and a communication unit, wherein the processing unit may be, for example, a processor, and the communication unit may be, for example, an input / output interface, a pin or a circuit, etc. The processing unit may execute the computer execution instructions stored in the storage unit so that the chip in the execution device executes the data processing method described in the above embodiment, or so that the chip in the training device executes the data processing method described in the above embodiment. Optionally, the storage unit is a storage unit in the chip, such as a register, a cache, etc. The storage unit may also be a storage unit located outside the chip in the wireless access device, such as a read-only memory (ROM) or other types of static storage devices that can store static information and instructions, a random access memory (RAM), etc.

[0272] For details, please refer to Fig.13 , Fig.13 A schematic diagram of the structure of a chip provided in an embodiment of the present application, the chip can be expressed as a neural network processor NPU 1300, NPU 1300 is mounted on the host CPU (Host CPU) as a coprocessor, and the host CPU assigns tasks. The core part of the NPU is the operation circuit 1303, which is controlled by the controller 1304 to extract matrix data from the memory and perform multiplication operations.

[0273] In some implementations, the operation circuit 1303 includes multiple processing units (Process Engine, PE) inside. In some implementations, the operation circuit 1303 is a two-dimensional systolic array. The operation circuit 1303 can also be a one-dimensional systolic array or other electronic circuits capable of performing mathematical operations such as multiplication and addition. In some implementations, the operation circuit 1303 is a general-purpose matrix processor.

[0274] For example, assume there is an input matrix A, a weight matrix B, and an output matrix C. The operation circuit takes the corresponding data of matrix B from the weight memory 1302 and caches it on each PE in the operation circuit. The operation circuit takes the matrix A data from the input memory 1301 and performs matrix operation with matrix B, and the partial result or final result of the matrix is ​​stored in the accumulator 1308.

[0275] The unified memory 1306 is used to store input data and output data. The weight data is directly transferred to the weight memory 1302 through the direct memory access controller (DMAC) 1305. The input data is also transferred to the unified memory 1306 through the DMAC.

[0276] BIU stands for Bus Interface Unit, i.e., bus interface unit 1310 , which is used for interaction between AXI bus, DMAC and instruction fetch buffer (IFB) 1309 .

[0277] The bus interface unit 1310 (Bus Interface Unit, BIU for short) is used for the instruction fetch memory 1309 to obtain instructions from the external memory, and is also used for the storage unit access controller 1305 to obtain the original data of the input matrix A or the weight matrix B from the external memory.

[0278] DMAC is mainly used to transfer input data in the external memory DDR to the unified memory 1306 or to transfer weight data to the weight memory 1302 or to transfer input data to the input memory 1301.

[0279] The vector calculation unit 1307 includes multiple operation processing units, and further processes the output of the operation circuit 1303 when necessary, such as vector multiplication, vector addition, exponential operation, logarithmic operation, size comparison, etc. It is mainly used for non-convolutional / fully connected layer network calculations in neural networks, such as Batch Normalization, pixel-level summation, upsampling of feature planes, etc.

[0280] In some implementations, the vector calculation unit 1307 can store the processed output vector to the unified memory 1306. For example, the vector calculation unit 1307 can apply a linear function; or a nonlinear function to the output of the operation circuit 1303, such as linear interpolation of the feature plane extracted by the convolution layer, and then, for example, a vector of accumulated values ​​to generate an activation value. In some implementations, the vector calculation unit 1307 generates a normalized value, a pixel-level summed value, or both. In some implementations, the processed output vector can be used as an activation input to the operation circuit 1303, for example, for use in a subsequent layer in a neural network.

[0281] An instruction fetch buffer 1309 connected to the controller 1304 is used to store instructions used by the controller 1304;

[0282] Unified memory 1306, input memory 1301, weight memory 1302 and instruction fetch memory 1309 are all on-chip memories. External memories are private to the NPU hardware architecture.

[0283] The processor mentioned in any of the above places may be a general-purpose central processing unit, a microprocessor, an ASIC, or one or more integrated circuits for controlling the execution of the above program.

[0284] It should also be noted that the device embodiments described above are merely schematic, wherein the units described as separate components may or may not be physically separated, and the components displayed as units may or may not be physical units, that is, they may be located in one place, or they may be distributed over multiple network units. Some or all of the modules may be selected according to actual needs to achieve the purpose of the scheme of this embodiment. In addition, in the drawings of the device embodiments provided by the present application, the connection relationship between the modules indicates that there is a communication connection between them, which may be specifically implemented as one or more communication buses or signal lines.

[0285] Through the description of the above implementation mode, the technicians in the field can clearly understand that the present application can be implemented by means of software plus necessary general hardware, and of course, it can also be implemented by special hardware including special integrated circuits, special CPUs, special memories, special components, etc. In general, all functions completed by computer programs can be easily implemented by corresponding hardware, and the specific hardware structure used to implement the same function can also be various, such as analog circuits, digital circuits or special circuits. However, for the present application, software program implementation is a better implementation mode in more cases. Based on such an understanding, the technical solution of the present application is essentially or the part that contributes to the prior art can be embodied in the form of a software product, which is stored in a readable storage medium, such as a computer floppy disk, a U disk, a mobile hard disk, a ROM, a RAM, a disk or an optical disk, etc., including a number of instructions to enable a computer device (which can be a personal computer, a training device, or a network device, etc.) to execute the methods described in each embodiment of the present application.

[0286] In the above embodiments, all or part of the embodiments may be implemented by software, hardware, firmware or any combination thereof. When implemented by software, all or part of the embodiments may be implemented in the form of a computer program product.

[0287] The computer program product includes one or more computer instructions. When the computer program instructions are loaded and executed on a computer, the process or function described in the embodiment of the present application is generated in whole or in part. The computer may be a general-purpose computer, a special-purpose computer, a computer network, or other programmable devices. The computer instructions may be stored in a computer-readable storage medium, or transmitted from one computer-readable storage medium to another computer-readable storage medium. For example, the computer instructions may be transmitted from a website site, a computer, a training device, or a data center by wired (e.g., coaxial cable, optical fiber, digital subscriber line (DSL)) or wireless (e.g., infrared, wireless, microwave, etc.) mode to another website site, computer, training device, or data center. The computer-readable storage medium may be any available medium that a computer can store or a data storage device such as a training device, a data center, etc. that includes one or more available media integrations. The available medium may be a magnetic medium, (e.g., a floppy disk, a hard disk, a tape), an optical medium (e.g., a DVD), or a semiconductor medium (e.g., a solid-state drive (SSD)), etc.

Claims

1. A video encoding method, characterized in that: The method comprises: Get multiple video frames; Processing the multiple video frames through an encoder to obtain an encoding result; wherein the encoder includes a first network layer; the first network layer includes an inter-frame compression module, the multiple video frames include M first video frames and N second video frames, and the inter-frame compression module is used to fuse feature representations of the M first video frames into feature representations of the N second video frames to obtain N feature representations; According to the encoding result, video-related tasks are performed to obtain a processing result.

2. The method according to claim 1, characterized in that The video-related tasks are video retrieval, video question answering or video description generation.

3. The method according to claim 1 or 2, characterized in that: The step of fusing the feature representations of the M first video frames into the feature representations of the N second video frames includes: The feature representation of each of the M first video frames is fused to the feature representation of the second video frame that is most similar to the N second video frames.

4. The method according to any one of claims 1 to 3, characterized in that: The M first video frames are the M video frames having the lowest correlation with other video frames among the multiple video frames.

5. The method according to any one of claims 1 to 4, characterized in that: The first video frame and the second video frame are interlaced with each other in the plurality of video frames.

6. The method according to any one of claims 1 to 5, characterized in that: The fusion is average pooling.

7. The method according to any one of claims 1 to 6, characterized in that: The encoder includes a second network layer; the first network layer and the second network layer are the same or different network layers, the second network layer includes an intra-frame compression module, the multiple video frames include a third video frame, the third video frame includes X first image blocks and Y second image blocks, and the intra-frame compression module is used to fuse feature representations of the X first image blocks into feature representations of the Y second image blocks to obtain Y feature representations.

8. The method according to claim 7, characterized in that The step of fusing the feature representations of the X first image blocks into the feature representations of the Y second image blocks includes: The feature representation of each first image block in the X first image blocks is fused to the feature representation of the second image block that is most similar to the Y second image blocks.

9. The method according to claim 7 or 8, characterized in that: The X first image blocks are X image blocks having the lowest correlation with other image blocks among the multiple image blocks included in the third video frame.

10. The method according to any one of claims 7 to 9, characterized in that: The first image block and the second image block are interlaced with each other in the third video frame.

11. A video encoding device, characterized in that: The device comprises: An acquisition module, used for acquiring multiple video frames; A processing module, configured to process the plurality of video frames through an encoder to obtain an encoding result; wherein the encoder includes a first network layer; the first network layer includes an inter-frame compression module, the plurality of video frames include M first video frames and N second video frames, and the inter-frame compression module is configured to fuse feature representations of the M first video frames into feature representations of the N second video frames to obtain N feature representations; According to the encoding result, video-related tasks are performed to obtain a processing result.

12. The device according to claim 11, characterized in that The video-related tasks are video retrieval, video question answering or video description generation.

13. The device according to claim 11 or 12, characterized in that The processing module is specifically used for: The feature representation of each first video frame in the M first video frames is fused to the feature representation of the second video frame that is most similar to the N second video frames.

14. The device according to any one of claims 11 to 13, characterized in that: The M first video frames are the M video frames with the lowest correlation with other video frames among the multiple video frames.

15. The device according to any one of claims 11 to 14, characterized in that: The first video frame and the second video frame are interlaced with each other in the plurality of video frames.

16. The device according to any one of claims 11 to 15, characterized in that The fusion is average pooling.

17. The device according to any one of claims 11 to 16, characterized in that The encoder includes a second network layer; the first network layer and the second network layer are the same or different network layers, the second network layer includes an intra-frame compression module, the multiple video frames include a third video frame, the third video frame includes X first image blocks and Y second image blocks, and the intra-frame compression module is used to fuse feature representations of the X first image blocks into feature representations of the Y second image blocks to obtain Y feature representations.

18. The device according to claim 17, characterized in that The processing module is specifically used for: The feature representation of each first image block in the X first image blocks is fused to the feature representation of the second image block that is most similar to the Y second image blocks.

19. The device according to claim 17 or 18, characterized in that The X first image blocks are X image blocks having the lowest correlation with other image blocks among the multiple image blocks included in the third video frame.

20. The device according to any one of claims 17 to 19, characterized in that The first image block and the second image block are interlaced with each other in the third video frame.

21. A computer storage medium, characterized in that The computer storage medium stores one or more instructions which, when executed by one or more computers, cause the one or more computers to perform the operations of the method of any one of claims 1 to 10.

22. A computer program product, characterized in that The method comprises computer-readable instructions, and when the computer-readable instructions are executed on a computer device, the computer device is caused to execute the method according to any one of claims 1 to 10.

23. A system comprising at least one processor and at least one memory; the processor and the memory are connected via a communication bus and communicate with each other; The at least one memory is used to store code; The at least one processor is configured to execute the code to perform the method according to any one of claims 1 to 10.

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