Image sensor, image sensing circuit, and image processing method

Abstract

The present disclosure provides an image sensor, an image sensing circuit and an image processing method. The image sensor comprises: a plurality of pixel rows arranged in a first direction, each of the pixel rows comprising a plurality of pixels arranged in a second direction intersecting the first direction; the plurality of pixel rows are configured to: in a counting mode, count received photons to obtain a count value; in a transfer mode, perform a plurality of transfer operations such that the count value of each of the pixel rows is transferred and output row by row; wherein in each of the transfer operations, the count value of each of the pixel rows other than a last pixel row is transferred to a next pixel row, the count value of the last pixel row is output, and the count value of each of the pixel rows other than a first pixel row is replaced by a count value from a previous pixel row.

Description

TECHNICAL FIELD

[0001] The present disclosure relates to the technical field of image processing, and particularly relates to an image sensor, an image sensing circuit and an image processing method. BACKGROUND

[0002] With the development of SPAD (Single Photon Avalanche Diode) device manufacturing technology and integrated circuits, PCI (Single Photon Counting Imaging) technology based on SPAD is applied. In a PCI image sensor, each pixel unit has an independent SPAD and a counting circuit, and the pixel unit is copied and expanded into a pixel array. Meanwhile, components such as a readout circuit and a control circuit are connected outside the pixel array to jointly constitute a PCI image sensor that can capture a target optical image. Frame rate (the number of output images per unit time) is one of the important performance indicators of an image sensor, and improving the frame rate of an image sensor is a key technical problem in the field. SUMMARY

[0003] Embodiments of the present disclosure provide an image sensor, an image sensing circuit and an image processing method.

[0004] In a first aspect, embodiments of the present disclosure provide an image sensor, comprising: a plurality of pixel rows arranged in a first direction, each of the pixel rows comprising a plurality of pixels arranged in a second direction intersecting the first direction; the plurality of pixel rows are configured to:

[0005] In the counting mode, counting received photons to obtain a count value;

[0006] In the transfer mode, a plurality of transfer operations are performed, so that the count value of each of the pixel rows is transferred and output row by row; wherein in each of the transfer operations, the count value of each of the pixel rows except the last pixel row is transferred to the next pixel row, the count value of the last pixel row is output, and the count value of each of the pixel rows except the first pixel row is replaced by the count value from the previous pixel row.

[0007] In a second aspect, embodiments of the present disclosure provide an image sensing circuit applied to an image sensor, the image sensor comprising a plurality of pixel rows arranged in a first direction, each of the pixel rows comprising a plurality of pixels arranged in a second direction intersecting the first direction;

[0008] The image sensor has a counting mode and a transfer mode, and the image sensing circuit comprises a counting circuit and a transfer circuit;

[0009] When the image sensor is in the counting mode, the plurality of pixel rows count received photons through the counting circuit to obtain a count value;

[0010] When the image sensor is in the transfer mode, the plurality of pixel rows are subjected to a plurality of transfer operations by the transfer circuit, so that the count values of each of the pixel rows are transferred and output row by row; wherein in each of the transfer operations, the count values of each of the pixel rows except the last pixel row are transferred to the next pixel row, the count value of the last pixel row is output, and the count values of each of the pixel rows except the first pixel row are replaced by the count values from the previous pixel row.

[0011] In a third aspect, the embodiments of the present disclosure provide an image processing method of an image sensor, the image sensor comprising a plurality of pixel rows arranged in a first direction, each of the pixel rows comprising a plurality of pixels arranged in a second direction intersecting the first direction; the processing method comprising:

[0012] In the counting mode, the plurality of pixel rows count received photons to obtain count values;

[0013] In the transfer mode, the plurality of pixel rows are subjected to a plurality of transfer operations, so that the count values of each of the pixel rows are transferred and output row by row; wherein in each of the transfer operations, the count values of each of the pixel rows except the last pixel row are transferred to the next pixel row, the count value of the last pixel row is output, and the count values of each of the pixel rows except the first pixel row are replaced by the count values from the previous pixel row.

[0014] In the embodiments of the present disclosure, in one imaging process, the plurality of pixel rows are exposed simultaneously, and the count values of each of the plurality of pixel arrays reflect the light intensity information of a single point, and the count values of the plurality of pixel rows can feed back the light intensity information of the multiple rows of images, and depict the digital image corresponding to the multiple rows of images. After the plurality of pixel rows complete the exposure at one time, the plurality of pixel rows start to be subjected to the plurality of transfer operations synchronously. In each of the transfer operations, the count values of each of the pixel rows are transferred to the next pixel row, and each of the pixel rows receives the count values from the previous pixel row. In this way, through N transfer operations, the count values of N pixel rows are transferred row by row, and the light intensity information of N rows of images can be obtained. Compared with the prior art, in order to obtain the light intensity information of N rows of images, the number of transfer operations is In the embodiments of the present disclosure, the number of transfer operations can be greatly reduced, and thus the readout time is shortened, the frame rate of the image sensor is improved, and better visual experience is provided for users. BRIEF DESCRIPTION OF DRAWINGS

[0015] Figure 1 A schematic diagram of an image sensor provided by the embodiments of the present disclosure is shown, which comprises a pixel array and a readout circuit.

[0016] Figure 2 For Figure 1 Partial enlarged view of the middle pixel array.

[0017] Figure 3 Schematic diagram of the image sensor provided by the embodiment of the present disclosure Figure 1 .

[0018] Figure 4 Schematic diagram of the image sensor provided by the embodiment of the present disclosure Figure 2 .

[0019] Figure 5 Schematic diagram of the image sensor provided by the embodiment of the present disclosure Figure 3 .

[0020] Figure 6 The logic relationship table between the first control signal, the count indication signal and the control count signal provided by the embodiment of the present disclosure.

[0021] Figure 7 The schematic diagram of the overflow feedback circuit provided by the embodiment of the present disclosure.

[0022] Figure 8 The logic relationship table between the count indication signal, the count pulse signal and the count trigger signal provided by the embodiment of the present disclosure.

[0023] Figure 9 The schematic diagram of the count feedback circuit provided by the embodiment of the present disclosure.

[0024] Figure 10 Schematic diagram of the image sensor provided by the embodiment of the present disclosure Figure 4 .

[0025] Figure 11 The schematic diagram of the asynchronous count structure of the image sensor provided by the embodiment of the present disclosure.

[0026] Figure 12 The schematic diagram of the synchronous transfer structure of the image sensor provided by the embodiment of the present disclosure.

[0027] Figure 13 The working timing diagram of the image sensor provided by the embodiment of the present disclosure.

[0028] Figure 14 The flowchart of the image processing method provided by the embodiment of the present disclosure. DETAILED DESCRIPTION

[0029] Example embodiments of the present disclosure will be described below in greater detail with reference to the accompanying drawings. While example embodiments of the present disclosure are shown in the drawings, it is to be understood that the present disclosure can be embodied in various forms without being limited to specific embodiments set forth herein. Rather, these embodiments are provided so that the present disclosure will be thorough and complete, and will fully convey the scope of the present disclosure to those skilled in the art.

[0030] In the following description, numerous specific details are set forth in order to provide a thorough understanding of the present disclosure. It will be apparent, however, to one skilled in the art that the present disclosure can be practiced without one or more of these specific details. In other instances, well-known features are not described in detail in order to avoid obscuring the present disclosure. In this description, references to "one embodiment" or "an embodiment" mean that a particular feature, structure, or characteristic described is included in at least one embodiment. The appearances of the phrase "in one embodiment" in various places in the specification are not necessarily all referring to the same embodiment.

[0031] In the drawings, like reference numerals refer to like elements throughout.

[0032] It is to be understood that the spatially relative terms "beneath", "below", "lower", "under", "above", "upper" and the like, can be used herein for ease of description to describe one element or feature's relationship to another element(s) or feature(s) as illustrated in the figures. It will be understood that the spatially relative terms are intended to encompass different orientations of the device in use or operation in addition to the orientation depicted in the figures. For example, if the device in the figures is turned over, elements described as "below" or "beneath" other elements or features would then be oriented "above" or "over" the other elements or features. Thus, the exemplary term "below" can encompass both an orientation of above and below. The device can be otherwise oriented (rotated 90 degrees or at other orientations) and the spatially relative descriptors used herein interpreted accordingly.

[0033] The terminology used herein is for the purpose of describing particular embodiments only and is not intended to be limiting of the present disclosure. As used herein, the singular forms "a", "an" and "the" are intended to include the plural forms as well, unless the context clearly indicates otherwise. It will be further understood that the terms "comprises" and / or "comprising", when used in this specification, specify the presence of stated features, integers, steps, operations, elements, and / or components, but do not preclude the presence or addition of one or more other features, integers, steps, operations, elements, components, and / or groups thereof. As used herein the term "and / or" includes any and all combinations of one or more of the associated listed items.

[0034] In a PCI image sensor, each pixel unit has an independent SPAD and counting circuit, and the pixel units are replicated and expanded into a pixel array (also referred to as a photosensitive region array). Meanwhile, components such as a readout circuit and a control circuit are connected outside the pixel array, and together constitute a PCI image sensor that can capture a target optical image.

[0035] Figure 1 A schematic diagram of an image sensor including a pixel array and a readout circuit is provided for embodiments of the present disclosure. Figure 2 For Figure 1 A partial enlarged view of the pixel array. As shown in Figure 1 , the image sensor includes a pixel array and a readout circuit. The pixel array includes a plurality of pixel rows ROW1, … ROW n-1 , ROW n , ROW n+1 and a plurality of pixel columns COL1, … COL n-1 , COL n , COL n+1 . The readout circuit includes a row selection module 10 and a shift register module 20. In the prior art, the row selection module 10 controls a row of pixels 30 to perform exposure and transfer of a counting value by controlling a row selection signal corresponding to the pixel row. For example, when ROW n row pixels are required to be exposed or the counting values in the ROW n row pixels are required to be transferred, the row selection module 10 enables the row selection signal corresponding to the ROW n row.

[0036] In the pixel array, adjacent pixels 30 in the same column have a cascading relationship to achieve transfer of the counting value, and the cascading relationship can be achieved by a selector. Specifically, as shown in Figure 2 , the output end of each pixel 30 in the pixel array is connected to the input end of a selector 40. In each column, the output end of the selector 40 corresponding to the previous pixel 30 is connected to the input end of the selector 40 corresponding to the next pixel 30. When the ROW n row is selected, the counting value in the pixel located at [ROW n , COL n ] is transferred to the pixel located at [ROW n-1 , COL n ]; then the ROW n-1 row is selected, and the counting value is transferred from the pixel located at [ROW n-1 , COL n ] to the pixel located at [ROW n-2 , COL n ]. In this way, the counting value is transferred to the pixel located at [ROW1, COL nThe pixel in the position is finally sampled by the downstream shift register module.

[0037] During the transfer, the count value of the ROW n is transferred to the ROW n-1 , and the delay of the ROW mux is D n , that is, the transfer delay of the selector. Finally, the count value of the ROW n is transferred out of the pixel array, which needs to be transferred for n times, so the delay of the count value of the ROW mux being transferred out of the pixel array is n*D sel +D sel , where D mux is the delay of the row selection signal.

[0038] By analogy, the readout delay for transferring an image of N rows is Taking an image of 1080P resolution as an example, N = 1080, assuming D mux is 0.5 ns, D sel is 5 ns, then the readout delay is about 300 us. In actual image sensors, D mux and D sel may be larger, and as the application requirement of image resolution develops, the value of N will be increased by 3-5 times, and the image readout delay will be further increased.

[0039] Frame rate is one of the important performance indicators of an image sensor. The frame rate can generally be represented as where T E is the exposure time, T readout is the readout time, that is, the readout delay, and T output is the output time. Too high readout time will seriously lower the frame rate of the image sensor, affecting the user's visual experience.

[0040] In view of this, the embodiment of the present disclosure provides an image sensor for shortening the readout time of an image. Figure 3 The schematic diagram of the image sensor provided by the embodiment of the present disclosure is shown in Figure 1 As shown in Figure 3 , the image sensor includes a pixel array, which includes a plurality of pixel rows Row and a plurality of pixel columns Col, the plurality of pixel rows Row are arranged in sequence in a first direction D1, and the plurality of pixel columns Col are arranged in sequence in a second direction D2 intersecting the first direction D1. Each pixel row Row includes a plurality of pixels 100 arranged along the second direction D2, each pixel column Col includes a plurality of pixels 100 arranged along the first direction D1, and in each pixel column Col, adjacent two pixels 100 are connected to each other.

[0041] The plurality of pixel rows Row are configured to: in a counting mode, count the received photons to obtain a count value; and in a transfer mode, perform a plurality of transfer operations, so that the count value of each pixel row is transferred row by row and output; wherein in each transfer operation, the count value of each pixel row except the last pixel row is transferred to the next pixel row, the count value of the last pixel row is output, and the count value of each pixel row except the first pixel row is replaced by the count value from the previous pixel row.

[0042] Figure 3 Three adjacent pixel rows Row n-1 , Row n , Row n+1 and three adjacent pixel columns Col n-1 , Col n , Col n+1 are shown, and the connection relationship and functions of the pixels in other pixel rows and other pixel columns can be analogized from the three pixel rows and three pixel columns. The pixel array shown in Figure 3 will be taken as an example to explain the scheme of the present disclosure in detail.

[0043] The imaging process includes an exposure phase and a transfer phase located after the exposure phase. The pixels have a counting mode in the exposure phase and have a transfer mode in the transfer phase. In the exposure phase, the plurality of pixel rows Row n-1 , Row n , Row n+1 simultaneously perform exposure, so that each pixel 100 counts the received photons and obtains a count value.

[0044] In the transfer phase, the plurality of pixel rows synchronously perform a plurality of transfer operations. Specifically, in each transfer operation, the count value of the last pixel row is output, and the count value of each pixel in each pixel row except the last pixel row is correspondingly transferred to the pixel in the same column in the next pixel row; and each pixel in each pixel row except the first pixel row correspondingly receives the count value from the pixel in the same column in the previous pixel row.

[0045] Here, the last pixel row refers to the pixel row whose count value is first output, and the first pixel row refers to the pixel row whose count value is last output. In an example, the last pixel row is the pixel row closest to a shift register (not shown in the figure) in a readout circuit, and the first pixel row is the pixel row farthest from the shift register. In the embodiment shown in Figure 3 , Row n-1 is the last pixel row, and Row n+1 is the first pixel row.

[0046] In the first transfer operation, the count values of Row n-1 are output to a shift register, the count values of Row n are transferred to Row n-1 , the count values of Row n+1 are transferred to Row n . Specifically, the count value of each pixel in Row n-1 is output to a shift register. The count value of the pixel in Row n located at [Row n , Col n-1 ] is transferred to the pixel at [Row n-1 , Col n-1 ], the count value of the pixel in Row n located at [Row n , Col n-1 ] is transferred to the pixel at [Row n , Col n ], and the count value of the pixel in Row n+1 located at [Row n-1 , Col n+1 ] is transferred to the pixel at [Row n+1 , Col n+1 ]. Similarly, the count values of the pixels in Row n-1 located at [Row n+1 , Col n ], [Row n+1 , Col n+1 ], and [Row n , Col n-1 ] are transferred to the pixels at [Row n , Col n ], [Row n , Col n+1 ], and [Row n-1 , Col n ], respectively. After the first transfer operation, the pixels in Row n hold the count values of the pixels in Row n+1 , the pixels in Row n-1 hold the count values of the pixels in Row n-1 , and the count values of the pixels in Row n are output.

[0047] In the second transfer operation, the count values of Row n held by Row n+1 are output to a shift register, and the count values of Row n-1Row. The specific steps are the same as the first transfer operation, that is, the count value of the pixel in the previous row is transferred to the pixel in the next row in the same column. After the second transfer operation is completed, Row n-1 Row. The count value of the pixel in Row n+1 Row is saved in Row n-1 Row. The count value of the pixel in Row n Row is output.

[0048] In the third transfer operation, the count value of the pixel in Row n-1 Row is saved in Row n+1 Row is output to the shift register. That is, after three transfer operations, the count values of the three rows of pixels are all output to the shift register. By analogy, N rows of pixels need to undergo N transfer operations to output all the count values.

[0049] As described above, in the prior art, N rows of pixels need to undergo transfer operations when imaging the imaging target, while in the embodiment, only N transfer operations are needed, greatly reducing the number of transfer operations and shortening the readout time.

[0050] In the embodiment, in one imaging process, multiple rows of pixels are exposed at the same time, and the count value of each pixel in the multiple pixel arrays reflects the light intensity information of a single point. The count values of multiple rows of pixels can reflect the light intensity information of multiple rows of images, and depict the digital image corresponding to the multiple rows of images. After the multiple rows of pixels complete exposure at one time, multiple transfer operations are performed synchronously. In each transfer operation, the count value of each row of pixels is transferred to the next row of pixels, and each row of pixels receives the count value from the previous row of pixels. In this way, through N transfer operations, the count values of N rows of pixels are transferred row by row, and the light intensity information of N rows of images can be obtained. Compared with the prior art, in order to obtain the light intensity information of N rows of images, N transfer operations are needed, while the scheme of the embodiment can greatly reduce the number of transfer operations, thereby shortening the readout time and improving the frame rate of the image sensor, thereby providing a better visual experience for the user.

[0051] In some embodiments, the multiple rows of pixels are configured to: enter a counting mode in response to a first control signal being in a first level state synchronously; and enter a transfer mode in response to the first control signal being in a second level state synchronously.

[0052] ​The first control signal, expo_en, is generated by a control circuit outside the pixel array. This first control signal, expo_en, is an exposure enable signal used to control the switching of pixels between counting mode and transfer mode. The first control signal, expo_en, can switch between a first level state and a second level state, that is, the exposure enable signal can switch between an active state and an inactive state. The first level may be higher than the second level, or lower than the second level; this disclosure does not limit this. For ease of understanding, the embodiments disclosed in this application are described using the example of the first control signal, expo_en, being in the first level state (expo_en indicating active exposure) and in the second level state (expo_en indicating inactive exposure).

[0053] like Figure 3 As shown, each pixel in the multiple pixel rows receives a first control signal `expo_en`, and the `expo_en` received by each pixel synchronously switches between a first level state and a second level state. When the `expo_en` received by each pixel synchronously switches to the first level state, all pixels in the multiple pixel rows are simultaneously in the exposure state and enter the counting mode. When the `expo_en` received by each pixel synchronously switches from the first level state to the second level state, all pixels in the multiple pixel rows are simultaneously in the non-exposure state and transition from the counting mode to the transfer mode.

[0054] In some embodiments, such as Figure 4 As shown, each pixel in multiple pixel rows can be coupled to the same signal source and receive the same first control signal, expo_en. Using the same first control signal makes it easier to simultaneously control multiple pixel rows for mode switching, and also improves the consistency of different pixels during mode switching, avoiding anomalies in the transfer operation due to inconsistent switching paces, thus improving the reliability of the transfer operation.

[0055] In some embodiments, the plurality of pixel rows are configured to: synchronously transfer count values ​​in response to a second control signal in a transfer mode; wherein the second control signal is a transfer clock signal comprising a plurality of periodic clock pulses, and the plurality of pixel rows perform a transfer operation in response to one clock pulse.

[0056] like Figure 3 As shown, each pixel in the multiple pixel rows receives a transfer clock signal clk_shift. The transfer clock signal clk_shift is generated by external control circuitry of the pixel array. The transfer clock signal clk_shift consists of multiple periodic clock pulses. Each pixel in the pixel array responds synchronously to the transfer clock signal, meaning that the rising edges and falling edges of the clock pulses received by each pixel are aligned with each other.

[0057] Multiple pixel rows respond to multiple clock pulses by performing multiple transition operations. This can be done by performing a transition operation once on the rising edge of each clock pulse, or by performing a transition operation once on the falling edge of each clock pulse; this disclosure does not impose any limitation on this. When N transition operations are required, at least N clock pulses are needed.

[0058] It should be noted that while a pixel can receive a transfer clock signal in transfer mode to perform count value transfer, this does not mean that the transfer clock signal can only be transmitted to the pixel when it is in transfer mode. In one embodiment, the control circuit can associate a first control signal with the transfer clock signal, so that the control circuit only transmits the transfer clock signal to the pixel when it enters transfer mode. In another embodiment, the control circuit may transmit the transfer clock signal to the pixel in both counting mode and transfer mode, but the pixel only responds to the transfer clock signal in transfer mode. In the first embodiment, the control circuit only transmits the transfer clock signal to the pixel in transfer mode, which reduces signal interference to the pixel and also reduces the pixel's power consumption. The second embodiment simplifies the design of the control circuit. In practical applications, any scheme can be adopted according to specific design requirements, and this disclosure does not impose any limitations.

[0059] In some embodiments, such as Figure 4 As shown, each pixel in the pixel array can be coupled to the same clock source and receive the same clock shift signal clk_shift, so that each shift operation can be performed synchronously under the control of the same clock shift signal clk_shift. In this embodiment, using the same shift clock signal clk_shift makes it easier to control multiple pixel rows to perform shift operations synchronously, avoiding the occurrence of abnormalities in the entire shift process due to the shift operation delay of individual pixel rows, thus improving the reliability of the shift operation.

[0060] Figure 5 Schematic diagram of the image sensor provided in the embodiments of this disclosure Figure 3 . Figure 5 This shows the structure of any three adjacent pixels in a certain pixel column, where the three pixels are located in the row. n-1 Row n Row and Row n+1 Yes. In some embodiments, such as Figure 5As shown, each pixel 100 includes a pixel cell 110 and a counter 120. The first input in1 of the counter 120 is coupled to the output of the pixel cell 110, and the second input in2 of the counter 120 is configured to receive a first control signal expo en. The pixel cell 110 generates a counting pulse signal photon pulse based on the received photons. The counter 120 enters a counting mode in response to the first control signal expo en being at a first level state, and counts the received counting pulse signal photon pulse to generate a count value. The counter 120 enters a shift mode in response to the first control signal expo en being at a second level state, and performs a shift operation in response to a second control signal (i.e., a shift clock signal clk shift).

[0061] For example, the pixel cell 110 includes a single-photon avalanche diode (SPAD) and a quenching circuit connected to the SPAD. When the pixel cell is exposed to light, the SPAD in a waiting state receives a light excitation, generates photo-generated electrons, and triggers an avalanche event. After the avalanche event occurs, the quenching circuit operates to quench the avalanche, and then the quenching circuit recharges the SPAD to restore it to the waiting state. In this process, the quenching circuit generates a digital signal pulse (i.e., a counting pulse) to the downstream counter. During the exposure phase, the SPAD repeatedly triggers an avalanche event, thereby generating a series of counting pulses, so that the count value of the counter continuously increases.

[0062] The counter 120 has two functional structures, one is an asynchronous counting structure, and the other is a synchronous shift structure. The counter is controlled by the first control signal expo en to switch between the counting mode and the shift mode, i.e., to select between the asynchronous counting structure and the synchronous shift structure. Specifically, when the first control signal is at the first level state, the counter selects the asynchronous counting structure and enters the counting mode. When the second control signal is at the second level state, the counter selects the synchronous shift structure and enters the shift mode. Here, the synchronous shift means that all pixel rows have data shift actions in one shift operation, i.e., the count value in the counter of the previous pixel row is shifted to the counter of the next pixel row in the adjacent two pixel rows.

[0063] In some embodiments, as shown in FIG. 2, the pixel array 100 includes a plurality of pixel rows 200, and each pixel row 200 includes a plurality of pixels 100. In some embodiments, as shown in FIG. 3, the pixel array 100 includes a plurality of pixel columns 300, and each pixel column 300 includes a plurality of pixels 100. Figure 5As shown, in each pixel row except the first pixel row, the third input terminal in3 of counter 120 is coupled to the first output terminal out1 of the corresponding counter 120 in the previous pixel row; in each pixel row except the last pixel row, the first output terminal out1 of counter 120 is coupled to the third input terminal in3 of the corresponding counter 120 in the next pixel row. In transfer mode, all counters 120 in multiple pixel rows perform multiple transfer operations; in each transfer operation, the counters 120 in each pixel row except the last pixel row transfer their count values ​​to the corresponding counter 120 in the next pixel row, and the counter 120 in the last pixel row outputs its count value; the count values ​​of the counters 120 in each pixel row except the first pixel row are replaced by the count values ​​transferred from the corresponding counter 120 in the previous pixel row.

[0064] by Figure 5 For example, Row consists of three pixels. n+1 The first output terminal out1 of the row counter is coupled to Row n The third input terminal in3 of the counter located in the same column of the row. n The first output terminal out1 of the row counter is coupled to Row n-1 The third input terminal in3 of the counter located in the same column of the row. n-1 The first output terminal out1 of the row counter is coupled to the shift register.

[0065] In transfer mode, only the counter in a pixel participates in the count value transfer. All counters across multiple pixel rows use a synchronous transfer structure and perform the count value transfer operation synchronously. Figure 5 For example, in the first transfer operation, Row... n-1 The counter in the row will output the count value. n The counter in the row transfers the count value to the row. n-1 OK n+1 The counter in the row transfers the count value to the row. n Okay. After the first transfer operation is completed, Row n-1 The row counter stores the original row. n The count value in the row counter, Row n The counter in the row stores the original row. n+1 The count value in the row counter, the original Row n-1 The count value in the row counter is output.

[0066] In the second transfer operation, Row n-1 The row counter will output the count value. nThe counter of the Row n-1 In the second transfer operation, the counter of the Row n-1 The counter of the Row n+1 The counter of the Row n The counter of the Row n-1 The counter of the Row

[0067] In the third transfer operation, the counter of the Row n-1 The counter of the Row n+1 The counter of the Row n The counter of the Row n-1 The counter of the Row

[0068] In some embodiments, when the transfer operation is performed, the third input end in3 of the counter 120 of the first pixel row is used to receive a reset value. The reset value is used to restore the first output end out1 of the counter 120 of the first pixel row to a default value. For example, the reset value can be a fixed value 0, so that the first output end out1 of the counter is reset to 0, that is, the state when the counter is not counting. In the transfer mode, through multiple transfer operations, the reset value 0 can be transferred from the counter of the first pixel row to the counter of the last pixel row row by row, so that the counter array of the entire pixel array can be automatically reset. It should be noted that the reset value can also be other values input through the third input end in3. The specific value can be set according to the measurement needs. For example, when the environment is relatively dark, the reflectivity of the imaging target is relatively small, or the imaging target is relatively far, the reset value can be a value greater than 0, so as to overall increase the counting base of the pixel array, so that the imaging is brighter and clearer. Conversely, when the environment is relatively bright, the reflectivity of the imaging target is relatively large, or the imaging target is relatively close, the reset value can be a value less than 0, so as to overall reduce the counting base of the pixel array, so that the imaging is not distorted due to overexposure.

[0069] In the embodiments of the present disclosure, taking the reset value received by the third input end in3 of the counter of the first pixel row as an example, the default value of the first output end out1 of the counter of the first pixel row is 0. Please refer to Figure 5 In the above first transfer operation, the third input end in3 of the counter of the Row n+1 The counter of the Row n+1 The counter of the Row n+1 The counter of the Row n The counter of the Row n The counter of the Row n+1The third input in3 of the row counter continues to receive the reset value 0, so that Row n+1 The row counter remains in the 0 state. In the third transfer operation, Row n The row counter transfers the 0 value to Row n-1 The row counter, Row n+1 The row counter transfers the 0 value to Row n The row counter, Row n+1 The third input in3 of the row counter continues to receive the reset value 0, so that Row n+1 The row counter remains in the 0 state. In this way, after three transfer operations, the original Row n+1 The row counter, Row n The row counter, Row n-1 The count values in the row counter are all output, and Row n+1 The row counter, Row n The row counter, Row n-1 The row counter is all reset to 0.

[0070] In this embodiment, by inputting a reset value to the third input in3 of the counter of the first pixel row, the count value transfer operation and the counter reset operation are performed at the same time, and when the transfer operation is completed, the counters of multiple pixel rows are reset synchronously, without the need for additional time to achieve the reset, which can shorten the operation time of the image sensor, and the counter can be automatically reset without the need to set an additional reset structure, which is conducive to reducing the area of the image sensor and saving costs.

[0071] For example, the third input in3 of the counter of the first pixel row can be fixed to receive a reset value, that is, the third input in3 is connected to a fixed voltage. For example, the third input in3 is grounded. In this way, without an additional reset signal, the circuit control can be simplified.

[0072] In some embodiments, as Figure 5 shown, each pixel further includes: an overflow feedback circuit 310 coupled to the second output out2 of the counter 120 and the control end of the pixel unit; the overflow feedback circuit 310 is configured to generate a control counting signal qch_en and output to the pixel unit 110 in response to the first control signal expo_en and the count indication signal OF output by the second output out2 of the counter 120. The pixel unit 110 is configured to generate a counting pulse signal based on the received photons in response to the control counting signal qch_en being in a first voltage state; or, stop generating the counting pulse signal in response to the control counting signal qch_en being in a second voltage state.

[0073] The count indication signal OF is used to indicate whether the count value of the counter is saturated. For example, the count indication signal OF also has a first level state and a second level state, one of which is used to indicate that the count is saturated, and the other is used to indicate that the count is not saturated. It should be noted that the saturation of the count value of the counter means that the count value reaches a preset target value, and does not mean that the count value must reach the maximum value of the counter.

[0074] It should be noted that the "first level state" and "second level state" in the present application are only used to represent two voltage states of different sizes, and are not limited to a specific voltage value. In other words, the first level state and the second level state of the first control signal, the count control signal, and the count indication signal are independent of each other and do not affect each other.

[0075] For example, the overflow feedback circuit 310, in response to the first control signal expo_en being in the first level state (i.e., the pixel is in the counting mode) and the count indication signal OF being in the first level state indicating that the count is not saturated, causes the control count signal qch_en to be in the first level state, allowing the pixel unit to generate the count pulse signal. In other cases, the pixel unit is prohibited from generating the count pulse signal.

[0076] For example, the overflow feedback circuit 310, in response to the count indication signal OF being in the second level state indicating that the count is saturated, causes the control count signal qch_en to be in the second level state, prohibiting the pixel unit from generating the count pulse signal. The overflow feedback circuit 310, in response to the first control signal expo_en being in the second level state (i.e., the pixel is in the transfer mode), causes the control count signal qch_en to be in the second level state to prohibit the pixel unit from generating the count pulse signal. That is, when the count indication signal OF indicates that the count is saturated or the pixel is in the transfer mode, the control count signal qcn_en prohibits the pixel unit from generating the count pulse signal.

[0077] It can also be understood that when the pixel is in the counting mode, the count saturation prohibits the pixel unit from generating the count pulse, and the count not saturated allows the pixel unit to generate the count pulse; when the pixel is in the transfer mode, whether the counter is saturated or not, the pixel unit is prohibited from generating the count pulse. Or it can be understood that when the count is not saturated, the pixel is in the counting mode to allow the pixel unit to generate the count pulse, and the pixel is in the transfer mode to prohibit the pixel unit from generating the count pulse; when the count is saturated, no matter which mode the pixel is in, the pixel unit is prohibited from generating the count pulse.

[0078] Under the premise of meeting the logical relationship among the first control signal expo_en, the count indication signal OF and the control count signal qch_en, since each of the three signals has two polarities (the first level state and the second level state), according to different pixel unit response modes (high level response, low level response, rising edge response or falling edge response), the polarity of the control count signal qch_en of the count pulse signal generated by the pixel unit is also different, and the polarity of qch_en is directly determined by the circuit structure of the overflow feedback circuit 310, the polarities of the first control signal expo_en and the count indication signal OF. Therefore, the specific circuit structure of the overflow feedback circuit 310 can be various. Figure 6 The following table provides the logical relationship among the first control signal expo_en, the count indication signal OF and the control count signal qch_en provided by the embodiment of the present disclosure. The following table is combined with Figure 6 Several overflow feedback circuits are provided, wherein the overflow feedback circuit can be determined based on the logical relationship.

[0079] Before providing the overflow feedback circuit, it is explained that the first control signal expo_en is valid to allow the pixel to enter the counting mode, and expo_en is invalid to prohibit the pixel from entering the counting mode, so that the pixel enters the transfer mode. The count indication signal OF is valid to prohibit the pixel unit from outputting the count pulse signal, and OF is invalid to allow the pixel unit to output the count pulse signal. The control count signal qch_en is valid to allow the pixel unit to output the count pulse, and qch_en is invalid to prohibit the pixel unit from outputting the count pulse.

[0080] It should be noted that in other embodiments, the count indication signal OF can be valid to allow the pixel unit to output the count pulse signal, and OF can be invalid to prohibit the pixel unit from outputting the count pulse signal. At this time, the logical relationship table among the first control signal expo_en, the count indication signal OF and the control count signal qch_en needs to be adjusted correspondingly, and the specific structure of the overflow feedback circuit can also be determined based on the adjusted logical relationship table.

[0081] In Example One, as Figure 6 and Figure 7As shown, the first control signal expo_en is configured to be low active, the count indication signal OF is configured to be high active, and the control count signal qch_en is configured to be high active, the logic expression among the three signals is: qch_en = ~ (expo_en | OF), then the overflow feedback circuit 310 can include an NOR gate, a first input end of the NOR gate receives expo_en, a second input end of the NOR gate is coupled to the second output end out2 of the counter 120 for receiving OF, and an output end of the NOR gate is coupled to a control end of the pixel unit 110 for outputting qch_en to the control end of the pixel unit. The NOR gate is configured to: in response to expo_en being low (active), OF being low (inactive), qch_en being high (active); in response to OF being high (active), qch_en being low (inactive); and in response to expo_en being high (inactive), qch_en being low (inactive).

[0082] In Example Two, compared with Example One, the count indication signal OF is modified to be low active, and the logic expression among the three signals is: qch_en = (~expo_en) & OF, then the overflow feedback circuit can include an NOR gate and an AND gate, an input end of the NOR gate receives expo_en, an output end of the NOR gate is coupled to a first input end of the AND gate, a second input end of the AND gate receives OF, and an output end of the AND gate outputs qch_en. Among them, the NOR gate outputs a high level in response to expo_en being low (active), and the AND gate makes qch_en high (active) in response to the high level output by the NOR gate and OF being high (inactive). The AND gate makes qch_en low (inactive) in response to OF being low (active). The NOR gate outputs a low level in response to expo_en being high (inactive), and the AND gate makes qch_en low (inactive) in response to the low level output by the NOR gate.

[0083] In Example Four, compared with Example Two, the first control signal expo_en is modified to be high active, and the logic expression among the three signals is: qch_en = expo_en & OF, then the overflow feedback circuit can include an AND gate, a first input end of the AND gate receives expo_en, a second input end of the AND gate receives OF, and an output end of the AND gate outputs qch_en. The AND gate is configured to: in response to expo_en being high (active) and OF being high (inactive), qch_en being high (active); in response to OF being low (active), qch_en being low (inactive); and in response to expo_en being low (inactive), qch_en being low (inactive).

[0084] In Example Five, compared with Example One, the control count signal qch_en is modified to be active low, and the logic expression among the three signals is qch_en = expo_en | OF. Then the overflow feedback circuit can include an OR gate, a first input of the OR gate receives expo_en, a second input of the OR gate receives OF, and an output of the OR gate outputs qch_en. The OR gate is configured to: in response to expo_en being low (active), OF being low (inactive), make qch_en low (active); in response to OF being high (active), make qch_en high (inactive); and in response to expo_en being high (inactive), make qch_en high (inactive).

[0085] In Example Eight, compared with Example One, the first control signal expo_en is modified to be active high, the count indication signal OF is modified to be active low, and the control count signal qch_en is modified to be active low. The logic expression among the three signals is qch_en = ~ (expo_en | OF). Then the overflow feedback circuit can include a NAND gate, a first input of the NAND gate receives expo_en, a second input of the NAND gate receives OF, and an output of the NAND gate outputs qch_en. The NAND gate is configured to: in response to expo_en being high (active), OF being high (inactive), make qch_en low (active); in response to OF being low (active), make qch_en high (inactive); and in response to expo_en being low (inactive), make the control count signal qch_en high (inactive).

[0086] Based on similar analysis, in Example Three, the overflow feedback circuit can include a NOT gate and an AND gate, an input of the NOT gate receives OF, an output of the NOT gate is coupled to a first input of the AND gate, a second input of the AND gate receives expo_en, and an output of the AND gate outputs qch_en. In Example Six, the overflow feedback circuit can include a NOT gate and an OR gate, an input of the NOT gate receives OF, an output of the NOT gate is coupled to a first input of the OR gate, a second input of the OR gate receives expo_en, and an output of the OR gate outputs qch_en. In Example Seven, the overflow feedback circuit can include a NOT gate and an OR gate, an input of the NOT gate receives expo_en, an output of the NOT gate is coupled to a first input of the OR gate, a second input of the OR gate receives OF, and an output of the OR gate outputs qch_en. The above-provided Examples One to Eight of the overflow feedback circuit are only examples and do not constitute a limitation on the overflow feedback circuit of the present disclosure. It should be understood that circuits replacing the logic gates in Examples One to Eight are also within the protection scope of the present disclosure. For example, an AND gate can be used to replace the NAND gate and the NOT gate.

[0087] For example, the overflow feedback circuit 310 is coupled to the quenching circuit in the pixel unit 110. The overflow feedback circuit turns off the quenching circuit after the counting saturation, and the quenching circuit no longer works so that the pixel unit no longer generates the counting pulse.

[0088] The overflow feedback circuit in the embodiments of the present disclosure can control the pixel unit to stop generating the counting pulse when the counter is saturated or the pixel enters the transition mode, thereby reducing the power consumption of the pixel unit.

[0089] In some embodiments, as shown in FIG. 3, each pixel further includes a counting feedback circuit 320, a first input end of the counting feedback circuit 320 is coupled to the second output end out2 of the counter, a second input end of the counting feedback circuit 320 is coupled to the output end of the pixel unit, and an output end of the counting feedback circuit 320 is coupled to the first input end in1 of the counter. Figure 5 The counting feedback circuit 320 is configured to: in response to the counting indication signal OF indicating that the counting is not saturated, allow the counting pulse signal photonpulse to enter the first input end in1 of the counter 120; and in response to the counting indication signal OF indicating that the counting is saturated (i.e., the OF signal is valid), prohibit the counting pulse signal photonpulse from entering the first input end in1 of the counter 120.

[0090] For example, the counting feedback circuit 120 is specifically configured to generate a counting trigger signal dlsb ck based on the counting indication signal OF and the counting pulse signal photonpulse and output to the first input end of the counter. When the counting indication signal OF is in a first level state indicating that the counting is not saturated, the counting feedback circuit 320 receives the counting pulse signal photonpulse and generates the counting trigger signal dlsb ck. Specifically, the counting feedback circuit 320 outputs a pulse (i.e., the counting trigger signal dlsb ck) for each received counting pulse signal. When the counting indication signal OF is in a second level state indicating that the counting is saturated, the counting feedback circuit 320 masks the counting pulse signal photonpulse and no longer outputs a pulse.

[0091] Under the premise that the counting feedback circuit 320 meets the above requirements, since the counting indication signal OF, the counting pulse signal photonpulse and the counting trigger signal dlsb ck all have two polarities, the specific circuit structure of the counting feedback circuit 320 can be various. Figure 8 The present disclosure provides a table of logical relationships among the counting indication signal OF, the counting pulse signal photonpulse and the counting trigger signal dlsb ck. The following will be described in combination with Figure 8 Several counting feedback circuits are provided, wherein the counting feedback circuit can be determined based on the logical relationship.

[0092] Before the embodiments are described in detail, the disclosure is first defined as follows. For example, if the counting pulse signal photonpulse (hereinafter simply written as pulse) is set to high level by default, when it is switched from high level to low level and then back to high level, a counting pulse is formed, then the counting pulse signal is called low level active, and the formed counting pulse is a negative pulse. Correspondingly, if the counting pulse signal pulse is set to low level by default, when it is switched from low level to high level and then back to low level, a counting pulse is formed, then the counting pulse signal is called high level active, and the formed counting pulse is a positive pulse.

[0093] Similarly, the counting trigger signal dlsb ck can also be low level active with a negative pulse, or high level active with a positive pulse.

[0094] In Example Nine, as shown in FIG. 9, the counting pulse signal pulse is low level active, the counting indication signal OF is high level active, and the counting trigger signal dlsb ck is high level active, then the logic expression is dlsb ck = ~(pulse | OF). In this configuration, the counting feedback circuit 320 includes an NOR gate, a first input end of the NOR gate is coupled to the second output end out2 of the counter 120 for receiving OF, a second input end of the NOR gate is coupled to the output end of the pixel unit 110 for receiving pulse, and an output end of the NOR gate is coupled to the first input end in1 of the counter 120 for outputting dlsb ck. The NOR gate is configured to: in response to OF being low level (invalid), the counting pulse signal pulse having a negative pulse, then the counting trigger signal dlsb ck having a positive pulse; in response to OF being high level (valid), no pulse being outputted. Figure 8 Figure 9 In Example Ten, compared with Example Nine, the counting indication signal OF is modified to be low level active, then the logic expression is dlsb ck = (~pulse) & OF. Then the counting feedback circuit can include an NOT gate and an AND gate, an input end of the NOT gate receiving pulse, an output end of the NOT gate being coupled to a second input end of the AND gate, a first input end of the AND gate receiving OF, and an output end of the AND gate outputting dlsb ck. Among them, the NOT gate outputs a positive pulse in response to the pulse having a negative pulse (active), and the AND gate outputs a positive pulse in response to OF being high level (invalid) and the NOT gate outputting a positive pulse. The AND gate does not output a pulse in response to OF being low level (active).

[0095] In Example Ten, compared with Example Nine, the counting indication signal OF is modified to be low level active, then the logic expression is dlsb ck = (~pulse) & OF. Then the counting feedback circuit can include an NOT gate and an AND gate, an input end of the NOT gate receiving pulse, an output end of the NOT gate being coupled to a second input end of the AND gate, a first input end of the AND gate receiving OF, and an output end of the AND gate outputting dlsb ck. Among them, the NOT gate outputs a positive pulse in response to the pulse having a negative pulse (active), and the AND gate outputs a positive pulse in response to OF being high level (invalid) and the NOT gate outputting a positive pulse. The AND gate does not output a pulse in response to OF being low level (active).

[0096] ​In Example Twelve, compared with Example Ten, the counting pulse signal pulse is modified to be high active, and the logic expression is dlsb ck = pulse & OF. In this configuration, the counting feedback circuit 320 can include an AND gate, the first input of the AND gate receives the OF, the second input receives the pulse, and the output outputs the counting trigger signal dlsb ck. The AND gate is configured to output a positive pulse of the counting trigger signal dlsb ck in response to the OF being high (inactive) and the counting pulse signal pulse having a positive pulse, and not output a pulse in response to the OF being low (active).

[0097] In Example Thirteen, compared with Example Nine, the counting trigger signal dlsb ck is modified to be low active, and the logic expression is dlsb ck = pulse | OF. In this configuration, the counting feedback circuit 320 can include an OR gate, the first input of the OR gate receives the OF, the second input receives the pulse, and the output outputs the counting trigger signal dlsb ck. The OR gate is configured to output a negative pulse of the counting trigger signal dlsb ck in response to the OF being low (inactive) and the counting pulse signal pulse having a negative pulse, and not output a pulse in response to the OF being high (active).

[0098] In Example Sixteen, compared with Example Nine, the counting pulse signal pulse is modified to be high active, the counting indication signal OF is modified to be low active, and the counting trigger signal dlsb ck is modified to be low active, and the logic expression is dlsb ck = ~ (pulse & OF). In this configuration, the counting feedback circuit 320 can include a NAND gate, the first input of the NAND gate receives the OF, the second input receives the pulse, and the output outputs the counting trigger signal dlsb ck. The NAND gate is configured to output a negative pulse of the counting trigger signal dlsb ck in response to the OF being high (inactive) and the counting pulse signal pulse having a positive pulse, and not output a pulse in response to the OF being low (active).

[0099] Based on similar analysis, in Example 11, the counting feedback circuit may include a NOT gate and an AND gate. The input of the NOT gate receives OF, the output of the NOT gate is coupled to the first input of the AND gate, the second input of the AND gate receives pulse, and the output of the AND gate outputs dlsb_ck. In Example 14, the counting feedback circuit may include a NOT gate and an OR gate. The input of the NOT gate receives OF, the output of the NOT gate is coupled to the first input of the OR gate, the second input of the OR gate receives pulse, and the output of the OR gate outputs dlsb_ck. In Example 15, the counting feedback circuit may include a NOT gate and an OR gate. The input of the NOT gate receives pulse, the output of the NOT gate is coupled to the second input of the OR gate, the first input of the OR gate receives OF, and the output of the OR gate outputs dlsb_ck. Examples 9 to 16 of the counting feedback circuits provided above in this disclosure are merely examples and do not constitute a limitation on the overflow feedback circuits of this disclosure. It should be understood that circuits that can replace the logic gates in Examples 9 to 16 are also within the scope of protection of this disclosure. For example, an AND gate can be used to replace a NAND gate and a NOT gate.

[0100] The counting feedback circuit in this embodiment can prevent the counting pulse signal from entering the first input terminal of the counter after the counter is saturated, thereby reducing the power consumption of the counter.

[0101] Figure 10 Schematic diagram of the image sensor provided in the embodiments of this disclosure Figure 4 In some embodiments, such as Figure 10 As shown in Figure (a), the counter (e.g., Figure 5 , Figure 7 and Figure 9 The counter 120 in the middle includes multiple cascaded trigger units, each trigger unit including a first selector 210, a second selector 220 and a trigger 230.

[0102] In each trigger unit, the clock input of trigger 230 is coupled to the output of the first selector 210, the input D of trigger 230 is coupled to the output of the second selector 220, and the output Q of trigger 230 is connected to the second selector 220 of the corresponding trigger unit of the counter in the next pixel row. The outputs Q of all triggers 230 in the counter constitute the first output out1 of the counter, used to output the count value. The output Q of the trigger in the last stage of the counter is either the clock input or the inverted output. It also forms the second output terminal out2 of the counter, which is used to output the count indication signal OF.

[0103] Figure 10Figure (b) is a partial enlarged view of the first selector 210 and the second selector 220. As shown in Figure (b), the control terminals of the first selector 210 and the second selector 220 are connected to the first control signal expo_en, so that expo_en can control the signal input of each trigger 230 in the counter through the first selector 210 and the second selector 220, thereby controlling the counter to switch between counting mode and switching mode.

[0104] In each counter, the first input of the first selector 210 in all trigger units is used to receive the second control signal clk_shift. The second input of the first selector 210 of the first-stage trigger unit serves as the first input in1 of the counter, used to receive the counting pulse signal after passing through the counting feedback circuit 320, i.e., the counting trigger signal dlsb_clk. The second input of the first selector 210 of each stage of the trigger unit other than the first-stage trigger unit is coupled to the output Q of the flip-flop of the previous stage trigger unit.

[0105] The first input terminals of the second selectors 220 in all trigger units of the counter constitute the third input terminal in3 of the counter, used to receive the count value of the corresponding counter in the previous pixel row, thereby realizing the count value transfer. The second input terminals of the second selectors 220 in each of the trigger units except the last stage are coupled to the inverted output terminal of the flip-flop in that stage of the trigger unit. The second input of the second selector 220 of the last-stage trigger unit is used to receive a preset value.

[0106] This embodiment uses the output Q of the flip-flop in the last stage of the trigger unit as an example to illustrate the second output, out2, of the counter. In counting mode, in the last stage of each counter, when the clock terminal of the flip-flop 230 receives a pulse from the output of the previous stage trigger unit, the preset value received by the second selector 220 is used to flip the signal at the output Q of the flip-flop, thereby switching the counting indication signal OF from a first level indicating that the count is not saturated to a second level indicating that the count is saturated. For example, as... Figure 10 As shown, the preset value is 1, that is, the second input terminal of the second selector 220 receives a fixed high level, causing the output terminal of the flip-flop to flip from 0 to 1, indicating that the count is saturated.

[0107] Here, it should be noted that, in Figure 6 In Example 3, when the count indicator signal is active high, the aforementioned overflow feedback circuit 310 includes NOT gates and AND gates. Another implementation uses the inverted output of the flip-flop in the last stage trigger unit. The second output terminal out2 of the counter makes the counting indication signal active low. Therefore, as in Example 4, the overflow feedback circuit can use only an AND gate. In other words, to simplify the structure of the overflow feedback circuit 310, either the output terminal Q of the flip-flop in the last stage trigger unit or the inverted output terminal can be selected. The second output terminal of the counter is out2.

[0108] Furthermore, it should be noted that in other embodiments, the second input terminal of the second selector 220 of the last stage triggering unit can also be coupled to the inverted output terminal of the trigger in the same stage triggering unit. This replaces the preset value to achieve the effect of flipping the output terminal Q. In this case, the output terminal Q of the flip-flop in the last stage trigger unit or the inverted output terminal can still be used. The second output terminal out2 of the counter is formed.

[0109] For example, the type of trigger can be a D flip-flop (DFF). It should be understood that in other embodiments, the trigger can also be an RS flip-flop, a JK flip-flop, etc. This disclosure does not limit the type of trigger; any trigger in the art that can be combined to form a counter can be applied to this disclosure. In practical applications, a suitable trigger can be selected according to design requirements. Furthermore, the trigger can be rising-edge triggered or falling-edge triggered. This disclosure does not limit this.

[0110] exist Figure 10 In the example, the trigger is a falling-edge triggered D flip-flop. In another embodiment, if a rising-edge triggered D flip-flop is used, the inverted output of flip-flop 230 in each stage of the triggering unit, except for the last stage, is... It is connected to the second input terminal of the first selector 210 in the next stage trigger unit. That is, in Figure 11 In the asynchronous counting structure shown, the inverted output terminal of the flip-flop 230 in other trigger units is... The clock terminal of the trigger 230 in the next stage trigger unit is connected to the clock terminal, and the output terminal Q of the trigger 230 is connected to the second input terminal of the second selector 220 in this stage trigger unit.

[0111] The counter implements its counting function through multiple flip-flops 230. Among the multiple flip-flops 230, the flip-flop located at the lowest bit of the counter is DLSB, which is the flip-flop in the first-stage trigger unit. The flip-flop located at the highest bit of the counter is DMSB, which is the flip-flop in the last-stage trigger unit.

[0112] Figure 11This is a schematic diagram of the asynchronous counting structure of an image sensor. When the first control signal expo_en is at the first level (valid), the counter enters the counting mode: each first selector 210 turns on its second input and output (i.e., turns on the output Q of the previous stage flip-flop and the clock input of the current stage flip-flop, so that the signal output by the output Q of the previous stage flip-flop can be used as the clock signal of the current stage flip-flop), and each second selector 220 turns on its second input and output (i.e., turns on the inverted output of the current stage flip-flop). The input terminal D is used to invert the output terminal of this stage of the flip-flop. The output signal can be used as the trigger signal for the flip-flop in this stage, enabling the counter to have an asynchronous counting structure. For example... Figure 11 As shown, when the counter adopts an asynchronous counting structure, there is no cascading relationship between the counters of different pixels in each column. In the counter of each pixel, multiple flip-flops DLSB, D1, D2...DMSB are connected to form a traveling wave asynchronous counter circuit.

[0113] During the pixel exposure stage, in pixel unit 110, the SPAD in the waiting state is photoexcited, generating photogenerated electrons and causing an avalanche event. After the avalanche event, the quenching circuit operates to extinguish the avalanche, and then the quenching circuit recharges the SPAD to return it to the waiting state. During this process, the quenching circuit also generates a pulse to counter 120. The DLSB of counter 120 receives this pulse, causing the count value of the entire traveling wave counting circuit to increase by 1.

[0114] During the exposure phase, the SPAD repeatedly generates avalanche events, causing the counter 120's count value to continuously increase. The last flip-flop of counter 120, DMSB, acts as an overflow protection register; when the signal at the DMSB's output Q or its inverted output... When the signal flips from its default value to a preset value, it indicates that all the preceding trigger counts have reached their maximum, signifying that the counter is saturated. For example, the output Q of the DMSB is used to output the count indication signal OF, whose default value is 0 and preset value is 1. In this embodiment, when the DMSB flips from 0 to 1, it indicates that the count is saturated.

[0115] See also Figure 11 After the output Q signal of the DMSB is flipped to 1, it serves as a count saturation flag. On the one hand, the overflow feedback circuit 310 switches the control count signal qch_en to the second level state, which means turning off the enable signal of the quenching circuit, so that the SPAD no longer generates avalanche events and therefore no longer generates count pulse signals. On the other hand, the count feedback circuit 320 shields the count pulse signal, so that the count pulse signal cannot be transmitted to the clock terminal of the DLSB, so that the counter will no longer work.

[0116] After the exposure phase is completed, the counter of each pixel stores the number of pulses detected in the exposure phase, i.e. the light intensity representation of the optical target.

[0117] The working mode of the counter 120 is described in detail as follows. When the first control signal expo_en is in the first level state (for example, the low level is effective to make the counter enter the counting mode), the first selector 210 and the second selector 220 are both turned on, so that the Q end of the flip-flop DFF n is connected to the clock end of the next-stage DFF n+1 , serving as the counting clock of the DFF n+1 ; the n end of the DFF is connected to the D end of the DFF itself.

[0118] In the embodiment, the DFF is all a falling edge flip-flop. Before the first falling edge of the counting clock of the DFF n occurs, the signal of the Q end is 0, and the signal of the n end is 1; after the first falling edge occurs, the Q end is flipped to 1, and the n+1 end is flipped to 0; at this time, the signal of the Q end of the DFF n serves as the signal of the clock end of the DFF n+1 , and an up edge jump from 0 to 1 occurs, which does not trigger the DFF n .

[0119] After the second falling edge of the counting clock of the DFF n occurs, the Q end is flipped to 0, and the n+1 end is flipped to 1; at this time, the signal of the Q end of the DFF n serves as the signal of the clock end of the DFF n+1 , and a down edge jump from 1 to 0 occurs, which triggers the flipping of the Q end and the n end of the DFF n .

[0120] In this way, using the counting pulse signal emitted by the pixel unit as the counting clock of the DLSB, with the continuous generation of the counting pulse, the Q ends of the three flip-flops appear the incremental changes of 000 (DMSB, DFF1, DLSB) -> 001 -> 010 -> 011 -> 100 (binary representation) (decimal representation, 0->1->2->3->4).

[0121] When the DMSB in the last-stage flip-flop unit appears the flipping, the counter reaches saturation, the quenching circuit is closed through the overflow feedback circuit, the counting is closed through the counting feedback circuit, and the pixel enters the dormant state, saving the power consumption.

[0122] Figure 12This is a schematic diagram of the synchronous transfer circuit structure for an image sensor. (See also...) Figure 12 When the first control signal expo_en is in the second level state (e.g., a high level is invalid, causing the counter to enter transfer mode), the first selector of each trigger unit in the counter turns on its first input and its output, and the second selector turns on its first input and its output, such that [Row n Col n DFF of position pixels n The D-end connection and the previous row [Row] n+1 Col n The corresponding DFF of the pixel n The Q input of all DFFs is connected to a unified transfer clock signal clk_shift, and the counter has a synchronous transfer structure.

[0123] After establishing this cascaded pixel relationship, the control transfer clock signal clk_shift is toggled. Since the DFF flip-flop is a falling-edge triggered type, when the falling edge of the transfer clock signal clk_shift arrives, [Row...] n+1 Col n ] pixel DFF n The trigger transfers the count value to [Row] n Col n ] pixel DFF n Trigger. This transfer process occurs simultaneously for each row, meaning all pixels are connected to the same transfer clock signal, and the transfer of N rows of data is completed after N clock pulses. Where, Row n The row count value was completed over N clock pulses. n →Row n-1 →Row n-2 The transition from Row 1 to Row 2 to Row 1 to shift reg occurs over these N clock pulses. n-1 The row count value completes the Row n-1 →Row n-2 The data transfer proceeds from Row 1 to Row 2, then to Row 2, then to Row 1, then to Shift Reg. This process continues for N clock pulses, completing the transfer of N rows of data.

[0124] Therefore, in this disclosure, when N pixel rows perform one imaging of the imaging target, the image transfer time is: Tclk_shift represents the delay of one data transfer between two adjacent pixel rows, i.e., the transmission delay of the second selector 220. For a 1080P resolution image, N=1080, and the clk_shift frequency is 50MHz (T clk_shiftIf the readout time is 20ns, then the readout time is approximately 20us. Compared to the 300ns in the existing technology, the readout time is greatly shortened, thus significantly improving the image frame rate and enhancing the user's visual experience.

[0125] exist Figure 12 In the illustrated embodiment, the counter operates as follows: when the transfer clock signal clk_shift toggles by one cycle and a falling edge appears in clk_shift, Row... n DFF of the line n The count value stored in, i.e., DFF n The Q terminal transmits the count value to the Row. n-1 DFF of the line n The D end.

[0126] Instead of shifting only one row at a time when the clock signal clk_shift toggles by one cycle, all pixel rows are shifted down simultaneously, significantly improving efficiency. The last pixel row, Row1, is then shifted down to a shift register outside the pixel array. Specifically, it is shifted into a shift register within a shift register, where it is then processed as needed.

[0127] Figure 13 This is a timing diagram of the operation of an image sensor provided in an embodiment of this disclosure. Figure 13 Showing Figure 10 The timing sequence of multiple signal and count value transfers in the corresponding image sensor. The first control signal is active low. For example... Figure 13 As shown, when the first control signal expo_en is set to 0, each selector conducts the corresponding path, causing the counter to use an asynchronous counting structure (or asynchronous counting path). Within each pixel row (as shown in rows N+2, N+1, and N in the figure), as shown at ① in the figure, each time a pixel unit responds to a photon, it triggers an avalanche event, which in turn triggers the quenching circuit to generate a counting pulse, and the corresponding counter increments by 1.

[0128] After a certain period of time, as shown in point ② of the figure, the first control signal expo_en is set to 1, the exposure ends, the quenching circuit is turned off, and no more counting pulses are generated. At the same time, each selector activates another path, causing the counter to use a synchronous transfer structure (or synchronous transfer path).

[0129] Next, as shown in Figure ③, the control circuit generates a continuous periodic transfer clock signal clk_shift; ③ represents the falling edge of the first period of the transfer clock signal clk_shift, and the count value P of the pixel in the (N+2)th row. N+2 The count value P of the pixels in row N+1 is passed to the pixels in row N+1. N+1 The count value P of the pixels in row N is passed to the pixels in row N.N The data of the first row of pixels is transferred to the Nth row of pixels; the same is true for the other rows of pixels, whose data is transferred to the next row, and the count value of the previous row is saved; the second period and the subsequent periods work in this way by analogy; all rows are transferred once in each period.

[0130] During the expo_en period 1, the shift clock signal clk_shift has multiple periods (i.e., multiple falling edges), and in some embodiments, the number of periods of the shift clock signal can be equal to the number N of rows of pixel rows, so that the pixels of the first row of pixels can be transferred to the last shift register and the counters of all rows of pixels are automatically reset to 0, as shown by the arrows in the figure. In other embodiments, the number of periods of the shift clock signal can be equal to the number N of rows of pixel rows plus 1, so that the counters of all rows of pixels are automatically reset to 0, and the shift register can also be automatically reset to 0.

[0131] As shown in Fig. 4 and Fig. 5, the data of the first row of pixels (the row of pixels farthest from the shift register) is fixed to 0, and in the subsequent transfer period, the data 0 is transferred to each pixel, achieving the function of resetting all pixel counters.

[0132] Figure 13 Assuming that the Nth row is the last row to be transferred, then as shown in Fig. 6, the count value P of the pixel of the Nth row is N The data is transferred to the shift register outside the pixel array. The downstream processing module will take away the data for processing in each transfer clock signal clk_shift period, and the data of the shift register is updated every period.

[0133] As shown in Fig. 7, after the transfer is completed, the first control signal expo_en is set to 0 again, and a new round of exposure counting and transfer process is started.

[0134] In summary, the image sensor provided by the embodiments of the present disclosure can complete exposure of N rows of pixels at a time, and after the one-time exposure is completed, all data is synchronously transferred, i.e., through 1 time of exposure and N times of transfer, the count values of N rows of pixels are all transferred out to obtain a digital image corresponding to the image. In addition, the image sensor further includes an overflow feedback circuit, which can inhibit the generation of a count pulse signal by a pixel unit after saturation of counting to reduce the power consumption of the pixel unit. The image sensor can further include a count feedback circuit, which can inhibit the count pulse signal from entering the counter to stop the operation of the counter after saturation of counting, thereby reducing the power consumption. It should be understood that the overflow feedback circuit and the count feedback circuit can be provided only one of them, or both. Furthermore, the image sensor can achieve automatic reset to 0 in the transfer operation, without the need to set an additional reset structure and reset signal, thereby saving circuit area, simplifying the circuit and reducing the cost.

[0135] The embodiment of the present disclosure further provides an image sensing circuit, which is applied to an image sensor, the image sensor comprising a plurality of pixel rows arranged in a first direction, each pixel row comprising a plurality of pixels arranged in a second direction intersecting the first direction; the image sensor has a counting mode and a transfer mode, and the image sensing circuit comprises a counting circuit and a transfer circuit. When the image sensor is in the counting mode, the plurality of pixel rows count received photons through the counting circuit to obtain counting values; when the image sensor is in the transfer mode, the plurality of pixel rows perform a plurality of transfer operations through the transfer circuit, so that the counting values of each pixel row are transferred and output row by row; in each transfer operation, the counting values of each pixel row except the last pixel row are transferred to the next pixel row, the counting value of the last pixel row is output, and the counting values of each pixel row except the first pixel row are replaced by the counting values from the previous pixel row.

[0136] The features of the image sensor provided by the embodiment of the present disclosure can be applied to the image sensing circuit, and have the same or similar technical effects. The present disclosure will not be repeated here.

[0137] The embodiment of the present disclosure provides an image processing method of an image sensor, Figure 14 For the flowchart of the image processing method provided by the embodiment of the present disclosure, the image sensor comprises a plurality of pixel rows arranged in a first direction, and each pixel row comprises a plurality of pixels arranged in a second direction intersecting the first direction. As shown in the figure, the image processing method comprises: Figure 14

[0138] S100: In the counting mode, the plurality of pixel rows count received photons to obtain counting values;

[0139] S200: In the transfer mode, the plurality of pixel rows perform a plurality of transfer operations, so that the counting values of each pixel row are transferred and output row by row; in each transfer operation, the counting values of each pixel row except the last pixel row are transferred to the next pixel row, the counting value of the last pixel row is output, and the counting values of each pixel row except the first pixel row are replaced by the counting values from the previous pixel row.

[0140] The image processing method described above on the image sensor side can be applied to the image processing method provided by the embodiment, and has the same or similar technical effects. The present disclosure will not be repeated here.

[0141] The features disclosed in the several device embodiments provided by the present disclosure can be combined arbitrarily without conflict, to obtain new device embodiments.

[0142] ​The above merely provides the specific implementation of the present disclosure, but the protection scope of the present disclosure is not limited thereto, and any person skilled in the art can easily think of the changes or replacements within the technical range disclosed by the present disclosure, which should be covered within the protection scope of the present disclosure.

Claims

1. An image sensor, characterized in that, include: Multiple pixel rows are arranged in a first direction, each pixel row comprising multiple pixels arranged in a second direction intersecting the first direction; The plurality of pixel rows are configured as follows: In counting mode, the received photons are counted to obtain a count value; In the transfer mode, multiple transfer operations are performed such that the count value of each pixel row is transferred and output row by row; wherein, in each transfer operation, the count value of each pixel row other than the last pixel row is transferred to the next pixel row, the count value of the last pixel row is output, and the count value of each pixel row other than the first pixel row is replaced by the count value from the previous pixel row.

2. The image sensor according to claim 1, characterized in that, The plurality of pixel rows are configured as follows: The system synchronously responds to the first control signal being at a first level state by entering the counting mode; and synchronously responds to the first control signal being at a second level state by entering the transfer mode.

3. The image sensor according to claim 2, characterized in that, The plurality of pixel rows are configured as follows: In the transfer mode, the multiple transfer operations are performed synchronously in response to a second control signal; wherein the second control signal is a transfer clock signal comprising a plurality of periodic clock pulses, and the plurality of pixel rows perform one transfer operation in response to one of the clock pulses.

4. The image sensor according to claim 3, characterized in that, Each pixel includes a pixel unit and a counter, wherein a first input terminal of the counter is coupled to the output terminal of the pixel unit, and a second input terminal of the counter is used to receive the first control signal; The pixel unit generates a counting pulse signal based on the received photons; The counter enters the counting mode in response to the first control signal being at a first level, counts the received counting pulse signals to generate the count value; and enters the transfer mode in response to the first control signal being at a second level.

5. The image sensor according to claim 4, characterized in that, In each of the pixel rows other than the first pixel row, the third input terminal of the counter is coupled to the first output terminal of the corresponding counter in the previous pixel row; in each of the pixel rows other than the last pixel row, the first output terminal of the counter is coupled to the third input terminal of the corresponding counter in the next pixel row. In the transfer mode, all counters of the plurality of pixel rows perform the transfer operation multiple times; wherein, in each transfer operation, the counters of each pixel row other than the last pixel row transfer the count value to the corresponding counter in the next pixel row, and the counter of the last pixel row outputs the count value; the count values ​​of the counters of each pixel row other than the first pixel row are replaced by the count value transferred from the corresponding counter in the previous pixel row.

6. The image sensor according to claim 5, characterized in that, During the transfer operation, the third input terminal of the counter of the first pixel row is used to receive a reset value.

7. The image sensor according to claim 4, characterized in that, Each pixel further includes: an overflow feedback circuit coupled to the second output terminal of the counter and the control terminal of the pixel unit; the overflow feedback circuit is configured to: generate a control counting signal and output it to the pixel unit in response to the first control signal and the counting indication signal output from the second output terminal of the counter; The pixel unit is configured to: generate a counting pulse signal based on the received photons in response to the control counting signal being at a first level; or, stop generating the counting pulse signal in response to the control counting signal being at a second level.

8. The image sensor according to claim 4, characterized in that, Each pixel further includes: a counting feedback circuit, wherein a first input terminal of the counting feedback circuit is coupled to a second output terminal of the counter, the second input terminal of the counting feedback circuit is coupled to the output terminal of the pixel unit, and the output terminal of the counting feedback circuit is coupled to the first input terminal of the counter; the counting feedback circuit is configured to: In response to the count indication signal output from the second output terminal of the counter indicating that the count is not saturated, the count pulse signal is allowed to enter the first input terminal of the counter; In response to the count indication signal indicating count saturation, the count pulse signal is prevented from entering the first input terminal of the counter.

9. The image sensor according to any one of claims 5 to 8, characterized in that, The counter includes multiple cascaded trigger units, each of which includes a first selector, a second selector, and a trigger. In each stage of the triggering unit, the clock terminal of the trigger is coupled to the output terminal of the first selector, the input terminal of the trigger is coupled to the output terminal of the second selector, the output terminal of the trigger is connected to the second selector of the corresponding triggering unit of the corresponding counter in the next pixel row, the output terminals of all the triggers in the counter constitute the first output terminal of the counter, and the output terminal or the inverted output terminal of the trigger of the last stage of the triggering unit in the counter also constitutes the second output terminal of the counter. The control terminals of the first and second selectors are connected to the first control signal. The first input terminal of the first selector is used to receive the second control signal; The second input terminal of the first selector of the first stage trigger unit serves as the first input terminal of the counter. The second input terminals of the first selectors of the other stage trigger units, excluding the first stage trigger unit, are coupled to the output terminal of the trigger of the previous stage trigger unit. The first input terminals of all the second selectors in the counter constitute the third input terminal of the counter; the second input terminals of all the second selectors are coupled to the inverted output terminal of the trigger in the same level of the trigger unit, or, the second input terminals of the second selectors in all other levels of the trigger unit except the last level of the trigger unit are coupled to the inverted output terminal of the trigger in the same level of the trigger unit, and the second input terminal of the second selector of the last level of the trigger unit is used to receive a preset value.

10. An image sensing circuit, applied in an image sensor, characterized in that, The image sensor includes a plurality of pixel rows arranged in a first direction, and each pixel row includes a plurality of pixels arranged in a second direction intersecting the first direction; The image sensor has a counting mode and a transfer mode, and the image sensing circuit includes a counting circuit and a transfer circuit. When the image sensor is in counting mode, the multiple pixel rows count the received photons through the counting circuit to obtain a count value; When the image sensor is in transfer mode, the plurality of pixel rows undergo multiple transfer operations through the transfer circuit, such that the count value of each pixel row is transferred and output row by row; wherein, in each transfer operation, the count value of each pixel row except the last pixel row is transferred to the next pixel row, the count value of the last pixel row is output, and the count value of each pixel row except the first pixel row is replaced by the count value from the previous pixel row.

11. An image processing method for an image sensor, characterized in that, The image sensor includes a plurality of pixel rows arranged in a first direction, and each pixel row includes a plurality of pixels arranged in a second direction intersecting the first direction; The image processing method includes: In counting mode, the multiple pixel rows count the received photons to obtain a count value; In the transfer mode, the plurality of pixel rows undergo multiple transfer operations, such that the count value of each pixel row is transferred and output row by row; wherein, in each transfer operation, the count value of each pixel row other than the last pixel row is transferred to the next pixel row, the count value of the last pixel row is output, and the count value of each pixel row other than the first pixel row is replaced by the count value from the previous pixel row.

Images