A method for manufacturing a circuit board, a double-sided and multilayer circuit board

Abstract

The application discloses a circuit board and a manufacturing method thereof, and relates to the technical field of electronic circuit additive manufacturing. The manufacturing method comprises the following steps: preparing a laminated body; the laminated body comprises a first insulating layer with vertically opposite first and second surfaces, and a metal foil layer formed on the first surface of the first insulating layer; etching the metal foil layer to form an etching circuit pattern; opening a first blind hole that penetrates through the first insulating layer and reaches the etching circuit pattern; forming a first printed circuit pattern on the second surface of the first insulating layer by using conductive paste, and filling the first blind hole to form a first conductive column that realizes conductive interconnection between the first printed circuit pattern and the etching circuit pattern; and electroplating the first printed circuit pattern to form a first plated circuit pattern. The application can effectively improve the production efficiency of the circuit board, and reduce the waste and pollution treatment cost by combining the printing process with the etching process.

Description

Technical Field

[0001] This invention belongs to the field of electronic circuit additive manufacturing technology, and particularly relates to a method for manufacturing circuit boards, and double-sided and multi-layer circuit boards. Background Technology

[0002] Most double-sided or multi-layer circuit boards on the market are manufactured using chemical etching technology. Although this technology is mature and can meet the requirements for producing high-precision circuit patterns, it results in low production efficiency, significant environmental pollution, and high costs for waste materials and pollution treatment. Summary of the Invention

[0003] In view of this, one objective of the present invention is to provide a method for manufacturing circuit boards, and double-sided and multi-layer circuit boards, thereby solving the problems of low production efficiency, high environmental pollution, and high waste and pollution treatment costs of traditional circuit board processes.

[0004] In some illustrative embodiments, the method of manufacturing the circuit board includes: preparing a laminate; the laminate includes: a first insulating layer having a first side and a second side vertically opposite each other, and a metal foil layer formed on the first side of the first insulating layer; etching the metal foil layer to form an etched circuit pattern; forming a first blind via penetrating the first insulating layer and extending to the etched circuit pattern; forming a first printed circuit pattern on the second side of the first insulating layer using a conductive paste, and filling the first blind via to form a first conductive pillar realizing a conductive interconnection between the first printed circuit pattern and the etched circuit pattern; and electroplating the first printed circuit pattern to form a first plated circuit pattern.

[0005] In some alternative embodiments, the minimum line width and / or minimum line spacing of the printed circuit pattern is greater than that of the etched circuit pattern.

[0006] In some alternative embodiments, the density of the printed circuit pattern on the insulating layer is less than that of the etched circuit pattern.

[0007] In some alternative embodiments, the etched but unplated stacked structure is used as a semi-process circuit board. Before plating, two semi-process circuit boards are temporarily bonded together with the etched circuit pattern side facing out. After plating is completed, the semi-process circuit boards are separated and restored.

[0008] In some alternative embodiments, before temporarily bonding the two semi-process circuit boards with the etched circuit pattern side together, the method further includes: forming a third insulating layer on the first side of the first insulating layer to shield the etched circuit pattern, thereby temporarily bonding the two semi-process circuit boards with the third insulating layer side together.

[0009] In some optional embodiments, the temporary bonding of the two semi-process circuit boards with etched circuit pattern surfaces specifically includes: achieving temporary bonding of the two semi-process circuit boards through an adhesive layer; wherein the adhesive layer includes: a first adhesive layer, a carrier layer, and a second adhesive layer stacked together; wherein the structural strength of the carrier layer is greater than that of the first adhesive layer and / or the second adhesive layer; and the adhesion of the first adhesive layer and / or the second adhesive layer to the carrier layer is greater than its adhesion to the semi-process circuit boards.

[0010] In some alternative embodiments, prior to applying the conductive paste, the method further includes: forming a base coating on the substrate of the conductive paste, wherein the conductive paste is applied on the base coating; wherein the base coating is used to enhance the adhesion of the conductive paste to the substrate.

[0011] In some optional embodiments, after etching the metal foil layer to form an etched circuit pattern, the method further includes: forming a second insulating layer on a first surface of the first insulating layer to shield the etched circuit pattern; opening a second blind via penetrating the second insulating layer and extending to the metal foil layer; forming a second printed circuit pattern on the side of the second insulating layer away from the metal foil layer using a conductive paste; filling the second blind via to form a second conductive pillar that achieves a conductive interconnection between the second printed circuit pattern and the etched circuit pattern; and electroplating a second plated circuit pattern on the second printed circuit pattern.

[0012] In some alternative embodiments, the first plated circuit pattern and / or the second plated circuit pattern are formed synchronously or asynchronously.

[0013] Another object of the present invention is to provide a double-sided circuit board to solve the problems in the prior art.

[0014] In some illustrative embodiments, the double-sided circuit board can be obtained by the fabrication method described above.

[0015] Another object of the present invention is to provide a multilayer circuit board to solve the problems in the prior art.

[0016] In some illustrative embodiments, the multilayer circuit board can be obtained by the fabrication method described above.

[0017] Compared with the prior art, this application has the following advantages:

[0018] This invention combines printing and etching processes, which can effectively improve the production efficiency of circuit boards and reduce waste and pollution treatment costs. Attached Figure Description

[0019] Figure 1 This is a flowchart example of the circuit board manufacturing method in an embodiment of the present invention;

[0020] Figure 2 This is a process example of the circuit board manufacturing method in the embodiments of the present invention;

[0021] Figure 3 This is a second example of the process for manufacturing a circuit board in this embodiment of the invention. Detailed Implementation

[0022] To make the objectives, technical solutions, and advantages of the embodiments of the present invention clearer, the technical solutions of the embodiments of the present invention will be clearly and completely described below with reference to the accompanying drawings. Obviously, the described embodiments are only some embodiments of the present invention, not all embodiments. Based on the embodiments of the present invention, all other embodiments obtained by those skilled in the art without creative effort are within the scope of protection of the present invention.

[0023] It should be noted that, where there is no conflict, the various technical features in the embodiments of the present invention can be combined with each other.

[0024] This invention discloses a method for manufacturing a circuit board, specifically, as follows: Figure 1-3 As shown, Figure 1 This is a flowchart example of the circuit board manufacturing method in an embodiment of the present invention; Figure 2 This is a process example of the circuit board manufacturing method in the embodiments of the present invention; Figure 3 This is a second example of the process for manufacturing a circuit board according to an embodiment of the present invention; the method for manufacturing the circuit board includes:

[0025] Step S11: Prepare a layer of stacked material;

[0026] The laminate includes: a first insulating layer 110 having a first surface and a second surface that are vertically opposite each other, and a metal foil layer 210 formed on the first surface of the first insulating layer 110;

[0027] Optionally, the first insulating layer may be made of rigid board or flexible board. Rigid board includes, but is not limited to: FR-4, CEM-1, 22F, CEM-3, wood, glass, plastic, PMMA (acrylic), etc.; flexible board includes, but is not limited to PET, PVC, PU, ​​PC, PP, PA, PI, CPI (transparent PI), TPE, TPU, TPV, etc.

[0028] Optionally, the metal foil layer includes, but is not limited to, gold, silver, copper, iron, aluminum, zinc, nickel, etc. The metal foil layer may also include a conductive alloy material with the aforementioned materials as its main components.

[0029] Alternatively, the metal foil layer may be formed on the first insulating layer by means of lamination or deposition (chemical deposition, vapor deposition or sputtering), and the present invention does not limit this.

[0030] Step S12: Etch the metal foil layer 210 to form an etched circuit pattern 210E;

[0031] The etching process for metal foil layers can be carried out through traditional chemical etching, which involves covering the metal foil layer with a resist / film and then obtaining the etched circuit pattern through processes such as exposure, development, etching, and film removal. This is existing technology and will not be elaborated upon in this application.

[0032] Step S13: Create a first blind hole 610 that penetrates the first insulating layer 110 and extends to the etched circuit pattern 210E;

[0033] In this embodiment of the invention, the first blind hole is not limited to being achieved by mechanical drilling or laser drilling. Specifically, it can be etched from the second side of the insulating layer until the etched circuit pattern is reached.

[0034] Optionally, after the first blind hole is processed, the process may further include: using a plasma generator to clean the inside of the blind hole, thereby removing residual insulating layer and exposing the complete metal surface at the bottom of the blind hole as much as possible, so as to improve the reliability of subsequent conductive interconnection and reduce contact resistance.

[0035] Preferably, the temperature of the insulating layer can be controlled to reach the glass transition temperature of the material, and then blind hole cleaning can be performed by plasma, which can effectively improve the removal effect of residual impurities.

[0036] Step S14: A first printed circuit pattern 310 is formed on the second surface of the first insulating layer 110 using conductive paste, and the first blind hole is filled to form a first conductive pillar 510 that realizes the conductive interconnection between the first printed circuit pattern 310 and the etched circuit pattern 210E.

[0037] Optionally, the first printed circuit pattern 310 and the first conductive post 510 can be formed by printing in one step or by printing in multiple steps, and this application does not impose any restrictions on this.

[0038] Furthermore, when the two are formed separately through multiple printing processes, the forming order of the conductive pillar and the first printed circuit pattern can be reversed, depending on the actual needs. That is, the hole can be filled first and then the surface can be printed, or the surface can be printed first and then the hole can be filled. This application does not impose any restrictions on this.

[0039] Optionally, the printing process used for the conductive paste in the embodiments of the present invention includes, but is not limited to, screen printing, direct writing printing, inkjet printing, etc.

[0040] Preferably, when using screen printing, the printed circuit pattern and conductive pillars can be formed separately through at least two printing processes. This allows for the adjustment of different printing parameters (such as the squeegee pressure (degree of downward pressure) in the printing processes with different requirements for the printed circuit pattern and conductive pillars, in order to meet the forming quality of surface forming and hole plugging.

[0041] The conductive paste in this embodiment of the invention refers to a composite low-temperature conductive paste that is mainly composed of conductive fillers, resin binders and solvents. After the paste is fully cured, the solvent will evaporate, thereby transforming it into a conductive film in which the conductive fillers are bound by the resin film-forming material.

[0042] The conductive filler is not limited to one or more of the following: metal particles, graphene, conductive carbon black, carbon nanotubes, and conductive particles with core-shell structures; the metal particles are not limited to one or more of the following: gold, silver, copper, iron, nickel, zinc, and silver-coated copper powder; the resin binder may be any commercially available resin, including but not limited to one or more of the following: epoxy resin, acrylic resin, naphthalene-containing epoxy resin, polyaromatic epoxy resin, multifunctional epoxy resin, bismaleimide resin, and polyimide resin. This application does not restrict the selection of solvents.

[0043] The curing method of the conductive paste in the embodiments of the present invention is not limited to thermosetting, photocuring, electromagnetic irradiation or other curing methods. The appropriate curing initiator can be selected or added according to actual needs.

[0044] During the curing process of the low-temperature conductive paste, the insulating layer may also be affected, resulting in shrinkage and deformation of the insulating layer. However, due to the presence of the etched circuit pattern that is closely bonded to it, the etched circuit pattern, which is not affected by the curing conditions, can hinder the shrinkage and deformation of the insulating layer to a certain extent. Although it is not as effective as the whole metal foil layer, it can still ensure the quality of the circuit board to a certain extent and reduce the difficulty of alignment compensation calculation in the corresponding process.

[0045] Step S15: Electroplating is performed on the first printed circuit pattern 310 to form a first plated circuit pattern 410.

[0046] The main function of plating circuit patterns is to improve one or more of the following properties of printed circuit patterns: conductivity, stability, solderability, oxidation resistance, and surface properties.

[0047] In some embodiments of the present invention, the metal foil layer can be a metal foil of the target thickness, thereby producing an etched circuit pattern of the target thickness directly through a chemical etching process. Therefore, it is not necessary to thicken the surface of the etched circuit pattern by plating. Thus, the etched circuit pattern can be shielded before step S15 to prevent it from contacting the electroplating solution.

[0048] Since the first printed circuit pattern requires electroplating to improve its conductivity and surface properties, it is difficult to control the precision in actual production if a thin metal foil is used to thicken it to the target thickness through an electroplating process. This is mainly because the conductive materials on both sides are different, so the same electroplating parameters cannot produce the same electroplating effect on both sides. During electroplating, the plating layer formation rate on the metal foil side is often much higher than that on the printed circuit side, making it difficult to balance the electroplating parameters of both sides in a single electroplating process. However, electroplating them separately would require additional cumbersome steps, greatly reducing production efficiency and making the actual cost difficult to estimate. Therefore, in this embodiment of the invention, by electroplating only the printed circuit pattern to form the plated circuit pattern, the thickness and other parameters of the plated circuit pattern can be effectively controlled.

[0049] In some embodiments, the plated metal includes, but is not limited to, gold, silver, copper, iron, aluminum, zinc, nickel, etc.

[0050] This invention combines printing and etching processes, which can effectively improve the production efficiency of circuit boards and reduce waste and pollution treatment costs.

[0051] The applicant discovered that the higher density and precision of double-sided / multi-layer circuit boards currently on the market can be achieved using only one or a few layers of two or more circuit boards, instead of designing all of them as higher precision circuits. Therefore, the circuits with higher precision requirements (i.e., the circuits occupying more actual area within a specified range) can be achieved using traditional etching processes, while the circuits of other layers can be achieved using printing processes with relatively lower precision.

[0052] Furthermore, since the etching is performed on the side with a higher density of deposits, the actual amount of metal foil etched is greatly reduced. This effectively reduces waste costs and pollution treatment costs while ensuring quality.

[0053] In some embodiments of the invention, the minimum line width and / or minimum line spacing of the printed circuit pattern (first printed circuit pattern and / or second printed circuit pattern) is greater than that of the etched circuit pattern.

[0054] In some embodiments, the density of the printed circuit pattern (first printed circuit pattern and / or second printed circuit pattern) on the insulating layer is less than that of the etched circuit pattern.

[0055] Optionally, the minimum line spacing and / or minimum line width of the etched circuit pattern can range from 1 to 100 μm, while the minimum line spacing and / or minimum line width of the printed circuit pattern (first printed circuit pattern and / or second printed circuit pattern) can range from 2 to 200 μm.

[0056] Those skilled in the art should understand that, although the two ranges overlap, the minimum line spacing and / or minimum line width of the etched circuit pattern can be selected as needed, and the actual parameters should be smaller than the minimum line spacing and / or minimum line width of the printed circuit pattern.

[0057] In some embodiments of the present invention, after etching the metal foil layer to form an etched circuit pattern, the method further includes:

[0058] A second insulating layer 120 is formed on the first surface of the first insulating layer 110 to shield the etched circuit pattern 210E;

[0059] A second blind via 620 is formed, penetrating the second insulating layer 120 and extending to the etched circuit pattern 210E;

[0060] A second printed circuit pattern 320 is formed on the side of the second insulating layer 120 away from the etched circuit pattern 210E using conductive paste, and a second conductive post 520 is formed by filling the second blind via to achieve conductive interconnection between the second printed circuit pattern 320 and the etched circuit pattern 210E.

[0061] A second plated circuit pattern 420 is formed by electroplating on the second printed circuit pattern 320.

[0062] The selection range of materials for the second insulating layer is the same as that for the first insulating layer.

[0063] This embodiment is applicable to the fabrication of a simple three-layer circuit board. The opening and cleaning of the second blind via, or the second printed circuit pattern, the second conductive post, the second plated circuit pattern, etc., can all refer to the aforementioned corresponding embodiments, and will not be repeated here.

[0064] In some embodiments, the first plated circuit pattern and / or the second plated circuit pattern are formed synchronously or asynchronously. The first and second plated circuit patterns can be formed simultaneously in a single electroplating process, or they can be formed separately; preferably, the first and second plated circuit patterns are formed simultaneously in a single electroplating process.

[0065] In some embodiments, an etched but unplated laminated structure can be used as a semi-process circuit board. Before plating, two semi-process circuit boards are temporarily bonded together with the etched circuit pattern on the side, and after plating, the semi-process circuit boards are separated and restored.

[0066] This embodiment uses two half-process circuit boards to shield their respective etched circuit patterns, preventing them from being affected by electroplating. On the other hand, it can also combine the two circuit boards into a temporary integrated structure, thereby improving electroplating efficiency, and then separating and restoring them after electroplating is completed.

[0067] In some embodiments, temporarily bonding the two semi-process circuit boards with etched circuit pattern surfaces specifically includes:

[0068] The two semi-process circuit boards are temporarily bonded together by an adhesive layer 800; wherein the adhesive layer 800 may include: a first adhesive layer, a carrier layer and a second adhesive layer stacked together; wherein the structural strength of the carrier layer is greater than that of the first adhesive layer and / or the second adhesive layer; and the adhesion of the first adhesive layer and / or the second adhesive layer to the carrier layer is greater than its adhesion to the semi-process circuit board.

[0069] By designing the carrier layer and double-sided adhesive layer, as well as their mutual adhesion, the problem of single adhesive layers being difficult to peel off due to lack of structural strength is solved, making the adhesive layer easier to remove. On the other hand, the addition of a carrier layer with a certain structural strength helps to reduce air bubbles between the adhesive bonding surfaces, making the bonding surfaces tighter and preventing the plating solution from leaking and causing undesirable plating on the metal foil surface.

[0070] Optionally, the carrier layer may include, but is not limited to, non-adhesive flexible or rigid boards.

[0071] In some embodiments, before temporarily bonding the two half-process circuit boards together with the surfaces containing the etched circuit patterns, the process may further include:

[0072] A third insulating layer is formed on the first side of the first insulating layer to shield the etched circuit pattern, thereby temporarily bonding the two semi-process circuit boards together with the sides of the third insulating layer in place.

[0073] In some embodiments, prior to applying the conductive paste, the method further includes: forming a base coating on the substrate of the conductive paste, wherein the conductive paste is applied on the base coating; wherein the base coating is used to enhance the adhesion of the conductive paste to the substrate.

[0074] The base layer includes, but is not limited to, a first base layer 910 between the first insulating layer 110 and the first printed circuit layer 310 and / or a second base layer 920 between the second insulating layer 120 and the second printed circuit layer 320.

[0075] In some embodiments, after electroplating is completed, the process may further include: forming a cover layer (first cover layer 710, second cover layer 720) on the etched circuit pattern and / or plated circuit pattern (first plated circuit pattern and / or second plated circuit pattern); wherein the cover layer shields part or all of the etched circuit pattern and / or plated circuit pattern. The cover film may be adhered to the etched circuit pattern and plated circuit pattern via a fourth adhesive layer and a fifth adhesive layer.

[0076] The cover layer partially or completely obscures the etched circuit pattern and / or plated circuit pattern (first plated circuit pattern and / or second plated circuit pattern). The areas of the etched circuit pattern and / or plated circuit pattern (first plated circuit pattern and / or second plated circuit pattern) exposed by the cover film are not limited to functions such as gold fingers or solder pads.

[0077] In some embodiments, the second or third insulating layer may be used as a cover layer.

[0078] Example 1

[0079] A method for manufacturing a double-sided circuit board includes:

[0080] S21. Prepare a laminate; the laminate includes: a first insulating layer having a first surface and a second surface that are vertically opposite each other, and a metal foil layer formed on the first surface of the first insulating layer;

[0081] S22. Etch the metal foil layer to form an etched circuit pattern;

[0082] S23. A first cover layer (second insulating layer) is formed on the first surface of the first insulating layer to shield the etched circuit pattern; wherein the first cover layer has an opening that exposes a portion of the etched circuit pattern;

[0083] S24. A first base coating is formed on the second surface of the first insulating layer;

[0084] S25. A first blind hole is made that penetrates the first base coating layer and the first insulating layer and extends to the etched circuit pattern;

[0085] S26. A first printed circuit pattern is formed on the first base coating using a conductive paste, and the first blind hole is filled to form a first conductive pillar that realizes the conductive interconnection between the first printed circuit pattern and the etched circuit pattern.

[0086] S27. Temporarily bond two semi-processed circuit boards that have undergone step S26 together with the surface where the first printed circuit pattern is located.

[0087] S28. Electroplating is performed on the first printed circuit patterns on both sides to form a first plated circuit pattern.

[0088] S29. Disassemble and restore the two half-process circuit boards;

[0089] S30. A second cover layer is formed on the first plated circuit pattern of the semi-process circuit board, and the second cover layer has an opening that exposes a portion of the first etched circuit pattern.

[0090] Example 2

[0091] A method for manufacturing a three-layer circuit board includes:

[0092] S41. Prepare a laminate; the laminate includes: a first insulating layer having a first surface and a second surface that are vertically opposite each other, and a metal foil layer formed on the first surface of the first insulating layer;

[0093] S42. Etch the metal foil layer to form an etched circuit pattern;

[0094] S43. A second insulating layer is formed on the first side of the first insulating layer to shield the etched circuit pattern;

[0095] S44. A first base coating is formed on the second surface of the first insulating layer, and a second base coating is formed on the side of the second insulating layer away from the etched circuit pattern;

[0096] S45. A first blind hole is formed that penetrates the first base coating and the first insulating layer and reaches the etched circuit pattern, and a second blind hole is formed that penetrates the second base coating and the second insulating layer and reaches the etched circuit pattern.

[0097] S46. A first printed circuit pattern is formed on the first base layer using conductive paste, and the first blind via is filled to form a first conductive pillar that achieves conductive interconnection between the first printed circuit pattern and the etched circuit pattern; and a second printed circuit pattern is formed on the second base layer using conductive paste, and the second blind via is filled to form a second conductive pillar that achieves conductive interconnection between the second printed circuit pattern and the etched circuit pattern.

[0098] S47. Electroplating a first plated circuit pattern on the first printed circuit pattern, and electroplating a second plated circuit pattern on the second printed circuit pattern.

[0099] S48. A cover layer is formed on the first plated circuit pattern and the second plated circuit pattern; wherein the cover layer has openings that expose portions of the first plated circuit pattern and the second plated circuit pattern.

[0100] This invention discloses a circuit board, which can be obtained by the above-described manufacturing method.

[0101] This invention discloses a double-sided circuit board, comprising: an etched circuit pattern 210E, a first insulating layer 110, a first printed circuit pattern 310, and a first plated circuit pattern 410 stacked sequentially; wherein the first plated circuit pattern 410 is formed on the first printed circuit pattern 310, and the first printed circuit pattern 310 and the etched circuit pattern 210E are interconnected by a first conductive post penetrating the first insulating layer 110.

[0102] In some embodiments, a first base coating layer is provided between the first insulating layer and the first printed circuit layer;

[0103] In some embodiments, the etched circuit pattern is provided with a first cover layer, and the first plated circuit pattern is provided with a second cover layer; wherein the first cover layer and the second cover layer are respectively provided with windows that expose a portion of the corresponding circuit pattern.

[0104] This invention discloses a multilayer circuit board, comprising: a first plated circuit pattern, a first printed circuit pattern, a first insulating layer, an etched circuit pattern, a second insulating layer, a second printed circuit pattern, and a second plated circuit pattern stacked sequentially; wherein, the first plated circuit pattern is formed on the first printed circuit pattern, the second plated circuit pattern is formed on the second printed circuit pattern, the first printed circuit pattern and the etched circuit pattern are interconnected by a first conductive post penetrating the first insulating layer, and the second printed circuit pattern and the etched circuit pattern are interconnected by a second conductive post penetrating the second insulating layer.

[0105] In some embodiments, a first base coat is provided between the first insulating layer and the first printed circuit layer; and a second base coat is provided between the second insulating layer and the second printed circuit layer.

[0106] In some embodiments, a second cover layer is provided on the first plated circuit pattern, and a first cover layer is provided on the second plated circuit pattern. The two cover layers are respectively provided with windows that expose a portion of the corresponding circuit pattern.

[0107] In some embodiments of the present invention, the minimum line width and / or minimum line spacing of the printed circuit pattern is greater than that of the etched circuit pattern.

[0108] In some embodiments, the density of the printed circuit pattern on the insulating layer is less than that of the etched circuit pattern.

[0109] The minimum line spacing and / or minimum line width of etched circuit patterns can range from 1 to 100 μm, while the minimum line spacing and / or minimum line width of printed circuit patterns can range from 2 to 200 μm.

[0110] Those skilled in the art should understand that, although the two ranges overlap, the minimum line spacing and / or minimum line width of the etched circuit pattern can be selected as needed, and the actual parameters should be smaller than the minimum line spacing and / or minimum line width of the printed circuit pattern.

[0111] Finally, it should be noted that the above embodiments are only used to illustrate the technical solutions of the present invention, and not to limit them; although the present invention has been described in detail with reference to the foregoing embodiments, those skilled in the art should understand that modifications can still be made to the technical solutions described in the foregoing embodiments, or equivalent substitutions can be made to some or all of the technical features; and these modifications or substitutions do not cause the essence of the corresponding technical solutions to deviate from the scope of the technical solutions of the embodiments of the present invention.

Claims

1. A method for manufacturing a circuit board, characterized in that, include: Prepare a layer of stacked material; The laminate consists of a first insulating layer having a first and a second surface that are vertically opposite each other, and a metal foil layer formed on the first surface of the first insulating layer; The metal foil layer is etched to form an etched circuit pattern; A first blind via is made, penetrating the first insulating layer and reaching the etched circuit pattern; A first printed circuit pattern is formed on the second surface of the first insulating layer using conductive paste, and the first blind hole is filled to form a first conductive pillar that realizes the conductive interconnection between the first printed circuit pattern and the etched circuit pattern. Electroplating is performed on the first printed circuit pattern to form a first plated circuit pattern; Among them, the conductive structure on the second side of the first insulating layer is only a composite of the first printed circuit pattern and the first plated circuit pattern. Wherein, the minimum line width and / or minimum line spacing of the printed circuit pattern is greater than that of the etched circuit pattern; and / or, the laying density of the printed circuit pattern on the insulating layer is less than that of the etched circuit pattern.

2. The manufacturing method according to claim 1, characterized in that, The etched but unplated stacked structure is used as a semi-process circuit board. Before electroplating, two semi-process circuit boards are temporarily bonded together with the etched circuit pattern on the side. After electroplating, the semi-process circuit boards are separated and restored.

3. The manufacturing method according to claim 2, characterized in that, Before temporarily bonding the two semi-process circuit boards together with the etched circuit pattern sides, the process also includes: A third insulating layer is formed on the first side of the first insulating layer to shield the etched circuit pattern, thereby temporarily bonding the two semi-process circuit boards together with the sides of the third insulating layer in place.

4. The manufacturing method according to claim 2, characterized in that, The temporary bonding of the two semi-process circuit boards with etched circuit pattern surfaces specifically includes: The two semi-process circuit boards are temporarily bonded together by an adhesive layer; wherein the adhesive layer comprises: a first adhesive layer, a carrier layer and a second adhesive layer stacked together; wherein the structural strength of the carrier layer is greater than that of the first adhesive layer and / or the second adhesive layer; and the adhesion of the first adhesive layer and / or the second adhesive layer to the carrier layer is greater than its adhesion to the semi-process circuit board.

5. The manufacturing method according to claim 1, characterized in that, Before applying the conductive paste, the method further includes: forming a base coating on the substrate of the conductive paste, wherein the conductive paste is applied on the base coating; wherein the base coating is used to improve the adhesion of the conductive paste to the substrate.

6. The manufacturing method according to claim 1, characterized in that, After etching the metal foil layer to form an etched circuit pattern, the process further includes: A second insulating layer is formed on the first surface of the first insulating layer to shield the etched circuit pattern; A second blind via is made, penetrating the second insulating layer and extending to the etched circuit pattern; A second printed circuit pattern is formed on the side of the second insulating layer away from the etched circuit pattern using a conductive paste, and a second conductive pillar is formed by filling the second blind via to achieve a conductive interconnection between the second printed circuit pattern and the etched circuit pattern; A second plated circuit pattern is formed by electroplating on the second printed circuit pattern.

7. The manufacturing method according to claim 6, characterized in that, The first plated circuit pattern and / or the second plated circuit pattern are formed synchronously or asynchronously.

8. A double-sided circuit board, characterized in that, Obtained by the manufacturing method as described in any one of claims 1-5.

9. A multilayer circuit board, characterized in that, Obtained by the manufacturing method as described in any one of claims 1-7.

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