Conductor device and preparation method thereof, memory and memory system

Abstract

The invention provides a semiconductor device and a preparation method thereof, a memory and a storage system, a first stack layer comprising a first insulating layer and a sacrificial layer is firstly formed, the first stack layer comprises a core region, a transition region and a connection region which are adjacent in a first direction, and the transition region is located between the core region and the connection region; and forming a first grid line isolation structure located in the core region and a second grid line isolation structure located in the transition region. The first grid line isolation structure comprises a plurality of first air gaps arranged in the first direction and first connecting parts located between every two adjacent first air gaps. The second grid line isolation structure comprises a plurality of second air gaps arranged in the first direction and second connecting parts located between every two adjacent second air gaps. Wherein the size of the second connecting part in the first direction is larger than that of the first connecting part in the first direction, so that the length of the filling part in the transition region can be increased by increasing the size of the second connecting part in the transition region, and the performance of the semiconductor device can be improved.

Description

Technical Field

[0001] The present disclosure generally relates to the field of electronic devices, and more particularly, to a semiconductor device and a method for manufacturing the same, a memory, and a storage system. Background Art

[0002] NAND memory devices are non-volatile storage products with low power consumption, light weight and good performance, and are widely used in electronic products. Planar NAND devices have reached their practical expansion limit. In order to further increase storage capacity and reduce the storage cost per bit, 3D NAND memory is proposed. In the 3D NAND memory structure, a stacked memory structure is realized by vertically stacking multiple layers of data storage units.

[0003] However, the performance of 3D NAND devices currently needs to be improved.

[0004] Public Content

[0005] The purpose of the present disclosure is to provide a semiconductor device and a method for manufacturing the same, a memory and a storage system, aiming to improve the performance of the semiconductor device.

[0006] In a first aspect, the present disclosure provides a method for preparing a semiconductor device, the method for preparing a semiconductor device comprising:

[0007] forming a first stacked layer, the first stacked layer comprising a first insulating layer and a sacrificial layer alternately stacked, the first stacked layer comprising a core region, a transition region and a connection region adjacent to each other in a first direction, the transition region being located between the core region and the connection region, and the first direction intersecting with a stacking direction of the first stacked layer;

[0008] A first gate line isolation structure located in the core area and a second gate line isolation structure located in the transition area are formed, wherein the first gate line isolation structure includes a plurality of first air gaps arranged along the first direction, and a first connecting portion located between two adjacent first air gaps; the second gate line isolation structure includes a plurality of second air gaps arranged along the first direction, and a second connecting portion located between two adjacent second air gaps; a size of the second connecting portion along the first direction is greater than a size of the first connecting portion along the first direction.

[0009] In some embodiments, a size of the second connecting portion along the first direction ranges from 25 to 55 nm.

[0010] In some embodiments, the step of forming a first gate line isolation structure located in the core region and a second gate line isolation structure located in the transition region includes:

[0011] Forming a hole structure that penetrates the first stacking layer along the stacking direction and is arranged at intervals along the first direction, wherein the hole structure includes a first hole structure located in the core area and a second hole structure located in the transition area;

[0012] Expanding the hole structure to form a first grid line gap located in the core area and a second grid line gap located in the transition area;

[0013] A filling layer is formed in the first gate line gap and the second gate line gap to form a first gate line isolation structure and a second gate line isolation structure.

[0014] In some embodiments, the step of forming a hole structure that penetrates the first stacking layer along the stacking direction and is arranged at intervals along the first direction includes:

[0015] Etching the first stacked layer along the stacking direction of the first stacked layer to form a first hole structure, a second hole structure and a third hole structure respectively located in the core area, the transition area and the connection area, the first hole structure and the second hole structure are arranged in a row along the first direction, and the third hole structure is arranged in multiple rows along the first direction;

[0016] Wherein, two adjacent rows of the third hole structures are staggered along the first direction, and the intervals between three adjacent third hole structures are equal.

[0017] In some embodiments, the step of expanding the hole structure comprises:

[0018] The first stacked layer around the first hole structure, the second hole structure and the third hole structure is etched to respectively form a first gate line gap, a second gate line gap and a third gate line gap extending along a first direction and interconnected.

[0019] In some embodiments, the pore spacing between two adjacent second pore structures is greater than the pore spacing between two adjacent first pore structures; the pore spacing between adjacent first pore structures and the second pore structure is greater than the pore spacing between two adjacent first pore structures; the pore spacing between adjacent third pore structures and the second pore structure is greater than the pore spacing between two adjacent first pore structures.

[0020] In some embodiments, the method for preparing the semiconductor device further includes:

[0021] In the process of forming the hole structure, a channel hole and a virtual channel hole are formed which penetrate the first stack layer along the stacking direction of the first stack layer;

[0022] The channel hole is located in the core area and between two adjacent rows of the first hole structure, and the virtual channel hole is located in the transition area and between two adjacent rows of the second hole structure.

[0023] In some embodiments, the step of forming a hole structure that penetrates the first stacking layer along the stacking direction and is arranged at intervals along the first direction includes:

[0024] Etching the first stacked layer along the stacking direction to form a first pore structure located in the core area and a second pore structure located in the transition area, wherein the second pore structure includes first sub-pore structures and second sub-pore structures alternately arranged along the first direction;

[0025] The maximum dimension of the first sub-hole structure along the first direction is equal to the maximum dimension of the first hole structure along the first direction, and the maximum dimension of the second sub-hole structure along the first direction is smaller than the maximum dimension of the first sub-hole structure along the first direction.

[0026] In some embodiments, the method for preparing the semiconductor device further includes:

[0027] Forming a second stacking layer on the first stacking layer, and forming a middle hole structure that penetrates the second stacking layer along the stacking direction and is arranged along the first direction, wherein the middle hole structure includes a first middle hole structure located in the core area and a second middle hole structure located in the transition area;

[0028] forming a third stacking layer on the second stacking layer, and forming an upper hole structure penetrating the second stacking layer along the stacking direction and arranged along the first direction, wherein the upper hole structure includes a first upper hole structure located in the core area and a second upper hole structure located in the transition area;

[0029] Among them, the middle hole structure is connected to the hole structure, and the upper hole structure is connected to the middle hole structure; the maximum size of the second hole structure along the first direction is smaller than the maximum size of the second middle hole structure along the first direction, and the maximum size of the second middle hole structure along the first direction is smaller than the maximum size of the second upper hole structure along the first direction.

[0030] In some embodiments, a maximum dimension of the first hole structure along the first direction, a maximum dimension of the first middle hole structure along the first direction, and a maximum dimension of the first upper hole structure along the first direction are all equal.

[0031] In some embodiments, the step of forming a filling layer in the first gate line gap and the second gate line gap comprises:

[0032] A second insulating layer and a first conductive layer are formed in the first gate line gap, the second gate line gap, and the third gate line gap.

[0033] In some embodiments, before the step of forming a second insulating layer and a first conductive layer in the first gate line gap, the second gate line gap, and the third gate line gap, the method for preparing the semiconductor device further includes:

[0034] The sacrificial layer in the first stacked layer of the core region is replaced with a gate layer.

[0035] In a second aspect, the present disclosure provides a semiconductor device, the semiconductor device comprising:

[0036] A first stacked structure, comprising a first insulating layer and a gate layer alternately stacked, the first stacked structure comprising a core region, a transition region and a connection region adjacent to each other in a first direction, the transition region being located between the core region and the connection region, and the first direction intersecting with a stacking direction of the stacked structure;

[0037] A first gate line isolation structure, penetrating the first stacking structure of the core area along the stacking direction and extending along the first direction;

[0038] A second gate line isolation structure, which penetrates the first stacking structure in the transition region along the stacking direction, and the second gate line isolation structure extends along the first direction and is connected to the first gate line isolation structure;

[0039] Among them, the first gate line isolation structure includes a plurality of first air gaps arranged along the first direction, and a first connecting portion located between two adjacent first air gaps; the second gate line isolation structure includes a plurality of second air gaps arranged along the first direction, and a second connecting portion located between two adjacent second air gaps; the size of the second connecting portion along the first direction is greater than the size of the first connecting portion along the first direction.

[0040] In some embodiments, the semiconductor device further includes a third gate line isolation structure, the third gate line isolation structure penetrates the first stacking structure of the connection region along the stacking direction, and the third gate line isolation structure extends along the first direction and is connected to the second gate line isolation structure;

[0041] The maximum dimension of the first gate line isolation structure in the second direction is smaller than the minimum dimension of the third gate line isolation structure in the second direction, and the second direction intersects the stacking direction and the first direction.

[0042] In some embodiments, the top view of the second gate line isolation structure includes a plurality of first arcs connected along the first direction, and the arc lengths of the plurality of first arcs are equal.

[0043] In some embodiments, the top view of the second gate line isolation structure further includes a second arc connected to the first arc, the second arc is located between two adjacent first arcs, and the arc length of the second arc is less than the arc length of the first arc.

[0044] In some embodiments, the semiconductor device further comprises:

[0045] A second stacking structure, located on the first stacking structure;

[0046] a middle gate line isolation structure, penetrating the second stacking layer along the stacking direction and extending along the first direction, the middle gate line isolation structure comprising a first middle gate line isolation structure located in the core area and the second middle gate line isolation structure located in the transition area;

[0047] a third stacking structure, located on the second stacking structure;

[0048] An upper gate line isolation structure, penetrating the third stacking layer along the stacking direction and extending along the first direction, the upper gate line isolation structure comprising a first upper gate line isolation structure located in the core area and a second upper gate line isolation structure located in the transition area;

[0049] Wherein, the first gate line isolation structure, the first middle gate line isolation structure and the first upper gate line isolation structure are connected in the stacking direction, and the second gate line isolation structure, the second middle gate line isolation structure and the second upper gate line isolation structure are connected in the stacking direction;

[0050] The maximum dimension of the second upper gate line isolation structure along the second direction is greater than the maximum dimension of the second middle gate line isolation structure along the second direction; the maximum dimension of the second middle gate line isolation structure along the second direction is greater than the maximum dimension of the second gate line isolation structure along the second direction.

[0051] In some embodiments, the first middle gate line isolation structure includes a plurality of first middle air gaps arranged along the first direction, and a first middle connecting portion located between two adjacent first middle air gaps;

[0052] The second middle gate line isolation structure includes a plurality of second middle air gaps arranged along the first direction, and a second middle connecting portion located between two adjacent second middle air gaps;

[0053] A dimension of the second middle connecting portion along the first direction is greater than a dimension of the first middle connecting portion along the first direction.

[0054] In some embodiments, the first upper gate line isolation structure includes a plurality of first upper air gaps arranged along the first direction, and a first upper connecting portion located between two adjacent first upper air gaps;

[0055] The second upper gate line isolation structure includes a plurality of second upper air gaps arranged along the first direction, and a second upper connecting portion located between two adjacent second upper air gaps;

[0056] A dimension of the first upper connecting portion along the first direction is greater than or equal to a dimension of the second upper connecting portion along the first direction.

[0057] In some embodiments, a dimension of the second upper connecting portion along the first direction is smaller than a dimension of the second middle connecting portion along the first direction; a dimension of the second middle connecting portion along the first direction is smaller than a dimension of the second connecting portion along the first direction.

[0058] In a third aspect, an embodiment of the present application provides a memory, including:

[0059] The semiconductor device provided by any of the above embodiments;

[0060] A peripheral circuit is electrically connected to the semiconductor device.

[0061] In a fourth aspect, an embodiment of the present application provides a storage system, including:

[0062] The memory provided by any of the aforementioned embodiments;

[0063] A controller is electrically connected to the memory and is used to control the memory to store data.

[0064] The present disclosure provides a semiconductor device and a method for preparing the same, a memory and a storage system. A first stacked layer including a first insulating layer and a sacrificial layer is first formed, wherein the first stacked layer includes a core region, a transition region and a connection region adjacent to each other in a first direction, wherein the transition region is located between the core region and the connection region. A first gate line isolation structure located in the core region and a second gate line isolation structure located in the transition region are then formed. The first gate line isolation structure includes a plurality of first air gaps arranged along a first direction, and a first connection portion located between two adjacent first air gaps. The second gate line isolation structure includes a plurality of second air gaps arranged along a first direction, and a second connection portion located between two adjacent second air gaps. The size of the second connection portion along the first direction is greater than the size of the first connection portion along the first direction. Therefore, compared with the first connection portion in the core region, by increasing the size of the second connection portion in the transition region, the length of the filled portion in the transition region can be increased, thereby improving the performance of the semiconductor device. BRIEF DESCRIPTION OF THE DRAWINGS

[0065] The technical solutions and other beneficial effects of the present invention will be made apparent by describing in detail the specific embodiments of the present invention in conjunction with the accompanying drawings.

[0066] Figure 1 is a schematic flow chart of a method for preparing a semiconductor device provided in some embodiments of the present disclosure;

[0067] Figure 2a-2g is a schematic diagram of the structure of a semiconductor device during the preparation process provided by some embodiments of the present application;

[0068] Figure 3a-3e is a schematic diagram of the structure of a semiconductor device during the preparation process provided by some embodiments of the present application;

[0069] Figure 4a-4c is a schematic diagram of the structure of a semiconductor device during the preparation process provided by some embodiments of the present application;

[0070] Figure 5 is a schematic diagram of a cross-sectional structure of a semiconductor device during the preparation process provided by some embodiments of the present application;

[0071] Figure 6 is a schematic diagram of the structure of a semiconductor device provided by some embodiments of the present application;

[0072] Figure 7 is a schematic diagram of the structure of a memory provided by some embodiments of the present application;

[0073] Figure 8 It is a schematic diagram of the structure of the storage system provided in some embodiments of the present application. DETAILED DESCRIPTION

[0074] The technical solutions in the embodiments of the present disclosure will be described clearly and completely below in conjunction with the drawings in the embodiments of the present disclosure. Obviously, the described embodiments are only part of the embodiments of the present disclosure, not all of the embodiments. Based on the embodiments in the present disclosure, all other embodiments obtained by those skilled in the art without creative work are within the scope of protection of the present disclosure.

[0075] It should be understood that although the terms first, second, etc. may be used herein to describe various components, these components should not be limited to these terms. These terms are used to distinguish one component from another component. For example, a first component may be referred to as a second component, and similarly, a second component may be referred to as a first component without departing from the scope of the present disclosure.

[0076] It should be understood that when a component is said to be "on" or "connected" another component, it can be directly on or connected to another component, or there may be an intervening component. Other words used to describe the relationship between components should be interpreted in a similar manner.

[0077] As used herein, the term "layer" refers to a material portion including an area with a thickness. A layer may extend over the entire lower or upper structure, or may have a range that is less than the range of the lower or upper structure. In addition, a layer may be an area of ​​a uniform or non-uniform continuous structure whose thickness is less than the thickness of a continuous structure. For example, a layer may be located between the top and bottom surfaces of a continuous structure or between any set of horizontal planes at the top and bottom surfaces. A layer may extend horizontally, vertically and / or along a tapered surface. A substrate may be a layer, which may include one or more layers, and / or may have one or more layers on, above and / or below it. A layer may include multiple layers. For example, an interconnect layer may include one or more conductive layers and a contact layer (wherein contacts, interconnect lines and / or vertical interconnect access (VIA) are formed) and one or more dielectric layers.

[0078] It should be noted that the illustrations provided in the embodiments of the present disclosure are only used to illustrate the basic concept of the present disclosure in a schematic manner. Although the illustrations only show components related to the present disclosure and are not drawn according to the number, shape and size of components in actual implementation, the type, quantity and proportion of each component in actual implementation may be changed arbitrarily, and the component layout type may also be more complicated.

[0079] This article uses Cartesian coordinates to represent directions, where "X" represents the first direction, "Y" represents the second direction, and "Z" represents the stacking direction. The first direction, the second direction, and the third direction intersect with each other, that is, X, Y, and Z intersect with each other, for example, they may be perpendicular to each other or at a certain angle.

[0080] See also Figure 1 , Figure 1 is a schematic diagram of a method for preparing a semiconductor device provided by some embodiments of the present disclosure. Figure 2a-2g , Figure 2a-2g The structure diagram of the semiconductor device provided in some embodiments of the present application during the preparation process is shown in FIG. The preparation method of the semiconductor device includes the following steps S1-S2.

[0081] Step S1: Form a first stacking layer 10, wherein the first stacking layer 10 includes a first insulating layer and a sacrificial layer alternately stacked, and the first stacking layer 10 includes a core area 10a, a transition area 10b and a connection area 10c adjacent to each other in a first direction (X), wherein the transition area 10b is located between the core area 10a and the connection area 10c, and the first direction (X) intersects with the stacking direction (Z) of the first stacking layer 10.

[0082] A substrate may be provided first, and then a first insulating layer and a sacrificial layer may be alternately deposited on the substrate to form the first stacked layer 10. Figure 2a As shown, the first stacked layer 10 includes a core area 10a, a transition area 10b and a connection area 10c which are arranged adjacent to each other in a first direction (X). The first stacked layer 10 in the core area 10a is used to form a storage channel structure, the first stacked layer 10 in the transition area 10b is used to form a virtual channel structure, and the first stacked layer 10 in the connection area 10c is used to form a conductive structure, such as a word line contact.

[0083] An exemplary material of the first insulating layer is silicon oxide, and an exemplary material of the sacrificial layer is silicon nitride. The deposition process of the first insulating layer and the sacrificial layer may be, but is not limited to, chemical vapor deposition (CVD), atomic layer deposition (ALD), physical vapor deposition (PVD) such as thermal oxidation, evaporation, sputtering, and other methods.

[0084] Step S2: forming a first gate line isolation structure 11a located in the core area 10a and a second gate line isolation structure 11b located in the transition area 10b, wherein the first gate line isolation structure 11a includes a plurality of first air gaps 111a arranged along the first direction (X), and a first connecting portion 112a located between two adjacent first air gaps 111a; the second gate line isolation structure 11b includes a plurality of second air gaps 111b arranged along the first direction (X), and a second connecting portion 112b located between two adjacent second air gaps 111b; the size of the second connecting portion 112b along the first direction (X) is greater than the size of the first connecting portion 112a along the first direction (X).

[0085] In some embodiments, a size of the second connection portion 112 b along the first direction (X) ranges from 25 nm to 55 nm.

[0086] Specifically, step S2 may include the following steps.

[0087] 1) forming a hole structure penetrating the first stacking layer 10 along the stacking direction (Z) and arranged at intervals along the first direction (X), wherein the hole structure includes a first hole structure 101a located in the core area 10a and a second hole structure 101b located in the transition area 10b.

[0088] like Figure 2a As shown, the first stacked layer 10 can be etched along the stacking direction (Z) of the first stacked layer 10 to form a plurality of hole structures, wherein the first hole structure 101a is located in the core region 10a, the second hole structure 101b is located in the transition region 10b, and the third hole structure 101c is located in the connection region 10c. The first hole structure 101a and the second hole structure 101b are arranged in a row along the first direction (X), and the third hole structure 101c is arranged in multiple rows along the first direction (X).

[0089] In some embodiments, two adjacent rows of the third hole structures 101c are staggered along the first direction (X), for example, the third hole structures 101c in the second row are not aligned with the third hole structures 101c in the first row, but the third hole structures 101c in the second row correspond to the areas between the third hole structures 101c in the first row. And in this staggered arrangement, the spacing between three adjacent third hole structures 101c is equal.

[0090] In some embodiments, in the etching process of the hole structure, a channel hole and a virtual channel hole (not shown in the figure) penetrating the first stacked layer 10 along the stacking direction (Z) of the first stacked layer 10 can also be formed, that is, the hole structure, the channel hole and the virtual channel hole are formed together. The channel hole is located in the core area 10a and between two adjacent rows of the first hole structure 101a, and the virtual channel hole is located in the transition area 10b and between two adjacent rows of the second hole structure 101b.

[0091] The method for preparing the semiconductor device further comprises: forming a channel structure and a dummy channel structure in the channel hole and the dummy channel hole respectively.

[0092] It should be noted that Figure 2a Only one row of the first hole structure 101a and the second hole structure 101b is shown. In fact, multiple rows of the first hole structure 101a and multiple rows of the second hole structure 101b are formed in the first stacked layer 10, and there is a gap between two adjacent rows. In other words, Figure 2aThe hole structure shown is a repeating unit, and multiple repeating units can be arranged in intervals along the second direction (Y). Therefore, the channel hole is formed in Figure 2a The virtual channel holes are formed on both sides of the first hole structure 101a along the second direction (Y). Figure 2a The second hole structure 101b is along both sides of the second direction (Y).

[0093] 2) Expanding the hole structure to form a first gate line gap 102a located in the core area 10a and a second gate line gap 102b located in the transition area 10b.

[0094] Specifically, the first stacked layer 10 around the first hole structure 101a, the second hole structure 101b and the third hole structure 101c can be etched to form a first gate line gap 102a, a second gate line gap 102b and a third gate line gap 102c extending along the first direction (X) and interconnected. Figure 2a The outline after the hole is expanded is as follows Figure 2a As shown by the dotted circle, multiple hole structures are connected after being expanded, and the overall outline (grid line gap) is as follows Figure 2b As shown by the dotted line, the gate line gaps include the first gate line gap 102a, the second gate line gap 102b and the third gate line gap 102c. Since the first gate line gap 102a is obtained by expanding the first hole structure 101a, the second gate line gap 102b is obtained by expanding the second hole structure 101b, and the third gate line gap 102c is obtained by expanding the third hole structure 101c, the first gate line gap 102a is located in the core area 10a, the second gate line gap 102b is located in the transition area 10b, and the third gate line gap 102c is located in the connection area 10c. Since the number of rows of the third hole structure 101c is large, the maximum size of the third gate line gap 102c along the second direction (Y) is greater than the maximum size of the second gate line gap 102b along the second direction (Y), and the maximum size of the third gate line gap 102c along the second direction (Y) is greater than the maximum size of the first gate line gap 102a along the second direction (Y).

[0095] In some embodiments, when the third hole structures 101c are staggered, the spacing between three adjacent third hole structures 101c is equal. Compared with the case where two rows of third hole structures 101c are aligned, the density of the third hole structures 101c can be improved. In this way, in the hole expansion process, the first stacking layer 10 between the third hole structures 101c is easier to remove, that is, the process window for hole expansion can be increased.

[0096] 3) A filling layer 103 is formed in the first gate line gap 102a and the second gate line gap 102b to form a first gate line isolation structure 11a and a second gate line isolation structure 11b.

[0097] It should be noted that before forming the filling layer 103 or after expanding the hole, the sacrificial layer in the first stacked layer 10 of the core area 10a and the transition area 10b needs to be replaced with a gate layer (such as tungsten), so that after expanding the hole, the first stacked layer 10 becomes a first stacked structure 10'. Before forming the filling layer 103, a conductive structure extending along the stacking direction (Z) needs to be formed between two adjacent third gate line gaps 102c.

[0098] In some specific embodiments, Figure 2c As shown, the second insulating layer and the first conductive layer can be sequentially deposited in the first gate line gap 102a, the second gate line gap 102b and the third gate line gap 102c, the second insulating layer is, for example, silicon oxide, and the first conductive layer is, for example, polysilicon. The arrows in the figure indicate the direction of gas during material deposition. Since the third gate line gap 102c has a larger size along the second direction (Y), the third gate line gap 102c is not filled.

[0099] like Figure 2d As shown, the second insulating layer and the first conductive layer located in the third gate line gap 102c are then removed to perform a process of connecting the conductive structure in the connection area 10c with the gate layer in the core area 10a. Specifically, after the third gate line gap 102c is hollowed out, the sacrificial layer around the third gate line gap 102c is replaced with a connecting layer (e.g., tungsten), so that the connecting layer can connect the gate layer and the conductive structure in the connection area 10c.

[0100] like Figure 2e As shown, finally, the second insulating layer and the first conductive layer are filled in the third gate line gap 102c, so as to form a filling layer 103 in the gate line gap.

[0101] In some embodiments, Figure 2d In the process of removing the second insulating layer and the first conductive layer, part of the filling layer 103 in the second gate line gap 102b will be removed. Figure 2e In the filling process, both the second gate line gap 102 b and the second gate line gap 102 b will be filled.

[0102] The filling layer 103 can be formed by any of the above-mentioned deposition processes. Due to the limitations of the deposition process, an air gap will be formed in the gate line gap. Therefore, the first gate line isolation structure 11a includes a first air gap 111a and a first connecting portion 112a, the second gate line isolation structure 11b includes a second air gap 111b and a second connecting portion 112b, and the third gate line isolation structure 11c includes a third air gap and a third connecting portion (not shown in the figure).

[0103] However, for the first gate line isolation structure 11a and the second gate line isolation structure 11b with smaller sizes, in order to ensure the performance of the semiconductor device (such as the supporting performance), it is necessary to ensure that the total length of the connection portion (including the first connection portion 112a and the second connection portion 112b) along the first direction (X) reaches a specific value to reduce the risk of adjacent air gaps being connected and improve the supporting performance. Therefore, the length of the second connection portion 112b can be increased by increasing the hole spacing of the second hole structure 101b in the transition region 10b, such as Figure 2a As shown, the hole spacing W1 between two adjacent second hole structures 101b is greater than the hole spacing between two adjacent first hole structures 101a. Figure 2e As shown, the length L1 of the second connection portion 112b is greater than the length L2 of the first connection portion 112a.

[0104] It should be noted that due to Figure 2a Only one first hole structure 101 a is shown, and therefore the hole distance between two adjacent first hole structures 101 a is not shown.

[0105] In some embodiments, if the area between the adjacent first hole structure 101a and the second hole structure 101b is divided into the core area 10a ( Figure 2a As shown), the hole spacing W2 between the adjacent first hole structures 101a and the second hole structures 101b is equal to the hole spacing between the two adjacent first hole structures 101a.

[0106] If the area between adjacent first hole structures 101a and second hole structures 101b is divided into transition zone 10b, the hole spacing between adjacent first hole structures 101a and second hole structures 101b (equal to the hole spacing between two adjacent second hole structures 101b) is greater than the hole spacing between two adjacent first hole structures 101a.

[0107] In some embodiments, if the area between the adjacent second hole structure 101b and the third hole structure 101c is divided into the connection area 10c ( Figure 2a As shown), the hole spacing between the adjacent third hole structure 101c and the second hole structure 101b is smaller than the hole spacing between the adjacent two first hole structures 101a.

[0108] If you will Figure 2a The second hole structure 101b near the connection area 10c is divided into the connection area 10c to become the third hole structure 101c, that is, the dotted line between the transition area 10b and the connection area 10c moves to the left to the left edge of the second hole structure 101b to make it the third hole structure 101c, then the hole spacing between the adjacent third hole structure 101c and the second hole structure 101b is greater than the hole spacing between the two adjacent first hole structures 101a. In general, the hole spacing in the transition area is larger than the hole spacing in the core area.

[0109] In some embodiments, the maximum dimensions of the first hole structure 101a, the second hole structure 101b, and the third hole structure 101c along the first direction (X) are all equal.

[0110] It should be noted that there are multiple first air gaps 111a and second air gaps 111b. Figure 2c Only three second air gaps 111b are shown in FIG. 1 , and in the etching process of removing the second insulating layer and the first conductive layer located in the third gate line gap 102c, two second air gaps 111b near the connection region 10c may be removed, forming a structure as shown in FIG. Figure 2f After the third gate line gap 102c is filled, the structure is as follows Figure 2g As shown, therefore Figure 2f and 2g The second connection is not shown. Figure 2f The etching process removes part of the second air gap 111b in the transition region 10b, so the length of the part of the filling layer 103 in the transition region 10b near the connection region 10c in the first direction (X) is greater than the length of the second connection portion in the transition region 10b. Figure 2g In the structure, the transition zone 10b also has multiple second air gaps 111b and multiple second connecting parts, and the length of the second connecting part along the first direction (X) is greater than the length L2 of the first connecting part 112a along the first direction (X).

[0111] In some embodiments, the total length of the connection portion can be increased by increasing the number of second hole structures 101b, but this will cause the transition region 10b to increase, so that the virtual channel structure in the transition region 10b increases accordingly, which in turn causes the storage space to be compressed. In the method for preparing a semiconductor device provided in the present application, the total length of the connection portion is increased by increasing the length of the second connection portion 112b to ensure performance, without increasing the number of virtual channel structures and the space of the transition region 10b, thereby increasing the storage space.

[0112] See also Figure 3a-3e , Figure 3a-3e It is a schematic diagram of the structure of a semiconductor device during the preparation process provided by some embodiments of the present application.

[0113] The method for preparing the semiconductor device also includes the above steps S1 and S2, and Figure 2a-2e The difference between the embodiments is that, in the step of forming the hole structure, the second hole structure 101b' comprises a first sub-hole structure 1011b and a second sub-hole structure 1012b which are alternately arranged along the first direction (X).

[0114] The maximum dimension R1 of the first sub-hole structure 1011b along the first direction (X) is equal to the maximum dimension R2 of the first hole structure 101a along the first direction (X), and the maximum dimension R3 of the second sub-hole structure 1012b along the first direction (X) is smaller than the maximum dimension R1 of the first sub-hole structure 1011b along the first direction (X). In other words, by reducing the size of the second sub-hole structure 1012b in the second hole structure 101b', the hole spacing between adjacent second hole structures 101b' is increased, so that the hole spacing of the second hole structure 101b' is greater than the hole spacing of the first hole structure 101a, and the length of the second connecting portion 112b can be increased subsequently.

[0115] like Figure 3b As shown, after the hole is expanded, a first gate line gap 102a, a second gate line gap 102b' and a third gate line gap 102c are formed. The structure after the second insulating layer and the first conductive layer are deposited is as shown in FIG. Figure 3c As shown, after removing the second insulating layer and the first conductive layer in the third gate line gap 102c, the structure is as follows Figure 3d As shown. Figure 3e As shown, after the third gate line gap 102c is filled, a first gate line isolation structure 11a, a second gate line isolation structure 11b' and a third gate line isolation structure 11c are formed. The second gate line isolation structure 11b' includes a second air gap 111b' and a second connecting portion 112b'.

[0116] It should be noted that the length L3 of the second connection portion 112b' along the first direction (X) is greater than the length of the first connection portion along the first direction (X). Figure 3e The first connection portion is not shown.

[0117] See also Figure 4a-4c and Figure 5 , Figure 4a-4c is a schematic diagram of the structure of a semiconductor device during the preparation process provided by some embodiments of the present application, Figure 5 It is a schematic diagram of the cross-sectional structure of a semiconductor device during the preparation process provided by some embodiments of the present application.

[0118] The method for preparing the semiconductor device includes the above steps S1-S2, wherein a plurality of first hole structures 11 and a plurality of second hole structures 12 are formed in the first stacked layer 10, wherein the first hole structures 11 are located in the core region 10a, and the second hole structures 12 are located in the transition region 10b.

[0119] The method for preparing the semiconductor device may also include: 1) forming a second stacking layer 20 on the first stacking layer 10, and forming a middle hole structure that penetrates the second stacking layer 20 along the stacking direction (Z) and is arranged along the first direction (X), the middle hole structure including a first middle hole structure 21 located in the core area 10a and a second middle hole structure 22 located in the transition area 10b; 2) forming a third stacking layer 30 on the second stacking layer 20, and forming an upper hole structure that penetrates the second stacking layer 20 along the stacking direction (Z) and is arranged along the first direction (X), the upper hole structure including a first upper hole structure 31 located in the core area 10a and a second upper hole structure 32 located in the transition area 10b.

[0120] in, Figure 4c The structure shown is after the hole structure is formed in the first stack layer 10. Figure 4b The structure shown is after the middle hole structure is formed in the second stacking layer 20. Figure 4a The structure shown is after the upper hole structure is formed in the third stacked layer 30. The middle hole structure is connected to the hole structure, and the upper hole structure is connected to the middle hole structure. Figure 4a The outline of the middle dotted circle connected to the third stacked layer 30 is the outline of the upper gate line gap. Figure 4b The outline of the middle dashed circle connected to the second stacked layer 20 is the outline of the middle grid line gap. Figure 4c The outline of the middle dotted circle connected to the first stacked layer 10 is the outline of the gate line gap (including the first gate line gap, the second gate line gap and the third gate line gap that are connected).

[0121] like Figure 5As shown, the maximum size of the first hole structure 11 along the first direction (X), the maximum size of the first middle hole structure 21 along the first direction (X), and the maximum size of the first upper hole structure 31 along the first direction (X) are all equal, which is D1. The maximum size D2 of the second hole structure 12 along the first direction (X) is smaller than the maximum size D3 of the second middle hole structure 22 along the first direction (X). The maximum size D3 of the second middle hole structure 22 along the first direction (X) is smaller than the maximum size D4 of the second upper hole structure 32 along the first direction (X). That is, from top to bottom, the size of the hole structure of the transition zone 10b gradually decreases, so compared with the first middle hole structure 21 and the first hole structure 11 of the core zone 10a, the hole spacing between the second middle hole structure 22 and the hole spacing between the second hole structure 12 are increased, thereby increasing the length of the second middle connecting portion and the second connecting portion after filling. Moreover, in the method for preparing a semiconductor device with multiple stacked layers, the second upper hole structure 32 has a larger size, which is beneficial to the filling process of the second middle hole structure 22 and the second hole structure 12 below, and can further increase the length of the filled part (connecting part).

[0122] In some embodiments, the maximum dimension D4 of the second upper hole structure 32 along the first direction (X) is less than or equal to the maximum dimension D1 of the first upper hole structure 31 along the first direction (X). When the maximum dimension D4 of the second upper hole structure 32 is less than the maximum dimension D1 of the first upper hole structure 31, the length of the first upper connecting portion can be increased.

[0123] The present disclosure also provides a semiconductor device. The semiconductor device in the present disclosure may be a wafer. After the wafer is cut, a plurality of chips may be formed, such as a three-dimensional memory. The three-dimensional memory may be applied to communication products, consumer electronic products, automotive products, aerospace products, artificial intelligence products or big data, etc. Among them, consumer electronic products include but are not limited to mobile phones, computers, tablets, cameras, smart glasses or game products, etc.

[0124] See also Figure 6 , Figure 6 is a schematic diagram of the structure of a semiconductor device provided in some embodiments of the present application. The semiconductor device is prepared by the method for preparing a semiconductor device provided in any of the above embodiments, so it can be combined with reference to Figure 2e and Figure 3e It should be noted that Figure 6 Examples and Figure 2e The difference lies in the number of first air gaps 111 a shown.

[0125] The semiconductor device includes a first stacked structure 10', a first gate line isolation structure 11a and a second gate line isolation structure 11b. The first stacked structure 10' includes a first insulating layer and a gate layer alternately stacked, and the first stacked structure 10' includes a core area 10a, a transition area 10b and a connection area 10c adjacent to each other in a first direction (X), and the transition area 10b is located between the core area 10a and the connection area 10c. The first gate line isolation structure 11a penetrates the first stacked structure 10' of the core area 10a along the stacking direction (Z) and extends along the first direction (X). The second gate line isolation structure 11b / 11b' penetrates the first stacked structure 10' of the transition area 10b along the stacking direction (Z), and the second gate line isolation structure 11b / 11b' extends along the first direction (X) and is connected to the first gate line isolation structure 11a. The first gate line isolation structure 11a includes a plurality of first air gaps 111a arranged along the first direction (X), and a first connecting portion 112a located between two adjacent first air gaps 111a. The second gate line isolation structure 11b / 11b' includes a plurality of second air gaps 111b arranged along the first direction (X), and a second connecting portion 112b located between two adjacent second air gaps 111b. The size L1 of the second connecting portion 112b along the first direction (X) is greater than the size L2 of the first connecting portion 112a along the first direction (X).

[0126] In some embodiments, the semiconductor device further includes a third gate line isolation structure 11c, wherein the third gate line isolation structure 11c penetrates the first stacking structure 10' of the connection area 10c along the stacking direction (Z), and the third gate line isolation structure 11c extends along the first direction (X) and is connected to the second gate line isolation structure 11b / 11b'. The maximum dimension of the first gate line isolation structure 11a in the second direction (Y) is smaller than the minimum dimension of the third gate line isolation structure 11c in the second direction (Y). The maximum dimension of the second gate line isolation structure 11b / 11b' in the second direction (Y) is also smaller than the minimum dimension of the third gate line isolation structure 11c in the second direction (Y).

[0127] In some embodiments, Figure 2e As shown, the top view of the second gate line isolation structure 11b / 11b' includes a plurality of first arcs connected along the first direction (X), and the arc lengths of the plurality of first arcs are equal.

[0128] In some embodiments, Figure 3eAs shown, the top view of the second gate line isolation structure 11b / 11b' further includes a second arc connected to the first arc, the second arc is located between two adjacent first arcs, and the arc length of the second arc is less than the arc length of the first arc.

[0129] In some embodiments, Figure 4a-4c After the dotted outline is filled on the basis of, the semiconductor device also includes a second stacking structure, a middle gate line isolation structure, a third stacking structure and an upper gate line isolation structure. The second stacking structure is located on the first stacking structure 10', and the middle gate line isolation structure runs through the second stacking structure along the stacking direction (Z) and extends along the first direction (X). The middle gate line isolation structure includes a first middle gate line isolation structure located in the core area 10a and a second middle gate line isolation structure located in the transition area 10b. The third stacking structure is located on the second stacking structure, and the upper gate line isolation structure runs through the third stacking structure along the stacking direction (Z) and extends along the first direction (X). The upper gate line isolation structure includes a first upper gate line isolation structure located in the core area 10a and a second upper gate line isolation structure located in the transition area 10b. Wherein, the first gate line isolation structure 11a, the first middle gate line isolation structure and the first upper gate line isolation structure are connected in the stacking direction (Z). The second gate line isolation structure, the second middle gate line isolation structure and the second upper gate line isolation structure are connected in the stacking direction (Z).

[0130] In some embodiments, the maximum dimension of the second upper gate line isolation structure along the second direction (Y) is greater than the maximum dimension of the second middle gate line isolation structure along the second direction (Y). The maximum dimension of the second middle gate line isolation structure along the second direction (Y) is greater than the maximum dimension of the second gate line isolation structure along the second direction (Y). That is, the maximum dimensions of the second upper gate line isolation structure, the second middle gate line isolation structure and the second gate line isolation structure gradually decrease from top to bottom.

[0131] The first middle gate line isolation structure includes a plurality of first middle air gaps arranged along the first direction (X), and a first middle connection portion located between two adjacent first middle air gaps. The second middle gate line isolation structure includes a plurality of second middle air gaps arranged along the first direction (X), and a second middle connection portion located between two adjacent second middle air gaps. The size of the second middle connection portion along the first direction (X) is greater than the size of the first middle connection portion along the first direction (X), thereby increasing the length of the second middle connection portion in the transition region 10b in the second stacking structure.

[0132] The first upper gate line isolation structure includes a plurality of first upper air gaps arranged along the first direction (X), and a first upper connection portion located between two adjacent first upper air gaps. The second upper gate line isolation structure includes a plurality of second upper air gaps arranged along the first direction (X), and a second upper connection portion located between two adjacent second upper air gaps. The size of the first upper connection portion along the first direction (X) is greater than the size of the second upper connection portion along the first direction (X), so the length of the second upper connection portion in the transition region 10b in the third stacking structure can be increased.

[0133] Therefore, for semiconductor devices with multiple stacked structures, for each stacked structure, the size of the connecting portion of the transition region 10b along the first direction (X) may be greater than the size of the connecting portion of the core region 10a along the first direction (X).

[0134] In some embodiments, since the maximum dimension D4 of the second upper hole structure 32 along the first direction (X) is less than or equal to the maximum dimension D1 of the first upper hole structure 31 along the first direction (X), the dimension of the first upper connecting portion along the first direction (X) may be less than or equal to the dimension of the second upper connecting portion along the first direction (X).

[0135] In some embodiments, since the maximum size of the hole structure of the transition zone 10b gradually decreases from top to bottom, the size of the second upper connecting portion along the first direction (X) is smaller than the size of the second middle connecting portion along the first direction (X); the size of the second middle connecting portion along the first direction (X) is smaller than the size of the second connecting portion 112b along the first direction (X), that is, the length of the connecting portion of the transition zone 10b gradually increases from top to bottom.

[0136] In the semiconductor device provided by the embodiment of the present disclosure, the size of the second connection portion 112b of the transition zone 10b along the first direction (X) is larger than the size of the first connection portion 112a of the core zone 10a along the first direction (X), which can ensure the supporting performance of the device and does not require the increase of the transition zone 10b, thereby increasing the storage space of the core zone 10a.

[0137] See also Figure 7 , Figure 7 1 is a schematic diagram of a memory structure provided in some embodiments of the present application. The memory 100 may be a three-dimensional memory, such as a 3D NAND or 3D NOR memory.

[0138] The memory 100 includes a semiconductor device 101 and a peripheral circuit 102. The semiconductor device 101 may be any semiconductor device in the above embodiments, and the peripheral circuit 102 may be a CMOS (complementary metal oxide semiconductor). The peripheral circuit 102 is electrically connected to the semiconductor device 101 to transmit signals to the semiconductor device 101. The peripheral circuit 102 may be used for logical operations and for controlling and detecting the switching states of each storage unit in the semiconductor device 101 through metal wiring to achieve data storage and reading.

[0139] Among them, the semiconductor device 101 includes: a first stacking structure, including a first insulating layer and a gate layer alternately stacked, the first stacking structure including a core area, a transition area and a connection area adjacent to each other in a first direction, the transition area is located between the core area and the connection area, and the first direction intersects with the stacking direction of the stacking structure; a first gate line isolation structure, which penetrates the first stacking structure of the core area along the stacking direction and extends along the first direction; a second gate line isolation structure, which penetrates the first stacking structure of the transition area along the stacking direction, and the second gate line isolation structure extends along the first direction and is connected to the first gate line isolation structure; wherein the first gate line isolation structure includes a plurality of first air gaps arranged along the first direction, and a first connecting portion located between two adjacent first air gaps; the second gate line isolation structure includes a plurality of second air gaps arranged along the first direction, and a second connecting portion located between two adjacent second air gaps; the size of the second connecting portion along the first direction is larger than the size of the first connecting portion along the first direction.

[0140] See also Figure 8 , Figure 8 2 is a schematic diagram of the structure of a storage system provided in some embodiments of the present application. The storage system 200 includes a memory 201 and a controller 202. The memory 201 may be a memory in any of the above embodiments. The memory 201 may include any semiconductor device in the above embodiments. The controller 202 is electrically connected to the memory 201 and is used to control the memory 201 to store data. The memory 201 may perform an operation of storing data based on the control of the controller 202.

[0141] In some embodiments, the storage system may be implemented as a storage device such as a universal flash storage (UFS) device, a solid state drive (SSD), a multimedia card in the form of MMC, eMMC, RS-MMC and micro MMC, a secure digital card in the form of SD, mini SD and micro SD, a Personal Computer Memory Card International Association (PCMCIA) card type storage device, a peripheral component interconnect (PCI) type storage device, a high-speed PCI (PCI-E) type storage device, a compact flash (CF) card, a smart media card or a memory stick, etc.

[0142] The semiconductor device in the memory 201 includes: a first stacking structure, including a first insulating layer and a gate layer alternately stacked, the first stacking structure including a core area, a transition area and a connection area adjacent to each other in a first direction, the transition area is located between the core area and the connection area, and the first direction intersects with the stacking direction of the stacking structure; a first gate line isolation structure, which penetrates the first stacking structure in the core area along the stacking direction and extends along the first direction; a second gate line isolation structure, which penetrates the first stacking structure in the transition area along the stacking direction, and the second gate line isolation structure extends along the first direction and is connected to the first gate line isolation structure; wherein the first gate line isolation structure includes a plurality of first air gaps arranged along the first direction, and a first connecting portion located between two adjacent first air gaps; the second gate line isolation structure includes a plurality of second air gaps arranged along the first direction, and a second connecting portion located between two adjacent second air gaps; the size of the second connecting portion along the first direction is larger than the size of the first connecting portion along the first direction.

[0143] The description of the above embodiments is only used to help understand the technical solutions and core ideas of the present invention. Ordinary technical personnel in this field should understand that they can still modify the technical solutions recorded in the aforementioned embodiments, or replace some of the technical features therein with equivalents. However, these modifications or replacements do not make the essence of the corresponding technical solutions deviate from the scope of the technical solutions of the embodiments of the present invention.

Claims

1. A method for preparing a semiconductor device, characterized in that: The method for preparing the semiconductor device comprises: forming a first stacked layer, the first stacked layer comprising a first insulating layer and a sacrificial layer alternately stacked, the first stacked layer comprising a core region, a transition region and a connection region adjacent to each other in a first direction, the transition region being located between the core region and the connection region, and the first direction intersecting with a stacking direction of the first stacked layer; A first gate line isolation structure located in the core area and a second gate line isolation structure located in the transition area are formed, wherein the first gate line isolation structure includes a plurality of first air gaps arranged along the first direction, and a first connecting portion located between two adjacent first air gaps; the second gate line isolation structure includes a plurality of second air gaps arranged along the first direction, and a second connecting portion located between two adjacent second air gaps; a size of the second connecting portion along the first direction is greater than a size of the first connecting portion along the first direction.

2. The method for preparing a semiconductor device according to claim 1, wherein: The size of the second connecting portion along the first direction ranges from 25 to 55 nm.

3. The method for preparing a semiconductor device according to claim 1, characterized in that: The step of forming a first gate line isolation structure located in the core area and a second gate line isolation structure located in the transition area includes: Forming a hole structure that penetrates the first stacking layer along the stacking direction and is arranged at intervals along the first direction, wherein the hole structure includes a first hole structure located in the core area and a second hole structure located in the transition area; Expanding the hole structure to form a first grid line gap located in the core area and a second grid line gap located in the transition area; A filling layer is formed in the first gate line gap and the second gate line gap to form a first gate line isolation structure and a second gate line isolation structure.

4. The method for preparing a semiconductor device according to claim 3, characterized in that: The step of forming a hole structure penetrating the first stacking layer along the stacking direction and arranged at intervals along the first direction comprises: Etching the first stacked layer along the stacking direction of the first stacked layer to form a first hole structure, a second hole structure and a third hole structure respectively located in the core area, the transition area and the connection area, the first hole structure and the second hole structure are arranged in a row along the first direction, and the third hole structure is arranged in multiple rows along the first direction; Wherein, two adjacent rows of the third hole structures are staggered along the first direction, and the intervals between three adjacent third hole structures are equal.

5. The method for preparing a semiconductor device according to claim 4, characterized in that: The step of expanding the hole structure comprises: The first stacked layer around the first hole structure, the second hole structure and the third hole structure is etched to respectively form a first gate line gap, a second gate line gap and a third gate line gap extending along a first direction and interconnected.

6. The method for preparing a semiconductor device according to claim 4, characterized in that: The hole spacing between two adjacent second hole structures is greater than the hole spacing between two adjacent first hole structures; the hole spacing between adjacent first hole structures and second hole structures is greater than the hole spacing between two adjacent first hole structures; the hole spacing between adjacent third hole structures and second hole structures is greater than the hole spacing between two adjacent first hole structures.

7. The method for preparing a semiconductor device according to claim 3, characterized in that: The method for preparing the semiconductor device further includes: In the process of forming the hole structure, a channel hole and a virtual channel hole are formed which penetrate the first stack layer along the stacking direction of the first stack layer; The channel hole is located in the core area and between two adjacent rows of the first hole structure, and the virtual channel hole is located in the transition area and between two adjacent rows of the second hole structure.

8. The method for preparing a semiconductor device according to claim 3, characterized in that: The step of forming a hole structure penetrating the first stacking layer along the stacking direction and arranged at intervals along the first direction comprises: Etching the first stacked layer along the stacking direction to form a first pore structure located in the core area and a second pore structure located in the transition area, wherein the second pore structure includes first sub-pore structures and second sub-pore structures alternately arranged along the first direction; The maximum dimension of the first sub-hole structure along the first direction is equal to the maximum dimension of the first hole structure along the first direction, and the maximum dimension of the second sub-hole structure along the first direction is smaller than the maximum dimension of the first sub-hole structure along the first direction.

9. The method for preparing a semiconductor device according to claim 3, characterized in that: The method for preparing the semiconductor device further includes: Forming a second stacking layer on the first stacking layer, and forming a middle hole structure that penetrates the second stacking layer along the stacking direction and is arranged along the first direction, wherein the middle hole structure includes a first middle hole structure located in the core area and a second middle hole structure located in the transition area; forming a third stacking layer on the second stacking layer, and forming an upper hole structure penetrating the second stacking layer along the stacking direction and arranged along the first direction, wherein the upper hole structure includes a first upper hole structure located in the core area and a second upper hole structure located in the transition area; Among them, the middle hole structure is connected to the hole structure, and the upper hole structure is connected to the middle hole structure; the maximum size of the second hole structure along the first direction is smaller than the maximum size of the second middle hole structure along the first direction, and the maximum size of the second middle hole structure along the first direction is smaller than the maximum size of the second upper hole structure along the first direction.

10. The method for preparing a semiconductor device according to claim 9, characterized in that: The maximum dimension of the first hole structure along the first direction, the maximum dimension of the first middle hole structure along the first direction, and the maximum dimension of the first upper hole structure along the first direction are all equal.

11. The method for preparing a semiconductor device according to claim 5, characterized in that: The step of forming a filling layer in the first gate line gap and the second gate line gap comprises: A second insulating layer and a first conductive layer are formed in the first gate line gap, the second gate line gap, and the third gate line gap.

12. The method for preparing a semiconductor device according to claim 11, characterized in that: Before the step of forming a second insulating layer and a first conductive layer in the first gate line gap, the second gate line gap and the third gate line gap, the method for preparing the semiconductor device further includes: The sacrificial layer in the first stacked layer of the core region is replaced with a gate layer.

13. A semiconductor device, characterized in that: The semiconductor device comprises: A first stacked structure, comprising a first insulating layer and a gate layer alternately stacked, the first stacked structure comprising a core region, a transition region and a connection region adjacent to each other in a first direction, the transition region being located between the core region and the connection region, and the first direction intersecting with a stacking direction of the stacked structure; A first gate line isolation structure, penetrating the first stacking structure of the core area along the stacking direction and extending along the first direction; A second gate line isolation structure, which penetrates the first stacking structure in the transition region along the stacking direction, and the second gate line isolation structure extends along the first direction and is connected to the first gate line isolation structure; Among them, the first gate line isolation structure includes a plurality of first air gaps arranged along the first direction, and a first connecting portion located between two adjacent first air gaps; the second gate line isolation structure includes a plurality of second air gaps arranged along the first direction, and a second connecting portion located between two adjacent second air gaps; the size of the second connecting portion along the first direction is greater than the size of the first connecting portion along the first direction.

14. The semiconductor device according to claim 13, characterized in that The semiconductor device further includes a third gate line isolation structure, wherein the third gate line isolation structure penetrates the first stacking structure of the connection region along the stacking direction, and the third gate line isolation structure extends along the first direction and is connected to the second gate line isolation structure; The maximum dimension of the first gate line isolation structure in the second direction is smaller than the minimum dimension of the third gate line isolation structure in the second direction, and the second direction intersects the stacking direction and the first direction.

15. The semiconductor device according to claim 13, wherein: The top view of the second gate line isolation structure includes a plurality of first arcs connected along the first direction, and the arc lengths of the plurality of first arcs are equal.

16. The semiconductor device according to claim 15, characterized in that The top view of the second gate line isolation structure further includes a second arc connected to the first arc, the second arc is located between two adjacent first arcs, and the arc length of the second arc is less than the arc length of the first arc.

17. The semiconductor device according to claim 13, characterized in that The semiconductor device further comprises: A second stacking structure, located on the first stacking structure; a middle gate line isolation structure, penetrating the second stacking structure along the stacking direction and extending along the first direction, the middle gate line isolation structure comprising a first middle gate line isolation structure located in the core area and a second middle gate line isolation structure located in the transition area; a third stacking structure, located on the second stacking structure; an upper gate line isolation structure, penetrating the third stacking structure along the stacking direction and extending along the first direction, the upper gate line isolation structure comprising a first upper gate line isolation structure located in the core area and a second upper gate line isolation structure located in the transition area; Wherein, the first gate line isolation structure, the first middle gate line isolation structure and the first upper gate line isolation structure are connected in the stacking direction, and the second gate line isolation structure, the second middle gate line isolation structure and the second upper gate line isolation structure are connected in the stacking direction; The maximum dimension of the second upper gate line isolation structure along the second direction is greater than the maximum dimension of the second middle gate line isolation structure along the second direction; the maximum dimension of the second middle gate line isolation structure along the second direction is greater than the maximum dimension of the second gate line isolation structure along the second direction.

18. The semiconductor device according to claim 17, characterized in that The first middle gate line isolation structure includes a plurality of first middle air gaps arranged along the first direction, and a first middle connecting portion located between two adjacent first middle air gaps; The second middle gate line isolation structure includes a plurality of second middle air gaps arranged along the first direction, and a second middle connecting portion located between two adjacent second middle air gaps; A dimension of the second middle connecting portion along the first direction is greater than a dimension of the first middle connecting portion along the first direction.

19. The semiconductor device according to claim 18, characterized in that The first upper gate line isolation structure includes a plurality of first upper air gaps arranged along the first direction, and a first upper connecting portion located between two adjacent first upper air gaps; The second upper gate line isolation structure includes a plurality of second upper air gaps arranged along the first direction, and a second upper connecting portion located between two adjacent second upper air gaps; A dimension of the first upper connecting portion along the first direction is greater than or equal to a dimension of the second upper connecting portion along the first direction.

20. The semiconductor device according to claim 19, characterized in that A dimension of the second upper connecting portion along the first direction is smaller than a dimension of the second middle connecting portion along the first direction; a dimension of the second middle connecting portion along the first direction is smaller than a dimension of the second connecting portion along the first direction.

21. A memory, characterized in that: include: A semiconductor device as claimed in any one of claims 13 to 20; A peripheral circuit is electrically connected to the semiconductor device.

22. A storage system, characterized in that: include: The memory as claimed in claim 21; A controller is electrically connected to the memory and is used to control the memory to store data.

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