Power semiconductor device and method of manufacturing power semiconductor device

Abstract

A power semiconductor device includes: a semiconductor body having a drift region of a first conductivity type; a first load terminal on a first side of the semiconductor body; a second load terminal on a second side of the semiconductor body opposite the first side, wherein the power semiconductor device is configured to conduct a load current between the first load terminal and the second load terminal; a control terminal located at the first side and configured to receive a control signal for controlling a load current; a first trench laterally limits a mesa for conducting a load current within an active region of the power semiconductor device at least partially surrounded by an edge termination region. The first trench includes a control trench electrically connected to the control terminal. The first trenches are arranged according to a first average pitch. The device also includes second trenches in a region laterally overlapping the control terminals, where the second trenches are arranged according to a second average pitch different from the first average pitch, and electrically connected to the control terminals.

Description

Technical Field

[0001] The present description relates to embodiments of a power semiconductor device and embodiments of a method of manufacturing a power semiconductor device. Background Art

[0002] Many functions of modern devices in automotive, consumer and industrial applications, such as converting electrical energy and driving electric motors or motors, rely on power semiconductor devices. For example, insulated gate bipolar transistors (IGBTs), metal oxide semiconductor field effect transistors (MOSFETs), and diodes, to name a few, have been used in a variety of applications including, but not limited to, switches in power supplies and power converters.

[0003] A power semiconductor device typically includes a semiconductor body configured to conduct a forward load current along a load current path between two load terminals of the device. The load current is typically conducted by means of an active region of the power semiconductor device. The active region is typically surrounded by an edge termination region that is terminated by the edge of the chip.

[0004] In the case of a controllable power semiconductor device, such as a transistor, the load current path can be controlled by means of an insulated electrode, usually referred to as a gate electrode. For example, upon receiving a corresponding control signal from a driver unit, for example via a control terminal of the device, the control electrode can set the power semiconductor device to one of a forward conducting state and a blocking state.

[0005] In addition, some devices provide reverse load current capability; that is, the active area of ​​the semiconductor body is also configured to conduct reverse load current along a reverse load current path between the two load terminals of the device. For example, the RC (reverse current) IGBT is a representative of such a device. In the RC IGBT, a single chip combines the IGBT structure and the diode structure.

[0006] Regardless of whether the device exhibits an RC configuration or not, it is generally a goal to design power semiconductor devices so that they exhibit high robustness, ie with respect to electrostatic discharge (ESD).

[0007] Customers may require a given ESD robustness. However, small chips often cannot provide a sufficient level of ESD robustness. Typical solutions to this problem include increasing the chip size and / or changing the contact scheme of the mesas and trenches in the active area. However, this may result in higher costs or reduced device performance. Summary of the invention

[0008] The subject matter of the independent claims is set out. Features of the exemplary embodiments are defined in the dependent claims.

[0009] According to an embodiment, a power semiconductor device includes: a semiconductor body having a drift region of a first conductivity type; a first load terminal located at a first side of the semiconductor body; a second load terminal located at a second side of the semiconductor body opposite to the first side, wherein the power semiconductor device is configured to conduct a load current between the first load terminal and the second load terminal; a control terminal located at the first side, configured to receive a control signal for controlling the load current; in an active area of ​​the power semiconductor device at least partially surrounded by an edge termination area, a first trench laterally limits a table for conducting the load current. The first trench includes a control trench electrically connected to the control terminal. The first trench is arranged according to a first average spacing. The device also includes a second trench in a region laterally overlapping with the control terminal, wherein the second trench is arranged according to a second average spacing different from the first average spacing and is electrically connected to the control terminal.

[0010] According to an embodiment, a power semiconductor device includes: a semiconductor body having a drift region of a first conductivity type; a first load terminal located at a first side of the semiconductor body; a second load terminal located at a second side of the semiconductor body opposite to the first side, wherein the power semiconductor device is configured to conduct a load current between the first load terminal and the second load terminal; a control terminal located at the first side, configured to receive a control signal for controlling the load current; in an active area of ​​the power semiconductor device at least partially surrounded by an edge termination area, a first trench laterally limits a table for conducting the load current. The first trench includes a control trench electrically connected to the control terminal. The first trench is arranged according to a first average spacing. The device also includes a second trench in a region laterally overlapping with the edge termination area, wherein the second trench is arranged according to a second average spacing different from the first average spacing and is electrically connected to the control terminal. In other words, the second trench can be arranged in the edge termination area and / or in a region laterally overlapping with the control terminal.

[0011] According to another embodiment, a method for manufacturing a power semiconductor device includes forming the following components: a semiconductor body having a drift region of a first conductivity type; a first load terminal located on a first side of the semiconductor body; a second load terminal located on a second side of the semiconductor body opposite to the first side, wherein the power semiconductor device is configured to conduct a load current between the first load terminal and the second load terminal; a control terminal located on the first side, configured to receive a control signal for controlling the load current; in an active area of ​​the power semiconductor device at least partially surrounded by an edge termination area, a first trench laterally limits a mesa for conducting the load current. The first trench includes a control trench electrically connected to the control terminal. The first trench is arranged according to a first average spacing. The device also includes a second trench in a region laterally overlapping with the control terminal, wherein the second trench is arranged according to a second average spacing different from the first average spacing and is electrically connected to the control terminal.

[0012] According to some embodiments described herein, a given ESD robustness is improved by adding dedicated structures using chip space that is not normally used for this purpose, for example, chip space below the control terminal (gate pad). Customized spacing and / or contact schemes different from the trenches in the cell field formed in the active area can be provided there. According to some embodiments, these structures can be added with only slight layout changes without adding additional process steps.

[0013] Those skilled in the art will recognize additional features and advantages upon reading the following detailed description, and upon viewing the accompanying drawings. BRIEF DESCRIPTION OF THE DRAWINGS

[0014] The components in the drawings are not necessarily to scale, instead, emphasis is placed on illustrating the principles of the present invention. In addition, in the drawings, the same reference numerals designate corresponding components. In the drawings:

[0015] Figure 1A schematically and exemplarily illustrates a horizontal projection of a power semiconductor device according to one or more embodiments;

[0016] Figure 1B The power semiconductor device according to one or more embodiments is schematically and exemplarily illustrated. Figure 1A A vertical cross section at the line C indicated in;

[0017] Figure 2 Schematically and exemplarily, the present invention is described in more detail according to one or more embodiments. Figure 1A Segment B of the horizontal projection of

[0018] Figure 3 Schematically and exemplarily, the present invention is described in more detail according to one or more embodiments. Figure 1A Segment A of the horizontal projection of

[0019] Figure 4 schematically and exemplarily illustrates a section of a vertical cross-section of a power semiconductor device according to one or more embodiments; and

[0020] Figure 5 A horizontally projected section of a power semiconductor device according to one or more embodiments is schematically and exemplarily illustrated. DETAILED DESCRIPTION

[0021] In the following detailed description, reference is made to the accompanying drawings, which form a part hereof, and in which is shown by way of illustration specific embodiments in which the invention may be practiced.

[0022] In this regard, directional terms, such as "top", "bottom", "below", "front", "rear", "back", "leading", "trailing", "above", etc., may be used with reference to the orientation of the figure being described. Since the components of the embodiments may be positioned in many different orientations, the directional terms are used for illustrative purposes and are in no way limiting. It is to be understood that other embodiments may be utilized and structural or logical changes may be made without departing from the scope of the present invention. Therefore, the following detailed description is not to be construed in a limiting sense, and the scope of the present invention is defined by the appended claims.

[0023] Reference will now be made in detail to various embodiments, one or more examples of which are illustrated in the drawings. Each example is provided by way of explanation and is not meant to be a limitation of the invention. For example, features illustrated or described as part of one embodiment may be used in other embodiments or used in conjunction with other embodiments to produce yet other embodiments. It is intended that the invention includes such modifications and variations. Examples are described using specific language, which should not be interpreted as limiting the scope of the appended claims. The drawings are not to scale and are for illustrative purposes only. For clarity, if not otherwise stated, identical elements or manufacturing steps have been indicated by identical reference numerals in different drawings.

[0024] The term "horizontal" as used in this specification is intended to describe an orientation substantially parallel to a horizontal surface of a semiconductor substrate or semiconductor structure. This may be, for example, the surface of a semiconductor wafer or die or chip. For example, both the first lateral direction X and the second lateral direction Y mentioned below may be horizontal directions, wherein the first lateral direction X and the second lateral direction Y may be perpendicular to each other.

[0025] The term "vertical" as used in this specification is intended to describe an orientation that is generally arranged perpendicular to a horizontal surface, i.e. parallel to the normal direction of the surface of the semiconductor wafer / chip / die. For example, the extension direction Z mentioned below may be an extension direction perpendicular to both the first lateral direction X and the second lateral direction Y. The extension direction Z is also referred to herein as the "vertical direction Z".

[0026] In this specification, n-doping is referred to as the “first conductivity type” and p-doping is referred to as the “second conductivity type.” Alternatively, the opposite doping relationship may be adopted, such that the first conductivity type may be p-doped and the second conductivity type may be n-doped.

[0027] In the context of this specification, the terms "in ohmic contact", "in electrical contact", "in ohmic connection" and "electrically connected" are intended to describe the presence of a low-ohmic electrical connection or a low-ohmic current path between two regions, sections, areas, parts or components of a semiconductor device, or between different terminals of one or more devices, or between a terminal or metallization or electrode and a part or component of a semiconductor device, where "low ohmic" may mean that the characteristics of the respective contact are substantially unaffected by ohmic resistance. Further, in the context of this specification, the term "in contact" is intended to describe the presence of a direct physical connection between two elements of the respective semiconductor device; for example, a transition between two elements in contact with each other may not include additional intermediate elements, etc.

[0028] Additionally, in the context of this specification, if not stated otherwise, the term "electrically insulated" is used in its generally reasonably understood context, and is thus intended to describe two or more components that are located separately from each other and there is no ohmic connection connecting those components. However, components that are electrically insulated from each other may nevertheless be coupled to each other, such as mechanically and / or capacitively and / or inductively and / or electrostatically (e.g., in the case of a "junction"). To give an example, two electrodes of a capacitor may be electrically insulated from each other and at the same time mechanically and capacitively coupled to each other, such as by means of an insulating portion, such as a dielectric.

[0029] The specific embodiments described in this specification relate to, but are not limited to, power semiconductor devices that can be used in power converters or power supplies. Therefore, in one embodiment, such a power semiconductor device can be configured to carry a load current to be fed to a load and / or provided by a power supply, respectively. For example, the power semiconductor device may include one or more active power semiconductor unit cells, such as a monolithic integrated diode cell, a derivative of a monolithic integrated diode cell, a monolithic integrated transistor cell, for example a monolithic integrated IGBT or MOSFET cell and / or its derivatives. Such a diode / transistor cell can be integrated in a single chip. A plurality of such cells can constitute a cell field arranged in an active region of the power semiconductor device.

[0030] The term "blocking state" of a power semiconductor device may refer to a situation when the power semiconductor is in a state configured to block a load current when an external voltage is applied. More specifically, the power semiconductor device may be configured to prevent a forward load current from passing through the power semiconductor device when a forward bias is applied. In contrast, the power semiconductor device may be configured to conduct a forward load current in a "conducting state" of the power semiconductor device when a forward bias is applied. The transition between the blocking state and the conducting state may be controlled by a control electrode, or more specifically, by the potential of the control electrode. Of course, the electrical characteristics may only be applicable within a predetermined operating range of an external voltage and current density within the power semiconductor device. Therefore, the term "forward biased blocking state" may refer to a situation where a power semiconductor device is in a blocking state when a forward bias is applied.

[0031] The term "power semiconductor device" as used in this specification is intended to describe a power semiconductor device on a single chip having a high voltage blocking and / or a high current carrying capability. In other words, such a power semiconductor device is intended for high currents, typically in the ampere range, such as greater than 1 ampere, such as up to tens or hundreds of amperes, and / or high voltages, typically above 15 V, more typically 100 V and above, such as up to at least 400 V or even higher, such as up to at least 3 kV, or even up to 10 kV or more, depending on the respective application.

[0032] For example, the term "power semiconductor device" as used in this specification does not refer to a logic semiconductor device used for, for example, storing data, computing data, and / or other types of semiconductor-based data processing.

[0033] For example, the power semiconductor device described below may be a single semiconductor chip, for example, in a stripe cell configuration (or honeycomb / needle cell configuration), and may be configured for use as a power component in low, medium and / or high voltage applications.

[0034] Figure 1A A horizontal projection of a power semiconductor device 1 according to one or more embodiments is schematically and exemplarily illustrated. Figure 1B A schematic and exemplarily diagrammatically illustrates a vertical cross section (at Figure 1A (at line C indicated in the figure).

[0035] If you consider Figures 2 to 5 , will better understand the following description, which will also be mentioned below Figures 2 to 5 .

[0036] The power semiconductor device 1 (also referred to herein as “device”) comprises in a single chip a semiconductor body 10 configured to conduct a load current between a first load terminal 11 at a first side 110 of the semiconductor body 10 and a second load terminal 12 at a second side 120 of the semiconductor body 10 .

[0037] The first side 110 and the second side 120 may be arranged opposite to each other. For example, the first side 110 is the front side of the device 1 and the second side 20 is the back side of the device 1. Therefore, the device 1 may present a vertical configuration according to which the load current in the device 1 follows a path parallel to the vertical direction Z.

[0038] The device 1 further comprises a drift region 100 of the first conductivity type within the semiconductor body 10. Herein, the term "drift region" has the meaning that a skilled person usually associates with it in the field of power semiconductor devices. For example, the vertical extension of the drift region 100 affects the voltage blocking capability of the device 1.

[0039] The device 1 further comprises a first trench 14 (and 16) and a second trench 17 extending, for example, along a vertical direction Z from the first side 110 to the second side 120. Each trench 14, 16, 17 comprises a trench electrode separated from the semiconductor body 10 by a trench insulator (see Figure 4 , which illustrates that the trench electrodes 171 of two of the second trenches 17 are separated from the semiconductor body 10 by the trench insulator 172). The other trenches 14 and 16 may be configured identically.

[0040] The first trenches 14, 16 may include a control trench 14, wherein each trench electrode 141 of the control trench 14 is electrically insulated from the first load terminal 11 and is configured to receive a control signal. To this end, according to an embodiment, each trench electrode 141 of the control trench 14 may be electrically connected to a control terminal 13 of the device 1, for example via a control trench contact 145 (see Figure 3 and 5 ).

[0041] The control trenches 14 laterally delimit the mesas 18 of the semiconductor body 10. Each mesa 18 is electrically connected to the first load terminal 11, for example by means of a respective mesa contact 185 extending from the first load terminal 11 into the semiconductor body 10, such as Figure 1Bexemplarily illustrated in FIG. Optionally, a planar contact may be used. Each mesa 18 may be configured for load current conduction. For example, each mesa 18 includes a semiconductor body region 102 of a second conductivity type electrically connected to a first load terminal 11, and optionally, a semiconductor source region 101 of a first conductivity type electrically connected to the first load terminal 11, wherein the semiconductor source region 101 is isolated from the drift region 100 by at least the semiconductor body region 102. The adjacent control trench electrode 141 may be configured to induce an inversion channel in the semiconductor body region 102 when receiving a corresponding turn-on control signal. This process may set the device 1 to a forward conduction state. The adjacent control trench electrode 141 may be configured to cut off the inversion channel in the semiconductor body region 102 when receiving a corresponding turn-off control signal, which may set the device 1 to a forward blocking state.

[0042] Figure 1B The configuration illustrated in FIG is merely exemplary. The above-described features of the power semiconductor device 1 may allow different trench mesa patterns to be designed on the first side 110. Such a pattern may include additional trench types and / or additional mesa types, for example as part of a first trench source trench 16, a floating trench or a second type control trench, etc., wherein the trench electrode of the first trench source trench 16 is connected, for example, via a source trench contact 165 (see FIG. Figure 5 ) is electrically connected to the first load terminal 11, the trench electrode of the floating trench is not connected to a defined potential, and the trench electrode of the second type control trench is connected to a different control terminal than the control trench electrode 141 to realize a dual-gate or multi-gate configuration. In addition, other types of mesas can also be realized, such as mesas with different threshold voltages, virtual mesa portions, etc.

[0043] The doped region 109 of the semiconductor body 10 below the drift region 100, adjacent to the second load terminal 12 at the second side 120, may be configured according to the specified characteristics of the device 1. For example, if the device 1 is to assume an IGBT configuration, the doped region 109 may be an emitter region of the second conductivity type. The emitter region is arranged in contact with the second load terminal 12. Furthermore, a field stop region (not shown) of the first conductivity type may be provided between the drift region 100 and the second load terminal 12, wherein the field stop region exhibits a greater dopant concentration than the drift region 100. If the device 1 is to assume a MOSFET configuration, the emitter region is omitted so that the field stop region (or another highly doped region of the first conductivity type) will be adjacent to the second load terminal 12. As known to the skilled person, if the device 1 is to assume an RC IGBT configuration, the emitter region may exhibit a sub-segment of the first conductivity type.

[0044] The above-described components of the power semiconductor device 1 are arranged in an active area 1-2 of the device 1, which is surrounded by an edge termination area 1-3. In the active area 1-2, the first trenches 14, 16 and the associated mesas 18 can form a cell field, which can present a honeycomb / needle cell configuration or a strip cell configuration. As known to the skilled person, the edge termination area 1-3 is usually not used for load current conduction. The edge termination area 1-3 is terminated by the chip edge 1-4.

[0045] For example, refer to Figure 2 , which illustrates in more detail Figure 1A In the indicated section B, third trenches 15 may be arranged in the edge termination region 1 - 3 . Furthermore, these third trenches 15 may include insulated trench electrodes which may be electrically connected to a defined potential, such as to the control terminal 13 , for example via third trench contacts 155 .

[0046] According to an embodiment, the third trench 15 in the edge termination region 1-3 may extend perpendicularly to the first trenches 14, 16 in the active region 1-2. According to an embodiment, the third trench 15 in the edge termination region 1-3 is separated from the first trenches 14, 16 in the active region 1-2.

[0047] To facilitate potential distribution of the control terminal 13, the device 1 may include a gate runner 135 extending from the control terminal 13 along the periphery of the active region 1-2. The gate runner is electrically connected to the control terminal 13.

[0048] For example, refer to Figure 3 , which illustrates in more detail Figure 1A In the section A indicated in FIG. 1 , the device 1 may include a second trench 17 in a region laterally overlapping the control terminal 13. The second trench 17 (see Figure 4 ) may include a second trench electrode 171, which is insulated from the semiconductor body 10 via a second trench insulator 172 and is electrically connected to the control terminal 13, for example via a second trench contact 175. The second trench 17 may be an inactive trench and is not configured to induce an inversion channel. For example, the second trench 17 is not arranged adjacent to the source region 101. Within the scope of the present application, the region that laterally overlaps with the control terminal 13 may not be considered as part of the active region 1-2, because the region does not contribute or does not contribute significantly to the forward load current of the device 1.

[0049] Insulation structure 119 (see Figure 1B and Figure 4) can separate the terminal structure including the control terminal 13 and the first load terminal 11 from the semiconductor body 10. The insulating structure 119 can be partially penetrated by the mesa contact 185 (connecting the mesa 18 to the first load terminal 11), the source trench contact 165 (connecting the source trench 16 to the first load terminal 11), the control trench contact 145 (connecting the control trench electrode 141 to the control terminal 13) and the second trench contact 175 (connecting the second trench electrode 171 to the control terminal 13).

[0050] According to an embodiment, each of the grooves 14, 15, 16, 17 may be in a stripe configuration. For example, according to the stripe configuration, the length of the groove is significantly greater than the width of the groove, such as Figure 2 , 3 and 5 of each of the best illustrated ones.

[0051] like Figure 1A As shown in the figure, the control terminal 13 is arranged at the first side 110 and can be configured as a gate pad with a plate-like geometry. The total lateral cross-sectional area of ​​the control terminal 13 (and accordingly, the chip area that overlaps laterally therewith) can amount to at least 1%, or at least 3%, of the total lateral cross-sectional area of ​​the active area 1-2. The total lateral cross-sectional area of ​​the control terminal 13, for example, does not exceed 25% of the total lateral cross-sectional area of ​​the active area 1-2. In addition, the control terminal 13 can be at least partially surrounded by the active area 1-2.

[0052] The second trench 17 is arranged below the control terminal 13 and in a region of the chip that laterally overlaps with it. The first trenches 14 and 16 are arranged in the active area 1-2 and, for example, do not extend or each only partially extend in the region of the chip that laterally overlaps with the control terminal 13. According to an embodiment, for example, if provided, the source trench 16 does not extend into the region of the chip that laterally overlaps with the control terminal 13. Similarly, it can be provided that the second trench 17 is only arranged in the chip region that laterally overlaps with the control terminal 13. For example, the second trench 17 is separated from the first trenches 14, 16. Optionally, for example, as Figure 3 As indicated in FIG. 1 , it is also possible that the second trench 17 seamlessly extends into the active region 1-2 to form the control trench 14 there, since both the second trench electrode 171 and the control trench electrode 141 are electrically connected to the control terminal 13. In the latter case, the second trench electrode 171 and the control trench electrode 141 of the same trench may be formed by a monolithic trench electrode. For example, Figure 3 As shown in FIG. 1 , at least one of the control grooves 14 extends into a region laterally overlapping with the control terminal 13 and is connected to the control terminal 13 in the region laterally overlapping with the control terminal, for example based on one of the control groove contacts 145. Optionally, the grooves are separated from each other, such as Figure 5Then, the control trench contact 145 may be arranged, for example, to connect the gate runner 135 to the control trench electrode (see Figure 1A Alternatively, a gate finger (not shown) extends into the active region 1 - 2 , so that the control trench electrode 141 can be connected to the control terminal 13 in the active region 1 - 2 .

[0053] Regardless of which of the configurations described in the preceding paragraphs is selected, according to an embodiment, it is provided (see Figure 2-5 ) The first trenches 14, 16 in the active area 1-2 are arranged according to a first average pitch p1, and the second trenches 17 in the area of ​​the chip laterally overlapping the control terminal 13 are arranged according to a second average pitch p2 different from the first average pitch p1.

[0054] For example, the two pitches p1 and p2 are independent of each other. This allows, for example, the second pitch p2 to be adjusted to improve ESD robustness.

[0055] In an embodiment, the second average spacing p2 is greater than the first average spacing p1, for example, Figure 3 and Figure 5 As shown in the figure as an example.

[0056] Furthermore, it may be provided that the first pitch p1 in the active area 1-2 is constant, and / or the second pitch p2 in the area laterally overlapping with the control terminal 13 is constant. Therefore, in some embodiments, the pitch is constant, so that each pitch in the active area 1-2 is equal to the first average pitch p1, and each pitch in the area laterally overlapping with the control terminal 13 is equal to the second average pitch p2.

[0057] The second average spacing p2 and the first average spacing p1 differ from each other by a ratio of at least 1 / 2. For example, the second average spacing p2 amounts to at least twice the first average spacing p1 or at most half the first average spacing p1. For example, the ratio between the second average spacing p2 and the first average spacing p1 is equal to an integer or equal to the reciprocal of an integer. For example, the ratio between the second average spacing p2 and the first average spacing p1 is equal to a non-integer fraction greater than 1, or equal to the reciprocal of a non-integer fraction greater than 1.

[0058] Each of the first trenches 14, 16 and the second trenches 17 may present the same width (e.g., along the first lateral direction) and / or the same depth (along the vertical direction Z). For example, each of the first trenches 14, 16 and the second trenches 17 is manufactured simultaneously based on the same processing steps. For example, in order to achieve the pitch difference, only the mask used is changed accordingly between the mask section associated with the active area 1-2 and the mask portion associated with the area laterally overlapping the control terminal 13.

[0059] In the examples, see Figure 4 , the device 1 further comprises a doped region 105 of a second conductivity type in a region laterally overlapping with the control terminal 13, wherein the second trench extends into the doped region 105. For example, the doped region 105 extends further along the vertical direction Z than the second trench 17. It can be provided that the doped region 105 does not extend into the active region 1-2. The doped region 105 can be electrically connected to the first load terminal 11. The transition between the doped region 105 and the drift region 100 can form a pn junction. As indicated above, the pn junction can be arranged below the bottom of the second trench 17.

[0060] For example, based on the second trenches 17 and the optional doped region 105, an effective gate-source capacitance can be defined. In addition, it can also be provided that one or more of the source trenches 16 that can be arranged in the active area 1-2 also extend into the chip area, which is below the control terminal 13 / laterally overlapping with the control terminal 13. Nevertheless, if one or more of the source trenches 16 extend into the area, the difference in average spacing as described above is maintained. At least the second trenches 17 are arranged in the area, wherein these second trenches can be configured to improve the ESD robustness of the power semiconductor device 1.

[0061] In an embodiment, the second grooves 17 may also extend into the edge termination region 1-3. However, even in this case, the difference in average spacing as described above is maintained. The second grooves 17 in the termination region 1-3 may be oriented perpendicularly or parallel to the first grooves 14, 16, in particular the control groove 14. For example, some of the second grooves 17 in the termination region 1-3 may be oriented perpendicularly, and some of the second grooves 17 in the termination region 1-3 may be oriented parallel to the first grooves 14, 16.

[0062] The semiconductor body 10 may be based on Si or a wide bandgap material, such as SiC or GaN.

[0063] This article also proposes a method for manufacturing a power semiconductor device.

[0064] For example, according to another embodiment, a method for manufacturing a power semiconductor device includes forming the following components: a semiconductor body having a drift region of a first conductivity type; a first load terminal located on a first side of the semiconductor body; a second load terminal located on a second side of the semiconductor body opposite to the first side, wherein the power semiconductor device is configured to conduct a load current between the first load terminal and the second load terminal; a control terminal located on the first side, configured to receive a control signal for controlling the load current; in an active area of ​​the power semiconductor device at least partially surrounded by an edge termination area, a first trench laterally limits a mesa for conducting the load current. The first trench includes a control trench electrically connected to the control terminal. The first trench is arranged according to a first average spacing. The device also includes a second trench in a region laterally overlapping with the control terminal, wherein the second trench is arranged according to a second average spacing different from the first average spacing and is electrically connected to the control terminal.

[0065] The above-described embodiments of the method correspond to the above-described embodiments of the power semiconductor device 1. Therefore, these embodiments of the method will not be described verbatim herein, but reference is made to the above.

[0066] For example, as indicated above, the first trenches 14, 16 and the second trenches 17 are formed based on the same processing steps. Forming the first trenches 14, 16 and the second trenches 17 may include using a mask, wherein the structure of the mask produces a difference between the second average pitch p2 and the first average pitch p1.

[0067] In the above, embodiments concerning a power semiconductor device and a corresponding manufacturing method are explained.

[0068] For example, these power semiconductor devices are based on silicon (Si). Accordingly, a single-crystal semiconductor region or layer, such as a semiconductor body and its regions / areas, such as regions, etc., may be a single-crystal Si region or Si layer. In other embodiments, polycrystalline or amorphous silicon may be used.

[0069] However, it should be understood that the semiconductor body 10 and its regions / areas can be made of any semiconductor material suitable for manufacturing semiconductor devices. Examples of such materials include, but are not limited to, the following: elemental semiconductor materials, such as silicon (Si) or germanium (Ge); Group IV compound semiconductor materials, such as silicon carbide (SiC) or silicon germanium (SiGe); binary, ternary or quaternary III-V semiconductor materials, such as gallium nitride (GaN), gallium arsenide (GaAs), gallium phosphide (GaP), indium phosphide (InP), indium gallium phosphide (InGaPa), aluminum gallium nitride (AlGaN), aluminum indium nitride (AlInN), indium gallium nitride (InGaN), aluminum gallium indium nitride (AlGaInN) or gallium arsenide phosphide (InGaAsP); and binary or ternary II-VI semiconductor materials, such as cadmium telluride (CdTe) and mercury cadmium telluride (HgCdTe), to name a few. The previously mentioned semiconductor materials are also referred to as "homojunction semiconductor materials". When two different semiconductor materials are combined, a heterojunction semiconductor material is formed. Examples of heterojunction semiconductor materials include, but are not limited to, the following: aluminum gallium nitride (AlGaN)-aluminum gallium indium nitride (AlGaInN), indium gallium nitride (InGaN)-aluminum gallium indium nitride (AlGaInN), indium gallium nitride (InGaN)-gallium nitride (GaN), aluminum gallium nitride (AlGaN)-gallium nitride (GaN), indium gallium nitride (InGaN)-aluminum gallium nitride (AlGaN), silicon-silicon carbide (SixC1-x) and silicon-SiGe heterojunction semiconductor materials. For power semiconductor switch applications, Si, SiC, GaAs and GaN materials are currently used.

[0070] Spatially relative terms such as "below," "below," "lower," "above," "upper," and the like are used for ease of description to explain the positioning of one element relative to a second element. These terms are intended to encompass different orientations of the corresponding devices in addition to those different orientations depicted in the figures. Further, terms such as "first," "second," and the like are also used to describe various elements, regions, sections, and the like, and are also not intended to be limiting. Throughout this description, the same terms may refer to the same elements.

Claims

1. A power semiconductor device (1), comprising: - a semiconductor body (10) having a drift region (100) of a first conductivity type; - a first load terminal (11) located on a first side (110) of the semiconductor body (10); a second load terminal located at a second side (120) of the semiconductor body (10) opposite to the first side (110), wherein the power semiconductor device (1) is configured to conduct a load current between the first load terminal (11) and the second load terminal (12); - a control terminal (13) located on the first side (110) and configured to receive a control signal for controlling a load current; - In an active area (1-2) of a power semiconductor device (1) at least partially surrounded by an edge termination area (1-3), a first trench (14, 16) laterally delimits a mesa (18) for conducting a load current, wherein the first trench (14, 16) o comprises a control groove (14) electrically connected to a control terminal (13), and o arranged according to a first average spacing (p1); - a second groove (17) in a region laterally overlapping the control terminal (13), wherein the second groove (17) is o arranged according to a second average pitch (p2) different from the first average pitch (p1); and oElectrically connected to the control terminal (13).

2. The power semiconductor device (1) according to claim 1, wherein: The second average pitch (p2) is greater than the first average pitch (p1).

3. The power semiconductor device (1) according to claim 1 or 2, wherein: A first pitch (p1) in the active region (1-2) is constant and / or a second pitch (p2) in the region laterally overlapping with the control terminal (13) is constant.

4. The power semiconductor device (1) according to one of the preceding claims, wherein: The second average pitch (p2) and the first average pitch (p1) differ from each other by a ratio of at least 1 / 2.

5. The power semiconductor device (1) according to one of the preceding claims, wherein: The first grooves (14, 16) and the second grooves (17) present the same width and / or the same depth.

6. The power semiconductor device (1) according to one of the preceding claims, further comprising a doped region (105) of the second conductivity type in a region laterally overlapping the control terminal (13), wherein the second trench extends into the doped region (105).

7. The power semiconductor device (1) according to claim 6, wherein: The doped region (105) is electrically connected to the first load terminal (11).

8. The power semiconductor device (1) according to claim 6 or 7, wherein: With respect to the vertical direction (Z), the doped region (105) extends further into the semiconductor body (10) than the second trench (17).

9. The power semiconductor device (1) according to one of the preceding claims, wherein: The control terminal (13) exhibits a pad configuration, wherein the total lateral cross-sectional area of ​​the control terminal (13) amounts to at least 1% of the total lateral cross-sectional area of ​​the active region (1-2).

10. The power semiconductor device (1) according to one of the preceding claims, wherein: The first trench (14, 16) includes a source trench (16) electrically connected to the first load terminal (11).

11. The power semiconductor device (1) according to claim 10, wherein at least one of the source trenches (16) extends into a region laterally overlapping with the control terminal (13).

12. The power semiconductor device (1) according to one of the preceding claims, wherein: The second trench (17) is configured to improve the electrostatic discharge (ESD) robustness of the power semiconductor device (1).

13. The power semiconductor device (1) according to one of the preceding claims, wherein: At least one of the control grooves (14) extends into a region laterally overlapping with the control terminal (13) and is connected to the control terminal (13) within the region laterally overlapping with the control terminal (13).

14. The power semiconductor device (1) according to one of the preceding claims, wherein: The power semiconductor device (1) is an IGBT or a MOSFET.

15. The power semiconductor device (1) according to one of the preceding claims, wherein: The semiconductor body (10) is based on a wide bandgap material, such as SiC or GaN.

16. A method of manufacturing a power semiconductor device (1), comprising forming the following components: - a semiconductor body (10) having a drift region (100) of a first conductivity type; - a first load terminal (11) located on a first side (110) of the semiconductor body (10); a second load terminal located at a second side (120) of the semiconductor body (10) opposite to the first side (110), wherein the power semiconductor device (1) is configured to conduct a load current between the first load terminal (11) and the second load terminal (12); - a control terminal (13) located on the first side (110) and configured to receive a control signal for controlling a load current; - within an active area (1-2) of the power semiconductor device (1) at least partially surrounded by an edge termination area (1-3), first trenches (14, 16) laterally bound a mesa (18) for conducting a load current, wherein the first trenches (14, 16) include a control trench (14) electrically connected to a control terminal (13) and arranged according to a first average pitch (p1); - second grooves (17) in a region laterally overlapping the control terminal (13), wherein the second grooves (17) are arranged according to a second average pitch different from the first average pitch (p1) and are electrically connected to the control terminal (13).

17. The method according to claim 16, wherein: The first trench (14, 16) and the second trench (17) are formed based on the same processing steps.

18. The method of claim 16 or 17, wherein forming the first trench (14, 16) and the second trench (17) comprises using a mask, wherein the structure of the mask produces a difference between the second average pitch (p2) and the first average pitch (p1).

19. A power semiconductor device (1), comprising - a semiconductor body (10) having a drift region (100) of a first conductivity type; - a first load terminal (11) located on a first side (110) of the semiconductor body (10); a second load terminal located at a second side (120) of the semiconductor body (10) opposite to the first side (110), wherein the power semiconductor device (1) is configured to conduct a load current between the first load terminal (11) and the second load terminal (12); - a control terminal (13) located on the first side (110) and configured to receive a control signal for controlling a load current; - In an active area (1-2) of a power semiconductor device (1) at least partially surrounded by an edge termination area (1-3), a first trench (14, 16) laterally delimits a mesa (18) for conducting a load current, wherein the first trench (14, 16) o comprises a control groove (14) electrically connected to a control terminal (13), and o arranged according to a first average spacing (p1); - a second trench (17) in a region laterally overlapping the edge termination region (1-3), wherein the second trench (17) is o arranged according to a second average pitch (p2) different from the first average pitch (p1); and oElectrically connected to the control terminal (13).

20. The power semiconductor device (1) according to claim 19, wherein at least some or all of the second trenches (17) are oriented parallel to the control trenches (14).

21. The power semiconductor device (1) according to claim 19 or 20, wherein at least some or all of the second trenches (17) are oriented perpendicularly to the control trenches (14).

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