Transverse IGBT (Insulated Gate Bipolar Translator) and preparation method thereof

Abstract

The invention relates to the technical field of semiconductors, in particular to a transverse IGBT (Insulated Gate Bipolar Translator) and a preparation method thereof. According to the transverse IGBT and the preparation method, the first drain electrode is introduced to serve as the cathode of the fly-wheel diode, the drain electrode metal electrodes of the N + region and the P + region are separated, so that an IGBT forward conductive channel and a fly-wheel conductive channel of the fly-wheel diode are separated, the IGBT forward conductive channel can only enter an epitaxial layer through the P + region, the number of hole carriers injected into the P + region is not affected, and therefore the reliability of the IGBT is improved. A freewheeling conductive channel of the freewheeling diode enters the N + through the epitaxial layer and does not enter the P + region to cause other electrical influences, compared with the published related patent, the problem that hole carriers injected into the P + region are greatly reduced relative to a normal IGBT device is solved, the process steps are simple, and the cost is low. Only one process step needs to be added, wherein the first drain electrode is introduced to serve as the cathode of the fly-wheel diode, and the process is completely compatible with the existing commercial IGBT preparation process.

Description

Technical Field

[0001] The present invention relates to the field of semiconductor technology, and in particular to a lateral IGBT and a preparation method thereof. Background Art

[0002] In the field of power electronic device technology, IGBT, as a commonly used power semiconductor, occupies a dominant position in the field of high-power power semiconductors. Due to its special structure, the traditional lateral IGBT does not have a body diode freewheeling channel, and can only connect a diode in parallel as a freewheeling diode, which increases the parasitic parameters between the IGBT and the diode, and also increases the power loss of the device.

[0003] At present, one way to solve this problem is to integrate a diode freewheeling channel inside the IGBT. The patent with publication number CN115101578A discloses an IGBT device with a reverse recovery diode and its preparation method. Through three ion implantations, three regions of N+, N++, and P+ are prepared from the edge to the center at the bottom of the epitaxial wafer, and then a drain metal is prepared at the bottom of the epitaxial wafer. This method integrates a reverse recovery diode in the IGBT, but the three regions of N+, N++, and P+ share a drain metal. When the device is forward-powered, the current flows preferentially from N+ and N++. The hole carriers injected into the P+ region will be greatly reduced compared to normal IGBT devices, which has a huge impact on the forward current capacity of the IGBT. The patent with publication number CN102931216B discloses an IGBT device with an integrated Schottky diode. Insulated gate bipolar transistor structure, this scheme integrates Schottky metal contacts at the cell spacing at the top of the epitaxial wafer, and prepares N+ and P+ regions at the bottom of the epitaxial wafer, but the N+ and P+ regions share a drain metal, and there is still a problem that the hole carriers injected into the above-mentioned P+ region will be greatly reduced relative to normal IGBT devices. The patent with publication number CN114373749A discloses a lateral IGBT structure with a freewheeling diode, which has an isolation layer prepared in the withstand voltage region, and the N+ and P+ regions share a collector. The isolation layer isolates the N+ region from the withstand voltage region. When the IGBT is working in the forward direction, the collector current can only flow from the P+ region into the withstand voltage region and the emitter. This structure will not cause the hole carriers injected into the above-mentioned P+ region to be greatly reduced relative to normal IGBT devices, but there is a problem of high technical difficulty in preparing the isolation layer in the withstand voltage region. Summary of the invention

[0004] In view of the problem that a diode needs to be connected in parallel as a freewheeling diode in practical applications of a lateral IGBT, the present invention provides a lateral IGBT and a method for preparing the same, introduces a first drain electrode as the cathode of the freewheeling diode, and utilizes the lateral IGBT body diode structure to achieve the purpose of freewheeling. Compared with the related patents that have been published, the problem that the hole carriers injected into the P+ region will be greatly reduced relative to a normal IGBT device will not be caused, and the process steps are simple, and only one process step needs to be added: introducing the first drain electrode as the cathode of the freewheeling diode, which is fully compatible with the current commercial IGBT preparation process.

[0005] The technical solution of the present invention is: A method for preparing a lateral IGBT comprises the following steps: Step S100, sequentially preparing a first heavily doped body region, a first heavily doped emitter region, and a second heavily doped source region in an epitaxial wafer provided with an insulating layer; Step S200, preparing a gate trench in the epitaxial wafer, and sequentially preparing a gate dielectric and polysilicon in the trench; Step S300, depositing a first isolation layer on the epitaxial wafer, opening a window to prepare a source trench, wherein the bottom of the source trench extends to the inside of the first heavily doped body region, and preparing a source metal in the source trench; Step S400, opening a window at the gate trench to prepare a gate metal; Step S500, opening a window at a first drain window opening position to prepare a first drain; Step S600, a window is opened at the second drain window opening position to prepare the second drain, and the entire device is prepared.

[0006] Specifically, step S100 includes: Step S110, using a photolithography process and a mask to protect the outer area of ​​the first heavily doped body region; forming the first heavily doped body region by a diffusion process or an ion implantation process; Step S120, using a photolithography process and a mask to protect the outer area of ​​the first heavily doped emitter region; forming the first heavily doped emitter region by a diffusion process or an ion implantation process; Step S130: adopting a photolithography process and using a mask to protect the outer area of ​​the second heavily doped source region; and forming the second heavily doped source region by a diffusion process or an ion implantation process.

[0007] Specifically, step S200 includes: Step S210, using a photolithography process and a mask to protect the outer area of ​​the gate trench; and forming the gate trench by an etching process; Step S220, using a mask to protect the outer area of ​​the gate trench through a photolithography process, and using a thermal oxidation technology to prepare a gate dielectric in the gate trench; Specifically, step S300 includes: Step S310, preparing a first isolation layer by chemical vapor deposition, protecting the outer region of the source trench by a photolithography process using a mask, and opening a window at the source trench by an etching process, wherein the bottom of the source trench extends to the inside of the first heavily doped body region; Step S320, preparing source metal in the source trench by a stripping process or an etching process, and the source metal forms an ohmic contact with the first heavily doped body region and the second heavily doped source region.

[0008] Specifically, step S400 includes: Step S410, using a mask to protect the outer area of ​​the gate trench through a photolithography process, and opening a window in the gate trench through an etching process; Step S420, preparing gate metal at the gate trench opening by a stripping process or an etching process, and the gate metal forms an ohmic contact with the polysilicon.

[0009] Specifically, step S500 includes: Step S510, using a mask to protect the outer area of ​​the first drain window through a photolithography process, and opening a window at the first drain window through an etching process; Step S520, preparing a first drain at the first drain window by a stripping process or an etching process.

[0010] Specifically, step S600 includes: Step S610, using a mask to protect the outer area of ​​the second drain window through a photolithography process, and opening a window at the second drain window through an etching process; Step S620, preparing a second drain at the second drain window by a stripping process or an etching process.

[0011] A lateral IGBT comprises an epitaxial wafer and a first isolation layer arranged in sequence from bottom to top; The epitaxial wafer is provided with: An insulating layer, disposed in the epitaxial wafer; A first heavily doped body region extends downward from the top surface of the epitaxial wafer and is spaced apart from the top surface of the insulating layer; A pair of first heavily doped emitter regions are provided, each extending downward from an end of the top surface of the epitaxial wafer; a second heavily doped source region extending downward from the top surface of the epitaxial wafer, with a bottom surface connected to the first heavily doped body region and a side portion connected to the first heavily doped emitter region; A pair of gate dielectrics are provided, symmetrically arranged at the end of the first heavily doped body region; the gate dielectrics are respectively in a U-shaped structure, extending downward from the top surface of the second heavily doped source region and passing through the first heavily doped body region; Polysilicon filled in the gate dielectric; A source metal extending downward from the top surface of the first isolation layer into the first heavily doped body region; A pair of gate metals are provided, each extending downward from the top surface of the first isolation layer into the polysilicon; A pair of first drain electrodes are provided, located between the gate trench and the first heavily doped emitter region, and respectively extend downward from the top surface of the first isolation layer to below the second heavily doped source region; A pair of second drain electrodes are provided, each extending downward from the top surface of the first isolation layer to the first heavily doped emitter region, and the bottom surface and the side surface of the second drain electrode are spaced apart from the first heavily doped emitter region.

[0012] Specifically, the bottom surface of the gate dielectric is located below the first heavily doped body region.

[0013] Specifically, the bottom surface of the first isolation layer is connected to the first heavily doped emitter region, the second heavily doped source region, the gate dielectric and the polysilicon respectively.

[0014] The present invention provides a lateral IGBT and a preparation method thereof, wherein a first drain electrode is introduced as the cathode of a freewheeling diode, and the drain metal electrodes of N+ and P+ regions are separated to separate the forward conductive channel of the IGBT and the freewheeling conductive channel of the freewheeling diode. The forward conductive channel of the IGBT can only enter the epitaxial layer through the P+ region, which does not affect the number of hole carriers injected into the P+ region. The freewheeling conductive channel of the freewheeling diode enters the N+ region through the epitaxial layer and does not enter the P+ region to cause other electrical effects. Compared with the related patents that have been published, the problem that the hole carriers injected into the P+ region will be greatly reduced relative to a normal IGBT device will not be caused. The process steps are simple, and only one process step needs to be added: introducing the first drain electrode as the cathode of the freewheeling diode. The process is fully compatible with the current commercial IGBT preparation process. BRIEF DESCRIPTION OF THE DRAWINGS

[0015] Figure 1 It is a process flow chart of the present invention; Figure 2 is a schematic diagram of the cross-sectional structure of an epitaxial wafer; Figure 3 is a schematic diagram of the cross-sectional structure of preparing the first heavily doped body region; Figure 4 It is a schematic diagram of the cross-sectional structure of preparing the first heavily doped emitter region; Figure 5 is a schematic diagram of the cross-sectional structure of preparing the second heavily doped source region; Figure 6 is a schematic diagram of the cross-sectional structure of the gate trench; Figure 7 is a schematic diagram of a cross-sectional structure of a gate dielectric prepared; Figure 8It is a schematic diagram of the cross-sectional structure of preparing polycrystalline silicon; Fig. 9 is a schematic diagram of the cross-sectional structure of preparing the first isolation layer; Fig.10 2 is a schematic diagram of the cross-sectional structure of the source trench; Fig.11 It is a schematic diagram of the cross-sectional structure of the source metal; Fig.12 Schematic diagram of the gate window cross-section structure; Fig.13 It is a schematic diagram of the cross-sectional structure of the gate metal preparation; Fig.14 is a schematic diagram of a cross-sectional structure of a first drain window; Fig.15 is a schematic diagram of the cross-sectional structure of preparing the first drain electrode; Fig.16 is a schematic diagram of a cross-sectional structure of a second drain window; Fig.17 is a schematic diagram of the cross-sectional structure of preparing the second drain; In the figure, 1 is the epitaxial wafer, 2 is the insulating layer, 3 is the first heavily doped body region, 4 is the first heavily doped emitter region, 5 is the second heavily doped source region, 6 is the gate trench, 7 is the gate dielectric, 8 is polysilicon, 9 is the first isolation layer, 10 is the source trench, 11 is the source metal, 12 is the gate window, 13 is the gate metal, 14 is the first drain window, 15 is the first drain, 16 is the second drain window, and 17 is the second drain. DETAILED DESCRIPTION

[0016] Embodiments of the present invention are described in detail below, examples of which are shown in the accompanying drawings, wherein the same or similar reference numerals throughout represent the same or similar elements or elements having the same or similar functions. The embodiments described below with reference to the accompanying drawings are exemplary and are only used to explain the present invention, and cannot be understood as limiting the present invention.

[0017] In the description of the present invention, it should be noted that, unless otherwise clearly specified and limited, the terms "installed", "connected", and "connected" should be understood in a broad sense, for example, it can be a fixed connection, a detachable connection, or an integral connection; it can be a mechanical connection or an electrical connection; it can be a direct connection, or it can be indirectly connected through an intermediate medium, or it can be the internal communication of two components. For ordinary technicians in this field, the specific meanings of the above terms in the present invention can be understood according to specific circumstances.

[0018] Reference below Figure 1-17 describe the invention; Step S100, sequentially preparing a first heavily doped body region 3, a first heavily doped emitter region 4 and a second heavily doped source region 5 in the epitaxial wafer 1 provided with the insulating layer 2, referring to Figure 2 , 3 , 4, 5 as shown; Step S110, using a photolithography process and a mask to protect the outer area of ​​the first heavily doped body region 3; forming the first heavily doped body region 3 by a diffusion process or an ion implantation process; Step S120, using a photolithography process and a mask to protect the outer area of ​​the first heavily doped emitter region 4; forming the first heavily doped emitter region 4 by a diffusion process or an ion implantation process; Step S130, using a photolithography process and a mask to protect the outer area of ​​the second heavily doped source region 5; forming the second heavily doped source region 5 by a diffusion process or an ion implantation process; Correspondingly, the epitaxial wafer 1 of this embodiment is a Si-based SOI epitaxial wafer, the first doped region is a P region, the second doped region is an N region, the thickness of the epitaxial wafer 1 is 100-2000um, the thickness of the first heavily doped body region 3 is 1-5um, the thickness of the first heavily doped emitter region 4 is 1-100um, the thickness of the second heavily doped source region 5 is set to 0.5-3um, and the doping concentration range of N-type doping is 1e 14 .cm -3 -1e 20 .cm -3 , the doping concentration range of P-type doping is 1e 15 .cm -3 -1e 20 .cm -3 , the relevant parameter settings are related to the electrical design of the device; In this embodiment, the thickness of the epitaxial wafer 1 is 300 μm, the thickness of the first heavily doped body region 3 is 2 μm, and the doping concentration is 3e 18 .cm -3 The thickness of the first heavily doped emitter region 4 is 6 um and the doping concentration is 5e 19 .cm -3 The second heavily doped source region 5 has a thickness of 1 um and a doping concentration of 1e 19. cm -3 , use ion implantation process to prepare the first heavily doped body region 3, the first heavily doped emitter region 4, and the second heavily doped source region 5.

[0019] Step S200, preparing a gate trench 6 in the epitaxial wafer 1, and sequentially preparing a gate dielectric 7 and polysilicon 8 in the trench 6, referring to Figure 6 , 7 , as shown in 8; Step S210, using a photolithography process and a mask to protect the outer area of ​​the gate trench 6; and forming the gate trench 6 by an etching process; Step S220, using a mask to protect the outer area of ​​the gate trench 6 through a photolithography process, and using a thermal oxidation technique to prepare a gate dielectric 7 in the gate trench 6; Step S230, preparing polysilicon 8 in the gate trench 6 by chemical vapor deposition; Correspondingly, the gate trench 6 extends downward from the top surface of the epitaxial wafer 1, and its bottom surface is lower than the bottom surface of the first heavily doped body region 3 and higher than the top surface of the insulating layer 2. The width range is set to 1-10um, and the interval between adjacent gate trenches is set to 1-10um. The gate dielectric 7 is located in the trench 6, and the polysilicon 8 is located in the trench 6, filling the trench 6 and contacting the gate dielectric 7. The upper surface of the polysilicon 8 is level with the upper surface of the gate trench 6. The gate dielectric 7 is made of SiO2, and the thickness is set to 10-500nm. The relevant parameter settings are related to the device electrical design. In this embodiment, the gate trench 6 has a depth of 4um and a width of 2um, and the interval between adjacent gate trenches is 2um. The trench 6 is prepared using an ICP dry etching process, 80nm SiO2 is prepared as a gate dielectric 7 using thermal oxidation technology, and polysilicon 8 is prepared using chemical vapor deposition.

[0020] Step S300, depositing a first isolation layer 9 on the epitaxial wafer 1, opening a window to prepare a source trench 10, the bottom of the source trench 10 extends to the inside of the first heavily doped body region 3, and preparing a source metal 11 in the source trench 10, referring to Fig. 9 , 10 , as shown in 11; Step S310, preparing a first isolation layer 9 by chemical vapor deposition, protecting the outer region of the source trench 10 by a photolithography process using a mask, and opening a window at the source trench 10 by an etching process, wherein the bottom of the source trench 10 extends to the inside of the first heavily doped body region 3; Step S320, preparing a source metal 11 in the source trench 10 by a stripping process or an etching process, and the source metal 11 forms an ohmic contact with the first heavily doped body region 3 and the second heavily doped source region 5; Accordingly, the first isolation layer 9 plays a protective role, and is made of SiO2 or Si3N4, with a thickness set to 10-5000nm. The source trench 10 is prepared by ICP dry etching, and the source trench 10 extends downward from the top surface of the first isolation layer 9 to the inside of the first heavily doped body region 3, and its bottom surface is higher than the bottom surface of the first heavily doped body region 3, and its width is less than the spacing distance between adjacent gate trenches 6, and the width range is set to 1-10um. The source metal 11 is arranged inside the source trench 10 to form an ohmic contact with the first heavily doped body region 3 and the second heavily doped source region 5. The relevant parameter settings are related to the device electrical design; In this embodiment, Si3N4 is used as the first isolation layer 9 with a thickness of 200 nm. ICP dry etching is used to open a window to prepare a source trench 10. The source trench 10 has a depth of 2 um and a width of 1.5 um. A stripping process is used to prepare a 2 um thick Ti / Al two-layer metal inside the source trench 10 as the source metal 11.

[0021] Step S400, opening a window at the gate trench 6 and preparing the gate metal 13, referring to Fig.12 , 13 As shown; Step S410, using a mask to protect the outer area of ​​the gate trench 6 through a photolithography process, and opening a window at the gate trench 6 through an etching process; Step S420, preparing a gate metal 13 at the opening of the gate trench 6 by a stripping process or an etching process, and the gate metal 13 forms an ohmic contact with the polysilicon 8; Correspondingly, the window depth at the gate trench 6 is greater than the thickness of the first isolation layer 9, and the window width is less than the width of the gate trench 6. The gate metal 13 extends downward from the top surface of the first isolation layer 9 into the polysilicon 8 to form an ohmic contact with the polysilicon 8. In this embodiment, a window is opened at the gate groove 6 by an etching process, with a window depth of 2um and a window width of 1.5um. A stripping process is used to prepare a 2um thick Ti / Al two-layer metal as the gate metal 13 to form an ohmic contact with the polysilicon 8.

[0022] Step S500, opening a window at the position of the first drain window 14, preparing the first drain 15, referring to Fig.14 , 15 As shown; Step S510, using a mask to protect the outer area of ​​the first drain window 14 through a photolithography process, and opening a window at the first drain window 14 through an etching process; Step S520, preparing the first drain electrode 15 at the first drain electrode window 14 by a stripping process or an etching process; Correspondingly, the window depth at the first drain window 14 is greater than the sum of the thicknesses of the first isolation layer 9 and the second heavily doped source region 5, and the window width is set to 1-5um. The first drain 15 passes through the second heavily doped source region 5 from the top surface of the first isolation layer 9 downward to form an ohmic contact with the second heavily doped source region 5; In this embodiment, an etching process is used to open a window at the first drain window 14, with a window depth of 1.5um and a window width of 1.5um. A stripping process is used to prepare a 1.5um thick Ti / Al two-layer metal as the first drain 15 to form an ohmic contact with the second heavily doped source region 5.

[0023] Step S600, a window is opened at the position of the second drain window 16, and a second drain 17 is prepared. The entire device is prepared. Fig.16 , 17 As shown; Step S610, using a mask to protect the outer area of ​​the second drain window 16 through a photolithography process, and opening a window at the second drain window 16 through an etching process; Step S620, preparing the second drain electrode 17 at the second drain electrode opening 16 by a stripping process or an etching process; Correspondingly, the window depth at the second drain window 16 is greater than the first isolation layer 9, less than the sum of the first isolation layer 9 and the first heavily doped emitter region 4, the window width is less than the width of the first heavily doped emitter region 4, and the second drain 17 extends downward from the top surface of the first isolation layer 9 to the inside of the first heavily doped emitter region 4, forming an ohmic contact with the first heavily doped emitter region 4; In this embodiment, an etching process is used to open a window at the second drain opening 16, with a window depth of 5.5um and a window width of 1.5um. A stripping process is used to prepare a 5.5um thick Ti / Al two-layer metal as the second drain 17 to form an ohmic contact with the first heavily doped emitter region 4.

[0024] A lateral IGBT, comprising an epitaxial wafer 1 and a first isolation layer 9 arranged in sequence from bottom to top; The epitaxial wafer 1 is provided with: The insulating layer 2 is arranged in the epitaxial wafer 1 and is spaced apart from the top surface and the bottom surface of the epitaxial wafer 1; A first heavily doped body region 3 extends downward from the top surface of the epitaxial wafer 1 and is spaced apart from the top surface of the insulating layer 2; A pair of first heavily doped emitter regions 4 are provided, each extending downward from the end of the top surface of the epitaxial wafer 1, and the bottom surface of each of the first heavily doped body region 3 and the top surface of the insulating layer 2; A second heavily doped source region 5 extends downward from the top surface of the epitaxial wafer 1, with a bottom surface connected to the first heavily doped body region 3 and a side portion connected to the first heavily doped emitter region 4; A pair of gate dielectrics 7 are symmetrically arranged at the ends of the first heavily doped body region 3; the gate dielectrics 7 are respectively in a U-shaped structure, extending downward from the top surface of the second heavily doped source region 5 and passing through the first heavily doped body region 3; the bottom surface of the gate dielectric 7 is located below the first heavily doped body region 3; Polysilicon 8, filled in the gate dielectric 7, with its top surface flush with the second heavily doped source region 5; The bottom surface of the first isolation layer 9 is respectively connected to the first heavily doped emitter region 4, the second heavily doped source region 5, the gate dielectric 7 and the polysilicon 8; The source metal 11 extends downward from the top surface of the first isolation layer 9 to the first heavily doped body region 3 to form an ohmic contact with the first heavily doped body region 3 and the second heavily doped source region 5; A pair of gate metals 13 are provided, each extending downward from the top surface of the first isolation layer 9 to the polysilicon 8 to form an ohmic contact with the polysilicon 8; A pair of first drain electrodes 15 are provided, located between the gate trench 6 and the first heavily doped emitter region 4, and respectively extend downward from the top surface of the first isolation layer 9 to below the second heavily doped source region 5, forming an ohmic contact with the second heavily doped source region 5; A pair of second drain electrodes 17 are provided, each extending downward from the top surface of the first isolation layer 9 to the first heavily doped emitter region 4 , and the bottom and side surfaces thereof are spaced apart from the first heavily doped emitter region 4 , so that the second drain electrode 17 forms an ohmic contact with the first heavily doped emitter region 4 .

[0025] The material of the SOI epitaxial wafer with the insulating layer 2 introduced inside the epitaxial wafer 1 in this case can be Si, SiC, GaN and other commonly used epitaxial materials for semiconductor devices; the first doping region and the second doping region have opposite doping types, that is, they can be P region and N region or N region and P region.

[0026] In view of the problem that a diode needs to be connected in parallel as a freewheeling diode in practical applications of a lateral IGBT, the present invention provides a lateral IGBT and a preparation method thereof, introduces a first drain electrode as the cathode of the freewheeling diode, separates the drain metal electrodes in the N+ and P+ regions, and separates the IGBT forward conduction channel and the freewheeling conduction channel of the freewheeling diode. The IGBT forward conduction channel can only enter the epitaxial layer through the P+ region, which does not affect the number of hole carriers injected into the P+ region. The freewheeling conduction channel of the freewheeling diode enters the N+ region through the epitaxial layer and will not enter the P+ region to cause other electrical effects. Compared with the relevant patents that have been published, the problem that the hole carriers injected into the P+ region will be greatly reduced relative to a normal IGBT device will not be caused. The process steps are simple, and only one process step needs to be added: introducing the first drain electrode as the cathode of the freewheeling diode. The process is fully compatible with the current commercial IGBT preparation process.

[0027] Regarding the contents disclosed in this case, there are a few points that need to be explained: (1) The drawings of the embodiments disclosed in this case only involve the structures involved in the embodiments disclosed in this case. Other structures can refer to the general design; (2) In the absence of conflict, the embodiments and features of the embodiments disclosed in this case may be combined with each other to obtain new embodiments; The above are only specific implementation methods disclosed in this case, but the protection scope of the present disclosure is not limited thereto. The protection scope disclosed in this case should be based on the protection scope of the claims.

Claims

1. A method for preparing a lateral IGBT, characterized in that: The following steps are involved: Step S100, sequentially preparing a first heavily doped body region (3), a first heavily doped emitter region (4) and a second heavily doped source region (5) in an epitaxial wafer (1) provided with an insulating layer (2); Step S200, preparing a gate trench (6) in the epitaxial wafer (1), and sequentially preparing a gate dielectric (7) and polysilicon (8) in the trench (6); Step S300, depositing a first isolation layer (9) on the epitaxial wafer (1), opening a window to prepare a source trench (10), wherein the bottom of the source trench (10) extends to the inside of the first heavily doped body region (3), and preparing a source metal (11) in the source trench (10); Step S400, opening a window at the gate trench (6) to prepare a gate metal (13); Step S500, opening a window at the position of the first drain electrode opening window (14) to prepare the first drain electrode (15); Step S600, a window is opened at the position of the second drain window (16), and a second drain (17) is prepared, and the entire device is prepared.

2. The method for preparing a lateral IGBT according to claim 1, characterized in that: Step S100 includes: Step S110, using a photolithography process and a mask to protect the outer region of the first heavily doped body region (3); forming the first heavily doped body region (3) by a diffusion process or an ion implantation process; Step S120, using a photolithography process and a mask to protect the outer region of the first heavily doped emitter region (4); forming the first heavily doped emitter region (4) through a diffusion process or an ion implantation process; Step S130, adopting a photolithography process and using a mask to protect the outer area of ​​the second heavily doped source region (5); and forming the second heavily doped source region (5) through a diffusion process or an ion implantation process.

3. The method for preparing a lateral IGBT according to claim 1, characterized in that: Step S200 includes: Step S210, using a photolithography process and a mask to protect the outer region of the gate trench (6); and forming the gate trench (6) through an etching process; Step S220, using a mask to protect the outer region of the gate trench (6) through a photolithography process, and using a thermal oxidation technique to prepare a gate dielectric (7) in the gate trench (6); Step S230, preparing polysilicon (8) in the gate trench (6) by chemical vapor deposition.

4. The method for preparing a lateral IGBT according to claim 1, characterized in that: Step S300 includes: Step S310, preparing a first isolation layer (9) by chemical vapor deposition, protecting the outer region of the source trench (10) by a photolithography process using a mask, and opening a window at the source trench (10) by an etching process, wherein the bottom of the source trench (10) extends to the inside of the first heavily doped body region (3); Step S320, preparing a source metal (11) in the source trench (10) by a stripping process or an etching process, wherein the source metal (11) forms an ohmic contact with the first heavily doped body region (3) and the second heavily doped source region (5).

5. The method for preparing a lateral IGBT according to claim 1, characterized in that: Step S400 includes: Step S410, using a mask to protect the outer area of ​​the gate trench (6) through a photolithography process, and opening a window at the gate trench (6) through an etching process; Step S420: preparing a gate metal (13) at the opening of the gate trench (6) by a stripping process or an etching process, so that the gate metal (13) forms an ohmic contact with the polysilicon (8).

6. The method for preparing a lateral IGBT according to claim 1, characterized in that: Step S500 includes: Step S510, using a mask to protect the outer area of ​​the first drain window (14) through a photolithography process, and opening a window at the first drain window (14) through an etching process; Step S520, preparing a first drain electrode (15) at the first drain electrode window (14) by a stripping process or an etching process.

7. The method for preparing a lateral IGBT according to claim 1, characterized in that: Step S600 includes: Step S610, using a mask to protect the outer area of ​​the second drain opening (16) through a photolithography process, and opening a window at the second drain opening (16) through an etching process; Step S620, preparing a second drain electrode (17) at the second drain electrode window (16) by a stripping process or an etching process.

8. A lateral IGBT, prepared by the method for preparing a lateral IGBT according to claim 1, characterized in that: It comprises an epitaxial wafer (1) and a first isolation layer (9) which are arranged in sequence from bottom to top; The epitaxial wafer (1) is provided with: An insulating layer (2) is arranged inside the epitaxial wafer (1); A first heavily doped body region (3) extending downward from the top surface of the epitaxial wafer (1) and having a spacing therebetween from the top surface of the insulating layer (2); A pair of first heavily doped emitter regions (4) are provided, each extending downward from an end of the top surface of the epitaxial wafer (1); a second heavily doped source region (5), extending downward from the top surface of the epitaxial wafer (1), with a bottom surface connected to the first heavily doped body region (3) and a side portion connected to the first heavily doped emitter region (4); A pair of gate dielectrics (7) are symmetrically arranged at the ends of the first heavily doped body region (3); the gate dielectrics (7) are respectively in a U-shaped structure, extending downward from the top surface of the second heavily doped source region (5) and passing through the first heavily doped body region (3); Polycrystalline silicon (8), filled in the gate dielectric (7); A source metal (11) extending downward from the top surface of the first isolation layer (9) into the first heavily doped body region (3); A pair of gate metals (13) are provided, each extending downward from the top surface of the first isolation layer (9) to the inside of the polysilicon (8); A pair of first drain electrodes (15) are provided, each extending downward from the top surface of the first isolation layer (9) to below the second heavily doped source region (5); A pair of second drain electrodes (17) are provided, each extending downward from the top surface of the first isolation layer (9) into the first heavily doped emitter region (4), and their bottom surfaces and side surfaces are spaced apart from the first heavily doped emitter region (4).

9. A lateral IGBT according to claim 8, characterized in that: The bottom surface of the gate dielectric (7) is located below the first heavily doped body region (3).

10. The lateral IGBT according to claim 8, characterized in that: The bottom surface of the first isolation layer (9) is respectively connected to the first heavily doped emitter region (4), the second heavily doped source region (5), the gate dielectric (7) and the polysilicon (8).

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