Passivation contact type back contact solar cell and preparation method thereof

Abstract

The invention discloses a passivation contact type back contact solar cell and a preparation method thereof, the cell comprises a crystalline silicon substrate, the front surface of the crystalline silicon substrate is a passivation anti-reflection layer, and the back surface of the crystalline silicon substrate is sequentially provided with a first tunneling layer, a first polycrystalline silicon layer, a second tunneling layer, a second polycrystalline silicon layer, a passivation layer and a metal electrode from inside to outside, the first polycrystalline silicon layer comprises a first n + polycrystalline silicon region, a first p + polycrystalline silicon region and a first isolation region, the second polycrystalline silicon layer comprises a second n + polycrystalline silicon region, a second p + polycrystalline silicon region and a second isolation region, and the doping concentration of boron in the first p + polycrystalline silicon region is lower than that of boron in the second p + polycrystalline silicon region; the doping concentration of phosphorus in the first n + polycrystalline silicon region is lower than the doping concentration of phosphorus in the second n + polycrystalline silicon region. A double-layer tunneling polycrystalline silicon structure is adopted on the back face of the cell, and low metal contact compounding, low non-metal contact area compounding and low contact resistivity can be met at the same time.

Description

Technical Field

[0001] The present invention relates to the technical field of solar cells, and in particular to a passivated contact type back contact solar cell and a preparation method thereof. Background Art

[0002] The back contact cell is a cell in which both the p+ doped region and the n+ doped region are placed on the back side (non-light-receiving side) of the cell. The light-receiving side of the cell is not blocked by any metal electrode, which effectively increases the short-circuit current of the cell and improves the energy conversion efficiency of the cell. The passivation contact technology is a technology that has emerged in recent years and has excellent contact without damaging the passivation film. It is to set an ultra-thin oxide layer on the surface of the silicon substrate as a tunneling layer, set a doped polysilicon layer on it, and then set a passivation film and metal electrodes on the doped polysilicon layer. The advantage of this structure is that carriers can be freely transmitted through the oxide layer, and at the same time, the oxide layer can provide good surface passivation for the surface of the silicon substrate.

[0003] The passivated contact back contact cell (IBC cell) refers to a passivated contact structure formed by an ultra-thin oxide layer and a doped polysilicon layer on the back. One of the difficulties of this structure is to prepare the N-type diffusion area and the P-type diffusion area on the back of the cell in a comb-like cross distribution. It usually requires two high-temperature diffusions and the intermediate high-temperature diffusion mask preparation, pattern etching, and cleaning processes. The preparation process is relatively complex and the cell yield is low. In addition, the structure of the existing IBC cells is a passivated contact structure formed by a single-layer tunneling oxide layer and a single-layer doped polysilicon layer. In this structure, the metal semiconductor composite and the non-metallic contact area have large composite losses, and the contact resistivity is large, resulting in low conversion efficiency of the cell.

[0004] Therefore, how to obtain IBC batteries with low metal semiconductor recombination, low non-metal contact area recombination and low contact resistivity through optimization of structure and preparation process has become a research focus. Summary of the invention

[0005] In view of the above problems, the purpose of the present invention is to provide a passivated contact back contact solar cell and a preparation method thereof. A double-layer tunneling polysilicon structure including a first tunneling oxide layer, a first polysilicon layer, a second tunneling oxide layer and a second polysilicon layer is sequentially deposited on the back of the solar cell, and a certain thickness of phosphorus ions and boron ions are respectively implanted on the surface of the second polysilicon layer by ion implantation technology. Under the action of high temperature annealing, boron and phosphorus are diffused inward to the first polysilicon layer by controlling the annealing temperature and time, thereby completing the doping of the second polysilicon layer and the first polysilicon layer. Due to the blocking effect of the second tunneling oxide layer, a certain concentration difference of phosphorus and boron will be formed between the doped second polysilicon layer and the doped first polysilicon layer in the final formed battery structure, which reduces the contact resistivity and also reduces the recombination of the metal contact area and the non-metal contact area, so that the battery meets the requirements of low metal contact recombination, low non-metal contact area recombination and low contact resistivity, thereby improving the open circuit voltage and conversion efficiency of the battery.

[0006] In view of the above object, the present invention first provides a method for preparing a passivated contact back contact solar cell, comprising the following steps:

[0007] (1) performing texturing on the crystalline silicon substrate to remove the damaged layer and form a pyramid light trapping structure;

[0008] (2) depositing a mask layer on the front surface of the crystalline silicon substrate treated in step (1);

[0009] (3) placing the crystalline silicon substrate treated in step (2) in a polishing solution so that the back surface is etched into a polished surface;

[0010] (4) depositing a first tunneling oxide layer, a first intrinsic amorphous silicon layer, a second tunneling oxide layer, and a second intrinsic amorphous silicon layer in sequence on the back surface of the crystalline silicon substrate after being etched in step (3);

[0011] (5) implanting phosphorus and boron on the back surface of the crystalline silicon substrate treated in step (4) by ion implantation to form an n+ implantation region and a p+ implantation region, respectively, with a gap left between the n+ implantation region and the p+ implantation region;

[0012] (6) placing the crystalline silicon substrate after the treatment in step (5) into an annealing furnace for high-temperature annealing treatment. Under the action of high-temperature annealing, the boron element in the p+ implantation region and the phosphorus element in the n+ implantation region respectively dope the first intrinsic amorphous silicon layer and the second intrinsic amorphous silicon layer with boron and phosphorus, and finally form a first p+ polycrystalline silicon region and a second p+ polycrystalline silicon region and a first n+ polycrystalline silicon region and a second n+ polycrystalline silicon region, wherein the doping concentration of the boron element in the first p+ polycrystalline silicon region is lower than the doping concentration of the boron element in the second p+ polycrystalline silicon region, and the doping concentration of the phosphorus element in the first n+ polycrystalline silicon region is lower than the doping concentration of the phosphorus element in the second n+ polycrystalline silicon region;

[0013] (7) placing the crystalline silicon substrate treated in step (6) into a cleaning machine for cleaning and drying, so that the mask layer and the oxide layer generated during annealing are completely removed;

[0014] (8) forming a passivation anti-reflection layer and a passivation layer on the front surface and the back surface of the crystalline silicon substrate treated in step (7), respectively;

[0015] (9) Printing a metal electrode on the back surface of the crystalline silicon substrate treated in step (8) by screen printing. After printing, the crystalline silicon substrate is transferred to a belt sintering furnace for sintering to form an ohmic contact.

[0016] In one embodiment of the present invention, the crystalline silicon substrate described in step (1) includes an N-type crystalline silicon substrate and a P-type crystalline silicon substrate, the resistivity of the crystalline silicon substrate is 0.3 to 10 Ω·cm, preferably 1 to 5 Ω·cm, and the thickness of the crystalline silicon substrate is 50 to 300 μm, preferably 80 to 200 μm.

[0017] In one embodiment of the present invention, the mask layer in step (2) is SiO2, SiN x 、SiN x O y At least one of the above, the deposition method of the mask layer is plasma enhanced chemical vapor deposition (PECVD) or low pressure chemical vapor deposition (LPCVD), and the thickness of the mask is 20 to 100 nm.

[0018] In one embodiment of the present invention, the polishing solution in step (3) is at least one of heated NaOH, KOH, and TMAH solutions, the heating temperature is 75-85° C., and the etching time is 50-120 seconds. After the crystalline silicon substrate is placed in the polishing solution, the front surface will not react with the polishing solution due to the presence of the mask layer, while the back surface will be etched into a polishing surface, and the mask layer will still remain after polishing is completed.

[0019] In one embodiment of the present invention, the first tunneling oxide layer described in step (4) is SiO2, and the deposition method includes one of high-temperature thermal oxidation, nitric acid oxidation, ozone oxidation, and CVD deposition. The thickness of the first tunneling layer is 0.8 to 3 nm, preferably 1 to 1.5 nm.

[0020] In one embodiment of the present invention, the deposition method of the first intrinsic amorphous silicon layer described in step (4) includes at least one of low pressure chemical vapor deposition (LPCVD), atmospheric pressure chemical vapor deposition (APCVD) and plasma enhanced chemical vapor deposition (PECVD), and the thickness of the first intrinsic amorphous silicon layer is 10 to 30 nm.

[0021] In one embodiment of the present invention, the second tunneling oxide layer described in step (4) is SiO2, and the deposition method includes one of high-temperature thermal oxidation, nitric acid oxidation, ozone oxidation, and CVD deposition. The thickness of the second tunneling layer is 0.8 to 3 nm, preferably 0.8 to 1.0 nm.

[0022] The electron penetration on both sides of the second tunnel oxide layer is related to the thickness of the second tunnel oxide layer. The thickness of the second tunnel oxide layer is preferably 0.8-1.0 nm. If the thickness is too thin, the chemical passivation effect is poor. If the thickness is too thick, it exceeds the penetration ability of the electrons, resulting in current loss. According to experimental simulation data, the optimal thickness of the second tunnel oxide layer is 0.9 nm.

[0023] In one embodiment of the present invention, the deposition method of the second intrinsic amorphous silicon layer described in step (4) includes at least one of low pressure chemical vapor deposition (LPCVD), atmospheric pressure chemical vapor deposition (APCVD) and plasma enhanced chemical vapor deposition (PECVD), and the thickness of the second intrinsic amorphous silicon layer is 50 to 80 nm.

[0024] In one embodiment of the present invention, in step (5), two ion sources are used to implant phosphorus and boron respectively. When implanting phosphorus or boron, a mask fixture is arranged between the back surface of the silicon wafer and the ion source to selectively implant boron ions or phosphorus ions. The mask fixture is made of graphite.

[0025] In one embodiment of the present invention, in step (5), when boron is implanted, a linear opening is provided on the mask fixture, and the width of the linear opening is 1950 to 2050 um. After the implantation is completed, a patterned p+ implantation layer is formed on the second intrinsic amorphous silicon layer; when phosphorus is implanted, a linear opening is provided on the mask fixture, and the width of the linear opening is 1950 to 2050 um. After the implantation is completed, a patterned n+ implantation layer is formed on the second intrinsic amorphous silicon layer. The p+ implantation layer and the n+ implantation layer are not in direct contact, and an area that is not implanted by ions is left between them. The opening pattern on the mask fixture can also be other arbitrarily arranged periodic or quasi-periodic arrays, and the pattern can be selected in a variety of ways according to needs, which is not limited here, and is only listed as an example.

[0026] In one embodiment of the present invention, in step (5), the dosage of boron implantation is 0.5×10 15 cm -2 ~3×10 15 cm -2 , preferably 1.5×10 15 cm -2 ~2.5×10 15 cm -2 The phosphorus implantation dose is 3×10 15 cm -2 ~8×10 15 cm -2 , preferably 4×10 15 cm -2 ~6×10 15 cm -2 .

[0027] In one embodiment of the present invention, in step (5), when boron and phosphorus are injected, the power supply voltage is 105-300V, preferably 150-250V, more preferably 180-220V, and the material transfer rate is 0.8-1.2m / min.

[0028] In one embodiment of the present invention, in step (6), the peak annealing temperature is 800-1100°C, preferably 850-1000°C, the annealing time is 30-200 min, preferably 60-200 min, and the ambient gas source is preferably N2 and O2.

[0029] In the present invention, the depth of boron and phosphorus implanted into the second intrinsic polysilicon layer is achieved by regulating the power supply voltage and the material transfer rate, so that the depth of ion implantation is 25 to 45 nm, and the ion concentration distribution is Gaussian distribution outside the core implantation depth. By injecting a certain dose of boron and phosphorus into the surface of the second intrinsic polysilicon layer, an ion implantation layer of a certain depth is formed on the surface of the second intrinsic polysilicon layer. Under the action of high-temperature annealing, the implanted boron or phosphorus will diffuse inward. By controlling the annealing temperature and annealing time, the phosphorus and boron in the second polysilicon layer are activated, and at the same time, part of the boron or phosphorus is doped into the first intrinsic polysilicon layer through the second tunneling oxide layer, forming a concentration difference between the second intrinsic polysilicon layer and the first intrinsic polysilicon layer, thereby improving the recombination loss of the solar cell and improving the conversion efficiency of the solar cell.

[0030] Under the high temperature of annealing, the boron element in the p+ implanted layer will dope the first intrinsic amorphous silicon layer and the second intrinsic amorphous silicon layer below, and finally form the first p+ polycrystalline silicon layer and the second p+ polycrystalline silicon layer, wherein the doping concentration of the boron element in the first p+ polycrystalline silicon layer is lower than the doping concentration of the boron element in the second p+ polycrystalline silicon layer. Under the high temperature of annealing, the phosphorus element in the n+ implanted layer will dope the first intrinsic amorphous silicon layer and the second intrinsic amorphous silicon layer below, and finally form the first n+ polycrystalline silicon layer and the second n+ polycrystalline silicon layer, wherein the doping concentration of the phosphorus element in the first n+ polycrystalline silicon layer is lower than the doping concentration of the phosphorus element in the second n+ polycrystalline silicon layer. The area in the first intrinsic amorphous silicon layer that is not ion-implanted is converted into the first isolation layer after annealing, and the area in the second intrinsic amorphous silicon layer that is not ion-implanted is converted into the second isolation layer after annealing.

[0031] In one embodiment of the present invention, the passivation anti-reflection layer in step (8) comprises AlO deposited on the front surface of the crystalline silicon substrate in sequence. x Dielectric film, SiN x Dielectric film and / or SiN x O y Dielectric film, the AlO x The dielectric film is deposited by plasma enhanced chemical vapor deposition (PECVD) or atomic layer deposition (ALD), and the film thickness is 3 to 10 nm. x Dielectric film or SiN x O y The dielectric film is deposited by plasma enhanced chemical vapor deposition (PECVD). x The thickness of the dielectric film is 5 to 30 nm, SiN x O y The thickness of the dielectric film is 40 to 80 nm.

[0032] In one embodiment of the present invention, the passivation layer in step (8) comprises AlO deposited in sequence: x Dielectric film and SiN x The dielectric film, the SiN x The dielectric film is deposited by plasma enhanced chemical vapor deposition (PECVD). x The thickness of the dielectric film is 50 to 90 nm.

[0033] In one embodiment of the present invention, in step (8), AlO with a thickness of 3 to 10 nm is firstly formed on the front and back surfaces of the crystalline silicon substrate. x The dielectric film is then deposited on the front surface by PECVD with a thickness of 5 to 30 nm. x Dielectric film, then SiN x A layer of SiN is deposited on the dielectric film x O y Dielectric film, and finally AlO on the back x A layer of SiN is deposited on the surface of the dielectric film. x Dielectric film.

[0034] In one embodiment of the present invention, in step (10), the metal electrode is silver.

[0035] The invention also discloses a passivated contact type back contact solar cell prepared according to the method.

[0036] In one embodiment of the present invention, the solar cell comprises a crystalline silicon substrate, the front side of the crystalline silicon substrate is a passivation anti-reflection layer, and the passivation anti-reflection layer is sequentially composed of a first AlO x Dielectric film, first SiN x Dielectric film and / or SiN x O y The back of the crystalline silicon substrate is composed of a first tunneling layer, a first polysilicon layer, a second tunneling layer, a second polysilicon layer, a passivation layer and a metal electrode from the inside to the outside, and the passivation layer is composed of a second AlO x Dielectric film and second SiN x The dielectric film is a silver electrode; wherein the first polysilicon layer comprises a first n+ polysilicon region, a first p+ polysilicon region and a first isolation region, the second polysilicon layer comprises a second n+ polysilicon region, a second p+ polysilicon region and a second isolation region, and the doping concentration of the boron element in the first p+ polysilicon region is lower than the doping concentration of the boron element in the second p+ polysilicon region, and the doping concentration of the phosphorus element in the first n+ polysilicon region is lower than the doping concentration of the phosphorus element in the second n+ polysilicon region.

[0037] In one embodiment of the present invention, the first AlO xDielectric film and second AlO x The thickness of the dielectric film is 3 to 10 nm. x The thickness of the dielectric film is 5 to 30 nm. x O y The thickness of the dielectric film is 40 to 80 nm. x The thickness of the dielectric film is 50 to 90 nm.

[0038] Beneficial effects:

[0039] (1) The back side of the back-contact solar cell of the present invention adopts a double-layer tunneling polysilicon structure, which can simultaneously meet the requirements of low metal contact recombination, low non-metal contact area recombination and low contact resistivity. On the one hand, the metal electrode only partially burns through the second n+ polysilicon layer and the second p+ polysilicon layer, and does not contact the crystalline silicon substrate, thereby reducing metal semiconductor recombination; on the other hand, the second n+ polysilicon layer and the second p+ polysilicon layer in contact with the metal electrode are heavily doped, which can greatly reduce the contact resistivity and reduce resistance loss; while the first n+ polysilicon layer and the first p+ polysilicon layer close to the crystalline silicon substrate are lightly doped, which reduces the recombination of the non-metal contact area and reduces the current loss caused by free carrier absorption.

[0040] (2) The double-layer tunneling polysilicon structure of the present invention can overcome the shortcomings of the single-layer tunneling polysilicon structure used in the prior art, meet the requirements of low metal area contact recombination, non-metal contact area recombination and resistance loss, and at the same time, by controlling the concentration difference of boron and phosphorus between the doped second polysilicon layer and the first polysilicon layer, the open circuit voltage and conversion efficiency of the battery are improved. The process technologies used in the preparation method are all mature technologies and are suitable for mass production and promotion.

[0041] (3) The present invention uses ion implantation technology to dope phosphorus and boron ions. The doping concentration of phosphorus and boron ions is easy to control. By controlling the implantation thickness and amount of phosphorus and boron, the thickness of the second intrinsic amorphous silicon layer, and the diffusion temperature and time and other parameters, the concentration of boron and phosphorus ions doped in the first intrinsic polycrystalline silicon layer can be effectively controlled, thereby effectively improving the performance of solar cells and the conversion efficiency. In addition, compared with the traditional method of diffusion using a diffusion furnace, the present invention uses an ion implantation method to implant boron or phosphorus into the surface of the second intrinsic polycrystalline silicon layer. Under the drive of high temperature, phosphorus and boron will be selectively and directionally doped into the first intrinsic polycrystalline silicon layer. When the same concentration difference is achieved, the ion implantation method of the present invention can effectively reduce the implantation amount of boron and phosphorus. In addition, the method of ion implantation combined with high-temperature annealing can improve the doping uniformity of phosphorus and boron in the intrinsic polycrystalline silicon layer, further improving the performance of the battery.

[0042] (4) The open circuit voltage of the passivated back-contact solar cell prepared by the method of the present invention can reach 749mV and the current density can reach 42mA / cm 2 , the fill factor reaches 85.5% and the conversion efficiency of the battery is as high as 26.8%. BRIEF DESCRIPTION OF THE DRAWINGS

[0043] Figure 1 It is a schematic cross-sectional view of the cell structure after step (1) of the method for preparing a passivated contact-type back-contact solar cell according to an embodiment of the present invention.

[0044] Figure 2 It is a schematic cross-sectional view of the cell structure after step (2) of the method for preparing a passivated contact-type back-contact solar cell according to an embodiment of the present invention.

[0045] Figure 3 It is a schematic cross-sectional view of the cell structure after step (3) of the method for preparing a passivated contact-type back-contact solar cell according to an embodiment of the present invention.

[0046] Figure 4 It is a schematic cross-sectional view of the cell structure after step (4) of the method for preparing a passivated contact-type back-contact solar cell according to an embodiment of the present invention.

[0047] Figure 5 It is a schematic cross-sectional view of the cell structure after step (5) of the method for preparing a passivated contact-type back-contact solar cell according to an embodiment of the present invention.

[0048] Figure 6 It is a schematic cross-sectional view of the cell structure after step (6) of the method for preparing a passivated contact-type back-contact solar cell according to an embodiment of the present invention.

[0049] Figure 7 It is a schematic cross-sectional view of the cell structure after step (7) of the method for preparing a passivated contact-type back-contact solar cell according to an embodiment of the present invention.

[0050] Figure 8 It is a schematic cross-sectional view of the cell structure after step (8) of the method for preparing a passivated contact-type back-contact solar cell according to an embodiment of the present invention.

[0051] Fig. 9 It is a schematic cross-sectional view of the cell structure after step (9) of the method for preparing a passivated contact-type back-contact solar cell according to an embodiment of the present invention.

[0052] Fig.10 The present invention is a flow chart of a method for preparing a passivated contact back-contact solar cell according to an embodiment of the present invention.

[0053] Fig.11 Schematic diagram of the mask 41 used in step (5) of the method for preparing a passivated contact-type back-contact solar cell according to an embodiment of the present invention.

[0054] Fig.12 Schematic diagram of the mask 42 used in step (5) of the method for preparing a passivated contact-type back-contact solar cell according to an embodiment of the present invention. DETAILED DESCRIPTION

[0055] The present invention is described in detail below with reference to examples.

[0056] Embodiment 1:

[0057] A method for preparing a passivated contact back contact solar cell comprises the following steps:

[0058] (1) The N-type crystalline silicon substrate 1 is subjected to a texturing treatment to remove the damaged layer and form a pyramid light trapping structure. The resistivity of the N-type crystalline silicon substrate 1 is 1 to 1.5 Ω·cm, and the thickness of the N-type crystalline silicon substrate 1 is 130 to 170 μm. The battery structure after completing this step is as follows: Figure 1 shown.

[0059] (2) using a plasma enhanced chemical vapor deposition (PECVD) method to deposit a layer of SiN on the front surface of the N-type crystalline silicon substrate 1 treated in step (1) X The mask 31 has a thickness of 35 to 45 nm. The battery structure after completing this step is as follows: Figure 2 shown.

[0060] (3) Place the N-type crystalline silicon substrate 1 in a polishing solution. The front surface will not react with the polishing solution due to the presence of the mask 31, while the back surface will be etched into a polished surface. The polishing solution is a heated NaOH solution (solution temperature 78-82°C, polishing time 60s). After polishing is completed, the mask 31 is still retained. The battery structure after completing this step is as follows Figure 3 shown.

[0061] (4) First, a first tunneling layer 201 is grown on the back surface of the N-type crystalline silicon substrate 1 by a high-temperature thermal oxidation method. The first tunneling layer 201 is SiO2 with a thickness of 1.0 to 1.5 nm. A first intrinsic amorphous silicon layer 701 with a thickness of 15 to 25 nm is grown on the first tunneling layer 201 using LPCVD equipment (low pressure chemical vapor deposition). Then, a second tunneling layer 202 is grown on the first intrinsic amorphous silicon layer 701 by a high-temperature thermal oxidation method. The second tunneling layer 202 is SiO2 with a thickness of 1.0 to 1.5 nm. A second intrinsic amorphous silicon layer 702 with a thickness of 75 to 85 nm is grown on the second tunneling layer 202 using LPCVD equipment (low pressure chemical vapor deposition). The battery structure after completing this step is as follows: Figure 4 shown.

[0062] (5) The back surface of the N-type crystalline silicon substrate 1 treated in step (4) is doped with ion implantation, wherein two ion sources are used, which can respectively implement boron implantation and phosphorus implantation, and a mask fixture is set between the back surface of the silicon wafer and the ion source to selectively implant boron ions or phosphorus ions. During boron ion implantation, the power supply voltage is 200V, the material transmission speed is 1m / min, and a mask 41 is set between the back surface of the N-type crystalline silicon substrate 1 and the ion beam. The material of the mask 41 is graphite, such as Fig.11 As shown, a linear opening 411 is provided on the mask 41, the width of the linear opening 411 is 1950-2050 um, and the boron implantation dose is 1.5×10 15 ~2.5×10 15 cm -2 After the implantation is completed, a patterned p+ implantation layer 500 is formed on the second intrinsic amorphous silicon layer 702; during the phosphorus ion implantation, the power supply voltage is 200V, the material transmission speed is 0.95m / min, and a mask 42 is set between the back surface of the N-type crystalline silicon substrate 1 and the ion beam. The material of the mask 42 is graphite, such as Fig.12 As shown, a linear opening 421 is provided on the mask 42, and the width of the linear opening 421 is 1950-2050 μm, and the phosphorus implantation dose is 4.5×10 15 ~5.5×10 15 cm -2 After the implantation is completed, a patterned n+ implantation layer 400 is formed on the second intrinsic amorphous silicon layer 702. The p+ implantation layer 500 and the n+ implantation layer 400 are not in direct contact, and there is an area between them that is not implanted with ions. The opening pattern on the mask 41 and the mask 42 can also be a periodic or quasi-periodic array with any other arrangement. There are many options for the pattern as needed, which are not limited here and are only listed as examples. The battery structure after completing this step is as follows Figure 5 shown.

[0063] (6) The N-type crystalline silicon substrate 1 treated in step (5) is placed in an annealing furnace for high-temperature annealing. The peak temperature of the annealing is 888-892°C, the annealing time is 120 minutes, and the ambient gas source is N2. Under the high temperature of the annealing, the boron element in the p+ injection layer 500 will dope the first intrinsic amorphous silicon layer 701 and the second intrinsic amorphous silicon layer 702 below, and finally form a first p+ polycrystalline silicon layer 501 and a second p+ polycrystalline silicon layer 502, wherein the doping concentration of the boron element in the first p+ polycrystalline silicon layer 501 is lower than the doping concentration of the boron element in the second p+ polycrystalline silicon layer 502. Under the action of high temperature during annealing, the phosphorus element in the n+ injection layer 400 will dope the first intrinsic amorphous silicon layer 701 and the second intrinsic amorphous silicon layer 702 below, and finally form the first n+ polycrystalline silicon layer 401 and the second n+ polycrystalline silicon layer 402, wherein the doping concentration of the phosphorus element in the first n+ polycrystalline silicon layer 401 is lower than the doping concentration of the phosphorus element in the second n+ polycrystalline silicon layer 402. The area of ​​the first intrinsic amorphous silicon layer 701 that has not been ion-implanted is converted into the first isolation layer 301 after annealing, and the area of ​​the second intrinsic amorphous silicon layer 702 that has not been ion-implanted is converted into the second isolation layer 302 after annealing. At this point, a double-layer tunneling polycrystalline silicon structure is formed on the back side of the N-type crystalline silicon substrate 1. The battery structure after completing this step is as shown below. Figure 6 shown.

[0064] (7) Place the N-type crystalline silicon substrate 1 after the treatment in step (6) into a cleaning machine for cleaning and drying. After cleaning, the mask 31 and the oxide layer generated during annealing are removed. The battery structure after completing this step is as follows: Figure 7 shown.

[0065] (8) A layer of AlO is formed on the front surface of the N-type crystalline silicon substrate 1 after being treated in step (7) by ALD (atomic layer deposition) x The dielectric film 12 has a thickness of 4.5 to 5.5 nm. A layer of AlO is also formed on the back side by ALD (atomic layer deposition). x The dielectric film 11 has a thickness of 4.5 to 5.5 nm. A layer of SiN with a thickness of 28 to 32 nm is deposited on the front surface by PECVD. x The dielectric film 13 is then formed on the SiN x A layer of SiN is deposited on the dielectric film 13. x O y The dielectric film 14 has a thickness of 48 to 52 nm. Finally, AlO x A layer of SiN is deposited on the surface of the dielectric film 11. x Dielectric film 15, SiN x The thickness of the dielectric film 15 is 83-87 nm.

[0066] AlO on the front surface of the silicon substratex Dielectric film 12, SiN x Dielectric film 13, SiN x O y The dielectric film 14 serves to passivate the front surface of the silicon substrate and reduce light reflection; the AlO x Dielectric film 11 and SiN x The dielectric film 15 serves to passivate the back surface of the silicon substrate. x The dielectric film 15 also acts as a barrier to AlO x The protection function of the dielectric film 11. After completing this step, the battery structure is as follows Figure 8 shown.

[0067] (9) Print the metal electrode 22 on the second n+ polysilicon layer 402 on the back surface of the N-type crystalline silicon substrate 1 after the treatment in step (8) by screen printing, and print the metal electrode 21 on the second p+ polysilicon layer 502 on the back surface. The metal electrodes 21 and 22 are silver. After the printing is completed, the N-type crystalline silicon substrate 1 is transferred to a belt sintering furnace for sintering to form an ohmic contact. The battery structure after completing this step is as follows: Fig. 9 So far, the manufacturing of the passivated contact type back contact solar cell of the present invention is completed.

[0068] The open circuit voltage of the solar cell prepared by the method of Example 1 is 749mV, and the current density is 42mA / cm 2 , the fill factor is 85.5% and the battery conversion efficiency is 26.8%.

[0069] Embodiment 2:

[0070] A method for preparing a passivated contact back contact solar cell comprises the following steps:

[0071] (1) The P-type crystalline silicon substrate 1 is textured to remove the damaged layer and form a pyramid light trapping structure. The resistivity of the P-type crystalline silicon substrate 1 is 1 to 1.5 Ω·cm; the thickness of the P-type crystalline silicon substrate 1 is 130 to 170 μm. The battery structure after completing this step is as follows: Figure 1 shown.

[0072] (2) using a plasma enhanced chemical vapor deposition (PECVD) method to deposit a layer of SiN on the front surface of the P-type crystalline silicon substrate 1 treated in step (1) X The mask 31 has a thickness of 35 to 45 nm. The battery structure after completing this step is as follows: Figure 2 shown.

[0073] (3) Place the P-type crystalline silicon substrate 1 in a polishing solution. The front surface will not react with the polishing solution due to the presence of the mask 31, while the back surface will be etched into a polished surface. The polishing solution is a heated NaOH solution (78-82°C, time 60s). After polishing is completed, the mask 31 is still retained. The battery structure after completing this step is as follows: Figure 3 shown.

[0074] (4) First, a first tunneling layer 201 is grown on the back surface of the P-type crystalline silicon substrate 1. The first tunneling layer 201 is SiO2, and the growth method is a high-temperature thermal oxidation method. The thickness of the first tunneling layer 201 is 1.0 to 1.5 nm. Use LPCVD equipment (low pressure chemical vapor deposition) to grow a first intrinsic amorphous silicon layer 701 with a thickness of 15 to 25 nm on the first tunneling layer 201. Then use a high-temperature thermal oxidation method to grow a second tunneling layer 202 on the first intrinsic amorphous silicon layer 701. The second tunneling layer 202 is SiO2 with a thickness of 0.8 to 1.0 nm. Then use LPCVD equipment (low pressure chemical vapor deposition) to grow a second intrinsic amorphous silicon layer 702 with a thickness of 75 to 85 nm on the second tunneling layer 202. The battery structure after completing this step is as follows. Figure 4 shown.

[0075] (5) The back surface of the P-type crystalline silicon substrate 1 treated in step (4) is doped with ion implantation, wherein two ion sources are used, which can respectively implement boron implantation and phosphorus implantation, and a mask fixture is set between the back surface of the silicon wafer and the ion source to selectively implant boron ions or phosphorus ions. During boron ion implantation, the power supply voltage is 200V, the material transmission speed is 1m / min, and a mask 41 is set between the back surface of the P-type crystalline silicon substrate 1 and the ion beam. The material of the mask 41 is graphite, such as Fig.11 As shown, a linear opening 411 is provided on the mask 41, the width of the linear opening 411 is 1950-2050 um, and the boron implantation dose is 1.5×10 15 ~2.5×10 15 cm -2 After the implantation is completed, a patterned p+ implantation layer 500 is formed on the second intrinsic amorphous silicon layer 702; during the phosphorus ion implantation, the power supply voltage is 200V, the material transmission speed is 0.95m / min, and a mask 42 is set between the back surface of the P-type crystalline silicon substrate 1 and the ion beam. The material of the mask 42 is graphite, such as Fig.12 As shown, a linear opening 421 is provided on the mask 42, and the width of the linear opening 421 is 1950-2050 μm, and the phosphorus implantation dose is 4.5×10 15 ~5.5×10 15 cm -2After the implantation is completed, a patterned n+ implantation layer 400 is formed on the second intrinsic amorphous silicon layer 702. The p+ implantation layer 500 and the n+ implantation layer 400 are not in direct contact, and there is an area between them that is not implanted with ions. The opening pattern on the mask 41 and the mask 42 can also be a periodic or quasi-periodic array with any other arrangement. There are many options for the pattern as needed, which are not limited here and are only listed as examples. The battery structure after completing this step is as follows Figure 5 shown.

[0076] (6) The P-type crystalline silicon substrate 1 treated in step (5) is placed in an annealing furnace for high-temperature annealing. The peak temperature of the annealing is 888-892°C, the annealing time is 120 minutes, and the ambient gas source is N2. Under the high temperature of the annealing, the boron element in the p+ injection layer 500 will dope the first intrinsic amorphous silicon layer 701 and the second intrinsic amorphous silicon layer 702 below, and finally form a first p+ polycrystalline silicon layer 501 and a second p+ polycrystalline silicon layer 502, wherein the doping concentration of the boron element in the first p+ polycrystalline silicon layer 501 is lower than the doping concentration of the boron element in the second p+ polycrystalline silicon layer 502. Under the action of high temperature during annealing, the phosphorus element in the n+ injection layer 400 will dope the first intrinsic amorphous silicon layer 701 and the second intrinsic amorphous silicon layer 702 below, and finally form the first n+ polycrystalline silicon layer 401 and the second n+ polycrystalline silicon layer 402, wherein the doping concentration of the phosphorus element in the first n+ polycrystalline silicon layer 401 is lower than the doping concentration of the phosphorus element in the second n+ polycrystalline silicon layer 402. The area of ​​the first intrinsic amorphous silicon layer 701 that has not been ion-implanted is converted into the first isolation layer 301 after annealing, and the area of ​​the second intrinsic amorphous silicon layer 702 that has not been ion-implanted is converted into the second isolation layer 302 after annealing. At this point, a double-layer tunneling polycrystalline silicon structure is formed on the back side of the P-type crystalline silicon substrate 1. The battery structure after completing this step is as shown below. Figure 6 shown.

[0077] (7) Place the P-type crystalline silicon substrate 1 after the treatment in step (6) into a cleaning machine for cleaning and drying. After cleaning, the mask 31 and the oxide layer generated during annealing are removed. The battery structure after completing this step is as follows: Figure 7 shown.

[0078] (8) A layer of AlO is formed on the front surface of the P-type crystalline silicon substrate 1 after the treatment in step (7) by ALD (atomic layer deposition) x The dielectric film 12 has a thickness of 4.5 to 5.5 nm. A layer of AlO is formed on the back by ALD (atomic layer deposition) x The dielectric film 11 has a thickness of 4.5 to 5.5 nm. A layer of SiN with a thickness of 28 to 32 nm is first deposited on the front surface by PECVD. x The dielectric film 13 is then formed on the SiN xA layer of SiN is deposited on the dielectric film 13. x O y The dielectric film 14 has a thickness of 48 to 52 μm; finally, AlO x A layer of SiN is deposited on the surface of the dielectric film 11. x Dielectric film 15, SiN x The thickness of the dielectric film 15 is 83-87 nm.

[0079] AlO on the front surface of the silicon substrate x Dielectric film 12, SiN x Dielectric film 13, SiN x O y The dielectric film 14 serves to passivate the front surface of the silicon substrate and reduce light reflection; the AlO x Dielectric film 11 and SiN x The dielectric film 15 serves to passivate the back surface of the silicon substrate. x The dielectric film 15 also acts as a barrier to AlO x The protection function of the dielectric film 11. After completing this step, the battery structure is as follows Figure 8 shown.

[0080] (9) Print the metal electrode 22 on the second n+ polysilicon layer 402 on the back surface of the P-type crystalline silicon substrate 1 after the treatment in step (8) by screen printing, and print the metal electrode 21 on the second p+ polysilicon layer 502 on the back surface. The metal electrodes 21 and 22 are silver. After the printing is completed, the P-type crystalline silicon substrate 1 is transferred to a belt sintering furnace for sintering to form an ohmic contact. The battery structure after completing this step is as follows: Fig. 9 So far, the manufacturing of the passivated contact type back contact solar cell of the present invention is completed.

[0081] The open circuit voltage of the solar cell prepared in this example is 746mV, and the current density is 41mA / cm 2 , the fill factor is 85.5% and the battery conversion efficiency is 26.15%.

[0082] Comparative Example 1

[0083] The difference between Comparative Example 1 and Example 1 is that in step (4), the first tunneling layer and the first intrinsic amorphous silicon layer are deposited in sequence only on the back surface of the N-type crystalline silicon substrate 1, wherein the thickness of the first tunneling layer is 1 to 1.5 nm, the thickness of the first intrinsic amorphous silicon layer is 115 to 125 nm, the initial doping concentration is the same as that of Implementation Example 1, and the other auxiliary materials used are the same as those of Example 1.

[0084] The open circuit voltage of the solar cell prepared in Comparative Example 1 is 742mV, and the current density is 42mA / cm 2, the fill factor is 84.5% and the battery conversion efficiency is 26.33%.

[0085] Comparative Example 2

[0086] The difference between Comparative Example 2 and Example 1 is that the thickness of the second intrinsic polysilicon layer is 23-27 nm.

[0087] The open circuit voltage of the solar cell prepared in Comparative Example 2 was 735 mV, and the current density was 41 mA / cm 2 , the fill factor is 82% and the battery conversion efficiency is 24.7%.

[0088] Comparative Example 3

[0089] The difference between Comparative Example 3 and Example 1 is that the thickness of the second intrinsic polysilicon layer is 115-125 nm.

[0090] The open circuit voltage of the solar cell prepared in Comparative Example 3 was 747 mV, and the current density was 41.5 mA / cm 2 , the fill factor is 85.0% and the cell conversion efficiency is 26.4%.

[0091] Comparative Example 4

[0092] The difference between Comparative Example 4 and Example 1 is that the injection amount of boron and phosphorus is reduced, and the injection amount of boron is 1.5×10 14 ~2.5×10 14 cm -2 The phosphorus injection amount is 4.5×10 14 ~5.5×10 14 cm -2 .

[0093] The short-circuit current density of the solar cell prepared in Comparative Example 4 is 42 mA / cm 2 , the open circuit voltage is 748mV, with little change, the fill factor is reduced to 80%, and the conversion efficiency is reduced from 26.8% to 25.1%.

[0094] Comparative Example 5

[0095] The difference between Comparative Example 5 and Example 1 is that the implanted dopants of boron and phosphorus are increased, and the implanted amount of boron is 1.5×10 17 ~2.5×10 17 cm -2 The phosphorus injection amount is 4.5×10 17 ~5.5×10 17 cm -2 .

[0096] The short-circuit current density of the solar cell prepared in Comparative Example 5 is 41 mA / cm 2, the open circuit voltage is 740mV, the fill factor remains unchanged at 85.5%, and the conversion efficiency of the battery decreases from 26.8% to 25.9%.

[0097] It can be seen from the experimental data of Example 1 and Comparative Example 1 that the open circuit voltage, fill factor and conversion efficiency of the solar cell with a double-layer tunneling oxide layer and a double-layer intrinsic polysilicon layer prepared by the method of the present invention are greater than those of the structure of a single-layer tunneling oxide layer and a single-layer intrinsic polysilicon layer. This is mainly because the structure of a single-layer tunneling oxide layer and a single-layer polysilicon layer has a large difference in the concentration of phosphorus and boron ions on both sides of the tunneling oxide layer during annealing. Low-temperature annealing is slow to activate, and high-temperature annealing is prone to phosphorus atoms / boron atoms penetrating the tunneling oxide layer, thereby causing conflicts in conductivity and passivation. Although increasing the doping concentration helps the metal gate line to lead out current and reduce contact resistance, it is easy to cause Auger recombination and reduce short-circuit current; although reducing the doping concentration helps to improve the passivation of the interface and protect the tunneling oxide layer, it is easy to cause an increase in contact resistance, affecting the output characteristics of the battery and reducing conversion efficiency.

[0098] The thickness of the second intrinsic polysilicon layer will also have a great impact on the performance of the solar cell of the present invention. The main reason is that the metal slurry is in direct contact with the second intrinsic polysilicon layer. When the metal slurry is sintered at high temperature, it will form an alloy with the polysilicon. If the thickness of the second intrinsic polysilicon layer is low, it will cause part of the alloy layer to melt through the tunneling oxide layer and enter the low-concentration first polysilicon layer, thereby increasing the contact resistance and affecting the output efficiency of the battery. In addition, after the tunneling oxide layer and the high-concentration polysilicon layer are penetrated by the alloy layer, it will cause the loss of the battery opening voltage, affecting the output efficiency of the battery. If the thickness of the second intrinsic polysilicon layer is thick, it is easy to cause the increase of Auger recombination in this area, affecting the output characteristics of the battery voltage and current.

[0099] In the present invention, the amount of boron and phosphorus injected has a greater impact on the performance of the solar cell. The amount of boron injected in the present invention is preferably 1.5×10 15 ~2.5×10 15 cm -2 , and the preferred amount of phosphorus implantation is 4.5×10 15 ~5.5×10 15 cm -2 If the injection volume is too low (10 14 cm -2 ), the injection amount at this time only maintains the passivation effect, resulting in an increase in the current transfer resistance of the battery, which leads to a significant degradation of the output characteristics. The electrical parameters are an increase in the series resistance Rs and a decrease in the fill factor from 85.5% to 80%, which leads to a decrease in the conversion efficiency of the battery. If the injection amount is too high (10 17 cm -2), at this time, the increase in the injection amount will bring negative effects, that is, the Auger recombination will increase, affecting the open circuit voltage and short circuit current, thereby causing a decrease in the conversion efficiency of the battery.

[0100] The embodiments provided above are not intended to limit the scope of the present invention, and the steps described are not intended to limit the execution order thereof. Those skilled in the art may make obvious improvements to the present invention in combination with existing common knowledge, which also fall within the scope of protection defined by the claims of the present invention.

Claims

1. A method for preparing a passivated contact back contact solar cell, characterized in that: The following steps are involved: (1) performing texturing treatment on a crystalline silicon substrate to remove a damaged layer and form a pyramid light trapping structure, wherein the crystalline silicon substrate is an N-type crystalline silicon substrate or a P-type crystalline silicon substrate, the resistivity of the crystalline silicon substrate is 0.3 to 10 Ω·cm, and the thickness of the crystalline silicon substrate is 50 to 300 μm; (2) depositing a mask layer on the front surface of the crystalline silicon substrate treated in step (1); (3) placing the crystalline silicon substrate treated in step (2) in a polishing solution so that the back surface is etched into a polished surface, wherein the polishing solution comprises at least one of a heated NaOH, KOH, and TMAH solution, the heating temperature is 75-85° C., and the etching time is 50-120 s; (4) depositing a first tunneling oxide layer, a first intrinsic amorphous silicon layer, a second tunneling oxide layer, and a second intrinsic amorphous silicon layer in sequence on the back surface of the crystalline silicon substrate after being etched in step (3); (5) implanting phosphorus and boron on the back surface of the crystalline silicon substrate treated in step (4) by ion implantation to form an n+ implantation region and a p+ implantation region, respectively, with a gap left between the n+ implantation region and the p+ implantation region; (6) placing the crystalline silicon substrate after the treatment in step (5) into an annealing furnace for high-temperature annealing treatment. Under the action of high-temperature annealing, the boron element in the p+ implantation region and the phosphorus element in the n+ implantation region respectively dope the first intrinsic amorphous silicon layer and the second intrinsic amorphous silicon layer with boron and phosphorus, and finally form a first p+ polycrystalline silicon region and a second p+ polycrystalline silicon region and a first n+ polycrystalline silicon region and a second n+ polycrystalline silicon region, wherein the doping concentration of the boron element in the first p+ polycrystalline silicon region is lower than the doping concentration of the boron element in the second p+ polycrystalline silicon region, and the doping concentration of the phosphorus element in the first n+ polycrystalline silicon region is lower than the doping concentration of the phosphorus element in the second n+ polycrystalline silicon region; (7) placing the crystalline silicon substrate treated in step (6) into a cleaning machine for cleaning and drying, so that the mask layer and the oxide layer generated during annealing are completely removed; (8) forming a passivation anti-reflection layer and a passivation layer on the front surface and the back surface of the crystalline silicon substrate treated in step (7), respectively; (9) Printing a metal silver electrode on the back surface of the crystalline silicon substrate treated in step (8) by screen printing. After printing, the crystalline silicon substrate is transferred to a belt sintering furnace for sintering to form an ohmic contact.

2. The preparation method according to claim 1, characterized in that: The mask layer in step (2) includes SiO2, SiN x 、SiN x O y At least one of the above, the deposition method of the mask layer is plasma enhanced chemical vapor deposition or low pressure chemical vapor deposition, and the thickness of the mask layer is 20 to 100 nm.

3. The preparation method according to claim 1, characterized in that: The first tunneling oxide layer described in step (4) is SiO2, and the deposition method includes one of high-temperature thermal oxidation, nitric acid oxidation, ozone oxidation, and CVD deposition. The thickness of the first tunneling layer is 0.8 to 3 nm; the deposition method of the first intrinsic amorphous silicon layer includes at least one of low-pressure chemical vapor deposition, atmospheric pressure chemical vapor deposition, and plasma enhanced chemical vapor deposition, and the thickness of the first intrinsic amorphous silicon layer is 10 to 30 nm; the second tunneling oxide layer is SiO2, and the deposition method includes one of high-temperature thermal oxidation, nitric acid oxidation, ozone oxidation, and CVD deposition, and the thickness of the second tunneling layer is 0.8 to 3 nm; the deposition method of the second intrinsic amorphous silicon layer includes at least one of low-pressure chemical vapor deposition, atmospheric pressure chemical vapor deposition, and plasma enhanced chemical vapor deposition, and the thickness of the second intrinsic amorphous silicon layer is 50 to 80 nm.

4. The preparation method according to claim 1, characterized in that: In step (5), two ion sources are used to implant phosphorus and boron respectively. When implanting phosphorus or boron, a mask fixture is set between the back surface of the silicon wafer and the ion source to selectively implant boron ions or phosphorus ions, wherein the mask fixture is made of graphite.

5. The preparation method according to claim 1, characterized in that: In step (5), when boron is implanted, a linear opening is set on the mask fixture, the width of the linear opening is 1950-2050 μm, and the dose of boron implantation is 0.5×10 15 cm -2 ~3×10 15 cm -2 After the implantation is completed, a patterned p+ implantation layer is formed on the second intrinsic amorphous silicon layer; when phosphorus is implanted, a linear opening is set on the mask fixture, and the width of the linear opening is 1950~2050um, 3×10 15 cm -2 ~8×10 15 cm -2 After the implantation is completed, a patterned n+ implantation layer is formed on the second intrinsic amorphous silicon layer; the p+ implantation layer and the n+ implantation layer are not in direct contact, and an area that is not implanted by ions is left between them.

6. The preparation method according to claim 1, characterized in that: In step (6), the peak annealing temperature is 800-1100° C., the annealing time is 30-200 min, and the ambient gas source is N 2 and / or O 2 .

7. The preparation method according to claim 1, characterized in that: The passivation anti-reflection layer in step (8) comprises AlO x Dielectric film, SiN x Dielectric film and / or SiN x O y Dielectric film, the AlO x The dielectric film is deposited by plasma enhanced chemical vapor deposition or atomic layer deposition, with a film thickness of 3 to 10 nm. x Dielectric film or SiN x O y The dielectric film is deposited by plasma enhanced chemical vapor deposition. x The thickness of the dielectric film is 5 to 30 nm, SiN x O y The thickness of the dielectric film is 40 to 80 nm.

8. The preparation method according to claim 1, characterized in that: The passivation layer in step (8) comprises AlO deposited in sequence x Dielectric film and SiN x The dielectric film, the SiN x The dielectric film is deposited by plasma enhanced chemical vapor deposition. x The thickness of the dielectric film is 50 to 90 nm.

9. A passivated contact-type back-contact solar cell prepared by the preparation method according to any one of claims 1 to 8, wherein the solar cell comprises a crystalline silicon substrate, the front side of the crystalline silicon substrate is a passivation anti-reflection layer, and the passivation anti-reflection layer is sequentially composed of a first AlO x Dielectric film, first SiN x Dielectric film and / or SiN x O y The back of the crystalline silicon substrate is composed of a first tunneling layer, a first polysilicon layer, a second tunneling layer, a second polysilicon layer, a passivation layer and a metal electrode from the inside to the outside, and the passivation layer is composed of a second AlO x Dielectric film and second SiN x The dielectric film and the metal electrode are silver electrodes; wherein, The first polysilicon layer includes a first n+ polysilicon region, a first p+ polysilicon region and a first isolation region, the second polysilicon layer includes a second n+ polysilicon region, a second p+ polysilicon region and a second isolation region, and the doping concentration of the boron element in the first p+ polysilicon region is lower than the doping concentration of the boron element in the second p+ polysilicon region, and the doping concentration of the phosphorus element in the first n+ polysilicon region is lower than the doping concentration of the phosphorus element in the second n+ polysilicon region.

10. The passivated contact back contact solar cell according to claim 9, characterized in that: The first AlO x Dielectric film and second AlO x The thickness of the dielectric film is 3 to 10 nm. x The thickness of the dielectric film is 5 to 30 nm. x O y The thickness of the dielectric film is 40 to 80 nm. x The thickness of the dielectric film is 50 to 90 nm.

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