SiC crystal with facet at edge, wafer thereof and semiconductor device

Abstract

The invention provides a SiC crystal with a facet at an edge, a wafer thereof and a semiconductor device, and relates to the technical field of silicon carbide wafers. The SiC crystal contains a facet region and a non-facet region; the facet area is located on the outer circumferential end face of the SiC crystal, the distance between the edge, away from the outer circumferential end face, of the facet area and the outer circumferential end face does not exceed 3% of the diameter of the SiC crystal, and the SiC crystal is obtained through direct growth by adopting a PVT method and is not subjected to subsequent processing. According to the SiC crystal disclosed by the invention, the facet area is fixed at the edge position of the crystal, and the facet area is removed in the subsequent crystal processing process, so that no facet area exists on the whole crystal and a wafer processed along with the crystal at a relatively low cutting loss rate.

Description

Technical Field

[0001] The present invention relates to the technical field of silicon carbide wafers, and in particular to a SiC crystal with a small face located at an edge, a wafer thereof, and a semiconductor device. Background Art

[0002] At present, silicon carbide crystals face two major problems: 1. Quality issues, which affect the yield, performance and reliability of silicon carbide devices; 2. Cost issues, which affect the application of silicon carbide in the terminal. Among them, the loss of material and device yield caused by material quality is also the main reason for the high cost and difficulty in application of silicon carbide crystals.

[0003] The quality problems of silicon carbide crystals fall into two categories: one is material quality and yield problems caused by defects, which are explicit quality problems; the other is material yield and device performance reliability problems caused by consistency problems.

[0004] At present, since facets are an inherent property of SiC crystals prepared by sublimation, such facets exist on SiC crystals and wafers prepared by conventional physical vapor transport (PVT). Among them, facets are commonly known as "growth characteristic faces", "growth facets", "characteristic growth faces", etc. in the art, and the corresponding English is "facet". In this application, growth characteristic faces do not refer to growth interfaces.

[0005] Improving quality and reducing costs are the goals of the sustainable development of silicon carbide crystal materials. Especially at the stage where the silicon carbide industry is rapidly entering large-scale production and application, the stability, consistency and reliability of silicon carbide material performance will play a vital role in the development of the industry. Summary of the invention

[0006] The inventors have found that when silicon carbide crystals are processed using the physical vapor transport method and SiC crystals are prepared using the physical vapor transport method, a {0001} face will appear at different positions of the crystal depending on the angle of the seed crystal used along the <11-20> direction. Usually, when a forward seed crystal is used for crystal growth, the {0001} facet will appear at the center of the crystal; when the bevel angle of the seed crystal used along the <11-20> direction increases, the {0001} facet will appear at the edge of the crystal and gradually migrate toward the center as the crystal grows. Facets at different positions have low transmittance in the facet area and poor transmittance uniformity in the wafer within the plane, as the doping concentration in the facet area is higher than that in the non-facet area. Figure 1As shown, the position and shape of the facet on the wafer can be directly observed from the appearance. The facet is crescent-shaped. Due to the high doping concentration at the facet, it exhibits a typical characteristic of lower resistivity than other areas, resulting in poor resistivity uniformity within the silicon carbide wafer surface. At the same time, the high doping concentration easily causes defects such as basal plane dislocation (BPD), edge dislocation (TED) and stacking fault (SF) in the facet area to be more likely to occur than in the non-facet area.

[0007] In order to solve the above problems, the first aspect of the present invention provides a SiC crystal with a small face located at the edge, the SiC crystal contains a small face area and a non-small face area; the small face area is located at the outer circumferential end face of the SiC crystal, and the distance between the edge of the small face area away from the outer circumferential end face and the outer circumferential end face does not exceed 3% of the diameter of the SiC crystal, and the SiC crystal is directly grown by the PVT method without subsequent processing.

[0008] A second aspect of the present invention provides a SiC wafer, wherein the SiC wafer is obtained by cutting the SiC crystal with the facet located at the edge by removing the facet area.

[0009] The SiC wafer does not contain any one or two or more of a small facet, a high-doping region and a defect aggregation region within the entire area.

[0010] A third aspect of the present invention provides a semiconductor device, wherein the semiconductor device comprises the above-mentioned SiC wafer.

[0011] Compared with the prior art, the present invention achieves at least one of the following beneficial effects:

[0012] (1) In the present invention, the SiC crystal with a small face located at the edge directly fixes the small face area at the edge of the crystal during the PVT growth process, and the distance between the edge of the small face area away from the outer circumferential end face and the outer circumferential end face does not exceed 3% of the diameter of the SiC crystal. In the subsequent processing of the crystal, the small face area is removed, and a low cutting loss rate is achieved, so that there is no small face area on the entire crystal and the wafer processed therefrom.

[0013] (2) The SiC wafer of the present invention has high uniformity, for example, electrical uniformity (for example, resistivity uniformity), transmittance uniformity, and defect distribution uniformity. In addition, the silicon carbide wafer of the present application has no small facet area visible to the naked eye.

[0014] (3) The silicon carbide wafer of the present invention has higher yield, performance and reliability at the device end. BRIEF DESCRIPTION OF THE DRAWINGS

[0015] The drawings described herein are used to provide a further understanding of the present invention and constitute a part of the present invention. The exemplary embodiments of the present invention and their descriptions are used to explain the present invention and do not constitute an improper limitation of the present invention. In the drawings:

[0016] Figure 1 An exemplary embodiment of a schematic structural diagram of a silicon carbide wafer containing facets visible to the naked eye according to the present invention is shown;

[0017] Figure 2 An exemplary embodiment of a schematic diagram of a facet growth process of the present invention is shown;

[0018] Figure 3 An exemplary embodiment of a schematic diagram of a SiC crystal structure in which a facet is located at an edge of the present invention is shown;

[0019] Figure 4 An exemplary embodiment of a SiC wafer structure schematic diagram of the present invention is shown. DETAILED DESCRIPTION

[0020] In order to more clearly illustrate the overall concept of the present invention, a detailed description is given below in an exemplary manner in conjunction with the accompanying drawings.

[0021] In the following description, many specific details are set forth to facilitate a full understanding of the present invention, but the present invention can also be implemented in other ways different from those described herein, and therefore, the scope of protection of the present invention is not limited by the specific embodiments disclosed below. In the description of this specification, the description of reference terms "one embodiment", "some embodiments", "example", "specific example", or "some examples" etc. means that the specific features, structures, materials or characteristics described in conjunction with the embodiment or example are included in at least one embodiment or example of the present invention. In this specification, the schematic representation of the above terms does not necessarily have to be directed to the same embodiment or example. Moreover, the specific features, structures, materials or characteristics described can be combined in any one or more embodiments or examples in a suitable manner.

[0022] In an exemplary embodiment of the present invention, a SiC crystal with a facet located at the edge contains a facet region and a non-facet region; the facet region is located at the outer circumferential end face of the SiC crystal, and the distance between the edge of the facet region away from the outer circumferential end face and the outer circumferential end face does not exceed 3% of the diameter of the SiC crystal, and the SiC crystal is directly grown by the PVT method without subsequent processing.

[0023] The outer circumferential end face refers to the edge position of the crystal lateral growth, or the edge position of the crystal. The edge of the facet region away from the outer circumferential end face refers to the end of the facet region close to the center of the silicon carbide crystal.

[0024] Optionally, the maximum cross-sectional area of ​​the facet region accounts for less than 10% of the cross-sectional area of ​​the crystal along the diameter direction; and / or the volume of the facet region accounts for less than 2% of the volume of the entire crystal. For example, the facet region can be located at the edge of the upper or lower angle of the crystal.

[0025] Optionally, the maximum cross-sectional area of ​​the small face region accounts for less than 5% of the cross-sectional area of ​​the crystal along the diameter direction; and / or the volume of the small face region accounts for less than 0.6% of the volume of the entire crystal. The overall shape of the small face region can be triangular, conical, spherical, ellipsoidal or rhombus. However, the present invention is not limited to this, and the small region can be irregularly shaped.

[0026] Optionally, the in-plane resistivity difference of the faceted region is more than 5 times the in-plane resistivity difference of the non-faceted region;

[0027] and / or the transmittance difference of the faceted area is more than 5 times the transmittance difference of the non-faceted area;

[0028] The TDV of the and / or facet area is more than 6 times that of the non-facet area.

[0029] Optionally, the in-plane resistivity difference of the faceted region is more than 8 times the in-plane resistivity difference of the non-faceted region;

[0030] and / or the transmittance difference of the faceted area is more than 14 times the transmittance difference of the non-faceted area;

[0031] The TDV of the and / or facet area is more than 10 times that of the non-facet area.

[0032] Optionally, the cross section of the small face region along the diameter direction is elliptical, crescent-shaped or circular. However, the present invention is not limited thereto, and the cross section of the small face region along the diameter direction may be irregularly shaped.

[0033] In another exemplary embodiment of the present invention, a SiC wafer is obtained by cutting the SiC crystal with the above-mentioned small face located at the edge by removing the small face area, and the SiC wafer does not contain any one or more of the small face, high doping area and defect aggregation area within the entire area.

[0034] Among them, the high-doped area refers to the "black spot birthmark" visible to the naked eye in the silicon carbide wafer, where the doping concentration is greater than the doping concentration in the non-small face area; the defect aggregation area refers to the "black spot birthmark" visible to the naked eye in the silicon carbide wafer, where the defect density is greater than the defect density in the non-small face area.

[0035] Optionally, the in-plane resistivity difference of the SiC wafer is not higher than 2 mΩ·cm;

[0036] and / or the transmittance difference is not higher than 3%;

[0037] and / or TDV less than 200cm -2 .

[0038] Preferably, the in-plane resistivity difference of the SiC wafer is not higher than 1 mΩ·cm;

[0039] and / or the transmittance difference is not higher than 2%;

[0040] and / or TDV less than 100cm -2 .

[0041] The total density variation (TDV) is defined as: a number of squares with a specific area are divided in the wafer, such as n squares with an area of ​​1mmx1mm, 2mmx2mm, 5mmx5mm, and 10mmx10mm, and the edge dislocation (TED) or screw dislocation (TSD) density in the square is d1, d2, d3...dn. TDV is the difference between the maximum TED / TSD density and the minimum TED / TSD density dmax-dmin. Due to the elimination of small faces, TDV is improved, eliminating the problem of low overall defect density and high local density.

[0042] Optionally, the SiC wafer is a silicon carbide wafer of any thickness, for example, the thickness of the SiC wafer is not less than 200 μm; or the thickness of the silicon carbide wafer is not less than 300 μm; or the thickness of the silicon carbide wafer is not less than 400 μm.

[0043] Optionally, the SiC wafer can be N 2 Doping or co-doping with any other elements. Specifically, nitrogen can be co-doped with any one or more elements of P, As, Ge, Sn, B, and Al, and the prepared silicon carbide wafer is conductive.

[0044] Optionally, the wafer size may be 4 inches, 6 inches, 8 inches, 10 inches or 12 inches.

[0045] Specifically, since the small face is an inherent property of SiC crystals prepared by sublimation, such small face areas exist on SiC crystals and wafers prepared by conventional physical vapor transport methods. In order to fix the small face at the edge of the crystal and remove it in the subsequent crystal processing process, so that there is no small face on the entire crystal rod and the wafer processed therefrom, the processing method of SiC crystals with small faces located at the edge of the present application includes the following steps:

[0046] S1 thermal field structure design: When the PVT method is used to prepare silicon carbide crystals, there is a radial temperature gradient on the crystal growth surface and the radial temperature gradient is continuous from the center to the edge. The radial temperature gradient will drive the small face to move toward the center of the crystal. A negative radial temperature gradient is set within 5mm of the crystal edge and the radial temperature gradient at the crystal edge is 0.1-5℃ / mm, while a positive and continuous temperature gradient is always maintained at the center of the crystal to ensure normal growth of the crystal. The negative radial temperature gradient at the edge of the crystal can cause the small face to change its movement trend from moving toward the center of the crystal to being fixed within 5mm of the crystal edge. Specifically, the movement trend of the small face can be referenced Figure 2 shown.

[0047] S2 Crystal diameter design: Use a seed crystal larger than the target silicon carbide crystal diameter for crystal growth. The seed crystal diameter is at least 5mm larger than the target crystal and wafer diameter. For example, the seed crystal diameter is 160mm and the wafer diameter is 150mm or the seed crystal diameter is 210mm and the wafer diameter is 200mm, so that the prepared SiC crystal has an edge processing allowance, such as Figure 3 shown.

[0048] The processing method of the above silicon carbide crystal breaks through the conventional continuous positive radial temperature distribution design, and innovatively designs a negative radial temperature gradient at the edge of the crystal growth, thereby locking the small facets in the edge area of ​​the crystal. This growth scheme is simple and easy to implement, and can ensure the stress and defect control under the continuous and small temperature gradient in the center area of ​​the crystal. Through the above innovation, the small facets can be fixed at the edge of the crystal and removed in the subsequent crystal processing process, so that there are no small faces on the entire crystal rod and the wafer processed therefrom. The structure of the faceless silicon carbide wafer is a reference Figure 4 As shown, it can be seen that the chip surface has a high degree of uniformity and consistency, and there is no "black spot birthmark" visible to the naked eye, which eliminates the problems of device end yield, performance loss and reliability degradation caused by the small surface.

[0049] Examples 1-5

[0050] According to the conditions in Table 1, the processing method of the SiC crystal with the facet located at the edge of Examples 1-5 includes the following steps:

[0051] S1 thermal field structure design: Silicon carbide crystals are prepared by PVT method. A radial temperature gradient is set on the crystal growth surface and the radial temperature gradient is continuous from the center to the edge. The positive radial temperature gradient is set to 0.1-5℃ / mm from the center to the edge of the crystal within 5mm. A negative (reverse) radial temperature gradient is set within 5mm of the edge of the crystal, and the reverse radial temperature gradient is 0.1-5℃ / mm. The center of the crystal always maintains a positive and continuous temperature gradient to ensure the normal growth of the crystal. The reverse radial temperature gradient at the edge of the crystal can change the movement trend of the small face from moving toward the center of the crystal to being fixed at the edge of the crystal.

[0052] S2 crystal diameter design: Use a seed crystal larger than the target silicon carbide crystal diameter for crystal growth. The seed crystal diameter is at least 5mm larger than the target crystal and wafer diameter, so that the prepared SiC crystal has edge processing allowance.

[0053] Comparative Example 1

[0054] The main difference from Example 2 is that a conventional continuous positive radial temperature distribution design is adopted.

[0055] Experimental example

[0056] The SiC crystal prepared by the above method with the facet located at the edge, the position test of the facet region in the crystal is shown in reference Table 1. Among them, the volume of the facet region can be calculated by calculus or modeling.

[0057] Table 1 Position test table of small facet area in crystal

[0058]

[0059] Referring to Table 1, it can be seen that the distance between the facet region and the crystal edge of the SiC crystal of the present application is controlled within 5 mm. The distance between the edge of the facet region away from the outer circumferential end face and the outer circumferential end face does not exceed 3% of the SiC crystal diameter.

[0060] The SiC crystals with small faces at the edges obtained in Examples 1-5 were processed to remove the small face areas, and then cut to obtain SiC wafers. Comparative Example 1 was cut to form silicon carbide wafers. The performance test of the SiC wafers is shown in Reference Table 2.

[0061] Among them, the in-plane resistivity difference is "the maximum in-plane resistivity - the minimum in-plane resistivity"; the transmittance difference is "the maximum transmittance - the minimum transmittance".

[0062] Table 2 SiC wafer performance test table

[0063] Thickness / μm In-plane resistivity difference / mΩ·cm Transmittance difference <![CDATA[TDV / cm -2 ]]> Example 1 350 0.60 1.5％ 45 Example 2 350 0.83 0.8％ 12 Example 3 350 0.85 0.6％ 38 Example 4 200 0.82 1.0％ 75 Example 5 500 1.5 3.1％ 150 Comparative Example 1 350 7 12％ 500

[0064] Referring to Table 2, it can be seen that the in-plane resistivity of the SiC wafer of the present application is uniform, there is no abnormally low-resistance area, and the transmittance and TDV are highly uniform.

[0065] On the basis of Examples 1-4, the SiC crystals prepared in Examples 1-4 were directly cut to obtain SiC wafers, and the performance of the obtained silicon carbide wafers containing small faces was tested, as shown in Table 3.

[0066] Table 3 Performance test table of silicon carbide wafers with small faces

[0067]

[0068] Referring to Table 3, it can be seen that the in-plane resistivity difference of the small facet area is more than 4 times the in-plane resistivity difference of the non-small facet area; the transmittance difference of the small facet area is more than 5 times the transmittance difference of the non-small facet area; the TDV of the small facet area is more than 6 times the TDV of the non-small facet area.

[0069] In summary, the SiC crystal of the present application limits the small face area to the edge of the crystal through the cooperation of the thermal field and the seed crystal during growth, and after it is removed through the subsequent processing process, the obtained silicon carbide wafer has no small face. Since the small face area is eliminated, the uniformity of resistivity and transmittance inside the silicon carbide wafer is greatly improved, and there is no accumulation of inclusions or dislocations, micropipes and other defects on the small face of the usual crystal inside the wafer, and the quality and yield of the wafer are greatly improved; the performance and reliability of the wafer in the subsequent device process and use process will be greatly improved.

[0070] The above description is only an embodiment of the present invention and is not intended to limit the present invention. For those skilled in the art, the present invention may have various modifications and variations. Any modification, equivalent substitution, improvement, etc. made within the spirit and principle of the present invention should be included in the scope of the claims of the present invention.

Claims

1. A SiC crystal with a facet located at the edge, characterized in that: The SiC crystal contains a small face region and a non-small face region; the small face region is located at the outer circumferential end face of the SiC crystal, the distance between the edge of the small face region away from the outer circumferential end face and the outer circumferential end face does not exceed 3% of the diameter of the SiC crystal, and the SiC crystal is directly grown by the PVT method without subsequent processing.

2. The SiC crystal according to claim 1, characterized in that: The maximum cross-sectional area of ​​the facet region accounts for less than 10% of the cross-sectional area of ​​the crystal along the diameter direction; and / or the volume of the small face region accounts for less than 2% of the total crystal volume.

3. The SiC crystal according to claim 2, characterized in that: The maximum cross-sectional area of ​​the facet region accounts for less than 5% of the cross-sectional area of ​​the crystal along the diameter direction; and / or the volume of the small face region accounts for less than 0.6% of the total crystal volume.

4. The SiC crystal according to claim 1, characterized in that: The in-plane resistivity difference of the area containing facets is more than 5 times that of the area without facets; and / or the transmittance difference of the faceted area is more than 5 times the transmittance difference of the non-faceted area; The TDV of the and / or facet area is more than 6 times that of the non-facet area.

5. The SiC crystal according to claim 4, characterized in that: The in-plane resistivity difference of the area containing facets is more than 8 times that of the area without facets; and / or the transmittance difference of the faceted area is more than 14 times the transmittance difference of the non-faceted area; The TDV of the and / or facet area is more than 10 times that of the non-facet area.

6. A SiC wafer, characterized in that: The SiC wafer is obtained by cutting the SiC crystal with a small face located at the edge according to any one of claims 1 to 5 above by removing the small face area, The SiC wafer does not contain any one or more of a small facet, a high-doping area and a defect aggregation area within the entire area.

7. The SiC wafer according to claim 6, characterized in that The SiC wafer in-plane resistivity difference is no more than 2 mΩ·cm; and / or the transmittance difference is not higher than 3%; and / or TDV less than 200cm -2 .

8. The SiC wafer according to claim 7, characterized in that: The resistivity difference within the SiC wafer plane is no more than 1mΩ·cm; and / or the transmittance difference is not higher than 2%; and / or TDV less than 100cm -2 .

9. The SiC wafer according to claim 7, characterized in that: The wafer size is 4 inches, 6 inches, 8 inches, 10 inches or 12 inches.

10. A semiconductor device, characterized in that: The semiconductor device comprises the SiC wafer according to any one of claims 6 to 9.

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