IGBT (Insulated Gate Bipolar Translator) with follow current capability and preparation method thereof

Abstract

The invention relates to the technical field of semiconductors, in particular to an IGBT (Insulated Gate Bipolar Translator) with follow current capability and a preparation method thereof. In order to solve the problem that an IGBT needs to be connected with a diode in parallel to serve as a freewheeling diode in practical application, the IGBT with the freewheeling capability and the preparation method thereof are provided, metal electrodes of N + and P + regions on the back face of an epitaxial wafer are isolated, so that an IGBT forward conductive channel is separated from a freewheeling conductive channel of the freewheeling diode, the IGBT forward conductive channel can only enter an epitaxial layer through the P + region, and the IGBT forward conductive channel is separated from the freewheeling conductive channel of the freewheeling diode through the metal electrodes of the N + and P + regions on the back face of the epitaxial wafer. The number of hole carriers injected into the P + region is not affected, a freewheeling conductive channel of the freewheeling diode enters the N + region through the epitaxial layer and does not enter the P + region to cause other electrical influences, compared with a normal IGBT device, the forward through-current capability is not affected, the process steps are simple, and the IGBT device is completely compatible with a current commercialized IGBT preparation process.

Description

Technical Field

[0001] The present invention relates to the field of semiconductor technology, and in particular to an IGBT with self-contained freewheeling capability and a preparation method thereof. Background Art

[0002] In the field of power electronic device technology, IGBT, as a commonly used power semiconductor, occupies a dominant position in the field of high-power power semiconductors.

[0003] Due to its special structure, the traditional IGBT does not have a body diode freewheeling channel and can only connect a diode in parallel as a freewheeling diode. This increases the parasitic parameters between the IGBT and the diode and also increases the power loss of the device.

[0004] At present, one way to solve this problem is to integrate a diode freewheeling channel inside the IGBT. The patent with publication number CN115101578A discloses an IGBT device with a reverse recovery diode and its preparation method. Through three ion implantations, three regions of N+, N++, and P+ are prepared from the edge to the center at the bottom of the epitaxial wafer, and then a drain metal is prepared at the bottom of the epitaxial wafer. This method integrates a reverse recovery diode in the IGBT, but the three regions of N+, N++, and P+ share a drain metal. When the device is powered on in the forward direction, the current flows preferentially from the N+ , N++ flows into the P+ region, and the hole carriers injected into the P+ region will be greatly reduced compared with normal IGBT devices, which will have a huge impact on the forward current capacity of the IGBT; the patent with publication number CN102931216B discloses an insulated gate bipolar transistor structure integrated with a Schottky diode. This solution integrates Schottky metal contacts at the cell spacing at the top of the epitaxial wafer, and prepares N+ and P+ regions at the bottom of the epitaxial wafer. However, the N+ and P+ regions share a drain metal, and there is still a problem that the hole carriers injected into the above-mentioned P+ region will be greatly reduced compared with normal IGBT devices. Summary of the invention

[0005] In response to the above problems, the present invention addresses the problem that IGBT needs to be connected in parallel with a diode as a freewheeling diode in practical applications, and provides an IGBT with self-contained freewheeling capability and a preparation method thereof that avoids affecting the forward current flow capacity, has simple process steps, and is fully compatible with the current commercial IGBT preparation process.

[0006] The technical solution of the present invention is: A method for preparing an IGBT with self-contained freewheeling capability comprises the following steps: Step S100, sequentially preparing a first heavily doped body region and a second heavily doped source region in the epitaxial wafer; Step S200, preparing a gate trench in the epitaxial wafer, and sequentially preparing a gate dielectric and polysilicon in the trench; Step S300, depositing a first isolation layer on the epitaxial wafer, opening a window to prepare a source trench, wherein the bottom of the source trench extends to the inside of the first heavily doped body region, and preparing a source metal in the source trench; Step S400, opening a window at the gate trench to prepare a gate metal; Step S500, thinning the epitaxial wafer, preparing a first heavily doped emitter region on the back of the epitaxial wafer, and preparing a first drain electrode on the surface of the first heavily doped emitter region; Step S600, depositing a second isolation layer on the back of the epitaxial wafer, opening a window at the interval between the first heavily doped emitter regions, and preparing a second drain at the window; Step S700, planarizing the back side of the epitaxial wafer, and the entire device is prepared.

[0007] Specifically, step S100 includes: Step S110, using a photolithography process and a mask to protect the outer area of ​​the first heavily doped body region; forming the first heavily doped body region by a diffusion process or an ion implantation process; Step S120: adopting a photolithography process and using a mask to protect the outer area of ​​the second heavily doped source region; and forming the second heavily doped source region by a diffusion process or an ion implantation process.

[0008] Specifically, step S200 includes: Step S210, using a photolithography process and a mask to protect the outer area of ​​the gate trench; and forming the gate trench by an etching process; Step S220, using a mask to protect the outer area of ​​the gate trench through a photolithography process, and using a thermal oxidation technology to prepare a gate dielectric in the gate trench; Step S230 , preparing polysilicon in the gate trench by chemical vapor deposition.

[0009] Specifically, step S300 includes: Step S310, preparing a first isolation layer by chemical vapor deposition, protecting the outer region of the source trench by a photolithography process using a mask, and opening a window at the source trench by an etching process, wherein the bottom of the source trench extends to the inside of the first heavily doped body region; Step S320, preparing source metal in the source trench by a stripping process or an etching process, and the source metal forms an ohmic contact with the first heavily doped body region and the second heavily doped source region.

[0010] Specifically, step S400 includes: Step S410, using a mask to protect the outer area of ​​the gate trench through a photolithography process, and opening a window in the gate trench through an etching process; Step S420, preparing gate metal at the gate trench opening by a stripping process or an etching process, and the gate metal forms an ohmic contact with the polysilicon.

[0011] Specifically, step S500 includes: Step S510, thinning the back of the epitaxial wafer by a thinning process, using a photolithography process and a mask to protect the outer area of ​​the first heavily doped emitter region; forming an interval of the first heavily doped emitter region by a diffusion process or an ion implantation process; Step S520: preparing a first drain electrode on the surface of the first heavily doped emitter region by a stripping process or an etching process.

[0012] Specifically, step S600 includes: Step S610, preparing a second isolation layer on the back of the epitaxial wafer by chemical vapor deposition, protecting the outer region of the first heavily doped emitter region spacing region by using a mask through a photolithography process, and opening a window in the first heavily doped emitter region spacing region through an etching process; Step S620, preparing a second drain at the window opening in the first heavily doped emitter region spacing region by a stripping process or an etching process, and forming an ohmic contact between the second drain and the second heavily doped substrate region.

[0013] An IGBT with self-contained freewheeling capability, comprising a second heavily doped substrate region, a second lightly doped voltage-resistant region, a first heavily doped body region, a second heavily doped source region and a first isolation layer arranged in sequence from bottom to top; The second heavily doped source region is provided with: A plurality of gate dielectrics are provided, each of which is in a U-shaped structure and extends downward from the top surface of the second heavily doped source region to the second lightly doped voltage-resistant region; There are several polysilicon layers, each of which is filled in the gate dielectric; There are multiple source metals, each extending downward from the top surface of the first isolation layer to the first heavily doped body region; A gate metal extends downward from the top surface of the first isolation layer into the polysilicon to form an ohmic contact with the polysilicon; The second heavily doped substrate region is provided with: A plurality of first heavily doped emitter regions are provided, each extending upward from the bottom surface of the epitaxial wafer at intervals; A first drain electrode is provided, and is respectively connected to the lower surface of the first heavily doped emitter region; A plurality of second isolation layers are provided, each of which is disposed on the side of the first drain electrode, and the top surfaces of the second isolation layers are connected to the first heavily doped emitter region and the second heavily doped substrate region respectively; A plurality of second drain electrodes are provided, each of which is located between adjacent second isolation layers and has a top surface connected to the second heavily doped substrate region; Specifically, the top surface of the polysilicon is flush with the top surface of the second heavily doped source region.

[0014] Specifically, the cross-sectional width of the first drain is smaller than the cross-sectional width of the first heavily doped emitter region.

[0015] In order to solve the problem that an IGBT needs to be connected in parallel with a diode as a freewheeling diode in practical applications, the present invention provides an IGBT with self-contained freewheeling capability and a preparation method thereof. The metal electrodes in the N+ and P+ regions on the back of an epitaxial wafer are isolated to separate the forward conductive channel of the IGBT and the freewheeling conductive channel of the freewheeling diode. The forward conductive channel of the IGBT can only enter the epitaxial layer through the P+ region, without affecting the number of hole carriers injected into the P+ region. The freewheeling conductive channel of the freewheeling diode enters the N+ through the epitaxial layer, and will not enter the P+ region to cause other electrical effects. Compared with a normal IGBT device, the forward current carrying capacity will not be affected, and the process steps are simple, which is fully compatible with the current commercial IGBT preparation process. BRIEF DESCRIPTION OF THE DRAWINGS

[0016] Figure 1 It is a process flow chart of the present invention; Figure 2 is a schematic diagram of the cross-sectional structure of preparing the first heavily doped body region; Figure 3 is a schematic diagram of the cross-sectional structure of preparing the second heavily doped source region; Figure 4 is a schematic diagram of the cross-sectional structure of the gate trench; Figure 5 is a schematic diagram of a cross-sectional structure of a gate dielectric prepared; Figure 6 It is a schematic diagram of the cross-sectional structure of preparing polycrystalline silicon; Figure 7 is a schematic diagram of the cross-sectional structure of preparing the first isolation layer; Figure 8 is a schematic diagram of the cross-sectional structure of the source trench; Fig. 9 It is a schematic diagram of the cross-sectional structure of the source metal; Fig.10 Schematic diagram of the gate window cross-section structure; Fig.11 It is a schematic diagram of the cross-sectional structure of the gate metal preparation; Fig.12 It is a schematic diagram of the cross-sectional structure of preparing the first heavily doped emitter region and the first drain; Fig.13 is a schematic diagram of the cross-sectional structure of preparing the second isolation layer; Fig.14 It is a schematic diagram of the cross-sectional structure of preparing the window opening of the second isolation layer; Fig.15 is a schematic diagram of the cross-sectional structure of the device in step S600; Fig.16 is a schematic diagram of the cross-sectional structure of the device in step S700; In the figure, 1 is the epitaxial wafer, 2 is the first heavily doped body region, 3 is the second heavily doped source region, 4 is the gate trench, 5 is the gate dielectric, 6 is polysilicon, 7 is the first isolation layer, 8 is the source trench, 9 is the source metal, 10 is the gate window, 11 is the gate metal, 12 is the first heavily doped emitter region, 13 is the first drain, 14 is the second isolation layer, 15 is the second drain, 16 is the second heavily doped substrate region, and 17 is the second lightly doped voltage-resistant region. DETAILED DESCRIPTION

[0017] Embodiments of the present invention are described in detail below, examples of which are shown in the accompanying drawings, wherein the same or similar reference numerals throughout represent the same or similar elements or elements having the same or similar functions. The embodiments described below with reference to the accompanying drawings are exemplary and are only used to explain the present invention, and cannot be understood as limiting the present invention.

[0018] In the description of the present invention, it should be noted that, unless otherwise clearly specified and limited, the terms "installed", "connected", and "connected" should be understood in a broad sense, for example, it can be a fixed connection, a detachable connection, or an integral connection; it can be a mechanical connection or an electrical connection; it can be a direct connection, or it can be indirectly connected through an intermediate medium, or it can be the internal communication of two components. For ordinary technicians in this field, the specific meanings of the above terms in the present invention can be understood according to specific circumstances.

[0019] Reference below Figure 1-16 describe the invention; Step S100, sequentially preparing a first heavily doped body region 2 and a second heavily doped source region 3 in the epitaxial wafer 1, referring to Figure 2 , 3 As shown; Step S110, using a photolithography process and a mask to protect the outer area of ​​the first heavily doped body region 2; forming the first heavily doped body region 2 by a diffusion process or an ion implantation process; Step S120, using a photolithography process and a mask to protect the outer area of ​​the second heavily doped source region 3; forming the second heavily doped source region 3 by a diffusion process or an ion implantation process; Correspondingly, the epitaxial wafer 1 of the present embodiment is a Si-based N-type epitaxial wafer, the first doped region is a P region, the second doped region is an N region, and is composed of a second heavily doped substrate region 16 and a second lightly doped voltage-resistant region 17 from bottom to top. The thickness of the epitaxial wafer 1 is 100-2000um, the thickness of the second heavily doped substrate region 16 is 90-1500um, the thickness of the second lightly doped voltage-resistant region 17 is 10-500um, the thickness of the first heavily doped body region 2 is 1-5um, the thickness of the second heavily doped source region 3 is set to 0.5-3um, and the doping concentration range of the N-type doping is 1e 14 .cm -3 -1e 20 .cm -3 , the doping concentration range of P-type doping is 1e 15 .cm -3 -1e 20 .cm -3 , the relevant parameter settings are related to the electrical design of the device; In this embodiment, the thickness of the epitaxial wafer 1 is 350 um, the thickness of the second heavily doped substrate region 16 is 330 um, and the doping concentration is 1e 19 .cm -3 The second lightly doped voltage-resistant region 17 has a thickness of 20 μm and a doping concentration of 1e 16 .cm -3 The thickness of the first heavily doped body region 2 is 2um and the doping concentration is 3e 18 .cm -3 The second heavily doped source region 3 has a thickness of 1 um and a doping concentration of 1e 19. cm -3 , use ion implantation process to prepare the first heavily doped body region 2 and the second heavily doped source region 3.

[0020] Step S200, preparing a gate trench 4 in the epitaxial wafer 1, and sequentially preparing a gate dielectric 5 and polysilicon 6 in the trench 4, referring to Figure 4 , 5 , as shown in 6; Step S210, using a photolithography process and a mask to protect the outer area of ​​the gate trench 4; and forming the gate trench 4 by an etching process; Step S220, using a mask to protect the outer area of ​​the gate trench 4 through a photolithography process, and using a thermal oxidation technique to prepare a gate dielectric 5 in the gate trench 4; Step S230, preparing polysilicon 6 in the gate trench 4 by chemical vapor deposition; Correspondingly, the gate trench 4 extends downward from the top surface of the epitaxial wafer 1, and its bottom surface is lower than the bottom surface of the first heavily doped body region 2 and higher than the bottom surface of the second lightly doped voltage-resistant region 17. The width range is set to 1-10um, and the spacing distance is set to 1-10um. The gate dielectric 5 is located in the trench 4, and is in contact with the second heavily doped source region 3, the first heavily doped body region 2, and the second lightly doped voltage-resistant region 17, respectively. The polysilicon 6 is located in the trench 4, fills the trench 4, and is in contact with the gate dielectric 5. The upper surface of the polysilicon 6 is level with the upper surface of the gate trench 4. The gate dielectric 5 is made of SiO2, and the thickness is set to 40-500nm. The relevant parameter settings are related to the device electrical design. In this embodiment, the gate trench 4 has a depth of 4um, a width of 2um, and a spacing of 2um. The trench 4 is prepared using an ICP dry etching process, 80nm SiO2 is prepared as a gate dielectric 5 using thermal oxidation technology, and polysilicon 6 is prepared using chemical vapor deposition.

[0021] Step S300, depositing a first isolation layer 7 on the epitaxial wafer 1, opening a window to prepare a source trench 8, the bottom of the source trench 8 extends to the inside of the first heavily doped body region 2, and preparing a source metal 9 in the source trench 8, referring to Figure 7 , 8 , as shown in 9; Step S310, preparing a first isolation layer 7 by chemical vapor deposition, protecting the outer region of the source trench 8 by a photolithography process using a mask, and opening a window at the source trench 8 by an etching process, wherein the bottom of the source trench 8 extends to the inside of the first heavily doped body region 2; Step S320, preparing a source metal 9 in the source trench 8 by a stripping process or an etching process, and the source metal 9 forms an ohmic contact with the first heavily doped body region 2 and the second heavily doped source region 3; Accordingly, the first isolation layer 7 plays a protective role, and is made of SiO2 or Si3N4, with a thickness set to 10-5000nm. The source trench 8 is prepared by ICP dry etching, and the source trench 8 extends downward from the top surface of the first isolation layer 7 to the inside of the first heavily doped body region 2, and its bottom surface is higher than the bottom surface of the first heavily doped body region 2, and its width is smaller than the spacing distance of the gate trench 4, and the width range is set to 1-10um. The source metal 9 is arranged inside the source trench 8, and forms an ohmic contact with the first heavily doped body region 2 and the second heavily doped source region 3. The relevant parameter settings are related to the device electrical design; In this embodiment, Si3N4 is used as the first isolation layer 7 with a thickness of 200 nm. ICP dry etching is used to open a window to prepare a source trench 8. The source trench 8 has a depth of 2 um and a width of 1.5 um. A stripping process is used to prepare a 2 um thick Ti / Al two-layer metal inside the source trench 8 as the source metal 9.

[0022] Step S400, opening a window at the gate trench 4 and preparing the gate metal 11, referring to Fig.10 , 11 As shown; Step S410, using a mask to protect the outer area of ​​the gate trench 4 through a photolithography process, and opening a window at the gate trench 4 through an etching process; Step S420, preparing a gate metal 11 at the opening of the gate trench 4 by a stripping process or an etching process, and the gate metal 11 forms an ohmic contact with the polysilicon 6; Correspondingly, the window depth at the gate trench 4 is greater than the thickness of the first isolation layer 7, and the window width is less than the width of the gate trench 4. The gate metal 11 extends downward from the top surface of the first isolation layer 7 into the polysilicon 6 to form an ohmic contact with the polysilicon 6. In this embodiment, a window is opened at the gate groove 4 by an etching process, with a window depth of 1 um and a window width of 1.5 um. A stripping process is used to prepare a 1 um thick Ti / Al two-layer metal as the gate metal 11 to form an ohmic contact with the polysilicon 6.

[0023] Step S500, thinning the epitaxial wafer, preparing a first heavily doped emitter region 12 on the back of the epitaxial wafer, and preparing a first drain electrode 13 on the surface of the first heavily doped emitter region 12, referring to Fig.12 As shown; Step S510, thinning the back of the epitaxial wafer by a thinning process, using a photolithography process and a mask to protect the outer area of ​​the first heavily doped emitter region 12; forming an interval of the first heavily doped emitter region 12 by a diffusion process or an ion implantation process; Step S520, preparing a first drain electrode 13 on the surface of the first heavily doped emitter region 12 by a stripping process or an etching process; Accordingly, the epitaxial wafer is thinned to a corresponding thickness through a thinning process, the thickness of the first heavily doped emitter region 12 is 1-50 um, the width is consistent with the width of the gate trench 4, and the first drain 13 is in contact with the first heavily doped emitter region 12 to form an ohmic contact, and the width thereof is smaller than the width of the first heavily doped emitter region 12; In this embodiment, the 350um thick epitaxial wafer 1 is thinned to 180um using a thinning process. The first heavily doped emitter region 12 has a thickness of 5um, a width of 2um, and a doping concentration of 1e 19. cm -3 The first heavily doped emitter region 12 is prepared by an ion implantation process, the width of the first drain electrode 13 is 1.8 um, and a 1 um thick Ti / Al is prepared by a lift-off process as the first drain electrode 13 .

[0024] Step S600, depositing a second isolation layer 14 on the back of the epitaxial wafer 1, opening a window at the interval between the first heavily doped emitter region 12, and preparing a second drain electrode 15 at the window, referring to Fig.13 , 14 , as shown in 15; Step S610, preparing a second isolation layer 14 on the back of the epitaxial wafer 1 by chemical vapor deposition, protecting the outer area of ​​the first heavily doped emitter region 12 spacing area by using a mask through a photolithography process, and opening a window in the first heavily doped emitter region 12 spacing area through an etching process; Step S620, preparing the second drain 15 at the window of the spacing area of ​​the first heavily doped emitter region 12 by a stripping process or an etching process, and the second drain 15 and the second heavily doped substrate region 16 form an ohmic contact; Accordingly, the second isolation layer 14 plays a protective and isolating role, and is made of SiO2 or Si3N4, and has the same thickness as the first drain 13. ICP dry etching is used to open a window at the interval area of ​​the first heavily doped emitter region 12, and the window width is smaller than the interval width of the first heavily doped emitter region 12, and the window depth is greater than the thickness of the second isolation layer 14. The second drain 15 extends upward from the lower surface of the second isolation layer 14 to fill the window in this step and form an ohmic contact with the second heavily doped substrate region 16. The relevant parameter settings are related to the electrical design of the device; In this embodiment, Si3N4 is used as the second isolation layer 14 with a thickness of 1 um. ICP dry etching is used to open a window in the spacing area of ​​the first heavily doped emitter region 12. The window depth is 1.1 um and the width is 1.8 um. A stripping process is used to prepare a 1.1 um thick Ti / Al as the second drain 15 at the window in this step.

[0025] Step S700, planarizing the back side of the epitaxial wafer 1, and the whole device is prepared. Fig.16 As shown; Accordingly, after the planarization process, there is no second isolation layer 14 below the first drain electrode 13, and the lower surfaces of the first drain electrode 13 and the second drain electrode 15 are level; In this embodiment, an ion etching process is used to perform a planarization process.

[0026] An IGBT with self-contained freewheeling capability, comprising a second heavily doped substrate region 16, a second lightly doped voltage-resistant region 17, a first heavily doped body region 2, a second heavily doped source region 3 and a first isolation layer 7 arranged in sequence from bottom to top; The second heavily doped source region 3 is provided with: The gate dielectric 5 is provided with a plurality of gate dielectrics, each of which is in a U-shaped structure and extends downward from the top surface of the second heavily doped source region (3) to the second lightly doped voltage-resistant region 17; There are several polysilicon 6, each of which is filled in the gate dielectric 5; the top surface of the polysilicon 6 is flush with the top surface of the second heavily doped source region 3; There are multiple source metals 9, which extend downward from the top surface of the first isolation layer 7 to the first heavily doped body region 2, respectively, to form ohmic contacts with the first heavily doped body region 2 and the second heavily doped source region 3; The gate metal 11 extends downward from the top surface of the first isolation layer 7 into the polysilicon 6 to form an ohmic contact with the polysilicon 6; The second heavily doped substrate region 16 is provided with: A plurality of first heavily doped emitter regions 12 are provided, each extending upward from the bottom surface of the epitaxial wafer 1 at intervals, and having a spacing from the upper surface of the second heavily doped substrate region 16; A plurality of first drain electrodes 13 are provided, each of which is connected to the lower surface of the first heavily doped emitter region 12 and has a cross-sectional width smaller than that of the first heavily doped emitter region 12; A plurality of second isolation layers 14 are provided, which are respectively arranged at the sides of the first drain 13, and the top surfaces thereof are respectively connected to the first heavily doped emitter region 12 and the second heavily doped substrate region 16, and the second isolation layers 14 between the first drains 13 are respectively connected to the first heavily doped emitter region 12 and the second heavily doped substrate region 16; There are several second drain electrodes 15, which are respectively located between adjacent second isolation layers 14, and the top surface is connected to the second heavily doped substrate region 16; the cross-sectional width of the second drain electrode 15 is smaller than the spacing between adjacent first heavily doped emitter regions 12; the first drain electrode 13 and the second drain electrode 15 are isolated by the second isolation layer 14; The epitaxial wafer 1 in the present case can be made of various commonly used epitaxial materials for semiconductor devices such as Si, SiC, GaN, etc., including a second heavily doped substrate region 16 and a second lightly doped voltage-resistant region 17 connected from bottom to top; the first doped region and the second doped region have opposite doping types, for example, they can be a P region and an N region or an N region and a P region.

[0027] In order to solve the problem that an IGBT needs to be connected in parallel with a diode as a freewheeling diode in practical applications, the present invention provides an IGBT with self-contained freewheeling capability and a preparation method thereof. The metal electrodes in the N+ and P+ regions on the back of an epitaxial wafer are isolated to separate the forward conductive channel of the IGBT and the freewheeling conductive channel of the freewheeling diode. The forward conductive channel of the IGBT can only enter the epitaxial layer through the P+ region, without affecting the number of hole carriers injected into the P+ region. The freewheeling conductive channel of the freewheeling diode enters the N+ through the epitaxial layer, and will not enter the P+ region to cause other electrical effects. Compared with a normal IGBT device, the forward current carrying capacity will not be affected, and the process steps are simple, which is fully compatible with the current commercial IGBT preparation process.

[0028] Regarding the contents disclosed in this case, there are a few points that need to be explained: (1) The drawings of the embodiments disclosed in this case only involve the structures involved in the embodiments disclosed in this case. Other structures can refer to the general design; (2) In the absence of conflict, the embodiments and features of the embodiments disclosed in this case may be combined with each other to obtain new embodiments; The above are only specific implementation methods disclosed in this case, but the protection scope of the present disclosure is not limited thereto. The protection scope disclosed in this case should be based on the protection scope of the claims.

Claims

1. A method for preparing an IGBT with self-contained freewheeling capability, characterized in that: The following steps are involved: Step S100, sequentially preparing a first heavily doped body region (2) and a second heavily doped source region (3) in the epitaxial wafer (1); Step S200, preparing a gate trench (4) in the epitaxial wafer (1), and sequentially preparing a gate dielectric (5) and polysilicon (6) in the trench (4); Step S300, depositing a first isolation layer (7) on the epitaxial wafer (1), opening a window to prepare a source trench (8), wherein the bottom of the source trench (8) extends to the inside of the first heavily doped body region (2), and preparing a source metal (9) in the source trench (8); Step S400, opening a window at the gate trench (4) to prepare a gate metal (11); Step S500, thinning the epitaxial wafer, preparing a spaced first heavily doped emitter region (12) on the back of the epitaxial wafer, and preparing a first drain electrode (13) on the surface of the first heavily doped emitter region (12); Step S600, depositing a second isolation layer (14) on the back side of the epitaxial wafer (1), opening a window at the interval between the first heavily doped emitter region (12), and preparing a second drain electrode (15) at the window; Step S700, planarizing the back side of the epitaxial wafer (1), and the entire device is prepared.

2. The method for preparing an IGBT with self-contained freewheeling capability according to claim 1, characterized in that: Step S100 includes: Step S110, using a photolithography process and a mask to protect the outer area of ​​the first heavily doped body region (2); forming the first heavily doped body region (2) by a diffusion process or an ion implantation process; Step S120, adopting a photolithography process and using a mask to protect the outer area of ​​the second heavily doped source region (3); and forming the second heavily doped source region (3) through a diffusion process or an ion implantation process.

3. The method for preparing an IGBT with self-contained freewheeling capability according to claim 1, characterized in that: Step S200 includes: Step S210, using a photolithography process and a mask to protect the outer region of the gate trench (4); and forming the gate trench (4) through an etching process; Step S220, using a mask to protect the outer region of the gate trench (4) through a photolithography process, and using a thermal oxidation technique to prepare a gate dielectric (5) in the gate trench (4); Step S230, preparing polysilicon (6) in the gate trench (4) by chemical vapor deposition.

4. The method for preparing an IGBT with self-contained freewheeling capability according to claim 1, characterized in that: Step S300 includes: Step S310, preparing a first isolation layer (7) by chemical vapor deposition, protecting the outer region of the source trench (8) by a photolithography process using a mask, and opening a window at the source trench (8) by an etching process, wherein the bottom of the source trench (8) extends to the inside of the first heavily doped body region (2); Step S320, preparing a source metal (9) in the source trench (8) by a stripping process or an etching process, wherein the source metal (9) forms an ohmic contact with the first heavily doped body region (2) and the second heavily doped source region (3).

5. The method for preparing an IGBT with self-contained freewheeling capability according to claim 1, characterized in that: Step S400 includes: Step S410, using a mask to protect the outer area of ​​the gate trench (4) through a photolithography process, and opening a window at the gate trench (4) through an etching process; Step S420: preparing a gate metal (11) at the window of the gate trench (4) by a stripping process or an etching process, so that the gate metal (11) forms an ohmic contact with the polysilicon (6).

6. The method for preparing an IGBT with self-contained freewheeling capability according to claim 1, characterized in that: Step S500 includes: Step S510, thinning the back of the epitaxial wafer by a thinning process, using a photolithography process and a mask to protect the outer area of ​​the first heavily doped emitter region (12); forming a spaced first heavily doped emitter region (12) by a diffusion process or an ion implantation process; Step S520: preparing a first drain electrode (13) on the surface of the first heavily doped emitter region (12) by a stripping process or an etching process.

7. The method for preparing an IGBT with self-contained freewheeling capability according to claim 1, characterized in that: Step S600 includes: Step S610, preparing a second isolation layer (14) on the back side of the epitaxial wafer (1) by chemical vapor deposition, protecting the outer region of the first heavily doped emitter region (12) spacing region by using a mask through a photolithography process, and opening a window in the first heavily doped emitter region (12) spacing region through an etching process; Step S620, preparing a second drain electrode (15) at a window in the spacing region of the first heavily doped emitter region (12) by a stripping process or an etching process, and forming an ohmic contact between the second drain electrode (15) and the second heavily doped substrate region (16).

8. An IGBT with self-following capability, prepared by the method for preparing an IGBT with self-following capability according to claim 1, characterized in that: It comprises a second heavily doped substrate region (16), a second lightly doped voltage-resistant region (17), a first heavily doped body region (2), a second heavily doped source region (3) and a first isolation layer (7) which are arranged in sequence from bottom to top; The second heavily doped source region (3) is provided with: A plurality of gate dielectrics (5) are provided, each of which is in a U-shaped structure and extends downward from the top surface of the second heavily doped source region (3) to the second lightly doped voltage-resistant region (17); A plurality of polysilicon (6) are provided and are respectively filled in the gate dielectric (5); A plurality of source metals (9) are provided, each extending downward from the top surface of the first isolation layer (7) to the first heavily doped body region (2); A gate metal (11) extends downward from the top surface of the first isolation layer (7) into the polysilicon (6) to form an ohmic contact with the polysilicon (6); The second heavily doped substrate region (16) is provided with: A plurality of first heavily doped emission regions (12) are provided, extending upward from the bottom surface of the epitaxial wafer (1) at intervals; A plurality of first drain electrodes (13) are provided, each of which is connected to the lower surface of the first heavily doped emitter region (12); A plurality of second isolation layers (14) are provided, each of which is arranged on the side of the first drain electrode (13), and the top surfaces of which are respectively connected to the first heavily doped emitter region (12) and the second heavily doped substrate region (16); A plurality of second drain electrodes (15) are provided, each of which is located between adjacent second isolation layers (14) and has a top surface connected to the second heavily doped substrate region (16).

9. The IGBT with self-contained freewheeling capability according to claim 8, characterized in that: The top surface of the polysilicon (6) is flush with the top surface of the second heavily doped source region (3).

10. The IGBT with self-contained freewheeling capability according to claim 8, characterized in that: The cross-sectional width of the first drain (13) is smaller than the cross-sectional width of the first heavily doped emitter region (12).

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