Planar gate IGBT (Insulated Gate Bipolar Translator) with fly-wheel diode and preparation method

Abstract

The invention relates to the technical field of semiconductors, in particular to a planar gate IGBT (Insulated Gate Bipolar Translator) with a fly-wheel diode and a preparation method. In order to solve the problem that a planar gate IGBT needs to be connected with a diode in parallel to serve as a fly-wheel diode in practical application, the planar gate IGBT with the fly-wheel diode and the preparation method of the planar gate IGBT with the fly-wheel diode are provided, and metal electrodes of a first heavily-doped emitter region and a second heavily-doped substrate region on the back face of an epitaxial wafer are isolated; a planar gate IGBT forward conductive channel is separated from a freewheeling conductive channel of a freewheeling diode, the IGBT forward conductive channel can only enter an epitaxial layer through a first heavily-doped emitter region without influencing the number of hole carriers injected into the first heavily-doped emitter region, and the freewheeling conductive channel of the freewheeling diode enters a second heavily-doped substrate region through the epitaxial layer without influencing the number of hole carriers injected into the second heavily-doped emitter region. Compared with a normal planar gate IGBT device, the planar gate IGBT device has the advantages that the forward through-current capability is not influenced, the process steps are simple, and the planar gate IGBT device is completely compatible with the existing commercial planar gate IGBT preparation process.

Description

Technical Field

[0001] The present invention relates to the field of semiconductor technology, and in particular to a planar gate IGBT with a freewheeling diode and a preparation method thereof. Background Art

[0002] In the field of power electronic device technology, IGBT is a commonly used power semiconductor and the most commonly used switching device in the field of high-power semiconductors. Due to its special structure, a conventional IGBT needs to be connected in parallel with a freewheeling diode in application, which increases the parasitic parameters between the IGBT and the diode, increases the power loss of the device, and increases the cost of IGBT application. Therefore, integrating a freewheeling diode is a technical route to solve this problem.

[0003] Existing patent documents, such as the public document with publication number CN115101578A, disclose an IGBT device with a reverse recovery diode and a preparation method thereof. Through three ion implantations, three regions of N+, N++, and P+ are prepared from the edge to the center at the bottom of the epitaxial wafer, and then a drain metal is prepared at the bottom of the epitaxial wafer. This method integrates a reverse recovery diode in the IGBT, but the three regions of N+, N++, and P+ share a drain metal. When the device is forward-powered, the current preferentially flows from N+ and N++, and the hole carriers injected into the P+ region will be greatly reduced relative to normal IGBT devices, which has a huge impact on the forward current capacity of the IGBT.

[0004] For example, the public document with publication number CN102931216B discloses an insulated gate bipolar transistor structure integrated with a Schottky diode. This solution integrates Schottky metal contacts at the cell spacing at the top of the epitaxial wafer, and prepares N+ and P+ regions at the bottom of the epitaxial wafer. However, the N+ and P+ regions share a drain metal, and there is still a problem that the hole carriers injected into the above-mentioned P+ region will be greatly reduced relative to normal IGBT devices.

[0005] Therefore, how to solve the impact of IGBT's forward current capacity is a technical problem that needs to be solved urgently in this case. Summary of the invention

[0006] In view of the above problems, the present invention provides a planar gate IGBT with a freewheeling diode and a preparation method thereof, which will not affect the forward current carrying capacity relative to normal IGBT devices, has simple process steps and is fully compatible with the current commercial IGBT preparation process.

[0007] The technical solution of the present invention is: A method for preparing a planar gate IGBT with a freewheeling diode, comprising the following steps: Step S100, preparing spaced first heavily doped body regions in the epitaxial wafer, preparing a plurality of spaced second heavily doped source regions in the first heavily doped body regions, and preparing a first heavily doped channel region in the second heavily doped source regions; Step S200, preparing a gate dielectric on the epitaxial wafer, and preparing polysilicon on the gate dielectric above the first heavily doped channel region; Step S300, depositing a first isolation layer on the epitaxial wafer, opening windows to prepare source metal, the source metal being in contact with the first heavily doped body region and the second heavily doped source region; Step S400, opening a window at the polysilicon, preparing a gate metal, and the gate metal is in contact with the polysilicon; Step S500, thinning the epitaxial wafer, preparing a first heavily doped emitter region on the back of the epitaxial wafer, and preparing a first drain electrode on the surface of the first heavily doped emitter region; Step S600, depositing a second isolation layer on the back of the epitaxial wafer, opening a window at the interval between the first heavily doped emitter regions, and preparing a second drain at the window; Step S700, planarizing the back side of the epitaxial wafer, and the entire device is prepared.

[0008] Specifically, step S100 includes: Step S110, using a photolithography process and a mask to protect the outer area of ​​the first heavily doped body region; forming a plurality of spaced first heavily doped body regions by a diffusion process or an ion implantation process; Step S120, using a photolithography process and a mask to protect the outer area of ​​the second heavily doped source region; forming a plurality of second heavily doped source regions spaced apart by a diffusion process or an ion implantation process; Step S130: using a photolithography process and a mask to protect the outer area of ​​the first heavily doped channel region; and forming the first heavily doped channel region through a diffusion process or an ion implantation process.

[0009] Specifically, step S200 includes: Step S210, preparing a gate dielectric on the epitaxial wafer using a thermal oxidation technique; Step S220 , using a mask to protect the outer region of the first heavily doped channel region through a photolithography process, and preparing polysilicon on the gate dielectric above the first heavily doped channel region through chemical vapor deposition.

[0010] Specifically, step S300 includes: Step S310, preparing a first isolation layer by chemical vapor deposition, protecting the outer region of the source metal by a mask through a photolithography process, and opening a window by an etching process; Step S320, using a stripping process or an etching process to prepare a source metal at the window, and the source metal is in contact with the first heavily doped body region and the second heavily doped source region.

[0011] Specifically, step S400 includes: Step S410, using a photolithography process, using a mask to protect the outer area of ​​the polysilicon window, and using an etching process to open a window in the polysilicon; Step S420: using a stripping process or an etching process, a gate metal is prepared at the window, and the gate metal contacts the polysilicon.

[0012] Specifically, step S500 includes: Step S510, thinning the back of the epitaxial wafer by a thinning process, using a photolithography process and a mask to protect the outer area of ​​the first heavily doped emitter region; forming an interval of the first heavily doped emitter region by a diffusion process or an ion implantation process; Step S520: preparing a first drain electrode on the surface of the first heavily doped emitter region by a stripping process or an etching process.

[0013] Specifically, step S600 includes: Step S610, preparing a second isolation layer on the back of the epitaxial wafer by chemical vapor deposition, protecting the outer region of the first heavily doped emitter region spacing region by using a mask through a photolithography process, and opening a window in the first heavily doped emitter region spacing region through an etching process; Step S620, preparing a second drain at the window opening in the first heavily doped emitter region spacing region by a stripping process or an etching process, and forming an ohmic contact between the second drain and the second heavily doped substrate region.

[0014] A planar gate IGBT with a freewheeling diode, comprising a second heavily doped substrate region, a second lightly doped withstand voltage region and a gate dielectric arranged in sequence from bottom to top; The second lightly doped voltage-resistant region is provided with: A plurality of first heavily doped body regions are provided and spaced apart, extending downward from the top surface of the epitaxial wafer respectively; There are a plurality of second heavily doped source regions, each extending downward from the top surface of the epitaxial wafer and symmetrically arranged inside the first heavily doped body region; A plurality of first heavily doped channel regions are provided, each extending downward from the top surface of the second heavily doped source region and symmetrically arranged inside the second heavily doped source region; The gate dielectric is provided with: Polycrystalline silicon, provided with a plurality of gate dielectric top surfaces respectively located above the first heavily doped channel region; A first isolation layer is deposited on the top surface of the gate dielectric between the top surface of the polysilicon and the adjacent polysilicon; A plurality of source metals are provided, each extending downward from the top surface of the first isolation layer, and each bottom surface is connected to the first heavily doped body region and the second heavily doped source region respectively; A plurality of gate metals are provided, each extending downward from the top surface of the first isolation layer into the polysilicon to form an ohmic contact with the polysilicon; The second heavily doped substrate region is provided with: A plurality of first heavily doped emitter regions are provided, each extending upward from the bottom surface of the epitaxial wafer at intervals; A plurality of first drain electrodes are provided, each extending downward from the lower surface of the first heavily doped emitter region; A plurality of second isolation layers are provided and are respectively deposited on the bottom surface of the second heavily doped substrate region and the bottom surface of the first heavily doped emitter region; A plurality of second drain electrodes are provided, each of which is disposed on the bottom surface of the second heavily doped substrate region and has a side portion connected to the second isolation layer.

[0015] Specifically, the cross-sectional width of the first drain is smaller than the cross-sectional width of the first heavily doped emitter region.

[0016] Specifically, the distance between adjacent first heavily doped emitter regions is greater than the width of the second drain cross section.

[0017] Beneficial effects of the present invention: In view of the problem that a planar gate IGBT needs to be connected in parallel with a diode as a freewheeling diode in practical applications, the present invention provides a planar gate IGBT with a freewheeling diode and a preparation method thereof. By isolating the metal electrodes of the first heavily doped emitter region and the second heavily doped substrate region on the back side of the epitaxial wafer, the forward conductive channel of the planar gate IGBT and the freewheeling conductive channel of the freewheeling diode are separated. The IGBT forward conductive channel can only enter the epitaxial layer through the first heavily doped emitter region, which does not affect the number of hole carriers injected into the first heavily doped emitter region. The freewheeling conductive channel of the freewheeling diode enters the second heavily doped substrate region through the epitaxial layer, and will not enter the first heavily doped emitter region to cause other electrical influences. Compared with a normal planar gate IGBT device, the forward current carrying capacity is not affected, and the process steps are simple, which is fully compatible with the current commercial planar gate IGBT preparation process. BRIEF DESCRIPTION OF THE DRAWINGS

[0018] Figure 1 It is a process flow chart of the present invention; Figure 2 is a schematic diagram of the cross-sectional structure of preparing the first heavily doped body region; Figure 3 is a schematic diagram of the cross-sectional structure of preparing the second heavily doped source region; Figure 4 is a schematic diagram of the cross-sectional structure of preparing the first heavily doped channel region; Figure 5 It is a schematic diagram of the cross-sectional structure of preparing polycrystalline silicon; Figure 6is a schematic diagram of the cross-sectional structure of preparing the first isolation layer; Figure 7 Schematic diagram of preparing the source window cross-sectional structure; Figure 8 It is a schematic diagram of the cross-sectional structure of the source metal; Fig. 9 It is a schematic diagram of the cross-sectional structure of preparing a gate window; Fig.10 It is a schematic diagram of the cross-sectional structure of the gate metal; Fig.11 It is a schematic diagram of the cross-sectional structure of preparing the first heavily doped emitter region and the first drain; Fig.12 is a schematic diagram of the cross-sectional structure of preparing the second isolation layer; Fig.13 It is a schematic diagram of a cross-sectional structure of a window opening at the interval area of ​​the first heavily doped emitter region; Fig.14 is a schematic diagram of the cross-sectional structure of preparing the second drain electrode; Fig.15 is a schematic diagram of the cross-sectional structure of the device in step S700; In the figure, 1 is the epitaxial wafer, 2 is the first heavily doped body region, 3 is the second heavily doped source region, 4 is the first heavily doped channel region, 5 is the gate dielectric, 6 is polysilicon, 7 is the first isolation layer, 8 is the source window, 9 is the source metal, 10 is the gate window, 11 is the gate metal, 12 is the first heavily doped emitter region, 13 is the first drain, 14 is the second isolation layer, 15 is the second drain, 16 is the second heavily doped substrate region, and 17 is the second lightly doped voltage-resistant region. DETAILED DESCRIPTION

[0019] Embodiments of the present invention are described in detail below, examples of which are shown in the accompanying drawings, wherein the same or similar reference numerals throughout represent the same or similar elements or elements having the same or similar functions. The embodiments described below with reference to the accompanying drawings are exemplary and are only used to explain the present invention, and cannot be understood as limiting the present invention.

[0020] In the description of the present invention, it should be noted that, unless otherwise clearly specified and limited, the terms "installed", "connected", and "connected" should be understood in a broad sense, for example, it can be a fixed connection, a detachable connection, or an integral connection; it can be a mechanical connection or an electrical connection; it can be a direct connection, or it can be indirectly connected through an intermediate medium, or it can be the internal communication of two components. For ordinary technicians in this field, the specific meanings of the above terms in the present invention can be understood according to specific circumstances.

[0021] Reference below Figure 1-15 describe the invention; A method for preparing a planar gate IGBT with a freewheeling diode, comprising the following steps: Step S100, preparing a plurality of first heavily doped body regions 2 at intervals in the epitaxial wafer 1, preparing a plurality of second heavily doped source regions 3 at intervals in the first heavily doped body region 2, and preparing a first heavily doped channel region 4 in the second heavily doped source region 3, referring to Figure 2-4 As shown; Step S110, using a photolithography process and a mask to protect the outer area of ​​the first heavily doped body region 2; forming a plurality of spaced first heavily doped body regions 2 by a diffusion process or an ion implantation process; Step S120, using a photolithography process and a mask to protect the outer area of ​​the second heavily doped source region 3; forming a plurality of second heavily doped source regions 3 arranged at intervals by a diffusion process or an ion implantation process; Step S130, using a photolithography process and a mask to protect the outer area of ​​the first heavily doped channel region 4; forming the first heavily doped channel region 4 by a diffusion process or an ion implantation process; Correspondingly, the epitaxial wafer 1 of the present embodiment is a Si-based N-type epitaxial wafer, the first doped region is a P region, the second doped region is an N region, and is composed of a second heavily doped substrate region 16 and a second lightly doped voltage-resistant region 17 from bottom to top. The thickness of the epitaxial wafer 1 is 100-2000um, the thickness of the second heavily doped substrate region 16 is 90-1500um, the thickness of the second lightly doped voltage-resistant region 17 is 10-500um, the thickness of the first heavily doped body region 2 is 1-10um, the width is 1-10um, and the spacing distance is 1-10um. The thickness of the second heavily doped source region 3 is set to 0.5-5um, the width is set to 0.5-5um, and the spacing distance is 0.5-5um. The thickness of the first heavily doped channel region 4 is equal to that of the second heavily doped source region 3, and the width is set to 0.25-2.5um. The doping concentration range of the N-type doping is 1e 14 .cm -3 -1e 20 .cm -3 , the doping concentration range of P-type doping is 1e 15 .cm -3 -1e 20 .cm -3 , the relevant parameter settings are related to the electrical design of the device; In this embodiment, the thickness of the epitaxial wafer 1 is 350 um, the thickness of the second heavily doped substrate region 16 is 330 um, and the doping concentration is 1e 19 .cm -3 The second lightly doped voltage-resistant region 17 has a thickness of 20 um and a doping concentration of 1e 16 .cm -3 The first heavily doped body region 2 has a thickness of 2um, a width of 5um, a spacing of 3um, and a doping concentration of 3e 18.cm -3 The second heavily doped source region 3 has a thickness of 1um, a width of 2um, an interval width of 1um, and a doping concentration of 1e 19. cm -3 ; The first heavily doped channel region 4 has a thickness of 1um, a width of 1um, and a doping concentration of 1e 18. cm -3 , a first heavily doped body region 2, a second heavily doped source region 3 and a first heavily doped channel region 4 are prepared using an ion implantation process.

[0022] Step S200, preparing a gate dielectric 5 on the epitaxial wafer 1, and preparing polysilicon 6 on the gate dielectric 5 above the first heavily doped channel region 4, such as Figure 5 As shown; Step S210, preparing a gate dielectric 5 on the epitaxial wafer 1 using a thermal oxidation technique; Step S220, using a mask to protect the outer region of the first heavily doped channel region 4 through a photolithography process, and preparing polysilicon 6 on the gate dielectric 5 above the first heavily doped channel region 4 through chemical vapor deposition; Accordingly, the gate dielectric 5 is made of SiO 2 , the thickness is set to 40-500nm, and the thickness of polysilicon 6 is set to 100nm-5um; In this embodiment, 80nm SiO 2 As the gate dielectric 5, 500 nm polysilicon 6 is prepared by chemical vapor deposition.

[0023] Step S300, depositing a first isolation layer 7 on the epitaxial wafer, opening a window to prepare a source metal 9, the source metal 9 is in contact with the first heavily doped body region 2 and the second heavily doped source region 3, refer to Figure 6 , 7 , as shown in 8; Step S310, preparing the first isolation layer 7 by chemical vapor deposition, using a mask to protect the outer area of ​​the source metal 9 by photolithography, and using an etching process to open a window; Step S320, using a stripping process or an etching process to prepare a source metal 9 at the opening, the source metal 9 is in contact with the first heavily doped body region 2 and the second heavily doped source region 3; Accordingly, the first isolation layer 7 plays a protective role and is made of SiO 2 Or Si 3 N 4 , the thickness is set to 10-5000nm, and the ICP dry etching is used to open the window. The source window 8 extends downward from the top surface of the first isolation layer 7 to the inside of the first heavily doped body region 2. The source metal 9 contacts the first heavily doped body region 2 and the second heavily doped source region 3 to form an ohmic contact. The relevant parameter settings are related to the device electrical design; In this embodiment, Si 3 N 4 As the first isolation layer 7, the thickness is set to 200nm, and the ICP dry etching is used to open the window. The source window 8 has a depth of 500nm. The stripping process is used to prepare a 500nm thick Ti / Al two-layer metal as the source metal 9.

[0024] Step S400, opening a window at the polysilicon 6, preparing a gate metal 11, the gate metal 11 is in contact with the polysilicon 6, refer to Fig. 9 , 10 As shown; Step S410, using a photolithography process, using a mask to protect the outer area of ​​the polysilicon 6 where the window is opened, and using an etching process to open a window in the polysilicon 6; Step S420 , using a stripping process or an etching process to prepare a gate metal 11 at the opening, the gate metal 11 is in contact with the polysilicon 6 .

[0025] Correspondingly, the window depth is greater than the thickness of the first isolation layer 7, and the gate metal 11 extends downward from the top surface of the first isolation layer 7 into the polysilicon 6, contacts the polysilicon 6 and forms an ohmic contact; In this embodiment, a window is opened by an ICP dry etching process, the window depth is 500 nm, and a 500 nm thick Ti / Al two-layer metal is prepared using a lift-off process as the gate metal 11, which contacts the polysilicon 6 to form an ohmic contact.

[0026] Step S500, thinning the epitaxial wafer, preparing a first heavily doped emitter region 12 on the back of the epitaxial wafer, and preparing a first drain electrode 13 on the surface of the first heavily doped emitter region 12, referring to Fig.11 As shown; Step S510, thinning the back of the epitaxial wafer by a thinning process, using a photolithography process and a mask to protect the outer area of ​​the first heavily doped emitter region 12; forming an interval of the first heavily doped emitter region 12 by a diffusion process or an ion implantation process; Step S520, preparing a first drain electrode 13 on the surface of the first heavily doped emitter region 12 by a stripping process or an etching process; Accordingly, the epitaxial wafer is thinned to a corresponding thickness through a thinning process, the thickness of the first heavily doped emitter region 12 is 1-50 um, the first drain 13 contacts the first heavily doped emitter region 12 and forms an ohmic contact, and its width is smaller than the width of the first heavily doped emitter region 12; In this embodiment, the 350um thick epitaxial wafer 1 is thinned to 180um using a thinning process. The first heavily doped emitter region 12 has a thickness of 5um, a width of 2um, and a doping concentration of 1e 19. cm -3The first heavily doped emitter region 12 is prepared by an ion implantation process, the width of the first drain electrode 13 is 1.8 um, and a 1 um thick Ti / Al is prepared by a lift-off process as the first drain electrode 13 .

[0027] Step S600, depositing a second isolation layer 14 on the back of the epitaxial wafer 1, opening a window at the interval between the first heavily doped emitter region 12, and preparing a second drain electrode 15 at the window, referring to Fig.12 , 13 , as shown in 14; Step S610, preparing a second isolation layer 14 on the back of the epitaxial wafer 1 by chemical vapor deposition, protecting the outer area of ​​the first heavily doped emitter region 12 spacing area by using a mask through a photolithography process, and opening a window in the first heavily doped emitter region 12 spacing area through an etching process; Step S620, preparing the second drain 15 at the window of the spacing area of ​​the first heavily doped emitter region 12 by a stripping process or an etching process, and the second drain 15 and the second heavily doped substrate region 16 form an ohmic contact; Accordingly, the second isolation layer 14 plays a protective and isolating role and is made of SiO 2 Or Si 3 N 4 , the thickness is the same as the thickness of the first drain 13, and a window is opened at the interval area of ​​the first heavily doped emitter region 12 by ICP dry etching, the window width is smaller than the interval width of the first heavily doped emitter region 12, and the window depth is greater than the thickness of the second isolation layer 14. The second drain 15 extends upward from the lower surface of the second isolation layer 14 to fill the window in this step and form an ohmic contact with the second heavily doped substrate region 16. The relevant parameter settings are related to the electrical design of the device; In this embodiment, Si 3 N 4 The thickness of the second isolation layer 14 is set to 1 um. ICP dry etching is used to open a window at the spacing area of ​​the first heavily doped emitter region 12. The window depth is 1.1 um. A stripping process is used to prepare 1.1 um thick Ti / Al at the window as the second drain 15 in this step.

[0028] Step S700, planarizing the back side of the epitaxial wafer 1, and the whole device is prepared. Fig.15 As shown; Accordingly, after the planarization process, there is no second isolation layer 14 below the first drain electrode 13, and the lower surfaces of the first drain electrode 13 and the second drain electrode 15 are level; In this embodiment, an ion etching process is used to perform a planarization process.

[0029] A planar gate IGBT with a freewheeling diode includes a second heavily doped substrate region 16, a second lightly doped withstand voltage region 17 and a gate dielectric 5 which are sequentially arranged from bottom to top; The second lightly doped voltage-resistant region 17 is provided with: The first heavily doped body regions 2 are provided with a plurality of spaced apart portions, extending downward from the top surface of the epitaxial wafer 1, respectively, and the bottom surfaces thereof are higher than the bottom surface of the second lightly doped voltage-resistant region 17; The second heavily doped source regions 3 are provided with a plurality of them, extending downward from the top surface of the epitaxial wafer 1, and symmetrically arranged inside the first heavily doped body region 2, and the bottom surface of the second heavily doped source region 3 is higher than the bottom surface of the first heavily doped body region 2; A plurality of first heavily doped channel regions 4 are provided, each extending downward from the top surface of the second heavily doped source region 3 and symmetrically arranged inside the second heavily doped source region 3, and the bottom surface of the first heavily doped channel region 4 is level with the bottom surface of the second heavily doped source region 3; The gate dielectric 5 is provided with: A plurality of polysilicon layers 6 are provided, each of which is located on the top surface of the gate dielectric 5 above the first heavily doped channel region 4; A first isolation layer 7, deposited on the top surface of the gate dielectric 5 between the top surface of the polysilicon 6 and the adjacent polysilicon 6; There are several source metals 9, which extend downward from the top surface of the first isolation layer 7, and the bottom surfaces are respectively connected to the first heavily doped body region 2 and the second heavily doped source region 3, and form ohmic contacts with the first heavily doped body region 2 and the second heavily doped source region 3; A plurality of gate metals 11 are provided, each extending downward from the top surface of the first isolation layer 7 to the inside of the polysilicon 6 to form an ohmic contact with the polysilicon 6; The second heavily doped substrate region 16 is provided with: A plurality of first heavily doped emitter regions 12 are provided, each extending upward from the bottom surface of the epitaxial wafer 1 at intervals, and the upper surface of the first heavily doped emitter region 12 is located below the upper surface of the second heavily doped substrate region 16; A plurality of first drain electrodes 13 are provided, each extending downward from the lower surface of the first heavily doped emitter region 12 , and the width of the first drain electrode 13 is smaller than the width of the first heavily doped emitter region 12 ; A plurality of second isolation layers 14 are provided and are respectively deposited on the bottom surface of the second heavily doped substrate region 16 and the bottom surface of the first heavily doped emitter region 12; There are a plurality of second drain electrodes 15 , each of which is disposed on the bottom surface of the second heavily doped substrate region 16 and connected to the second isolation layer 14 at its side.

[0030] The epitaxial wafer 1 in the present case can be made of various commonly used epitaxial materials for semiconductor devices such as Si, SiC, GaN, etc., including a second heavily doped substrate region 16 and a second lightly doped voltage-resistant region 17 connected from bottom to top; the first doped region and the second doped region have opposite doping types, which can be a P region and an N region or an N region and a P region.

[0031] In view of the problem that a planar gate IGBT needs to be connected in parallel with a diode as a freewheeling diode in practical applications, the present invention provides a planar gate IGBT with a freewheeling diode and a preparation method thereof. By isolating the metal electrodes of the first heavily doped emitter region 12 and the second heavily doped substrate region 16 on the back side of the epitaxial wafer 1, the forward conductive channel of the planar gate IGBT and the freewheeling conductive channel of the freewheeling diode are separated. The IGBT forward conductive channel can only enter the epitaxial layer through the first heavily doped emitter region 12, which does not affect the number of hole carriers injected into the first heavily doped emitter region 12. The freewheeling conductive channel of the freewheeling diode enters the second heavily doped substrate region 16 through the epitaxial layer, and does not enter the first heavily doped emitter region 12 to cause other electrical effects. Compared with a normal planar gate IGBT device, the forward current carrying capacity is not affected, and the process steps are simple, which is fully compatible with the current commercial planar gate IGBT preparation process.

[0032] Regarding the contents disclosed in this case, there are a few points that need to be explained: The drawings of the embodiments disclosed in this case only involve the structures involved in the embodiments disclosed in this case, and other structures can refer to the usual designs; In the absence of conflict, the embodiments and features of the embodiments disclosed in this case can be combined with each other to obtain new embodiments; The above are only specific implementation methods disclosed in this case, but the protection scope of the present disclosure is not limited thereto. The protection scope disclosed in this case should be based on the protection scope of the claims.

Claims

1. A method for preparing a planar gate IGBT with a freewheeling diode, characterized in that: The following steps are involved: Step S100, preparing a first heavily doped body region (2) at intervals in the epitaxial wafer (1), preparing a plurality of second heavily doped source regions (3) at intervals in the first heavily doped body region (2), and preparing a first heavily doped channel region (4) in the second heavily doped source regions (3); Step S200, preparing a gate dielectric (5) on the epitaxial wafer (1), and preparing polysilicon (6) on the gate dielectric (5) above the first heavily doped channel region (4); Step S300, depositing a first isolation layer (7) on the epitaxial wafer, opening a window to prepare a source metal (9), wherein the source metal (9) is in contact with the first heavily doped body region (2) and the second heavily doped source region (3); Step S400, opening a window at the polysilicon (6) to prepare a gate metal (11), wherein the gate metal (11) is in contact with the polysilicon (6); Step S500, thinning the epitaxial wafer, preparing a spaced first heavily doped emitter region (12) on the back of the epitaxial wafer, and preparing a first drain electrode (13) on the surface of the first heavily doped emitter region (12); Step S600, depositing a second isolation layer (14) on the back side of the epitaxial wafer (1), opening a window at the interval between the first heavily doped emitter region (12), and preparing a second drain electrode (15) at the window; Step S700, planarizing the back side of the epitaxial wafer (1), and the entire device is prepared.

2. The method for preparing a planar gate IGBT with a freewheeling diode according to claim 1, characterized in that: Step S100 includes: Step S110, using a photolithography process and a mask to protect the outer area of ​​the first heavily doped body region (2); forming a plurality of spaced first heavily doped body regions (2) by a diffusion process or an ion implantation process; Step S120, using a photolithography process and a mask to protect the outer area of ​​the second heavily doped source region (3); forming a plurality of second heavily doped source regions (3) arranged at intervals by a diffusion process or an ion implantation process; Step S130: using a photolithography process and a mask to protect the outer region of the first heavily doped channel region (4); and forming the first heavily doped channel region (4) through a diffusion process or an ion implantation process.

3. The method for preparing a planar gate IGBT with a freewheeling diode according to claim 1, characterized in that: Step S200 includes: Step S210, preparing a gate dielectric (5) on the epitaxial wafer (1) using a thermal oxidation technique; Step S220: Protect the outer region of the first heavily doped channel region (4) using a mask through a photolithography process, and prepare polysilicon (6) on the gate dielectric (5) above the first heavily doped channel region (4) through chemical vapor deposition.

4. The method for preparing a planar gate IGBT with a freewheeling diode according to claim 1, characterized in that: Step S300 includes: Step S310, preparing a first isolation layer (7) by chemical vapor deposition, using a photolithography process to protect the outer region of the source metal (9) using a mask, and using an etching process to open a window; Step S320: using a stripping process or an etching process to prepare a source metal (9) at the opening, the source metal (9) being in contact with the first heavily doped body region (2) and the second heavily doped source region (3).

5. The method for preparing a planar gate IGBT with a freewheeling diode according to claim 1, characterized in that: Step S400 includes: Step S410, using a photolithography process and a mask to protect the outer area of ​​the polysilicon (6) where the window is opened, and using an etching process to open a window in the polysilicon (6); Step S420: using a stripping process or an etching process to prepare a gate metal (11) at the opening, the gate metal (11) being in contact with the polysilicon (6).

6. The method for preparing a planar gate IGBT with a freewheeling diode according to claim 1, characterized in that: Step S500 includes: Step S510, thinning the back of the epitaxial wafer by a thinning process, using a photolithography process and a mask to protect the outer area of ​​the first heavily doped emitter region (12); forming a spaced first heavily doped emitter region (12) by a diffusion process or an ion implantation process; Step S520: preparing a first drain electrode (13) on the surface of the first heavily doped emitter region (12) by a stripping process or an etching process.

7. The method for preparing a planar gate IGBT with a freewheeling diode according to claim 1, characterized in that: Step S600 includes: Step S610, preparing a second isolation layer (14) on the back side of the epitaxial wafer (1) by chemical vapor deposition, protecting the outer region of the first heavily doped emitter region (12) spacing region by using a mask through a photolithography process, and opening a window in the first heavily doped emitter region (12) spacing region through an etching process; Step S620, preparing a second drain electrode (15) at a window in the spacing region of the first heavily doped emitter region (12) by a stripping process or an etching process, and forming an ohmic contact between the second drain electrode (15) and the second heavily doped substrate region (16).

8. A planar gate IGBT with a freewheeling diode, prepared by the method for preparing a planar gate IGBT with a freewheeling diode according to claim 1, characterized in that: It comprises a second heavily doped substrate region (16), a second lightly doped voltage-resistant region (17) and a gate dielectric (5) which are arranged in sequence from bottom to top; The second lightly doped voltage-resistant region (17) is provided with: A plurality of first heavily doped body regions (2) are provided and spaced apart, each extending downward from the top surface of the epitaxial wafer (1); A plurality of second heavily doped source regions (3) are provided, each extending downward from the top surface of the epitaxial wafer (1) and symmetrically arranged inside the first heavily doped body region (2); A plurality of first heavily doped channel regions (4) are provided, each extending downward from the top surface of the second heavily doped source region (3) and symmetrically arranged inside the second heavily doped source region (3); The gate dielectric (5) is provided with: The polysilicon (6) is provided with a plurality of gate dielectrics (5) respectively located on the top surface of the first heavily doped channel region (4); A first isolation layer (7) deposited on the top surface of the gate dielectric (5) between the top surface of the polysilicon (6) and the adjacent polysilicon (6); A plurality of source metals (9) are provided, each extending downward from the top surface of the first isolation layer (7), and each having a bottom surface connected to the first heavily doped body region (2) and the second heavily doped source region (3); A plurality of gate metals (11) are provided, each extending downward from the top surface of the first isolation layer (7) into the polysilicon (6) to form an ohmic contact with the polysilicon (6); The second heavily doped substrate region (16) is provided with: A plurality of first heavily doped emission regions (12) are provided, extending upward from the bottom surface of the epitaxial wafer (1) at intervals; A plurality of first drain electrodes (13) are provided, each extending downward from the lower surface of the first heavily doped emitter region (12); A second isolation layer (14) is provided, and is deposited on the bottom surface of the second heavily doped substrate region (16) and the bottom surface of the first heavily doped emitter region (12) respectively; A plurality of second drain electrodes (15) are provided, each of which is arranged on the bottom surface of the second heavily doped substrate region (16) and has a side portion connected to the second isolation layer (14).

9. A planar gate IGBT with a freewheeling diode according to claim 8, characterized in that: The cross-sectional width of the first drain (13) is smaller than the cross-sectional width of the first heavily doped emitter region (12).

10. The planar gate IGBT with a freewheeling diode according to claim 8, characterized in that: The distance between adjacent first heavily doped emission regions (12) is greater than the cross-sectional width of the second drain (15).

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