Silicon carbide MOSFET device for improving reliability of trench gate vertex angle gate oxide and preparation method

Abstract

The invention relates to the technical field of semiconductors, in particular to a silicon carbide MOSFET (Metal-Oxide-Semiconductor Field Effect Transistor) device for improving trench gate vertex angle gate oxide reliability and a preparation method. The key structure of the invention comprises three parts: an N-region outside a trench gate oxide layer comprises a bottom and a side wall, and the gate oxide layer is separated, so that the effect of an interface state on channel electron scattering is reduced, and the channel mobility is improved; according to two structures at the bottom of the trench, namely a layer of PP region and NN regions at two sides of a vertex angle, a PN junction is formed below the gate trench under reverse bias of the device, and the maximum field intensity in a gate oxide layer is transferred to the PN junction, so that the possibility that the gate oxide layer is broken down by an electric field is effectively eliminated, the reliability of the device is improved, and the reliability of the device is improved. And meanwhile, the highly doped NN region is used as a conductive region, so that the on resistance of a current path can be reduced.

Description

Technical Field

[0001] The present invention relates to the field of semiconductor technology, and in particular to a silicon carbide MOSFET device capable of improving gate oxygen reliability at a trench gate top angle and a preparation method thereof. Background Art

[0002] As the third-generation wide bandgap semiconductor material, silicon carbide has many advantages such as large bandgap width, high critical breakdown field strength, high thermal conductivity, fast carrier saturation drift velocity, and high thermal stability. Therefore, silicon carbide-based power devices are widely used in high-power and high-end application fields such as high temperature, high pressure, and high frequency.

[0003] MOSFET is one of the basic components of integrated circuit power devices. Silicon carbide MOSFET has lower loss and higher voltage resistance than traditional silicon-based MOSFET. Silicon carbide MOSFET is divided into planar gate and trench gate MOSFET according to the technical route. The biggest difference between trench gate silicon carbide MOSFET and planar gate silicon carbide MOSFET is that the conductive channel adopts trench gate, which increases the contact area, reduces the size of the device, significantly improves the power density, and improves the ability of the gate to control the channel current. However, the disadvantage is that the gate of the trench gate silicon carbide MOSFET is subjected to a higher field strength, especially the electric field concentration at the two top corners at the bottom of the trench gate, which will cause the gate oxide layer at the top corners to be broken down prematurely, causing device failure. Therefore, how to improve the reliability of the trench gate oxide layer is a technical problem that needs to be solved urgently in this case. Summary of the invention

[0004] In view of the above problems, the present invention provides a silicon carbide MOSFET device and a preparation method which reduce the interface electric field at the gate oxide, avoid early breakdown failure, and improve the reliability of the device.

[0005] The technical solution of the present invention is: A method for preparing a silicon carbide MOSFET device with improved gate oxygen reliability at a trench gate top angle comprises the following steps: S100, forming an N-drift layer and an N-epitaxial layer in sequence on an N+ substrate; S200, forming a pair of NN regions on the N-epitaxial layer by etching; S300, forming a PP region between a pair of NN regions by ion implantation; S400, epitaxially growing on the N-drift layer to form an N-epitaxial layer covering the NN region and the PP region; S500, forming a trench region extending to the top surface of the PP region by trench etching on the N-epitaxial layer; S600, sequentially implanting a PW region and an N+ region on the N-epitaxial layer, and implanting a P+ region extending to the PW region on the N+ region; S700, sequentially forming an N-region, a gate oxide layer and a Poly layer used as a gate electrode lead in the trench region; S800, forming an isolation dielectric layer by depositing oxide on the N-epitaxial layer and the trench region to isolate the gate and source of the device; S900, forming an ohmic contact alloy layer on the side of the isolation dielectric layer, and forming a source metal layer on the top of the device by metal sputtering; finally forming a drain metal layer by metal sputtering and backside thinning process.

[0006] Specifically, in step S500, the concentration of the N-epitaxial layer is 5E15-1E16cm -2 .

[0007] Specifically, in step S200, a pair of NN regions are formed by epitaxial growth and etching processes, and the doping concentration is 5E16-5E17 cm -2 , with a thickness range of 0.5-1.5um to cover the bottom corner of the groove area.

[0008] Specifically, in step S300, the thickness of the PP region is 0.4-1 μm, and the doping concentration is 1E17-5E18 cm -2 .

[0009] Specifically, in step S300 , the bottom surface of the PP region and the bottom surface of the NN region are in the same plane.

[0010] Specifically, in step S600, ion implantation is performed in the N-epitaxial layer to form a PW region, and the doping concentration is 1E12-1E14cm -2 .

[0011] Specifically, in step S700, the doping concentration of the N-region is 1E14-6E14cm -2 .

[0012] Specifically, in step S700 , the depth of the N-region is greater than the depth of the trench gate oxide layer.

[0013] A silicon carbide MOSFET device for improving the reliability of gate oxide at the top angle of a trench gate comprises a drain metal layer, an N+ substrate layer, an N-drift layer, an N-epitaxial layer, a PW region, an N+ region, an ohmic contact alloy layer and a source metal layer arranged in sequence from bottom to top; The N-epitaxial layer is provided with: A pair of NN regions are provided and spaced apart in the N-epitaxial layer; The PP zone is arranged between a pair of the NN zones, and its bottom surface is in the same plane as the bottom surface of the NN zone; A P+ region extending downward from the top surface of the N+ region into the PW region, with a gap between the P+ region and the bottom surface of the PW region; The N- region has a U-shaped cross section, extending downward from the top surface of the N+ region to the top surface of the PP region, and the side is connected to the NN region; The gate oxide layer has a U-shaped cross section and extends downward along the inner side wall of the N-region; A Poly layer, disposed in the gate oxide layer, with a top surface flush with the gate oxide layer and a top surface of the N-region respectively; An isolation dielectric layer is provided on the top surfaces of the N+ region, the N- region, the gate oxide layer and the Poly layer.

[0014] Specifically, the ohmic contact alloy layer is located on the side of the isolation dielectric layer, and the bottom surface is connected to the top surfaces of the N+ region and the P+ region respectively.

[0015] The key structure of the present invention includes three parts: the N-region outside the trench gate oxide layer includes the bottom and the sidewalls, which separates the gate oxide layer, thereby reducing the effect of the interface state on the channel electron scattering and improving the channel mobility; the two structures at the bottom of the trench, namely a PP region and the NN region on both sides of the top corner. When the device is under reverse bias, a PN junction is formed under the gate trench, and the maximum field strength in the gate oxide layer is transferred to the PN junction, effectively eliminating the possibility of the gate oxide layer being broken down by the electric field, thereby improving the reliability of the device. At the same time, the highly doped NN region as a conductive region can also reduce the on-resistance of the current path. BRIEF DESCRIPTION OF THE DRAWINGS

[0016] Figure 1 is a structural schematic diagram of step S100 of the present invention; Figure 2 is a structural schematic diagram of step S200 of the present invention; Figure 3 is a schematic structural diagram of step S300 of the present invention; Figure 4 is a structural schematic diagram of step S400 of the present invention; Figure 5 is a schematic structural diagram of step S500 of the present invention; Figure 6 is a schematic structural diagram of step S600 of the present invention; Figure 7 is a schematic structural diagram of step S700 of the present invention; Figure 8 is a structural schematic diagram of step S800 of the present invention; Fig. 9 is a structural schematic diagram of step S900 of the present invention; Fig.10 is a structural schematic diagram of step S1000 of the present invention; Fig.11 is a schematic diagram of the structure of step S1100 of the present invention; Fig.12is a schematic diagram of the structure of step S1200 of the present invention; Fig.13 is a schematic diagram of the structure of step S1300 of the present invention; Fig.14 is a schematic diagram of the structure of step S1400 of the present invention; Fig.15 is a schematic structural diagram of step S1500 of the present invention; Fig.16 is a schematic diagram of the structure of step S1600 of the present invention; In the figure, 1 is N+ substrate, 2 is N- drift region, 3 is NN region, 4 is PP region, 5 is N- epitaxial layer, 6 is trench region, 7 is PW region, 8 is N+ region, 9 is P+ region, 10 is N- region, 11 is gate oxide layer, 12 is Poly layer, 13 is isolation dielectric layer, 14 is ohmic contact alloy layer, 15 is source metal layer, and 16 is drain metal layer. DETAILED DESCRIPTION

[0017] The present invention is described in detail below in conjunction with specific practical cases. Examples of the embodiments are shown in the accompanying drawings, and the schematic implementation methods of the present invention and their descriptions are only used to explain the present invention and are not intended to limit the present invention.

[0018] S100, refer to Figure 1 As shown, an N-drift layer 2 is formed by epitaxial growth on an N+ substrate 1; S200, refer to Figure 2 As shown, an N-epitaxial layer is formed by epitaxial growth on the N-drift layer 2; S300, refer to Figure 3 As shown, a pair of NN regions 3 are formed on the N-epitaxial layer by etching; In step S300, a pair of NN regions 3 are formed by epitaxial growth and etching process, and the doping concentration is 5E16-5E17 cm -2 , with a thickness ranging from 0.5 to 1.5 um to cover the bottom corners of the trench area 6.

[0019] S400, refer to Figure 4 As shown, a PP region 4 located between a pair of NN regions 3 is formed on the N-drift layer 2 by Al ion implantation; In step S400, the thickness of PP region 4 is in the range of 0.4-1um, and the doping concentration is 1E17-5E18 cm -2 The bottom surface of the PP region 4 is flush with the bottom surface of the NN region 3 , wrapping the bottom of the trench region 6 to reduce electric field concentration.

[0020] S500, refer to Figure 5 As shown, an N-epitaxial layer 5 is formed by epitaxial growth on the N-drift layer 2; S600, refer to Figure 6 As shown, a trench region 6 is formed on the N-epitaxial layer 5 by trench etching; S700, reference Figure 7 As shown, a PW region 7 is formed on the N-epitaxial layer 5 by Al ion implantation; Step S700: Ion implantation is performed in the N-epitaxial layer 5 to form a PW region 7, with a doping concentration of 1E12-1E14 cm-2. S800, reference Figure 8 As shown, an N+ region 8 is formed on the N- epitaxial layer 5 by N ion implantation; S900, refer to Fig. 9 As shown, a P+ region 9 is formed on the top surface of the N+ region 8 by Al ion implantation; S1000, refer to Fig.10 As shown, an N-region 10 is formed in the trench region 6 by N ion implantation and etching; In step S1000, the doping concentration of N-region 10 is 1E14-6E14cm -2 The depth of the N-region 10 is greater than the depth of the trench gate oxide layer 11 , and the bottom of the trench region 6 is inside the PW region 7 , and is interconnected with the N+ region 8 and the P+ region 9 .

[0021] S1100, reference Fig.11 As shown, a gate oxide layer 11 is formed in the trench region 6 by high temperature deposition and oxidation growth; S1200, refer to Fig.12 As shown, a Poly layer 12 is formed in the trench region 6 by polysilicon deposition, which is used as a gate electrode lead; S1300, refer to Fig.13 As shown, an isolation dielectric layer 13 is formed by depositing oxide on the N-epitaxial layer 5 and the trench region 6 to isolate the gate and source of the device; S1400, reference Fig.14 As shown, a metal layer for ohmic contact is formed on the N-epitaxial layer 5 by a metal sputtering process. After sputtering, a high-temperature annealing is performed to improve lattice defects so that the front sputtered metal is alloyed with SiC to form an ohmic contact alloy layer 14; S1500, refer to Fig.15 As shown, a source metal layer 15 is formed on the isolation dielectric layer 13 and the ohmic contact alloy layer 14 by a metal sputtering process, and the bottom of the source metal layer 15 is respectively connected to the ohmic contact alloy layer 14 and the isolation dielectric layer 13, and is used as a source electrode lead; S1600, reference Fig.16 As shown, a drain metal layer 16 is formed under the N+ substrate 1 by metal sputtering and backside thinning process, and is led out through a drain electrode.

[0022] A silicon carbide MOSFET device for improving the reliability of trench gate top angle gate oxide comprises a drain metal layer 16, an N+ substrate layer 1, an N-drift layer 2, an N-epitaxial layer 5, a PW region 7, an N+ region 8, an ohmic contact alloy layer 14 and a source metal layer 15 arranged in sequence from bottom to top; The N-epitaxial layer 5 is provided with: A pair of NN regions 3 are provided, which are spaced apart and arranged in the N-epitaxial layer 5; The PP zone 4 is arranged between a pair of the NN zones 3, and the bottom surfaces of the PP zone 4 and the NN zone 3 are in the same plane; A P+ region 9 extends downward from the top surface of the N+ region 8 into the PW region 7 and has a gap with the bottom surface of the PW region 7; The N- region 10 has a U-shaped cross section, extending downward from the top surface of the N+ region 8 to the top surface of the PP region 4, and the side portion is connected to the NN region 3; The gate oxide layer 11 has a U-shaped cross section and extends downward along the inner side wall of the N-region 10; A Poly layer 12 is disposed in the gate oxide layer 11, and its top surface is flush with the gate oxide layer 11 and the top surface of the N-region 10 respectively; An isolation dielectric layer 13 is disposed on the top surfaces of the N+ region 8 , the N− region 10 , the gate oxide layer 11 and the Poly layer 12 .

[0023] The ohmic contact alloy layer 14 is located on the side of the isolation dielectric layer 13, and the bottom surface is connected to the top surfaces of the N+ region 8 and the P+ region 9 respectively.

[0024] In this embodiment, the top surface of the ohmic contact alloy layer 14 is located below the isolation dielectric layer 13 .

[0025] The bottom surface of the source metal layer 15 is connected to the ohmic contact alloy layer 14 and the isolation dielectric layer 13 respectively.

[0026] The present invention forms a PN junction with the electric field limiting structure of the PP region 4 at the bottom of the trench region 6 and the N-drift region 2. The depletion layer of the PN junction reduces the electric field strength applied to the oxide layer at the bottom of the gate trench to the level of a common planar structure, thereby avoiding the concentration of the gate electric field and improving the reliability of the device. The low-doped N-type SiC on the sidewalls of the gate trench effectively reduces the scattering effect of the SiC-SiO2 interface state on channel electrons, improves electron mobility, and reduces the on-resistance of the device; at the same time, the P+ electric field limiting structure in the bottom area of ​​the trench reduces the electric field strength applied to the gate trench oxide layer, and the two highly doped NN conductive areas at the top corners can also reduce the on-resistance of the current path.

[0027] Regarding the contents disclosed in this case, there are a few points that need to be explained: (1) The drawings of the embodiments disclosed in this case only involve the structures involved in the embodiments disclosed in this case. Other structures can refer to the general design; (2) In the absence of conflict, the embodiments and features of the embodiments disclosed in this case may be combined with each other to obtain new embodiments; The above are only specific implementation methods disclosed in this case, but the protection scope of the present disclosure is not limited thereto. The protection scope disclosed in this case should be based on the protection scope of the claims.

Claims

1. A method for preparing a silicon carbide MOSFET device with improved gate oxide reliability at a trench gate top angle, characterized in that: The following steps are involved: S100, forming an N-drift layer (2) and an N-epitaxial layer in sequence on an N+ substrate (1); S200, forming a pair of NN regions (3) on the N-epitaxial layer by etching; S300, forming a PP region (4) between a pair of NN regions (3) by ion implantation; S400, epitaxially growing on the N-drift layer (2) to form an N-epitaxial layer (5) covering the NN region (3) and the PP region (4); S500, forming a trench region (6) extending to the top surface of the PP region (4) on the N-epitaxial layer (5) by trench etching; S600, sequentially implanting a PW region (7) and an N+ region (8) on the N-epitaxial layer (5), and implanting a P+ region (9) extending to the PW region (7) on the N+ region (8); S700, sequentially forming an N-region (10), a gate oxide layer (11), and a Poly layer (12) used as a gate electrode lead in the trench region (6); S800, forming an isolation dielectric layer (13) by depositing oxide on the N-epitaxial layer (5) and the trench region (6) to isolate the gate and source of the device; S900, forming an ohmic contact alloy layer (14) on the side of the isolation dielectric layer (13), and forming a source metal layer (15) on the top of the device by metal sputtering; and finally forming a drain metal layer (16) by metal sputtering and backside thinning process.

2. The method for preparing a silicon carbide MOSFET device with improved gate oxygen reliability at a trench gate top angle according to claim 1, characterized in that: In step S200, a pair of NN regions (3) are formed by epitaxial growth and etching processes, with a thickness ranging from 0.5 to 1.5 um, so as to cover the bottom corners of the trench region (6).

3. The method for preparing a silicon carbide MOSFET device with improved gate oxygen reliability at a trench gate top angle according to claim 1, characterized in that: In step S300, the thickness of the PP region (4) is 0.4-1 um.

4. The method for preparing a silicon carbide MOSFET device with improved gate oxygen reliability at a trench gate top angle according to claim 1, characterized in that: In step S300, the bottom surface of the PP region (4) and the bottom surface of the NN region (3) are in the same plane.

5. The method for preparing a silicon carbide MOSFET device with improved gate oxygen reliability at a trench gate top angle according to claim 1, characterized in that: In step S600, ions are implanted into the N-epitaxial layer (5) to form a PW region (7).

6. The method for preparing a silicon carbide MOSFET device with improved gate oxygen reliability at a trench gate top angle according to claim 1, characterized in that: In step S700, the depth of the N-region (10) is greater than the depth of the trench gate oxide layer (11).

7. The method for preparing a silicon carbide MOSFET device with improved gate oxygen reliability at trench gate top angle according to claim 1, characterized in that: In step S500, the concentration of the N-epitaxial layer (5) is 5E15-1E16cm -2 .

8. The method for preparing a silicon carbide MOSFET device with improved gate oxygen reliability at a trench gate top angle according to claim 1, characterized in that: In step S700, the doping concentration of the N-region (10) is 1E14-6E14cm -2 .

9. A silicon carbide MOSFET device with improved gate oxide reliability at a trench gate top angle, prepared by the method for preparing a silicon carbide MOSFET device with improved gate oxide reliability at a trench gate top angle according to any one of claims 1 to 8, characterized in that: It comprises a drain metal layer (16), an N+ substrate layer (1), an N-drift layer (2), an N-epitaxial layer (5), a PW region (7), an N+ region (8), an ohmic contact alloy layer (14) and a source metal layer (15) which are arranged in sequence from bottom to top; The N-epitaxial layer (5) is provided with: A pair of NN regions (3) are provided and are spaced apart and arranged in the N-epitaxial layer (5); A PP zone (4) is arranged between a pair of the NN zones (3), and its bottom surface is in the same plane as the bottom surface of the NN zone (3); A P+ region (9) extending downward from the top surface of the N+ region (8) into the PW region (7), with a gap between the P+ region (9) and the bottom surface of the PW region (7); The N-region (10) has a U-shaped cross-section, extends downward from the top surface of the N+ region (8) to the top surface of the PP region (4), and is connected to the NN region (3) at its side; The gate oxide layer (11) has a U-shaped cross-section and extends downward along the inner side wall of the N-region (10); A Poly layer (12) is arranged in the gate oxide layer (11), and its top surface is flush with the gate oxide layer (11) and the top surface of the N-region (10); An isolation dielectric layer (13) is provided on the top surfaces of the N+ region (8), the N- region (10), the gate oxide layer (11) and the Poly layer (12).

10. The silicon carbide MOSFET device with improved gate oxygen reliability at trench gate top angle according to claim 9, characterized in that: The ohmic contact alloy layer (14) is located on the side of the isolation dielectric layer (13), and the bottom surface is connected to the top surfaces of the N+ region (8) and the P+ region (9) respectively.

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