A high-breakdown honeycomb-shaped quasi-vertical enhancement-mode GaN transistor and its fabrication method

Abstract

This invention discloses a high-breakdown honeycomb-shaped quasi-vertical enhancement-mode GaN transistor and its fabrication method, belonging to the field of semiconductor device technology. The aforementioned honeycomb-shaped quasi-vertical enhancement-mode GaN transistor includes an epitaxial substrate, a low-resistivity substrate, a drain contact electrode, a lightly doped channel layer, a gate field plate dielectric, a gate dielectric, a gate metal electrode, a gate-source isolation dielectric, a honeycomb channel structure, a heavily doped channel layer, an isolation passivation layer, and a source contact electrode. The honeycomb channel structure is a columnar three-dimensional structure with a hexagonal cross-section. Based on the honeycomb channel structure design, this invention not only achieves enhancement-mode characteristics based on the charge depletion structure of the columnar channel but also effectively mitigates the peak electric field at the terminal under high voltage, thereby obtaining a high-breakdown quasi-vertical enhancement-mode GaN transistor.

Description

Technical Field

[0001] This invention belongs to the field of semiconductor device technology, and particularly relates to a high-breakdown honeycomb-shaped quasi-vertical enhancement-mode GaN transistor and its fabrication method. Background Technology

[0002] Third-generation semiconductor GaN materials possess excellent properties such as wide bandgap, high breakdown field strength, high saturated electron drift velocity, and high-concentration heterojunction two-dimensional electron gas. They are the preferred structure for fabricating high-power, high-breakdown-voltage, and high-frequency power electronic devices, and have important application prospects in wireless communication, power systems, detection, and other fields.

[0003] Lateral power devices based on AlGaN / GaN heterostructures have achieved excellent performance over the past decade. On-silicon substrate voltage-controlled power devices have been introduced and applied. However, for high-voltage, high-current applications, quasi-vertical structures should be preferred due to their advantages: 1) their module cell area does not affect breakdown voltage; 2) the surface is far from high-electric-field regions, minimizing the trapping effect; 3) when the source and drain contacts are vertically positioned on opposite sides of the wafer, current extraction is easier, achieving high current levels; 4) due to the wider current and electric field distribution, they exhibit superior thermal performance. However, quasi-vertical devices still face some challenges. Common Fin-based structures heavily rely on electron beam direct writing equipment, significantly impacting production efficiency and increasing costs, thus limiting their application scenarios.

[0004] Therefore, developing a quasi-vertical enhancement-mode GaN transistor with high breakdown that can be efficiently realized based on step lithography is of great significance for practical applications. Summary of the Invention

[0005] Objectives of the invention: The first objective of the present invention is to provide a high-breakdown honeycomb-shaped quasi-vertical enhancement-mode GaN transistor, and the second objective of the present invention is to provide a method for fabricating the above-mentioned quasi-vertical enhancement-mode GaN transistor.

[0006] Technical Solution: The high-breakdown honeycomb quasi-vertical enhancement-mode GaN transistor of the present invention includes an epitaxial substrate, a low-resistivity substrate, a drain contact electrode, a lightly doped channel layer, a gate field plate dielectric, a gate dielectric, a gate metal electrode, a gate-source isolation dielectric, several honeycomb channel structures, a lightly doped channel layer, an isolation passivation layer, and a source contact electrode; wherein, the low-resistivity substrate is disposed on the epitaxial substrate, the drain contact electrode and the lightly doped channel layer are disposed on the low-resistivity substrate, the drain contact electrode is distributed at both ends of the lightly doped channel layer, and the honeycomb channel structure is disposed on the lightly doped... On the channel layer, the angled surface formed by the honeycomb channel structure and the low-doped channel layer consists of, from bottom to top, a gate field plate dielectric, a gate dielectric, a gate metal electrode, and a gate-source isolation dielectric. The gate dielectric and the gate metal electrode have the same height and are higher than the height of the gate field plate dielectric. The top of the gate-source isolation dielectric is filled with an isolation passivation layer, which is at the same level as the top of the honeycomb channel structure. The high-doped channel layer is disposed on the honeycomb channel structure, and the top of the high-doped channel layer and the isolation passivation layer is the source contact electrode. The honeycomb channel structure is a columnar three-dimensional structure with a hexagonal cross-section.

[0007] Further, the epitaxial substrate is any one of SiC, Si, sapphire, diamond, and GaN self-supporting substrates; the low-resistivity substrate is any one of SiC, Si, diamond, and GaN substrate materials, and the effective carrier concentration should be greater than 10. 18 The materials used for the low-doped channel layer and the honeycomb channel structure are n-type carriers with a concentration of less than 10. 17 The GaN material; the highly doped channel layer has an n-type carrier concentration greater than 10. 18 GaN materials.

[0008] Furthermore, the gate dielectric is a combination of single-layer or multi-layer stacked structures of HfO2, ZrO2, Si3N4, SiO2, Al2O3, and AlNO, with a total thickness of 5-20 nm.

[0009] Furthermore, the gate metal electrode is a high work function metal, located on the upper part of the gate dielectric and surrounding the honeycomb channel structure; the high work function metal is one of W, Ni, Pt, and TiN.

[0010] Furthermore, the source contact electrode and the drain contact electrode are ohmic contacts formed by annealing low work function metals.

[0011] Furthermore, the low work function metal is one of Ti-Al alloy, Ti-Al-Ti-Au alloy, Ti-Al-Ni-Au alloy, and Ti-Al-Mo-Au alloy.

[0012] Furthermore, the gate plate dielectric is one or more of SiO2, Si3N4, and Al2O3 dielectrics with a thickness of 200-400 nm.

[0013] Furthermore, the isolation passivation layer is one or more of SiO2, Si3N4, and Al2O3 media.

[0014] The fabrication method of the above-mentioned quasi-vertical enhancement-mode GaN transistor includes the following steps:

[0015] 1) A low-resistivity substrate, a lightly doped channel layer, a honeycomb channel structure layer, and a heavily doped channel layer are sequentially fabricated on top of an epitaxial substrate using an epitaxial growth method.

[0016] 2) Define a mask layer in the highly doped channel layer, and then form the main mesa by etching.

[0017] 3) Patterning is performed on the formed main platform to generate an etching mask layer, and a honeycomb channel structure is obtained through etching (9);

[0018] 4) Deposit and etch the gate field plate dielectric on the honeycomb channel structure and the low-doped channel layer;

[0019] 5) A gate dielectric and a gate metal electrode layer are deposited on the gate field plate dielectric and formed by etching to form a gate control structure;

[0020] 6) Grow a gate-source isolation dielectric and an isolation passivation layer on the formed gate control structure, and expose the honeycomb channel structure and the top of the highly doped channel layer by etching.

[0021] 7) Define a mask for the source and drain contacts above the isolation passivation layer and the low-resistivity substrate, deposit a low work function metal by evaporation or sputtering, and form the source and drain contacts by a stripping annealing process to obtain a high-breakdown honeycomb quasi-vertical enhancement-mode GaN transistor.

[0022] Further, in step 1), the epitaxial growth method includes metal-organic chemical vapor deposition (MOCVD), molecular beam epitaxy (MBE), and hydride vapor phase epitaxy (HVPE).

[0023] Furthermore, in step 2), the mask is fabricated using optical lithography or electron beam direct writing.

[0024] Furthermore, in step 3), the etching method includes dry etching and wet etching.

[0025] Furthermore, in steps 4) and 5), the growth methods of the gate field plate dielectric, the gate source isolation dielectric, and the isolation passivation layer include low-pressure chemical vapor deposition (LPCVD), plasma-enhanced chemical vapor deposition (PECVD), and atomic layer deposition (ALD).

[0026] Invention Principle: In this invention, the honeycomb-shaped quasi-vertical enhancement-mode GaN transistor includes an epitaxial substrate, a low-resistivity substrate, a lightly doped channel layer, a heavily doped channel layer, an insulating dielectric, contact electrodes, and a passivation layer. The source and drain electrodes are ohmic contacts formed by depositing low work function metals on the heavily doped channel layer and the low-resistivity substrate and then annealing. The gate electrode is a voltage-controlled structure composed of metal and a gate dielectric. The honeycomb-shaped quasi-vertical structure can fully utilize the large-area depletion gate formed by its interaction to achieve the fabrication of highly efficient enhancement-mode devices that are independent of direct-write operations on electronic books. Using this structure simplifies epitaxial layer design, thereby reducing wafer and manufacturing costs.

[0027] Beneficial effects: Compared with the prior art, the present invention has the following significant effects: (1) Conventional quasi-vertical enhancement-mode GaN transistors use a top Fin strip structure. The fabrication of this structure requires direct electron beam writing to achieve a sufficiently thin structure for sidewall depletion, thereby realizing enhancement mode. Its complex process and the high cost and low efficiency of direct electron beam writing make it difficult to apply in the process production environment. The honeycomb structure of the present invention uses a hexagonal columnar structure similar to a honeycomb. The sidewall depletion of this structure is more efficient, so it can be completed by stepper lithography machine, which has the huge advantages of high efficiency and low cost, and solves the key technical problem of quasi-vertical devices in practical applications; (2) Compared with the traditional Fin strip structure, the honeycomb columnar structure used in the present invention can reduce the electric field concentration effect at the bottom of the column under high voltage through more electric field terminal dispersion points at the bottom, thereby achieving a higher breakdown voltage and a smaller leakage current than the traditional structure; (3) The epitaxial structure used in the present invention is simpler and easier to obtain than the aperture-type vertical GaN crystal structure that requires P-type or I-type GaN layers, which also greatly reduces the cost of substrate materials required for this process. Attached Figure Description

[0028] Figure 1 The diagram shows a honeycomb-shaped quasi-vertical enhancement-mode GaN transistor. (a) is a cross-sectional view, and (b) is a top view of the honeycomb channel structure.

[0029] Figure 2 This is a schematic diagram of the fabrication process for a high-breakdown, honeycomb-shaped quasi-vertical enhancement-mode GaN transistor. Detailed Implementation

[0030] The present invention will now be described in further detail with reference to the embodiments and accompanying drawings.

[0031] Example 1: As Figure 1 As shown, the high-breakdown honeycomb quasi-vertical enhancement-mode GaN transistor provided in this embodiment includes an epitaxial substrate 1, a low-resistivity substrate 2, a drain contact electrode 3, a lightly doped channel layer 4, a gate field plate dielectric 5, a gate dielectric 6, a gate metal electrode 7, a gate-source isolation dielectric 8, a honeycomb channel structure 9, a lightly doped channel layer 10, an isolation passivation layer 11, and a source contact electrode 12; wherein, the low-resistivity substrate 2 is disposed on the epitaxial substrate 1, the drain contact electrode 3 and the lightly doped channel layer 4 are disposed on the low-resistivity substrate 2, the drain contact electrode 3 is distributed at both ends of the lightly doped channel layer 4, and the honeycomb channel structure 9 is disposed in the lightly doped channel layer 4. On layer 4, the angled surface formed by the honeycomb channel structure 9 and the low-doped channel layer 4 consists of, from bottom to top, a gate field plate dielectric 5, a gate dielectric 6, a gate metal electrode 7, and a gate-source isolation dielectric 8. The gate dielectric 6 and the gate metal electrode 7 have the same height and are higher than the height of the gate field plate dielectric 5. The top of the gate-source isolation dielectric 8 is filled with an isolation passivation layer 11, and it is at the same level as the top of the honeycomb channel structure 9. The high-doped channel layer 10 is disposed on the honeycomb channel structure 9. The top of the high-doped channel layer 10 and the isolation passivation layer 11 is the source contact electrode 12. The honeycomb channel structure 9 is a columnar three-dimensional structure with a hexagonal cross-section.

[0032] like Figure 2 As shown, the fabrication method of the honeycomb-shaped quasi-vertical enhancement-mode GaN transistor includes the following specific steps:

[0033] 1) such as Figure 2 As shown in (a), a low-resistivity substrate 2, a lightly doped channel layer 4, a honeycomb channel structure layer, and a heavily doped channel layer 10 are sequentially grown on top of an epitaxial substrate 1 using an epitaxial growth method. The epitaxial substrate 1 is any one of SiC, Si, sapphire, diamond, and GaN self-supporting substrates; the low-resistivity substrate 2 is any one of SiC, Si, diamond, and GaN substrate materials, and the effective carrier concentration should be greater than 10. 18 The materials used for the low-doped channel layer 4 and the honeycomb channel structure layer are n-type carriers with a concentration of less than 10. 17 GaN material; highly doped channel layer 10 with n-type carrier concentration greater than 10 18 GaN materials;

[0034] 2) such as Figure 2 As shown in (a), a mask layer is defined in the highly doped channel layer 10, and then the main mesa is formed by etching.

[0035] 3) such as Figure 2 As shown in (b), patterning is performed on the formed main platform to generate an etching mask layer. After etching, a honeycomb channel structure 9 is obtained, as shown in Figure 9. Figure 2 As shown in (c);

[0036] 4) such as Figure 2 As shown in (d), a gate field plate dielectric 5 is deposited and etched on the honeycomb channel structure 9 and the low-doped channel layer 4, wherein the gate field plate dielectric 5 is one or more of SiO2, Si3N4, and Al2O3 dielectrics with a thickness of 200-400nm obtained by different growth methods.

[0037] 5) such as Figure 2 As shown in (e), a gate dielectric 6 and a gate metal electrode 7 layer are deposited and etched on the gate field plate dielectric 5 to form a gate control structure. The gate dielectric 6 is a combination of single-layer or multi-layer stacked structures of HfO2, ZrO2, Si3N4, SiO2, Al2O3, and AlNO based on different growth technologies, with a total thickness of 5-20 nm. The high work function metal is one of W, Ni, Pt, and TiN as the gate metal electrode 7.

[0038] 6) such as Figure 2 As shown in (f), a gate source isolation medium 8 and an isolation passivation layer 11 are grown on the formed gate control structure, and the top of the honeycomb channel structure 9 and the highly doped channel layer 10 are exposed by etching. The isolation passivation layer 11 is one or more of SiO2, Si3N4 and Al2O3 media obtained by different growth methods.

[0039] 7) such as Figure 2 As shown in (g), a mask for the source contact electrode 12 and the drain contact electrode 3 is defined above the isolation passivation layer 11 and the low-resistivity substrate 2. A low work function metal is deposited by evaporation or sputtering, and the source contact electrode 12 and the drain contact electrode 3 are formed by a stripping annealing process. The low work function metal is one of Ti-Al alloy, Ti-Al-Ti-Au alloy, Ti-Al-Ni-Au alloy, and Ti-Al-Mo-Au alloy.

[0040] The present embodiment has now been described in detail with reference to the accompanying drawings. Based on the above description, those skilled in the art should have a clear understanding of the present invention, "A High-Breakthrough-Value Honeycomb Quasi-Vertical Enhancement-Type GaN Transistor and Its Fabrication Method." The fabrication method proposed in this invention achieves lower production costs while increasing the breakdown voltage of the device, thereby enabling the efficient and reliable manufacture of quasi-vertical enhancement-type GaN transistors with high breakdown voltage.

[0041] It should be noted that implementations not shown or described in the accompanying drawings or the main text of the specification are all forms known to those skilled in the art and are not described in detail. Furthermore, the definitions of the various elements and methods described above are not limited to the specific structures, shapes, or methods mentioned in the embodiments; those skilled in the art can easily modify or substitute them, for example, a GaN layer can be replaced with an AlGaN layer.

[0042] It should also be noted that this document provides examples of parameters containing specific values, but these parameters need not be exactly equal to the corresponding values, but can approximate the corresponding values ​​within acceptable error tolerances or design constraints. Directional terms mentioned in the embodiments, such as "up," "down," "front," "back," "left," and "right," are only for reference to the accompanying drawings and are not intended to limit the scope of protection of this invention. Furthermore, unless specifically described or steps must occur in sequence, the order of the above steps is not limited to those listed above and can be varied or rearranged according to the desired design. Moreover, the above embodiments can be used in combination with each other or with other embodiments based on design and reliability considerations; that is, technical features from different embodiments can be freely combined to form more embodiments.

[0043] The specific embodiments described above further illustrate the purpose, technical solution, and beneficial effects of the present invention. It should be understood that the above descriptions are merely specific embodiments of the present invention and are not intended to limit the present invention. Any modifications, equivalent substitutions, improvements, etc., made within the spirit and principles of the present invention should be included within the protection scope of the present invention.

Claims

1. A high-breakdown, honeycomb-shaped quasi-vertical enhancement-mode GaN transistor, characterized in that, The system includes an epitaxial substrate (1), a low-resistivity substrate (2), a drain contact electrode (3), a lightly doped channel layer (4), a gate field plate dielectric (5), a gate dielectric (6), a gate metal electrode (7), a gate-source isolation dielectric (8), a honeycomb channel structure (9), a heavily doped channel layer (10), an isolation passivation layer (11), and a source contact electrode (12). The low-resistivity substrate (2) is disposed on the epitaxial substrate (1), the drain contact electrode (3) and the lightly doped channel layer (4) are disposed on the low-resistivity substrate (2), the drain contact electrode (3) is distributed at both ends of the lightly doped channel layer (4), and the honeycomb channel structure (9) is disposed on the lightly doped channel layer (4). The honeycomb channel structure (9) and the lightly doped channel layer (4) form a [missing information - likely a typo, should be "together"]. The included surface consists of, from bottom to top, a gate field plate dielectric (5), a gate dielectric (6), a gate metal electrode (7), and a gate-source isolation dielectric (8). The gate dielectric (6) and the gate metal electrode (7) have the same height and are higher than the gate field plate dielectric (5). The top of the gate-source isolation dielectric (8) is filled with an isolation passivation layer (11), which is at the same level as the top of the honeycomb channel structure (9). The highly doped channel layer (10) is disposed on the honeycomb channel structure (9). The top of the highly doped channel layer (10) and the isolation passivation layer (11) is the source contact electrode (12). The honeycomb channel structure (9) is a columnar three-dimensional structure with a hexagonal cross-section. The fabrication method of the quasi-vertical enhancement-mode GaN transistor includes the following steps: 1) A low-resistivity substrate (2), a low-doped channel layer (4), a honeycomb channel structure layer and a high-doped channel layer (10) are sequentially prepared on top of an epitaxial substrate (1) using an epitaxial growth method. 2) Define a mask layer on the highly doped channel layer (10), and then form the main mesa by etching. 3) Patterning is performed on the formed main platform to generate an etching mask layer, and a honeycomb channel structure is obtained through etching (9). 4) A gate field plate dielectric (5) is deposited and etched on the honeycomb channel structure (9) and the low-doped channel layer (4). 5) A gate dielectric (6) and a gate metal electrode (7) layer are deposited on the gate field plate dielectric (5) and formed by etching to form a gate control structure; 6) A gate-source isolation dielectric (8) and an isolation passivation layer (11) are grown on the formed gate control structure, and the top of the honeycomb channel structure (9) and the highly doped channel layer (10) are exposed by etching; 7) Define a mask for the source contact electrode (12) and drain contact electrode (3) above the isolation passivation layer (11) and the low-resistivity substrate (2), deposit a low work function metal by evaporation or sputtering, and form the source contact electrode (12) and drain contact electrode (3) by a stripping annealing process to obtain a honeycomb-shaped quasi-vertical enhancement GaN transistor with high breakdown.

2. The quasi-vertical enhancement-mode GaN transistor according to claim 1, characterized in that, The epitaxial substrate (1) is any one of SiC, Si, sapphire, diamond, and GaN self-supporting substrates; the low-resistivity substrate (2) is any one of SiC, Si, diamond, and GaN substrate materials, and the effective carrier concentration should be greater than 10. 18 The materials of the low-doped channel layer (4) and the honeycomb channel structure (9) are n-type carriers with a concentration of less than 10. 17 The GaN material; the highly doped channel layer (10) has an n-type carrier concentration greater than 10. 18 GaN materials.

3. The quasi-vertical enhancement-mode GaN transistor according to claim 1, characterized in that, The gate dielectric (6) is a combination of single-layer or multi-layer stacked structures of HfO2, ZrO2, Si3N4, SiO2, Al2O3, and AlNO, with a total thickness of 5-20 nm.

4. The quasi-vertical enhancement-mode GaN transistor according to claim 1, characterized in that, The gate metal electrode (7) is a high work function metal, located on the upper part of the gate dielectric (6) and surrounding the honeycomb channel structure (9); the high work function metal is one of W, Ni, Pt and TiN.

5. The quasi-vertical enhancement-mode GaN transistor according to claim 1, characterized in that, The source contact electrode (12) and drain contact electrode (3) are ohmic contacts formed by annealing low work function metals.

6. The quasi-vertical enhancement-mode GaN transistor according to claim 5, characterized in that, The low work function metal is one of Ti-Al alloy, Ti-Al-Ti-Au alloy, Ti-Al-Ni-Au alloy, and Ti-Al-Mo-Au alloy.

7. The quasi-vertical enhancement-mode GaN transistor according to claim 1, characterized in that, The grid plate medium (5) is one or more of SiO2, Si3N4, and Al2O3 media with a thickness of 200-400nm.

8. The quasi-vertical enhancement-mode GaN transistor according to claim 1, characterized in that, The isolation passivation layer (11) is one or more of SiO2, Si3N4, and Al2O3 media.

9. The quasi-vertical enhancement-mode GaN transistor according to claim 1, characterized in that, In step 3), the etching method includes dry etching and wet etching.

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