Semiconductor device and preparation method thereof, power module, power conversion circuit, and vehicle

Abstract

The present application discloses a semiconductor device, a manufacturing method thereof, a power module, a power conversion circuit, and a vehicle, relating to the field of semiconductor technologies. The semiconductor device includes a semiconductor body, a channel layer, a gate structure, a source electrode, and a drain electrode. The channel layer is disposed on a first surface and is in electrical contact with a well region within the semiconductor body. The channel layer includes a two-dimensional semiconductor material, and the bandgap range of the material is 0.28 eV to 4.0 eV, and the electron mobility is greater than or equal to 100 cm<supgt;2< / supgt> / Vs. The gate structure is disposed on a side of the channel layer away from the semiconductor body. The source electrode is at least partially disposed on the first surface and is in electrical contact with the channel layer. The drain electrode is disposed on a second surface. In the present application, the channel layer is not restricted by lattice matching and does not require a high-temperature treatment process. The source electrode is directly in electrical contact with the channel layer to form an ohmic contact without forming a heavily doped region. The device has a high mobility and a simpler structure, which is beneficial to simplifying the production process, improving the device quality, and achieving the goal of cost reduction and efficiency improvement.

Description

Technical Field

[0001] This application belongs to the field of semiconductor technology, and particularly relates to a semiconductor device and a manufacturing method thereof, a power module, a power conversion circuit, and a vehicle. Background Art

[0002] As a typical third-generation wide-bandgap semiconductor material, silicon carbide has excellent properties such as a high critical breakdown electric field, a wide bandgap, a high thermal conductivity, and a high electron saturation drift velocity. However, it also has obvious disadvantages, namely, poor mobility. How to improve the mobility of semiconductor devices is a key research direction in this field. Summary of the Invention

[0003] Embodiments of this application provide a semiconductor device and a manufacturing method thereof, a power module, a power conversion circuit, and a vehicle, which are used to improve the mobility of semiconductor devices.

[0004] To achieve the above object, embodiments of this application provide the following technical solutions:

[0005] In a first aspect, a semiconductor device is provided. The semiconductor device includes a semiconductor body, a channel layer, a gate structure, a source electrode, and a drain electrode. Among them, the semiconductor body is set to a first conductivity type and includes opposite first and second surfaces. The semiconductor body further includes a well region set to a second conductivity type, and the well region is disposed on the first surface. The channel layer is disposed on the first surface and is in electrical contact with the well region. The channel layer includes a two-dimensional semiconductor material, and the bandgap range of the material is 0.28 eV to 4.0 eV, and the electron mobility is greater than or equal to 100 cm 2 / Vs. The gate structure is disposed on a side of the channel layer away from the semiconductor body. At least a part of the source electrode is disposed on the first surface and is in electrical contact with the channel layer. The drain electrode is disposed on the second surface.

[0006] In some embodiments, the material of the channel layer includes at least one of two-dimensional black phosphorus, two-dimensional indium arsenide, bismuth selenoxide, bismuth oxy-selenite, palladium diselenide, and indium selenide.

[0007] In some embodiments, a part of the source electrode is disposed on the first surface, and another part is disposed between the channel layer and the gate structure.

[0008] In some embodiments, the gate structure includes a first gate conductive layer and a second gate conductive layer stacked, and the second gate conductive layer is disposed on a side of the first gate conductive layer away from the semiconductor body. The material of the second gate conductive layer includes graphene.

[0009] In some embodiments, the material of the source electrode includes graphene, and / or the material of the drain electrode includes graphene.

[0010] In a second aspect, the present application also provides a method for manufacturing a semiconductor device, including the following steps S10 to S50:

[0011] Step S10: Form a well region in a semiconductor body. The semiconductor body is set to a first conductivity type and includes opposite first and second surfaces. The well region is set to a second conductivity type and is located on the first surface.

[0012] Step S20: Form a channel layer on the first surface. The channel layer is in electrical contact with the well region. The channel layer includes a two-dimensional semiconductor material, and the bandgap range of the material is 0.28 eV to 4.0 eV, and the electron mobility is greater than or equal to 100 cm 2 / Vs.

[0013] Step S30: Form a source electrode. At least a part of the source electrode is located on the first surface and is in electrical contact with the channel layer.

[0014] Step S40: Form a gate structure. The gate structure is located on a side of the channel layer away from the semiconductor body.

[0015] Step S50: Form a drain electrode on the second surface.

[0016] In some embodiments, forming the channel layer on the first surface includes: transferring the channel layer to the first surface by using a dry transfer process or a wet transfer process.

[0017] On the other hand, an embodiment of the present application also provides a power module. The power module includes a substrate and the semiconductor device as described in any of the above embodiments, and the substrate is used to carry the semiconductor device.

[0018] In still another aspect, an embodiment of the present application also provides a power conversion circuit. The power conversion circuit is used for one or more of current conversion, voltage conversion, and power factor correction. The power conversion circuit includes a circuit board and the semiconductor device as described in any of the above embodiments, and the semiconductor device is electrically connected to the circuit board.

[0019] In still another aspect, an embodiment of the present application also provides a vehicle. The vehicle includes a load and the power conversion circuit as described in the above embodiment. The power conversion circuit is used to convert alternating current to direct current, convert alternating current to alternating current, convert direct current to direct current, or convert direct current to alternating current and then input it to the load.

[0020] In the embodiments provided by the present application, the semiconductor device includes a semiconductor body, a channel layer, a gate structure, a source electrode, and a drain electrode. The channel layer directly uses a material with an electron mobility greater than or equal to 100 cm 2For the formation of the / Vs material, two-dimensional semiconductor materials are not restricted by lattice matching and do not require high-temperature treatment processes, thus ensuring device size stability, surface roughness, and device consistency. Moreover, the bandgap range of the material of the channel layer is 0.28 eV to 4.0 eV, having good breakdown voltage capabilities and thermal stability.

[0021] In the embodiments provided in the present application, the source electrode forms an ohmic contact directly with the channel layer without the need to form a heavily doped region, and the device structure is simpler, which is beneficial for optimizing the production process steps.

[0022] That is to say, the semiconductor device provided in the embodiments of the present application not only has a high mobility, but also has a simpler structure, which is beneficial for simplifying the production process, improving the device quality, and achieving the goal of cost reduction and efficiency increase.

[0023] In addition, for the preparation of this semiconductor device, the present application also provides a preparation method. This preparation method has a simple process and is easy to operate. It can be prepared using existing relatively mature processes, and the production process is less difficult. That is to say, the preparation method provided in the embodiments of the present application is more concise, the process steps are optimized, the preparation cost is lower, and it is beneficial for simply and efficiently preparing a semiconductor device with high mobility.

[0024] The above power module, power conversion circuit, and vehicle have the same structure and beneficial technical effects as the semiconductor device provided in some of the above embodiments, and will not be elaborated here. Description of the Drawings

[0025] The above and / or additional aspects and advantages of the present application will become apparent and be readily understood from the description of the embodiments in conjunction with the following drawings, where:

[0026] Figure 1 is a schematic structural diagram of a semiconductor device provided in an embodiment of the present application;

[0027] Figure 2 is a flowchart of a method for preparing a semiconductor device provided in an embodiment of the present application;

[0028] Figures 3 to 9 is a diagram of each step for preparing a semiconductor device provided in an embodiment of the present application;

[0029] Figure 10 is a schematic structural diagram of a power module provided in an embodiment of the present application;

[0030] Figure 11 is a schematic structural diagram of a power conversion circuit provided in an embodiment of the present application;

[0031] Figure 12 is a schematic structural diagram of a vehicle provided in an embodiment of the present application.

[0032] Among them, the reference numerals are as follows:

[0033] 10 - semiconductor device; 11 - semiconductor body; 12 - channel layer; 13 - gate structure 13; 14 - source electrode; 15 - drain electrode; P1 - first surface; P2 - second surface; 16 - well region; 17 - gate insulating layer; 131 - first gate conductive layer 131; 132 - second gate conductive layer; 200 - power module; 201 - substrate; 300 - power conversion circuit; 301 - circuit board; 400 - vehicle; 401 - load. Detailed implementation manners

[0034] Next, the technical solutions in some embodiments of the present application will be clearly and completely described in conjunction with the accompanying drawings. Apparently, the described embodiments are only a part of the embodiments of the present application, rather than all the embodiments. Based on the embodiments provided by the present application, all other embodiments obtained by those of ordinary skill in the art belong to the scope of protection of the present application.

[0035] Unless otherwise required by the context, throughout the specification and claims, the term "comprising" is interpreted in an open, inclusive sense, i.e., "including, but not limited to".

[0036] Hereinafter, the terms "first" and "second" are only used for descriptive purposes and cannot be construed as indicating or implying relative importance or implicitly specifying the quantity of the indicated technical features. Thus, the features defined with "first" and "second" may explicitly or implicitly include one or more of such features. In the description of the embodiments of the present application, unless otherwise stated, the meaning of "a plurality of" is two or more.

[0037] When describing some embodiments, the expression "connected" and its derivatives may be used. The term "connected" should be understood in a broad sense. For example, "connected" may be a fixed connection, a detachable connection, or integrated; it may be directly connected or indirectly connected through an intermediate medium. For example, when describing some embodiments, the term "connected" may be used to indicate that two or more components have direct physical contact or electrical contact with each other.

[0038] In addition, the use of "based on" means open and inclusive, because a process, step, calculation, or other action "based on" one or more of the stated conditions or values may in practice be based on additional conditions or values beyond the stated ones.

[0039] It should be understood that when a layer or element is referred to as being on another layer or substrate, it may be directly on the other layer or substrate, or there may be an intermediate layer between the layer or element and the other layer or substrate.

[0040] Exemplary embodiments are described herein with reference to cross-sectional views that are idealized exemplary drawings. In the drawings, the thickness of layers and the area of regions are enlarged for clarity. Thus, variations in the shape relative to the drawings due to, for example, manufacturing techniques and / or tolerances are contemplated. Accordingly, the exemplary embodiments should not be construed as limited to the shapes of the regions shown herein, but include shape deviations caused by, for example, manufacturing. Thus, the regions shown in the drawings are schematic in nature, and their shapes are not intended to represent the actual shape of the regions of the device and are not intended to limit the scope of the exemplary embodiments.

[0041] Examples of the embodiments are shown in the drawings, where like or similar reference numerals designate like or similar elements or elements having the same or similar functions throughout. The embodiments described below with reference to the drawings are exemplary only for explaining the present application and should not be construed as limiting the present application.

[0042] As mentioned in the background art, how to improve the mobility of semiconductor devices is a key research direction in the field.

[0043] Currently, to improve the device mobility, the industry mainly adopts boron doping annealing technology and the method of optimizing the trench structure. However, in the boron doping annealing technology, the high-temperature annealing temperature is usually 1700 °C, and the silicon carbide material will evaporate, thus affecting the dimensional stability and surface roughness of the device, and the annealing uniformity is difficult to control, which easily affects the device consistency. In addition, the method of optimizing the trench structure will make the device have a trench corner and a right (or obtuse) angle structure at the bottom, and this structure will intensify the local electric field, thereby making the oxide layer prone to breakdown.

[0044] To avoid the above problems, an embodiment of the present application provides a semiconductor device 10, as Figure 1 shown, Figure 1 is a schematic structural diagram of a semiconductor device provided by an embodiment of the present application.

[0045] The semiconductor device 10 includes a semiconductor body 11, a channel layer 12, a gate structure 13, a source 14, and a drain 15. Among them, the semiconductor body 11 is set to a first conduction type, including opposite first surface P1 and second surface P2, and the semiconductor body 11 further includes a well region 16 set to a second conduction type, and the well region 16 is disposed on the first surface P1. Exemplarily, the first conduction type may be an N-type conduction type, and the second conduction type may be a P-type conduction type.

[0046] The channel layer 12 is disposed on the first surface P1 and is in electrical contact with the well region 16. The channel layer 12 includes a two-dimensional semiconductor material, and the bandgap range of the material is 0.28 eV to 4.0 eV, such as 0.28 eV, 0.30 eV, 0.80 eV, 1.2 eV... 4.0 eV, etc. The electron mobility is greater than or equal to 100 cm 2 / Vs, such as 100 cm 2 / Vs, 130 cm 2 / Vs, 150 cm 2 / Vs, 200 cm 2 / Vs, etc. The gate structure 13 is disposed on the side of the channel layer 12 away from the semiconductor body 11. The source 14 is at least partially disposed on the first surface P1 and is in electrical contact with the channel layer 12. The drain 15 is disposed on the second surface P2.

[0047] According to relevant research, the boron doping annealing technology can increase the device mobility to about 100 cm 2 / Vs. In the embodiment of the present application, a material with an electron mobility greater than or equal to 100 cm 2 / Vs is directly used to form the channel layer 12. The two-dimensional semiconductor material of the channel layer 12 is not restricted by lattice matching and does not require a high-temperature treatment process, thereby ensuring device size stability, surface roughness, and device consistency. Moreover, the bandgap range of the material of the channel layer 12 is 0.28 eV to 4.0 eV, having good voltage resistance and thermal stability.

[0048] In addition, in the embodiment of the present application, the source 14 is directly in electrical contact with the channel layer 12 to form an ohmic contact, without the need to form a heavily doped region, and the device structure is simpler, which is beneficial to optimizing the production process steps.

[0049] That is, the semiconductor device 10 provided by the embodiment of the present application not only has a high mobility, but also has a simpler structure, which is beneficial to simplifying the production process, improving the device quality, and achieving the goal of cost reduction and efficiency increase.

[0050] Exemplarily, in some embodiments, the material of the channel layer 12 includes at least one of two-dimensional black phosphorus, two-dimensional indium arsenide, bismuth selenoxide, bismuth oxy selenite, palladium diselenide, and indium selenide.

[0051] The above materials are all two-dimensional semiconductor materials, all having high electron mobility, adjustable bandgap, and good electronic properties. For example, the bandgap of two-dimensional black phosphorus is about 1.7 eV, and the electron mobility is about 1000 cm 2 / Vs. The bandgap of two-dimensional indium arsenide (InAs) is about 1.59 eV, and the electron mobility is about 490 cm 2 / Vs. The bandgap of monolayer bismuth oxyselenide (Bi2O2Se) is approximately 0.8 eV, and the electron mobility is approximately 450 cm 2 / Vs. The bandgap of monolayer bismuth selenite (Bi2SeO5) is approximately 3.9 eV, and the electron mobility is approximately 300 cm 2 / Vs. The bandgap of monolayer palladium diselenide (PdSe2) is approximately 1.37 eV, and the electron mobility is approximately 130 cm 2 / Vs. The bandgap of monolayer indium selenide (InSe) is approximately 2.11 eV, and the electron mobility is approximately 1000 cm 2 / Vs.

[0052] Exemplarily, taking two-dimensional black phosphorus as an example, when the first conduction type of the semiconductor body 11 is the N-type conduction type and the second conduction type of the well region 16 is the P-type conduction type, the two-dimensional black phosphorus is P-type two-dimensional black phosphorus.

[0053] The two-dimensional black phosphorus semiconductor material layers are under the action of van der Waals forces, having advantages such as high mobility, ultra-thin nanoscale thickness, and not needing to consider lattice matching limitations, innovative integration, etc., being easy to process, being beneficial to be applied in the manufacturing process, and being able to improve the mobility of the semiconductor device 10.

[0054] The same applies to other materials, which will not be elaborated one by one here.

[0055] In some embodiments, as Figure 1 shown, a part of the source electrode 14 is disposed on the first surface P1, and another part is disposed between the channel layer 12 and the gate structure 13.

[0056] Exemplarily, as Figure 1 shown, the semiconductor device 10 further includes a gate insulating layer 17. A part of the source electrode 14 is disposed on the first surface P1 in electrical contact with the well region 16, and another part is disposed between the channel layer 12 and the gate structure 13 and is in electrical contact with the channel layer 12. Wherein, the gate insulating layer 17 is located between the source electrode 14 and the gate structure 13 for preventing the source electrode 14 and the gate structure 13 from short-circuiting.

[0057] The gate structure 13 is used to control the channel conduction state. When the device is conducting, the current flows from the source electrode 14 through the channel layer 12, the well region 16, and the JFET region (or the epitaxial layer in the semiconductor body 11) and finally reaches the drain electrode 15.

[0058] In some embodiments, as Figure 1 shown, the gate structure 13 includes a first gate conductive layer 131 and a second gate conductive layer 132 stacked. The second gate conductive layer 132 is disposed on the side of the first gate conductive layer 131 away from the semiconductor body 11, and the material of the second gate conductive layer 132 includes graphene.

[0059] Exemplarily, the material of the first gate conductive layer 131 includes polysilicon, and the material of the gate insulating layer 17 includes silicon dioxide. The contact surface defect between polysilicon and silicon dioxide is relatively small, which is beneficial to improving the device performance.

[0060] Graphene with atomic layer thickness is thin, light, and has high strength, and has good thermal conductivity and electrical conductivity. The material of the second gate conductive layer 132 includes graphene, making the semiconductor device 10 have good heat dissipation and easy integration.

[0061] In addition, the van der Waals force of graphene enables it to combine with any substrate without being restricted by lattice matching, which is beneficial to simplifying the manufacturing process. That is, a good electrical contact can be formed between the second gate conductive layer 132 and the first gate conductive layer 131, and the manufacturing process corresponding to the gate structure 13 is relatively simple.

[0062] In some embodiments, the material of the source electrode 14 includes graphene, and / or the material of the drain electrode 15 includes graphene.

[0063] Two-dimensional graphene materials have excellent mechanical properties, can reach the atomic layer thickness, and have good thermal conductivity and electrical conductivity. The van der Waals force of graphene enables it to combine with any substrate without being restricted by lattice matching. Based on this, using graphene materials to form the source electrode 14 and / or the drain electrode 15, the corresponding manufacturing process is relatively simple, and it is beneficial to improve the heat dissipation and high-temperature resistance characteristics of the semiconductor device 10.

[0064] Since the interaction between graphene and two-dimensional semiconductor materials is weak, it is beneficial to reduce the Fermi pinning effect and is beneficial to forming a good ohmic contact. The source electrode 14 is directly in electrical contact with the channel layer 12 to form an ohmic contact, and there is no need to form a heavily doped region. The device structure is simpler, which is beneficial to optimizing the production process steps and achieving the goal of cost reduction and efficiency improvement.

[0065] Exemplarily, in some embodiments, as Figure 1 shown, the material of the channel layer 12 of the semiconductor device 10 includes two-dimensional black phosphorus, the material of the first gate conductive layer 131 in the gate structure 13 includes polysilicon, the material of the second gate conductive layer 132 includes graphene, the material of the source electrode 14 includes graphene, and the material of the drain electrode 15 includes graphene. That is, graphene is used as the electrode of the semiconductor device 10, and two-dimensional black phosphorus is used as the transmission channel.

[0066] Graphene with atomic layer thickness is thin and light, and has high strength, good thermal conductivity and electrical conductivity, making the device have good heat dissipation and easy integration. Two-dimensional black phosphorus has excellent properties such as high mobility and interlayer van der Waals force. As a channel material, it is not restricted by lattice matching, has integration diversity, and is suitable for ultrafast response devices. At the same time, the interaction between graphene and two-dimensional black phosphorus materials is weak, which well reduces the Fermi pinning effect, forms a good ohmic contact with the two-dimensional semiconductor channel, and does not require an additional injection process to form a heavily doped region to achieve ohmic contact between metal and semiconductor, which is beneficial to optimizing the process steps and achieving the purpose of cost reduction and efficiency improvement.

[0067] Based on this, the semiconductor device 10 has the characteristics of high temperature resistance and high mobility, and has a simple structure, so the corresponding manufacturing process is simplified, that is, a semiconductor device with high mobility and high temperature resistance can be simply and efficiently manufactured at a lower cost.

[0068] In a second aspect, the present application also provides a method for manufacturing a semiconductor device, as Figure 2 shown, Figure 2 is a flowchart of the method for manufacturing a semiconductor device provided by an embodiment of the present application, Figures 3 to 9 is a diagram of each step for manufacturing a semiconductor device provided by an embodiment of the present application.

[0069] The manufacturing method includes the following steps S10 to step S50:

[0070] Step S10: As Figure 3 shown, a well region 16 is formed in the semiconductor body 11. The semiconductor body 11 is set to the first conductivity type, including opposite first surface P1 and second surface P2. The well region 16 is set to the second conductivity type, and the well region 16 is located on the first surface P1.

[0071] Exemplarily, a mask can be formed and patterned, and under the action of the mask, the semiconductor body 11 is ion-implanted to form the well region 16.

[0072] Step S20: As Figure 4 shown, a channel layer 12 is formed on the first surface P1. The channel layer 12 is in electrical contact with the well region 16. The channel layer 12 includes a two-dimensional semiconductor material, and the bandgap range of the material is 0.28 eV to 4.0 eV, and the electron mobility is greater than or equal to 100 cm 2 / Vs.

[0073] Exemplarily, in some embodiments, forming the channel layer 12 on the first surface P1 includes: transferring the channel layer 12 to the first surface P1 by a dry transfer process or a wet transfer process.

[0074] For example, in some embodiments, the material of the channel layer 12 includes at least one of two-dimensional black phosphorus, two-dimensional indium arsenide, bismuth selenoxide, bismuth oxy-selenite, palladium diselenide, indium selenide, etc. Taking two-dimensional black phosphorus as an example, since the van der Waals force acts between the two-dimensional black phosphorus layers, it can be transferred onto the semiconductor body 11 through a dry transfer process or a wet transfer process without going through a high-temperature treatment process, and without the steps of preparing and removing a mask, or ion implantation, etc. The preparation process is simple, which is beneficial to ensuring the device size stability, surface roughness, and device consistency.

[0075] Step S30: As Figure 5 shown, a source electrode 14 is formed, and at least a part of the source electrode 14 is located on the first surface P1 and is in electrical contact with the channel layer 12.

[0076] Exemplarily, as Figure 5 shown, a part of the source electrode 14 is disposed on the first surface P1, and the other part is disposed on the channel layer 12. The material of the source electrode 14 includes graphene.

[0077] In some embodiments, the source electrode 14 can be formed as an entire layer of graphene by chemical vapor deposition, and then patterned to obtain the required source electrode 14.

[0078] In some other embodiments, the graphene material of the source electrode 14 can be transferred onto the first surface P1 through a wet transfer process and be in electrical contact with the channel layer 12.

[0079] The van der Waals force of graphene enables it to combine with any substrate without being restricted by lattice matching. Therefore, only through the steps of the wet transfer process, the graphene electrode can be prepared without the steps of preparing and removing a mask and photolithography, etc. The preparation method is relatively simple.

[0080] Taking the material of the channel layer 12 including two-dimensional black phosphorus and the material of the source electrode 14 including graphene as an example, two-dimensional black phosphorus and graphene can directly form an ohmic contact without the steps of multiple ion implantations to form a heavily doped region in the related art. That is, in the embodiments of the present application, the source electrode 14 and the channel layer 12 can be directly in electrical contact to form an ohmic contact without multiple ion implantations, and the process steps are simplified.

[0081] Step S40: As Figures 6 to 8 shown, a gate structure 13 is formed, and the gate structure 13 is located on the side of the channel layer 12 away from the semiconductor body 11.

[0082] As Figure 6As shown, after forming the source electrode 14, the gate insulating layer 17 is first formed. On the one hand, the gate insulating layer 17 can provide a flat surface for the subsequent preparation of the gate structure 13. On the other hand, the gate insulating layer 17 can play a role in protection and isolation, preventing the gate structure 13 from being electrically connected to the source electrode 14 and causing a short circuit.

[0083] After that, as Figure 7 shown, the first gate conductive layer 131 is formed. The material of the first gate conductive layer 131 includes polysilicon.

[0084] Then, as Figure 8 shown, the second gate conductive layer 132 is formed. In some embodiments, the material of the second gate conductive layer 132 includes graphene. For example, through a wet transfer process, the graphene material is transferred to the side of the first gate conductive layer 131 away from the semiconductor body 11.

[0085] The first gate conductive layer 131 and the second gate conductive layer 132 stacked together form the gate structure 13.

[0086] Step S50: As Figure 9 shown, a drain electrode 15 is formed on the second surface P2.

[0087] In some embodiments, the material of the drain electrode 15 includes graphene. Exemplarily, through a wet transfer process, the graphene material is transferred onto the second surface P2, and thus the drain electrode 15 is formed.

[0088] So far, the semiconductor device 10 is fabricated.

[0089] The above fabrication method has a simple process, is easy to operate, can be fabricated using existing relatively mature processes, and has a low production process difficulty.

[0090] Two-dimensional semiconducting materials with high mobility such as two-dimensional black phosphorus have excellent properties. As a channel material, it is not restricted by lattice matching, has integration diversity, and is suitable for ultrafast response devices. In the embodiments of the present application, through a dry transfer process or a wet transfer process, two-dimensional semiconducting materials with high mobility such as two-dimensional black phosphorus are transferred onto the semiconductor body 11 to form the channel layer 12, so as to fabricate a semiconductor device 10 with high mobility. The process is simple and highly operable, without processes such as high-temperature annealing or ion doping, which is beneficial to improving the dimensional stability, surface roughness, and device consistency of the device. Moreover, without processes such as trench etching, it is beneficial to improve the electric field uniformity and avoid premature breakdown of the device.

[0091] In addition, graphene with atomic layer thickness is thin and light but has high strength, and has good thermal conductivity and electrical conductivity, enabling good heat dissipation and easy integration of devices. In the embodiments of the present application, by virtue of the property that graphene can be combined with any substrate and is not restricted by lattice matching, graphene materials are used to prepare the gate-source electrodes and drain electrodes, and only relevant electrodes can be prepared through the wet transfer process steps, without the need to prepare a mask or perform photolithography and other processes, and the preparation method is simpler.

[0092] The interaction between graphene and two-dimensional black phosphorus materials is weak, which well reduces the Fermi pinning effect and can form a good ohmic contact. That is, in the embodiments of the present application, there is no need for an additional injection process to form a heavily doped region to achieve an ohmic contact between a metal and a semiconductor material, optimizing the process steps and achieving the purpose of cost reduction and efficiency improvement.

[0093] That is, the preparation method provided by the embodiments of the present application is more concise, the process steps are optimized, the preparation cost is lower, which is conducive to simply and efficiently preparing a semiconductor device 10 with high mobility and high temperature resistance.

[0094] On the other hand, the embodiments of the present application also provide a power module. Figure 10 It is a schematic structural diagram of the power module provided by the embodiments of the present application.

[0095] As Figure 10 shown, the power module 200 includes a substrate 201 and the semiconductor device 10 in any of the above embodiments, and the substrate 201 is used to carry the semiconductor device 10.

[0096] Exemplarily, the power module 200 can be used as a power amplifier, a power converter, a power controller, a power management module, or a power regulator. The power amplifier is used to amplify the power of an electrical signal. The power converter is used to convert electrical energy from one form to another. For example, the power converter can be an AC / DC converter or a DC / DC converter. The power controller is a device used to control the power flow. The power management module is used to manage the power supply to ensure stable and efficient distribution of the power to different parts of an electronic device. The power regulator is used to regulate the power output to meet the requirements of a specific application.

[0097] On the other hand, the embodiments of the present application also provide a power conversion circuit. Figure 11 It is a schematic structural diagram of the power conversion circuit provided by the embodiments of the present application.

[0098] As Figure 11 shown, the power conversion circuit 300 includes a circuit board 301 and the semiconductor device 10 in any of the above embodiments. The semiconductor device 10 is electrically connected to the circuit board 301, and the power conversion circuit 300 can be used for current conversion, voltage conversion, or power factor correction.

[0099] Exemplarily, the power conversion circuit 300 can be used as one of an AC / DC converter, an AC / AC converter, a DC / DC converter, a DC / AC inverter, or a power factor correction (PFC) circuit. Among them, the AC / DC converter is used to convert alternating current into direct current, the AC / AC converter is used to convert alternating current into alternating current, the DC / DC converter is used to convert direct current into direct current, the DC / AC inverter is used to convert direct current into alternating current, and the power factor correction circuit is used to improve the power factor of the power supply and reduce the harmonic pollution of the power grid.

[0100] On the other hand, an embodiment of the present application also provides a vehicle. Figure 12 It is a schematic structural diagram of the vehicle provided by the embodiment of the present application.

[0101] As Figure 12 shown, the vehicle 400 includes a load 401 and the power conversion circuit 300 in the above embodiment. After the power conversion circuit 300 converts alternating current into direct current, converts alternating current into alternating current, converts direct current into direct current, or converts direct current into alternating current, it is input to the load 401 to supply power to the load 401.

[0102] As described above, it is only the specific implementation manner of the present application, but the protection scope of the present application is not limited thereto. Any person skilled in the art within the technical scope disclosed by the present application, thinking of changes or substitutions, should be covered within the protection scope of the present application. Therefore, the protection scope of the present application should be subject to the protection scope of the claims.

Claims

1. A semiconductor device, characterized in that, Comprising: A semiconductor body, which is set to a first conduction type and includes opposite first and second surfaces; the semiconductor body further includes a well region set to a second conduction type, and the well region is disposed on the first surface; A channel layer is disposed on the first surface and is in electrical contact with the well region; the channel layer includes a two-dimensional semiconductor material, and the bandgap range of the material is 0.28 eV to 4.0 eV, and the electron mobility is greater than or equal to 100 cm 2 / Vs; A gate structure, which is disposed on a side of the channel layer away from the semiconductor body; A source electrode, at least part of which is disposed on the first surface, and another part is disposed between the channel layer and the gate structure, and the source electrode is in electrical contact with the channel layer; A drain electrode, which is disposed on the second surface.

2. The semiconductor device according to claim 1, wherein The material of the channel layer includes at least one of two-dimensional black phosphorus, two-dimensional indium arsenide, bismuth selenoxide, bismuth oxy-selenite, palladium diselenide, and indium selenide.

3. The semiconductor device according to claim 1, wherein The gate structure includes a first gate conductive layer and a second gate conductive layer stacked, and the second gate conductive layer is disposed on a side of the first gate conductive layer away from the semiconductor body; The material of the second gate conductive layer includes graphene.

4. The semiconductor device according to any one of claims 1 to 3, characterized in that, The material of the source electrode includes graphene, and / or the material of the drain electrode includes graphene.

5. A method for manufacturing a semiconductor device, characterized in that, Comprising: Forming a well region in the semiconductor body, the semiconductor body being set to a first conduction type and including opposite first and second surfaces; the well region is set to a second conduction type and the well region is located on the first surface; A channel layer is formed on the first surface, and the channel layer is in electrical contact with the well region; the material of the channel layer includes a two-dimensional material, the bandgap range of the material of the channel layer is 0.28 eV to 4.0 eV, and the electron mobility is greater than or equal to 100 cm 2 / Vs; Forming a source electrode, at least part of the source electrode being located on the first surface, and another part being disposed between the channel layer and the gate structure, and the source electrode is in electrical contact with the channel layer; Forming a gate structure, the gate structure being located on a side of the channel layer away from the semiconductor body; Forming a drain electrode on the second surface.

6. The preparation method according to claim 5, characterized in that, Forming a channel layer on the first surface, including: Transferring the channel layer to the first surface by a dry transfer process or a wet transfer process.

7. A power module, characterized in that, Comprising: At least one semiconductor device as described in any one of claims 1 to 4; A substrate, which is used to carry the semiconductor device.

8. A power conversion circuit, characterized in that, The power conversion circuit is used for one or more of current conversion, voltage conversion, and power factor correction; The power conversion circuit includes a circuit board and at least one semiconductor device as described in any one of claims 1 to 4, and the semiconductor device is electrically connected to the circuit board.

9. A vehicle, characterized in that, Comprising: A load and the power conversion circuit as described in claim 8, and the power conversion circuit is used to convert alternating current to direct current, convert alternating current to alternating current, convert direct current to direct current, or convert direct current to alternating current and then input it to the load.

Images