Transistor device

Abstract

A transistor device is disclosed. A transistor device comprises a semiconductor body (100) and a plurality of transistor cells (1). Each transistor element comprises a drift region (11) of a first doping type and a source region (13); a body region (12) of a second doping type complementary to the first doping type; a field shaping region (31) of a second doping type connected to the source node (S); and a gate electrode (21) connected to the gate node (G). The gate electrode (21) is arranged in a trench (23) extending from the first surface (101) into the semiconductor body (100), the gate electrode (21) being dielectrically insulated from the body region (12) by a gate dielectric (22), at least part of the gate electrode (21) being dielectrically insulated from the drift region (11) by a field dielectric (32), the field shaping region (31) adjoining the trench (23), and the field dielectric (32) comprising a high-k dielectric.

Description

Technical Field

[0001] The present disclosure generally relates to a transistor device, and more particularly to a silicon carbide (SiC) based transistor device. Background Art

[0002] Silicon carbide (SiC) has a higher band gap than silicon (Si), so that SiC can withstand higher electric fields than silicon. Therefore, compared with a vertical transistor device based on silicon with a given voltage blocking capability, the length of the drift region can be reduced in a vertical transistor device based on SiC with the same voltage blocking capability. The reduced length of the drift region results in a lower on-resistance of the SiC device compared to the silicon device. The reduction in on-resistance (i.e., the resistance of the transistor device in the on state) results in lower conduction losses and is a continuing goal in the design of transistor devices.

[0003] A vertical SiC transistor device can be implemented with a trench gate electrode, which is a gate electrode arranged in a trench extending from the surface into the SiC semiconductor body. The trench gate electrode is dielectrically insulated from the semiconductor body by a gate dielectric.

[0004] High electric fields that may occur in SiC-based transistor devices may damage the gate dielectric. Conventional SiC-based transistor devices therefore include doped regions of a doping type that is complementary to the doping type of the drift region and that are connected to the source node (source electrode) of the transistor device. These doped regions are located below the gate trench and, together with the drift region, form a JFET that protects the gate dielectric from high electric fields in the blocking state of the transistor device.

[0005] Between the drift region and the JFET region, the device comprises a pn junction. Even in the on-state of the transistor device, this pn junction involves a space charge region (depletion region), which reduces the width of the conduction path of the transistor device in the on-state. Even if a fully shaped JFET region would be possible, this limits the minimum possible cell pitch.

[0006] Therefore, there is a need for an improved SiC based transistor device. Summary of the invention

[0007] One example relates to a transistor device. The transistor device includes a semiconductor body and a plurality of transistor cells. Each transistor cell includes: a drift region and a source region of a first doping type; a body region of a second doping type complementary to the first doping type; a field shaping region of the second doping type connected to a source node; and a gate electrode connected to the gate node. The gate electrode is arranged in a trench extending from a first surface into the semiconductor body and is dielectrically insulated from the body region by a gate dielectric. At least a portion of the gate electrode is dielectrically insulated from the drift region by a field dielectric. The field shaping region is adjacent to the trench. The field dielectric includes a high-k dielectric.

[0008] In a vertical direction of the semiconductor body, the field shaping region may extend deeper into the semiconductor body than the trench.

[0009] According to one example, the body region is connected to the source node, and the field shaping region is adjacent to the body region so as to be connected to the source node via the body region. According to another example, the body region is connected to the source node via a contact region, the contact region having a higher doping concentration than the rest of the body region, and the field shaping region is adjacent to the contact region so as to be connected to the source node via the contact region.

[0010] In each case, the field shaping region may include a plurality of first segments that are spaced apart from one another along the sidewalls of the trench and are each connected to the source node. In a vertical direction of the semiconductor body, the first segments extend further in the direction of the first surface than the drift region. The field shaping region may also include a second segment that is adjacent to the first segment and spaced apart from the body region.

[0011] According to one example, the field dielectric is symmetric with respect to a center plane of the trench. According to another example, the field dielectric is asymmetric with respect to a center plane of the trench.

[0012] A transistor device according to another example includes a semiconductor body and a plurality of transistor cells. Each transistor cell includes: a drift region and a source region of a first doping type; a body region of a second doping type complementary to the first doping type; and a gate electrode connected to a gate node. The gate electrode and the field electrode are arranged in a trench extending from the first surface into the semiconductor body, the field electrode is dielectrically insulated from the gate electrode in the trench, the gate electrode is dielectrically insulated from the body region by a gate dielectric, the field electrode is dielectrically insulated from the drift region by a field dielectric, and the field dielectric includes a high-k dielectric.

[0013] The transistor device may further comprise: a field shaping region of the second doping type connected to the source node. The field shaping region may adjoin the trench and may extend deeper into the semiconductor body than the trench in a vertical direction of the semiconductor body. The field electrode may be connected to the source node.

[0014] In each of the transistor arrangements, each transistor cell may further comprise a compensation region of the second doping type adjoining the drift region. The compensation region may adjoin the field shaping region.

[0015] Additionally, in each of the transistor devices, a maximum thickness of the gate dielectric may be less than a maximum thickness of the field dielectric.The gate dielectric may include silicon dioxide or a high-k dielectric.

[0016] Furthermore, in each of the transistor arrangements, the relative permittivity of the high-k dielectric is higher than 5, higher than 10, or higher than 20. In each case, the semiconductor body may be a SiC semiconductor body. BRIEF DESCRIPTION OF THE DRAWINGS

[0017] The following examples are explained with reference to the accompanying drawings. The accompanying drawings are used to illustrate certain principles, and only the aspects necessary for understanding these principles are illustrated. The accompanying drawings are not necessarily drawn to scale. In the accompanying drawings, the same reference numerals indicate similar features.

[0018] Figure 1 shows a vertical cross-sectional view of a transistor device having a plurality of transistor cells, each transistor cell including a field dielectric and a field shaping region according to one example;

[0019] Figure 2 Schematically illustrates when the transistor device is in a blocking state (off state) Figure 1 Equipotential lines of the electric field in a transistor arrangement of the type illustrated in FIG.

[0020] Figure 3A and 3B Shows different examples Figure 1 A horizontal cross-sectional view of a transistor device of the type illustrated in FIG.

[0021] Figure 4 shows a superjunction device implemented as Figure 1 A vertical cross-sectional view of a transistor device of the type illustrated in FIG.

[0022] Figure 5 Show according to Figure 1 A variation of a transistor device;

[0023] Fig. 6A and 6B Shows different examples Figure 5 A horizontal cross-sectional view of a transistor device of the type illustrated in FIG.

[0024] Figure 7-8 Show Figure 1 Further variations of transistor devices of the type illustrated in;

[0025] Fig. 9A and9B illustrates an example for connecting the source and body regions of a transistor cell to a source node of a transistor device;

[0026] Figures 10A-10C Another example for connecting the source region and the body region of a transistor cell to a source node is shown;

[0027] Fig.11 shows a vertical cross-sectional view of a transistor arrangement having a plurality of transistor cells, each transistor cell comprising a field electrode;

[0028] Fig.12 According to an example Fig.12 A horizontal cross-sectional view of a transistor device of the type illustrated in FIG. 1 ; and

[0029] Fig.13 A top view of a transistor device according to an example is shown. DETAILED DESCRIPTION

[0030] In the following detailed description, reference is made to the accompanying drawings. The accompanying drawings form a part of the description and, for the purpose of illustration, show examples of how the invention may be used and implemented. It should be understood that the features of the various embodiments described herein may be combined with each other unless specifically noted otherwise.

[0031] Figure 1 A transistor device according to one example is shown. More particularly, Figure 1 A vertical cross-sectional view of a portion of a transistor arrangement is shown. The transistor arrangement comprises a semiconductor body 100 and a plurality of transistor cells 1. The semiconductor body 100 comprises a first surface 101 and a second surface 102. The second surface 102 is opposite to the first surface 101 and is spaced apart from the first surface 101 in a vertical direction z of the semiconductor body 100.

[0032] According to one example, the semiconductor body 100 is a single crystal semiconductor body. According to one example, the semiconductor body 100 includes single crystal silicon carbide (SiC). According to one example, the single crystal SiC is a single crystal SiC of 4H polymorph, 3H polymorph or 6H polymorph. However, using single crystal SiC to realize the semiconductor body 100 is only an example. Other semiconductor materials (such as silicon (Si)) can also be used.

[0033] Reference Figure 1, each transistor cell includes a drift region 11, a body region 12 and a source region 13. Each of the drift region 11, the body region 12 and the source region 13 is a doped semiconductor region and is arranged in the semiconductor body 100. The drift region 11 and the source region 13 are doped regions of a first doping type (conductivity type), and the body region 12 is a doped region of a second doping type (conductivity type) complementary to the first doping type. According to an example, the body region 12 is adjacent to both the source region 13 and the drift region 11, wherein the body region 12 is arranged between the source region 13 and the drift region 11. The source region 13 and the body region 12 of each transistor cell 1 are connected to the source node S.

[0034] Figure 1 The transistor arrangement illustrated in FIG is a vertical transistor arrangement. This includes that in the vertical direction z of the semiconductor body 100, the body region 12 of each transistor cell is arranged between the source region 13 and the drift region 11. In addition, in the vertical direction z, the drift region 11 is arranged between the body region 12 and the optional drain region 15 explained below in this article.

[0035] In the following, the body region 12, the source region 13 and the drift region 11 are referred to as “active device regions”. According to one example, the doping concentration of the active device region is selected from the following ranges: the drift region 11: at 5E14 cm -3 and 5E17 cm -3 Between; Main area 12: 1E16 cm -3 and 1E18 cm -3 Source region 13: higher than 1E19 cm -3 .

[0036] In addition, each transistor cell 1 comprises a gate electrode 21. The gate electrode 21 is arranged adjacent to the body region 12, is dielectrically insulated from the body region 12 by a dielectric layer 22 (the dielectric layer 22 is briefly referred to as a gate dielectric in the following), and is connected to a gate node G. In addition, the gate electrode 21 is arranged in a trench 23 extending from the first surface 101 into the semiconductor body 100. The trench 23 including the gate electrode 21 is also referred to as a gate trench in the following.

[0037] According to an example, the gate electrode 21 extends substantially in a vertical direction of the semiconductor body 100. The first trench 23 is spaced apart from the second surface 102. According to an example, the gate electrode 21 comprises a metal or a highly doped polycrystalline semiconductor material such as, for example, polysilicon.

[0038] Reference Figure 1Each transistor cell 1 further comprises a field shaping region 31 of the second doping type. The field shaping region 31 is connected to the source node S and adjoins the gate trench 23. When the transistor device is in the blocking state, the field shaping region 31 is used to shape the field in the drift region 11. This is explained in further detail below in this document. The connection between the field shaping region 31 and the source node S is only at Figure 1 The connection between the field shaping region 31 and the source node S can be implemented in various ways. Examples for connecting the field shaping region 31 to the source node S are explained in further detail herein below with reference to further examples.

[0039] According to Figure 1 According to an example illustrated by solid lines in FIG. 2 , in the vertical direction z, the field shaping region 31 extends deeper into the semiconductor body 100 than the gate trench 23. That is, compared with the bottom of the trench 23, the lower end of the field shaping region 31 (i.e., the end of the field shaping region 31 facing away from the first surface 101) is further away from the first surface 101.

[0040] According to Figure 1 According to another example illustrated by dashed lines in FIG. 2 , in the vertical direction z, the field shaping region 31 extends shallower in the semiconductor body 100 than the gate trench 23 .

[0041] According to one example, the doping concentration of the field shaping region 31 is such that, in the blocking state of the transistor device, the field shaping region 31 cannot be completely depleted of charge carriers. According to another example, the doping concentration of the field shaping region 31 is such that, in the blocking state, the field shaping region 31 can be completely depleted of charge carriers. In this example, for example, the doping concentration is 1E15 cm -3 and 1E17cm -3 In the range between.

[0042] In addition, at least part of the gate electrode 21 of each transistor cell is dielectrically insulated from the drift region 11 by a further dielectric layer 32. In those regions of the gate trench 23 where the gate electrode 21 is adjacent to the drift region 11, the gate electrode 21 serves as a field electrode. The further dielectric layer 32 separating the gate electrode 21 from the drift region 11 is briefly referred to as the field dielectric 32 in the following. According to an example, “at least part of the gate electrode 21 is insulated from the drift region 11 by the field dielectric 32” comprises that at least in those regions of the bottom of the gate trench 23 where the field shaping region 31 is not adjacent to the bottom of the gate trench 23, the field dielectric 32 is arranged between the gate electrode 21 and the drift region 11. The bottom of the gate trench 23 is that part of the gate trench 23 which faces the second surface 102.

[0043] It should be noted that not the entire portion of the gate electrode 21 located adjacent to the drift region 11 is insulated from the drift region 11 by the field dielectric 32. Figure 1 As shown in , parts of the gate electrode 21 may also be insulated from the drift region 11 by a gate dielectric 22. In particular, this applies to those parts of the gate electrode which are close to the PN junction between the body region 12 and the drift region 11.

[0044] The field dielectric 32 is a high-k dielectric. According to one example, this includes: the relative dielectric constant K of the field dielectric 32 is higher than the relative dielectric constant of silicon dioxide (SiO2), which has a relative dielectric constant of approximately 3.9. SiO2 ≈3.9. According to one example, the material of the field dielectric 32 is selected such that the relative dielectric constant K of the field dielectric 32 is higher than 5, higher than 10, higher than 20, or even higher than 30. The relative dielectric constant of a high-k dielectric may also be referred to as a K factor.

[0045] Examples of materials for implementing the field dielectric 32 include, but are not limited to, Al2O3 (aluminum oxide) having a K factor of about 9, ZrO2 (zirconium oxide) having a K factor of about 25, HfO2 (hafnium oxide) having a K factor of about 25, silicon-doped HfO2, AlN (aluminum nitride), AlSiO2 having a K factor between 7 and 10, and x (aluminum silicate), TiO2 (titanium oxide), Y2O3 (yttrium oxide) or Si3N4 (silicon nitride) with a K factor of about 16. The field dielectric 32 may consist entirely of the same material, such as one of the materials explained above. According to another example, the field dielectric 32 includes a layer stack having two or more different dielectric layers. At least one of these two or more layers may include one of the high-k materials explained above.

[0046] According to one example, the gate dielectric 22 comprises silicon oxide (SiO 2 ). According to another example, the gate dielectric 22 comprises a high-k dielectric. The material of the high-k dielectric may be one of the examples explained herein before with reference to the field dielectric 32 .

[0047] According to an example, the field dielectric 32 is thicker than the gate dielectric 22, that is to say, the field dielectric 32 has a greater thickness than the gate dielectric 22. The thickness of the field dielectric 32 is given by the shortest distance between the gate electrode 21 and the semiconductor material of the semiconductor body 100 in the region of the field dielectric 32. The thickness of the gate dielectric 22 is given by the shortest distance between the gate electrode 21 and the material of the semiconductor body 100 in the region of the gate dielectric 22. In absolute values, for example, the thickness of the gate dielectric 22 is between 20 nm and 150 nm.

[0048] exist Figure 1 In the figure, the gate node G and the source node S, the connection between the gate electrode 21 of the individual transistor cell 1 and the gate node G, and the connection between the source region 13 and the body region 12 and the source node S are only schematically illustrated. The gate node and the source node can be realized using conventional metallization, and the connection can be realized using conventional wiring technology. An example for realizing such circuit nodes and such connections is further explained below in this article.

[0049] Reference Figure 1 , the transistor device may further include a drain node D. Figure 1 The drain node D schematically illustrated in FIG. 1 is electrically connected to the drift region 11 of each transistor cell 1. Figure 1 According to the example illustrated by the dashed line in FIG. 1 , the drain node D is connected to the drift region 11 via the drain region 15. According to one example, the drain region 15 has the same doping type as the drift region 11 and has a higher doping concentration. According to one example, the doping concentration of the drain region 15 is at least 100 times the doping concentration of the drift region 11. According to one example, the doping concentration of the drain region 15 is higher than 5E18 cm -3 .

[0050] exist Figure 1 In FIG. 1 , several transistor cells 1 of a transistor arrangement are shown. Figure 1 It can be seen that two (or more) transistor cells may share active device regions 11, 12, 13, 15. Figure 1 In the example shown in FIG. 1 , for example, the drift regions 11 of the plurality of transistor cells are formed by the same doping region of the semiconductor body 100 . Similarly, the drain regions 15 of the transistor cells 1 may be formed by the same doping region of the semiconductor body 100 .

[0051] The transistor device can be implemented as an n-type transistor device or as a p-type transistor device. In an n-type transistor device, the doped regions of the first doping type (drift region 11 and source region 13) are n-type regions, and the doped regions of the second doping type (body region 12, field shaping region 31) are p-type regions. In a p-type transistor device, the drift region 11 and source region 13 are p-type regions, and the body region 12 is an n-type region.

[0052] In addition, the transistor device can be implemented as an enhancement mode device or as a depletion mode device. In an enhancement mode device, the body region 12 of each transistor cell 1 is adjacent to the gate dielectric 22 of the corresponding transistor cell (e.g. Figure 1 ). In a depletion mode device, in addition to the body region 12, each transistor cell 1 also includes a channel region of the same doping type as the source region 13 between the body region 12 and the gate dielectric 22. However, such a channel region is not shown in the figure. Figure 1 middle.

[0053] By applying a driving voltage (gate-source voltage) between the gate node G and the source node S, according to Figure 1 The transistor device can be operated in a conventional manner. The transistor device is in an on-state (conductive state) when a driving voltage is applied between the gate node G and the source node S, which induces a conductive channel in the body region 12 along the gate dielectric 22 between the source region 13 and the drift region 11 in each transistor cell 1. For example, when a positive driving voltage higher than the threshold voltage is applied between the gate node G and the source node S, the n-type transistor device is in an on-state.

[0054] In the on state, in each transistor cell, current can flow from the source node S to the drain node D via the source region 13 , the conductive channel in the body region 12 , and the drift region 11 .

[0055] In order to distribute the current more evenly in the drift region 11 when the transistor device is in the on state, the drift region 11 may include a current extension region 14. The current extension region 14 is a part of the drift region 11 and has a higher doping concentration than the rest of the drift region 11. According to an example, the doping concentration of the current extension region 14 is between 2 and 100 times the doping concentration of the rest of the drift region 11, in particular between 3 and 10 times.

[0056] exist Figure 1 In the example illustrated in FIG. 1 , in each transistor cell 1 , the current extension region 14 is adjacent to the body region 12 . However, this is only an example. It is also possible to implement the current extension region 14 in such a way that the current extension region 14 is separated from the body region 12 in the vertical direction z.

[0057] Reference Figure 1 , the gate trench 23 with the gate electrode 21 extends into the drift region 11. According to an example, the current extension region 14 extends deeper in the semiconductor body 100 in the vertical direction z as seen from the first surface 101 than the gate trench 23 and the field shaping region 31.

[0058] The transistor device is in an off state when the conductive channel in the body region 12 is interrupted. In the off state, when a voltage is applied between the drain node D and the source node S, which voltage reversely biases the PN junction between the body region 12 and the drift region 11 of the individual transistor cell 1, a space charge region (depletion region) expands in the drift region 11 and in the body region 12. This depletion region is associated with an electric field.

[0059] The maximum value of the electric field may occur in the drift region 11 close to the PN junction between the body region 12 and the drift region 11 and thus close to the gate trench 23 with the gate electrode 21. If, for example, the potential of the gate electrode 21 in the off state is equal to the potential of the source region 13 and the body region 12, the vertical component E of the electric field in the gate dielectric 22 22 Depend on

[0060]

[0061] The approximate value is given by, where ε11 indicates the relative dielectric constant (K factor) of the semiconductor material of the semiconductor body 100, ε22 indicates the relative dielectric constant (K factor) of the dielectric material of the gate dielectric 22, and E 11 1 indicates the magnitude of the electric field in the drift region 11 in a region adjacent to the gate dielectric 22. Referring to the above, the gate dielectric 22 may include silicon oxide (SiO2) having a relative dielectric constant of about 3.9.

[0062] The vertical component of the electric field is that component of the electric field that is essentially perpendicular to the interface between the semiconductor material of the semiconductor body 100 and the field dielectric 32 .

[0063] For example, silicon carbide of the 4H polymorph has a relative permittivity of about 9.6. Thus, if the semiconductor material of semiconductor body 100 comprises silicon carbide and gate dielectric 22 comprises silicon oxide, then according to equation (1), the dielectric field E in the silicon oxide is greater than the dielectric field in the adjacent semiconductor material. 22 It may be significantly higher (about 2.5 times). This may have the effect that the electric field in the gate dielectric 22 may become higher than the critical electric field of the gate dielectric.

[0064] The critical electric field of silicon carbide is between 2 MV / cm and 3 MV / cm. The critical electric field of the intrinsic breakdown of silicon oxide is between 8 MV / cm and 10 MV / cm, which is more than 2.5 times the critical electric field of silicon carbide. However, due to the groove morphology and defects in the manufacturing process of the gate dielectric 22, the safe operating electric field of the gate dielectric 22 may be less than the theoretical critical electric field of the material used to realize the gate dielectric 22. Therefore, in order to realize a reliable device, the electric field in the dielectric layer separating the gate electrode 21 from the drift region 11 should not exceed a certain value, which is, for example, 2 times the critical electric field of the material of the semiconductor body 100.

[0065] In accordance with Figure 1In the transistor device 1, in the off state of the transistor device, the gate electrode 21 generates a space charge region (depletion region) in the drift region 11 in those sections adjacent to the gate trench. This is due to the fact that in the off state, the potential of the gate electrode 21 is much lower than the potential in the drift region 11. According to one example, the potential of the gate electrode 21 in the off state is essentially equal to the potential of the source node S.

[0066] Referring to the above, the field dielectric 32 is arranged between a portion of the gate electrode 21 and the drift region 11, and therefore, is arranged in a region where the highest electric field may occur when the transistor device is in an off state. Due to the high K factor (higher than 4) of the high-k dielectric, under the same operating conditions, the electric field occurring in the field dielectric 32 is lower than a comparable electric field in a transistor device in which the field dielectric is replaced by a dielectric layer comprising a conventional gate dielectric material (such as silicon oxide). Therefore, the use of a high-k dielectric to implement the dielectric layer 32 separating at least a portion of the gate electrode 21 from the drift region 11 increases the robustness of the transistor device, compared to a conventional transistor device in which the dielectric separating the gate electrode from the drift region is made of the same material as the gate dielectric.

[0067] Furthermore, the gate electrode 21 in combination with the field dielectric 32 serves as a field electrode, which shapes the electric field in the drift region 11 in a section adjacent to the gate trench 23 and therefore also in a section where the drift region 11 is adjacent to the body region 12. In particular, the gate electrode 21 in combination with the field dielectric 32 shapes the electric field in the drift region 11 so that the electric field close to the body region 12 is low enough to avoid that the gate dielectric 22, which may be adjacent to the drift region 11 close to the body region 12, is not damaged when the transistor device is in a blocking state.

[0068] In addition, the presence of the field shaping region 31 reduces the gate-drain capacitance of the transistor device, which is the capacitance of the transistor device between the gate node G and the drain node D. When the transistor device is turned off, the gate-drain capacitance is charged, and when the transistor device is turned on, the gate-drain capacitance is discharged. Charging and discharging the gate-drain capacitance is associated with losses, which are part of the switching losses of the transistor device. Basically, the higher the gate-drain capacitance and the higher the voltage associated with charging the gate-drain capacitance, the higher the switching losses. Therefore, reducing the gate-drain capacitance helps to reduce switching losses that may occur in the transistor device.

[0069] On the other hand, the presence of the field shaping region 31 increases the gate-source capacitance, which is the capacitance between the gate node G and the source node S. When the transistor device is turned on, the gate-source capacitance is charged, and when the transistor device is turned off, the gate-drain capacitance is discharged. However, the voltage associated with charging the gate-source capacitance is generally lower than the voltage associated with charging the gate-drain capacitance. For example, the voltage associated with charging the gate-source capacitance is generally lower than 20 or 30 V, while the voltage associated with charging the gate-drain capacitance may be in the range of several hundred volts.

[0070] Thus, in general, reducing the gate-drain capacitance and increasing the gate-source capacitance at the same time helps reduce switching losses that may occur in the transistor device. In addition, reducing the gate-drain capacitance and increasing the gate-source capacitance reduces the ratio Cgd / Cgs between the gate-drain capacitance and the gate-source capacitance. When the transistor device is used as an electronic switch and has been turned off, the low Cgd / Cgs ratio can help prevent parasitic turn-on induced by the rapidly increasing voltage between the drain node and the source node.

[0071] In addition, the field shaping region 31 connected to the source node S forms a body diode together with the drift region 11 .

[0072] The field shaping effect of the gate electrode 21 in combination with the field dielectric 32 is enhanced by the field shaping region 31 which extends deeper in the drift region 11 in the vertical direction z than the gate trench 23 with the gate electrode 21. This is illustrated in FIG. Figure 2 middle.

[0073] Figure 2 The electric field in the drift region 11 close to the gate trench in the blocking state of the transistor device is shown. More specifically, Figure 2 The diagram shows equipotential lines 200 of the electric field that may occur in the blocking state of the transistor device. Figure 2 It can be seen that the field shaping region 31 "pushes" equipotential potential lines away from the field dielectric 32. In this way, the field shaping region 31 has a positive effect with regard to reducing the electric field in the gate dielectric 22 and in the region of the PN junction between the body region 12 and the drift region 11.

[0074] Referring to the above, the field shaping region 31 can be implemented so that the doping concentration is so high that the field shaping region 31 is not completely depleted of charge carriers when the transistor device is in the blocking state and the maximum voltage is applied between the drain node and the source node. The "maximum voltage" is the highest voltage that the transistor device can withstand. In this case, Figure 2 As shown in FIG. 3 , most of the field shaping region 31 is free of electric field.

[0075] According to another example, the doping concentration of the field shaping region 31 is such that, when the transistor device is in the off state, the field shaping region 31 is completely depleted of charge carriers. In this case, an electric field may also occur in the field shaping region 31. However, the field shaping region 31 shapes the electric field in the drift region 11 such that the electric field in the drift region 11 close to the gate dielectric 11 is reduced.

[0076] The size of the field shaping region 31 can be smaller than the size of the JFET region in a conventional transistor device. In particular, the distance between the bottom of the gate trench 23 and the bottom of the field shaping region 31 adjacent to the gate trench 23 can be smaller than the corresponding distance in a conventional transistor device. In addition, the size of the field shaping region 31 in the lateral direction facing away from the gate trench 23 can be smaller than the corresponding size in a conventional transistor device. Thus, the spacing given by the center-to-center distance between two adjacent gate trenches 23 can be reduced, for example, compared to a conventional transistor device, so that a higher number of transistor cells can be realized on the same area. The latter leads to a reduced size of the transistor device at a given on-resistance, or to a reduced on-resistance at a given size. The on-resistance is the resistance of the transistor device in the on-state.

[0077] According to an example, the width of the field shaping region 31 (i.e., the dimension of the field shaping region 31 in the lateral direction x) is less than 50%, less than 25%, less than 10%, or even less than 5% of the shortest distance between two adjacent gate trenches 23. According to an example, in absolute value, the width of the field shaping region 31 in the lateral direction x is less than 200 nanometers, or even less than 100 nanometers.

[0078] Referring above, the field shaping region 31 may extend deeper in the semiconductor body 100 than the gate trench 23. In this example, for example, the size of the portion of the field shaping region 31 extending beyond the trench bottom in the vertical direction z is between 100 and 500 nanometers.

[0079] According to an example, the (shortest) distance between two adjacent gate trenches 23 is selected from between 0.5 micrometers and 2 micrometers. For example, the trench width (i.e. the (smallest) dimension of the gate trench 23 in the first lateral direction x) is between 0.3 micrometers and 1.0 micrometers. Based on this, for example, the spacing given by the center-to-center distance of two adjacent gate trenches 23 (and given by the trench width plus the trench distance) is between 0.8 micrometers and 3.0 micrometers.

[0080] The voltage blocking capability of the transistor device depends inter alia on the length of the drift region 11. The length of the drift region 11 is essentially given by the (shortest) distance between the body region 12 and the drain region 15. According to one example, the length of the drift region 11 is selected from between 2 micrometers and 30 micrometers. A SiC-based transistor device can be realized such that the voltage blocking capability is essentially equal to 150 V per 1 μm length of the drift region (compared to silicon, where the voltage blocking capability is only about 10 V to 15 V per 1 μm length of the drift region).

[0081] Figure 1 A vertical cross-sectional view of several transistor cells 1 is shown. In a horizontal plane (ie, substantially parallel to the first surface 101 and the second surface 102 and perpendicular to Figure 1 The transistor cell 1 can be implemented in various ways in a plane of the cross-sectional plane AA shown in FIG. 1 . An example of a transistor arrangement shown in a horizontal plane cutting through the source region 13 is shown in FIG. Figure 3A and 3B middle.

[0082] exist Figure 3A and 3B In the figure, reference numeral 2 indicates a gate structure, each gate structure includes a gate electrode 21, a gate dielectric 22 and a field dielectric 32, wherein the gate electrode 21, the gate dielectric 22 and the field dielectric 32 are not explicitly shown in the figure. Figure 3A and 3B middle.

[0083] Reference Figure 3A , the transistor cell 1 can be implemented as an elongated transistor cell, which can also be referred to as a stripe cell. In this example, the gate structure 2 (having a gate electrode, a gate dielectric and a field dielectric) is elongated in the horizontal (lateral) direction of the semiconductor body 100. Similarly, the source region 13 and the body region 12 (the body region 12 is not visible in FIG. 3 ) are elongated, wherein each source region 13 and body region 12 is arranged between two adjacent gate trenches 23.

[0084] according to Figure 3B In another example illustrated in , the transistor cell 1 can be implemented as a hexagonal transistor cell. In this example, the gate trench 23 has a hexagonal cross-section in a horizontal cross-section plane of the semiconductor body 100 , which is a cross-section plane that is substantially parallel to the first surface 101 .

[0085] Referring to the above, the semiconductor body 100 may include single crystal SiC of 4H or 6H polymorph. In this example, the gate structure 2 may be arranged within the crystal of the single crystal SiC semiconductor body so that the channel region (formed in the body region 12 along the gate dielectric 22 when the transistor device is in the on state) is aligned to match the vertical crystal planes of the semiconductor body. This is beneficial in view of the reduction of the channel resistance.

[0086] Figure 4 Diagram Figure 1 A variation of the transistor arrangement shown in FIG. Figure 4 The transistor device is implemented as a super junction device. In this case, each transistor cell 1 includes a compensation region 16 of a second doping type. The compensation region 16 is connected to the source node S. In addition, the compensation region 16 is adjacent to the drift region 11, so that a PN junction is formed between the compensation region 16 and the drift region 11. According to an example, the size of the compensation region 16 in the vertical direction z is at least 20% of the size (length) of the drift region 11 in the vertical direction z. For example, the doping concentration of the compensation region 16 is in the range of the doping concentration of the drift region 11.

[0087] Referring to the above, the compensation region 16 is connected to the source node S. Figure 4 In the example illustrated in FIG. 1 , the compensation region 16 is adjacent to the field shaping region 31 , so that the compensation region 16 is connected to the source node S via the field shaping region 31 and the body region 12 . Figure 4 When the transistor device is in the off state, the depletion region expands, also starting at the PN junction between the drift region 11 and the compensation region 16, so that part of the dopants included in the drift region 11 is "compensated" by the dopants included in the compensation region 16. Therefore, at a given voltage blocking capability, the drift region 11 can be realized with a higher doping concentration, resulting in a lower on-resistance, compared to conventional (non-superjunction) devices. This is a well-known effect, so that no further explanation is needed in this regard.

[0088] Reference Figure 1 Each gate trench 23 has a first sidewall 231 and a second sidewall 232 opposite to the first sidewall 231. Figure 1 In the example illustrated in FIG. 1 , the field shaping region 31 is adjacent to the second sidewall 232 and extends to or into the body region 12 along the second sidewall 232 . The gate dielectric 22 may be arranged along the two sidewalls 231 , 232 of the gate trench 23 . Figure 1In the example of FIG. 1 , the field shaping region 31 interrupts the conductive channel in the body region 12 along the second sidewall 232. (In fact, in this example, the body region 12 adjacent to the second sidewall 232 of the gate trench 23 of one transistor cell is the body region 12 of the adjacent transistor cell.) Therefore, in this example, the conductive channel in the body region 12 is formed only along the first sidewall 231 of the gate trench 23.

[0089] Figure 5 Show according to Figure 1 A variation of the transistor device. Figure 5 In the transistor device of FIG. 1 , the field shaping region 31 of each transistor cell 1 is adjacent to the second sidewall 232. However, at least a portion of the field shaping region 31 is separated from the body region 12 in the vertical direction z. In this example, in the on state of the transistor device, a conductive channel between the source region 13 and the drift region 11 is formed along both the first sidewall 231 and the second sidewall 232. Figure 1 Compared with transistor devices, this reduces the Figure 5 The on-state of the transistor device.

[0090] A section of the field shaping region 31 extending further in the direction of the first surface 101 than the drift region 11 (such as Figure 1 and 4 The segment of the field shaping region 31 illustrated in FIG. 1 is referred to below as a first segment (with reference numeral 310). The segment of the field shaping region 31 separated from the body region 12 in the vertical direction z is referred to below as a second segment 311.

[0091] The second segment 311 is optional. Therefore, according to one example, the second segment 311 is omitted. In this example, along the corresponding gate trench 23, one field shaping region 31 includes several first segments, which are separated from each other in the second lateral direction y and are all connected to the source node S.

[0092] An example of a field shaping zone 31 having a first section 310 and optionally a second section 311 is illustrated in FIG. Fig. 6A and 6B middle. Fig. 6A and 6B Each of the above is shown in a horizontal cross-sectional plane BB extending along the junction between the body region 12 and the drift region 11 according to Figure 5 A horizontal cross-sectional view of a transistor device. Fig. 6A A transistor arrangement having an elongated transistor cell is shown, and Figure 6B A transistor arrangement having hexagonal transistor cells is shown.

[0093] Reference Fig. 6A and 6BThe field shaping region 31 of each transistor cell includes a plurality of segments 310 extending to the main region 12 (at Fig. 6A and 6B ) and are connected to the source node S. These segments 310 may be referred to as connection segments. Fig. 6A and 6B , the connection sections 310 of one field shaping region 31 are adjacent to the corresponding gate trenches 23 and are separated from each other.

[0094] In accordance with Fig. 6A In the example of FIG. 1 , the connection regions 310 are separated from each other in the longitudinal direction of the gate trench 23. Fig. 6A The vertical cross-sectional view of the device shown in FIG. Figure 5 For example, a vertical cross-sectional view in a vertical cross-sectional plane cutting through the connecting section 310 corresponds to Figure 1 Vertical cross-sectional view shown in the figure.

[0095] In accordance with Figure 6B In the example of FIG. 3 , the connection regions 310 are spaced apart from each other along the periphery of the respective (hexagonal) trenches. It should be noted that in this respect, the hexagonal gate trench is only one example of a post-shaped trench. Other types of post-shaped gate trenches 23 (such as gate trenches with a rectangular or circular cross-section) may also be implemented. Figure 6B The vertical cross-sectional view of the device shown in FIG. Figure 5 The view shown in the figure.

[0096] Figure 7 Show Figure 5 and a variation of the transistor arrangement illustrated in FIG. 6. Figure 7 In the transistor device, each transistor unit 1 includes Figure 5 6: a first field shaping region 311, corresponding to the field shaping region 31 explained previously in this document and adjoining the second gate trench sidewall 232; and a second field shaping region 312, adjoining the first gate trench sidewall 231. Figure 5 and 6A -6B explained in the field shaping area 31, each of these first and second field shaping areas 311, 312 can be implemented according to Figure 7 According to an example illustrated by dashed lines in FIG. 3 , the first field shaping regions 311 , 312 are adjacent to each other below the trench bottom.

[0097] like Figure 7 As shown on the left side of FIG. 2 , the first and second field shaping regions 311 , 312 are adjacent to the sidewall section and the bottom section of the gate trench 23 . However, this is only an example. Figure 7 In another example shown on the right side of the figure, the first and second field shaping regions 311, 312 are essentially adjacent to the bottom of the trench. In both examples, the first and second field shaping regions 311, 312 are formed by Figure 7 The corresponding connection area not visible in the figure is connected to the source node S.

[0098] Referring to the examples explained herein before, the gate trench 23 of each transistor cell 1 may be essentially symmetrical with respect to a center plane of the respective gate trench 23. The “center plane” is a plane extending in the vertical direction z of the semiconductor body 100. According to an example, the first and second field shaping regions 311, 312 are symmetrical with respect to the center plane of the gate trench 23.

[0099] Reference Figure 1 and 4 -5, the field dielectric 32 can be implemented to be symmetrical with respect to the center plane of the corresponding gate trench 23. In each of these examples, the field dielectric 32 completely covers the bottom of the corresponding gate trench 23 and extends along a portion of each of the first sidewall 231 and the second sidewall 232 in the direction of the body region 12. However, the symmetrical field dielectric 32 is only an example. It is also possible to implement a transistor cell 1 with an asymmetrical field dielectric. An example of an asymmetrical field dielectric 32 is illustrated in Figure 8 middle.

[0100] Figure 8 The transistor device shown in the figure is based on Figure 1 The transistor device shown in FIG. Figure 1 The transistor device of FIG. 1 is different in that the field dielectric 32 is asymmetric. This includes that the gate dielectric 22 extends further along the second side wall 232 in the vertical direction z than along the first side wall 231. This includes that the field dielectric 32 extends closer along the second side wall 232 in the direction of the body region than along the first side wall 231. Figure 8 In the example illustrated in , along the second sidewall 232, the gate dielectric 22 extends essentially to the trench bottom and is arranged between the gate electrode 21 and the field shaping region 31. A portion of the field dielectric 32 adjoins the field shaping region 31, so that at the trench bottom, the field dielectric 32 is arranged between the gate electrode 21 and the drift region 11 or the optional compensation region 16. Along the first sidewall 231, the field dielectric 32 extends from the trench bottom in the direction of the body region 12.

[0101] In accordance with Figure 8In the example of , a large part of the field shaping region 31 is separated from the gate electrode 21 by the gate dielectric 22. This results in a reduced gate-source capacitance compared to a device with a symmetric field dielectric, in which a large part of the field shaping region 31 is separated from the gate electrode 21 by the field dielectric 23.

[0102] Referring to the above, the source region 13 and the body region 12 are connected to the source node S of the transistor device. Two examples for connecting the source region 13 and the body region 12 of the transistor cell 1 to the source node S are explained below.

[0103] Referring to the above, the field shaping region 31 is connected to the source node S. An example for connecting the field shaping region 31 to the source node S is illustrated in FIG. Fig. 9A and 9B middle.

[0104] exist Fig. 9A and 9B In the example illustrated in , the transistor device comprises a source metallization 41 on top of an insulating layer 43. The insulating layer 43 is formed on top of the first surface 101 of the semiconductor body 100 and electrically insulates the gate electrode 21 from the source metallization 41. The source metallization 41 is connected to a source node S, or forms a source node S of the transistor device. In addition, the transistor device comprises a conductive via 42, which extends through the insulating layer 43 to the semiconductor body 100 and is connected to the source region 13 and the body region 12, so that the conductive via 42 connects the source region 13 and the body region 12 to the source metallization 41. The conductive via 42 is also referred to as a source via in the following.

[0105] Fig. 9A and 9B The transistor cell 1 of the transistor device shown in the figure is based on Figure 1 However, this is only an example. Fig. 9A and 9B The way in which the source region 13 and the body region 12 are connected to the source metallization 41 as shown in FIG. 1 is independent of the specific implementation of the transistor cell 1. Fig. 9A and 9B In the transistor arrangement, any other type of transistor cell 1 explained herein before may also be used.

[0106] In accordance with Fig. 9AIn the example of FIG. 1 , the source via 42 extends through the source region 13 into the body region 12. In those regions where the source via 42 adjoins the body region 12, the body region 12 may have a contact region 17 having a higher doping concentration than the rest of the body region 12. The higher doping concentration is used to achieve an ohmic contact between the source via 42 and the corresponding body region 12. According to an example, the field shaping region 31 adjoins the contact region 17, so that the field shaping region 31 is connected to the source node via the contact region 17 and the source via 42. In this example, the contact region 17 is separated from the first surface 101.

[0107] In accordance with Fig. 9B In the example of , the contact region 17 is arranged next to the source region 13 in the lateral direction x, adjoins the body region 12, and may adjoin the first surface 101. In addition, each of the field shaping regions 31 adjoins a corresponding one of the contact regions 17. Each of the contact region 17 and the source region 11 is connected to a corresponding source via 42.

[0108] Figures 10A-10C Another example for connecting the source region 13 and the body region 12 to the source metallization 41 is illustrated. Fig. 10A shows a vertical cross-sectional view of the transistor arrangement in a first section plane DD, Fig. 10B shows a vertical cross-sectional view of the transistor arrangement in a second section plane EE, and Fig. 10C A top view of a first surface 101 of a semiconductor body 100 is shown. Figures 10A-10C 9 in that the source via 42 extends to or into the source region 13, but does not extend through the source region 13 to the body region 12. In this example, the body region 12 includes a section extending to the first surface 101, wherein the section of the body region 12 extending to the first surface 101 is connected to the source via 42 in order to connect the body region 12 to the source metallization 41.

[0109] Fig.11 FIG. 2 shows a vertical cross-sectional view of a transistor device according to another example. Fig.11 The transistor device is based on Figure 1 transistor device, and according to Figure 1 The transistor device of 100 is different in that each transistor cell 1 further comprises a field electrode 33 in addition to the field dielectric 32. The field electrode 33 is arranged in the gate trench 23 and, as seen from the first surface 101, is arranged below the gate electrode 21 and the body region 12. The field electrode 33 is dielectrically insulated from the drift region 11 by the field dielectric 32 and from the gate electrode 21 by a further dielectric layer 24. According to an example, the further dielectric layer 24 comprises the same material as the gate dielectric 22.

[0110] Reference Fig.11 , each transistor cell may include a field shaping region 31. However, the field shaping region 31 is optional and therefore Fig.11 is shown as a dotted line. Figure 1 The example shown in the figure, Fig.11 The field shaping area 31 illustrated in FIG. 1 is implemented. However, this is only an example. Any other type of field shaping area 31 explained previously in this document may also be used according to Fig.11 transistor device.

[0111] The field dielectric 32 is a high-k dielectric. Everything explained above in this document with respect to the field dielectric 32 therefore applies to the Fig.11 Field dielectric 32. According to Fig.11 The function of the transistor device is similar to the function of the transistor device explained previously in this article. Compared with the transistor device explained previously in this article, according to Fig.11 The transistor arrangement has a lower gate-drain capacitance, which is the capacitance between the gate node G and the drain node. In particular, this applies when the field electrode 33 is connected to the source node S.

[0112] In order to connect the field electrode 33 to the source node S, the field electrode 33 may include a section extending to the first surface 101 of the semiconductor body 100 . Fig.12 A top view of the first surface 101 of the transistor arrangement is shown, with a section of the field electrode 33 extending to the first surface 101 .

[0113] The section of the field electrode 33 extending to the first surface 101 is connected to the source node S. According to an example, the transistor device comprises a source metallization 41 (not shown in FIG. 1 ) of the type explained herein before. Fig.11 and 12 In this example, the section of the field electrode 33 extending to the first surface 101 can be connected to the source metallization using source vias in the same way as explained herein before with respect to the source region 13 .

[0114] Fig.13 A top view of a transistor arrangement according to any of the examples explained herein before is shown. More particularly, Fig.13 4 shows a top view of a semiconductor body 100 with a source metallization 41. An example of a gate structure 2 and its position below the source metallization 41 is illustrated in dashed lines in FIG. Fig.13In this example, below the source metallization 41, the gate structure 2 extends beyond the source metallization 41 and is connected to a gate runner 52. The gate runner 52 is formed on top of the insulating layer 43 and is connected to a gate pad 51. The gate pad 51 is connected to a gate node G, or forms a gate node G of the transistor device.

[0115] according to Fig.13 The transistor device of FIG. 4 comprises only one source metallization 41. However, this is only an example. According to another example (not shown), the transistor device comprises several source metallizations, each source metallization is connected to the source node S, and the transistor device comprises two or more gate tracks 52, each gate track 52 is connected to the gate pad 51. For example, several gate tracks can be used for Fig.12 In a transistor arrangement of the type illustrated in . In such a transistor arrangement, a field electrode segment extending to the first surface 101 interrupts the gate electrode 21 , so that each of the different segments of the gate electrode needs to be connected to a respective gate track.

Claims

1. A transistor arrangement comprising a semiconductor body (100) and a plurality of transistor cells (1), wherein each transistor cell comprises: A drift region (11) and a source region (13) of a first doping type; a main body region (12) of a second doping type complementary to the first doping type; The field shaping region (31) of the second doping type is connected to the source node (S); and A gate electrode (21), connected to a gate node (G), wherein the gate electrode (21) is arranged in a trench (23) extending from the first surface (101) into the semiconductor body (100), wherein the gate electrode (21) is dielectrically insulated from the body region (12) by a gate dielectric (22), wherein at least a portion of the gate electrode (21) is dielectrically insulated from the drift region (11) by a field dielectric (32), wherein the field shaping region (31) is adjacent to the trench (23), and The field dielectric (32) comprises a high-k dielectric.

2. The transistor device according to claim 1, In the vertical direction (z) of the semiconductor body (100), the field shaping region (31) extends deeper in the semiconductor body (100) than the trench (23).

3. A transistor device as claimed in claim 1 or 2, wherein the body region (12) is connected to the source node (S), and The field shaping region (31) is adjacent to the body region (12) so as to be connected to the source node (S) via the body region (12).

4. A transistor device as claimed in claim 1 or 2, wherein the body region (12) is connected to the source node (S) via a contact region (17), wherein the contact region (17) has a higher doping concentration than the rest of the body region (12), and The field shaping region (31) is adjacent to the contact region (17) so as to be connected to the source node (S) via the contact region (12).

5. A transistor arrangement as claimed in any one of the preceding claims, The field shaping region (31) includes a plurality of first segments (31), which are separated from each other along the sidewalls of the trench (23) and are all connected to the source node (S).

6. The transistor device as claimed in claim 5, Wherein, in a vertical direction (z) of the semiconductor body (100), the first section (310) extends further in the direction of the first surface (101) than the drift region (11).

7. The transistor device as claimed in claim 6, The field shaping region (31) further comprises a second section (311), wherein the second section (311) is adjacent to the first section (310) and is separated from the main body region (12).

8. A transistor device as claimed in any one of claims 1 to 7, The field dielectric (32) is symmetrical relative to the center plane of the trench.

9. A transistor device as claimed in any one of claims 1 to 7, The field dielectric (32) is asymmetric relative to a center plane of the trench.

10. A transistor arrangement comprising a semiconductor body (100) and a plurality of transistor cells (1), wherein each transistor cell comprises: A drift region (11) and a source region (13) of a first doping type; a main body region (12) of a second doping type complementary to the first doping type; a gate electrode (21) connected to the gate node (G); and wherein the gate electrode (21) and the field electrode (33) are arranged in a trench (23) extending from the first surface (101) into the semiconductor body (100), wherein the field electrode (33) is dielectrically insulated from the gate electrode (21) in the trench (23), wherein the gate electrode (21) is dielectrically insulated from the body region (12) by a gate dielectric (22), wherein the field electrode (33) is dielectrically insulated from the drift region (11) by a field dielectric (32), and The field dielectric (32) comprises a high-k dielectric.

11. The transistor device of claim 10, further comprising: The field shaping region (31) of the second doping type is connected to the source node (S).

12. The transistor device according to claim 11, The field shaping region (31) adjoins the trench (23) and extends deeper in the semiconductor body (100) than the trench in a vertical direction (z) of the semiconductor body (100).

13. A transistor arrangement as claimed in any one of claims 10 to 12, Wherein the field electrode (33) is connected to the source node (S).

14. A transistor arrangement as claimed in any one of the preceding claims, Each transistor cell further comprises a compensation region (16) of the second doping type, The compensation region (16) is adjacent to the drift region (11).

15. The transistor device as claimed in claim 14, The compensation region (16) is adjacent to the field shaping region (31).

16. A transistor arrangement as claimed in any one of the preceding claims, The maximum thickness of the gate dielectric (22) is smaller than the maximum thickness of the field dielectric (32).

17. A transistor device as claimed in any one of claims 1 to 16, The gate dielectric (22) comprises silicon dioxide.

18. A transistor device as claimed in any one of claims 1 to 16, The gate dielectric (22) comprises a high-k dielectric.

19. A transistor arrangement as claimed in any one of the preceding claims, The relative dielectric constant of the high-k dielectric is higher than 5, higher than 10, or higher than 20.

20. The transistor arrangement as claimed in any one of the preceding claims, wherein the semiconductor body (100) is a SiC semiconductor body.

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