Wide SOA shield gate MOSFET device and manufacturing method thereof

Abstract

The invention provides a wide SOA shield gate MOSFET device and a manufacturing method thereof. The wide SOA shield gate MOSFET device comprises a substrate, an epitaxial layer, a groove, a shield gate, a control gate, a first isolation dielectric layer, a P well region, an N + injection region, a contact hole and a hole bottom contact region, the P well region comprises a first P well region which is formed only in a general injection mode after the control gate is formed, the MOSFET device is characterized in that the P well region further comprises a second P well region which is formed by band plate injection after the general injection mode, and / or the distances between at least one contact hole and the boundary of the adjacent groove are different. And cellular-level uniform heat dissipation is provided, the thermal stability of a power device in thermal design is improved, and an MOSFET device with a wide SOA is provided.

Description

Technical Field

[0001] The present invention relates to the field of semiconductor technology, and in particular to a wide SOA shielded gate MOSFET device and a manufacturing method thereof. Background Art

[0002] The shielded gate MOSFET (Split Gate MOSFET, abbreviated as SGT-MOSFET) power device is an improved trench power MOSFET based on the traditional trench MOSFET (U-MOSFET). It has fast switching speed, low loss and better device performance.

[0003] When pursuing a small Rsp (characteristic on-resistance), the choice is to continue to reduce Pitch (the distance between adjacent trenches, the size of a cell) to achieve a lower resistance, which will increase the power density. Due to thermal instability, the ZTC (zero temperature coefficient) point increases, which inevitably reduces the safe operating area (SOA). In some hot-swap, switch switching and other applications, the power MOSFET is required to work in linear mode for several milliseconds or longer under high voltage and high current conditions. If the SOA is insufficient, the tube is easily burned out due to the positive electron coupling effect, so it is particularly important to improve the SOA of the device.

[0004] SOA refers to the safe operating area of ​​MOSFET devices, which is called Safer Operating Area in English. It refers to the safe operating range of MOSFET (metal oxide semiconductor field effect transistor). Figure 1 As shown in the figure, IDS (i.e., drain-to-source current, unit A) is the on-state current, VDS (i.e., drain-to-source voltage, unit V), Single Pulse refers to a single pulse, and the figure shows the VDS-IDS curves of MOSFET devices under DC, pulse durations of 100μs, 10ms, and 1ms, respectively. Max RθJC refers to the maximum junction-to-case thermal resistance. Figure 1 It can be seen that when the MOS tube is working normally, the voltage and current should not exceed the limit range of SOA. The importance of this concept is reflected in evaluating whether the working state of the MOS tube is safe, especially in applications such as hot plug, motor drive and switching power supply.

[0005] The ZTC (Zero Temperature Coefficient) point is an important parameter to characterize the thermal stability of MOS devices. Figure 2As shown, VGS is the driving voltage, IDS is the on-current, and the on-current of the device above the ZTC point is I DS (Drain-to-Source Current, unit: A) has a negative temperature characteristic with temperature T, and the device is in a thermally stable state. Below the ZTC point, the device has a positive temperature characteristic, and the device is in a thermally unstable state. Because the on-current and temperature have a positive feedback relationship, thermal burnout is very likely to occur. For the same device, if the threshold voltage Vth (Threshold Voltage) is high, its ZTC point will be correspondingly low. If the threshold voltage Vth is low, the ZTC point will be correspondingly high. This can be demonstrated from experimental tests. However, for certain application requirements, due to the limitation of the drive voltage VGS, the threshold voltage Vth is certain and cannot be too large or too small. For example, hot-swap and switching power supplies generally require a 2V range, and motor drives require a 3V range.

[0006] Figure 3 The first part is the Rds(on) limit line. Rds(on) is the drain-source resistance of the MOSFET in the on state. This line indicates the maximum drain-source current (IDS) and drain-source voltage (VDS) combination that the MOSFET can withstand under a given gate voltage (VGS). The second part is the current limit line. This line indicates the maximum drain-source current (IDS) that the MOSFET can withstand under any conditions. The third part is the power limit line. This line indicates the maximum allowable power dissipation of the MOSFET. The fourth part is the thermal stability limit line. This line indicates the maximum allowable IDS and VDS combination caused by thermal effects when the MOSFET works for a long time. The fifth part is the breakdown voltage limit line. This line indicates the maximum allowable drain-source voltage (VDS) of the MOSFET. Exceeding this voltage may cause the MOSFET to break down. The extension of the thermal stability limit line in the fourth part is also a representation of the device's ability to cope with the linear mode. The greater the extension of this line, the stronger the ability of the MOSFET to maintain stable operation under high power dissipation and high temperature conditions. If this line is wider and extends farther, it means that the MOSFET has strong thermal management capabilities at high power dissipation and can operate stably over a wider current and voltage range. Summary of the invention

[0007] Based on the above records, the present invention provides a wide SOA shielded gate MOSFET device and a manufacturing method thereof, aiming to solve the technical problem in the prior art that the thermal stability of MOSFET devices needs to be improved.

[0008] A wide SOA shielded gate MOSFET device, comprising:

[0009] A substrate, an epitaxial layer is grown on the surface of the substrate, a groove is etched on the epitaxial layer, a shielding grid is formed in the groove, a control grid is arranged on the shielding grid, the shielding grid and the control grid are separated by a first isolation dielectric layer, and a platform area is formed between the grooves;

[0010] A P-well region, and an N+ implantation region formed on the upper surface of the P-well region in the platform region, the P-well region including a first P-well region formed only by general implantation after forming a control gate;

[0011] A second isolation dielectric layer covering the N+ implantation region;

[0012] A contact hole, wherein the contact hole penetrates the second isolation dielectric layer and the N+ implantation region, and the bottom of the contact hole forms a bottom contact region;

[0013] The MOSFET device is also characterized in that the P-well region further includes a second P-well region formed by strip implantation after general implantation, and / or the distances between at least one contact hole and the boundaries of adjacent trenches are different.

[0014] Furthermore, when the MOSFET device is characterized in that the distances between at least one contact hole and the boundaries of adjacent grooves are different, and the cell of the MOSFET device is a strip cell, at least one contact hole has: the distances between the contact hole and the boundaries of the strip grooves on the left and right sides are different.

[0015] Furthermore, when the characteristic P-well region of the MOSFET device also includes a second P-well region formed by strip implantation after general implantation, and the cell of the MOSFET device is a square cell, the boundary of the second P-well region is in the groove, and one second P-well region covers one or more complete cells.

[0016] Furthermore, when the characteristic of the MOSFET device includes a P-well region further including a second P-well region formed by strip implantation after general implantation, and the cell of the MOSFET device is a strip-shaped cell, the second P-well region is in a strip shape;

[0017] The length direction of each second P-well region is perpendicular to the length direction of the trench.

[0018] Further, when the characteristic of the MOSFET device includes a P-well region further including a second P-well region formed by strip implantation after general implantation, and the cell of the MOSFET device is a strip-shaped cell, the second P-well region is a strip-like shape;

[0019] The length direction of each second P-well region is perpendicular to the length direction of the trench, and the second P-well region is divided into a plurality of sections along the length direction, and the widths of two adjacent sections are different.

[0020] Furthermore, when the characteristic of the MOSFET device includes a P-well region further including a second P-well region formed by strip implantation after general implantation, and the cell of the MOSFET device is a strip-shaped cell, the second P-well region is in a strip shape;

[0021] The length direction of each second P-well region is parallel to the length direction of the trench.

[0022] Furthermore, a boundary on the second P-well region parallel to the length direction of the trench is located in a platform region between two adjacent trenches.

[0023] Furthermore, a boundary of the second P-well region parallel to the length direction of the trench is in the trench.

[0024] Further, when the characteristic of the MOSFET device exists in the P-well region and also includes a second P-well region formed by performing strip implantation after the general implantation method;

[0025] The ratio between the total area of ​​the second P-well region and the total area of ​​the first P-well region is 1:4 to 1:3.

[0026] A method for preparing a wide SOA shielded gate MOSFET device, characterized in that it is used to prepare the aforementioned wide SOA shielded gate MOSFET device, comprising:

[0027] Step A1, preparing a substrate, growing an epitaxial layer on the surface of the substrate, etching grooves on the epitaxial layer, and forming a platform region between the grooves;

[0028] Step A2, forming a shielding gate in the trench;

[0029] Step A3, forming a first isolation dielectric layer on the shielding gate;

[0030] Step A4, forming a control gate on the first isolation dielectric layer;

[0031] Step A5, forming a P-well region, the P-well region including a first P-well region formed only by general injection after forming the control gate;

[0032] Step A6, forming an N+ implantation region on the upper surface layer of the P-well region of the platform region;

[0033] Step A7, forming a second isolation dielectric layer, wherein the second isolation dielectric layer covers the N+ implantation region;

[0034] Step A8, forming a contact hole, the contact hole penetrates the second isolation dielectric layer and the N+ implantation region, and the bottom of the contact hole forms a bottom contact region;

[0035] The formed MOSFET device is also characterized by: the P-well region further includes a second P-well region formed by strip implantation after general implantation, and / or the distances between at least one contact hole and the boundaries of adjacent trenches are different.

[0036] The beneficial technical effects of the present invention are:

[0037] (1) forming a first P-well region and a second P-well region by two injections, and / or shifting the contact hole, thereby forming a cold trench region and a hot trench region on the device. The cold trench region can provide uniform heat dissipation at the cell level for the hot trench region, thereby improving the thermal stability in the thermal design of the power device;

[0038] (2) The cold channel region has a larger threshold voltage Vth, which can reduce the zero temperature coefficient ZTC of the boost device;

[0039] (3) When the hot and cold trenches are connected in parallel, the overall turn-on voltage of the device is still the low threshold voltage of the hot trench area, which does not affect the customization of the overall turn-on voltage of the device;

[0040] (4) Although the threshold voltage of the cold channel region is high, the driving voltage VGS of the device during normal conduction is generally more than 3 times greater than the device turn-on voltage Vth (threshold voltage). When the device is turned on normally, it has little effect on the on-voltage of the device, and it only exists in a certain small range, further compressing the impact on the on-resistance of the device.

[0041] (5) The proportion of the cold trench area can be freely adjusted according to the actual application. The larger the proportion of the cold trench area, the better the linear capability of the device, the wider the thermal stability limit line of the fourth part of the SOA, and the greater the impact on the on-resistance of the device. On the contrary, the smaller the proportion of the cold trench area, the smaller the impact on the on-resistance of the device, but the improvement in linear capability is correspondingly reduced. In this way, we can adjust the on-resistance R according to different application requirements. DS It can freely and flexibly compromise with SOA and has good scalability of product series in segmented application fields. BRIEF DESCRIPTION OF THE DRAWINGS

[0042] Figure 1 It is a schematic diagram of the SOA region of a MOSFET device;

[0043] Figure 2 It is a schematic diagram of the zero temperature coefficient point (ZTC) of the MOSFET device;

[0044] Figure 3 This is a diagram illustrating the limit lines of the MOSFET SOA region;

[0045] Figure 4 , Figure 14-17It is a schematic plan view of the design of the second P-well region of a wide SOA shielded gate MOSFET device of the present invention;

[0046] Figure 5-Figure 6 A schematic plan view of a contact hole offset design for a wide SOA shielded gate MOSFET device according to the present invention;

[0047] Figure 7-Figure 13 A schematic diagram of the structure of a method for preparing a wide SOA shielded gate MOSFET device during the preparation process of the present invention;

[0048] Fig.18 The present invention is a flowchart of the steps of a method for preparing a wide SOA shielded gate MOSFET device.

[0049] Among them, 1-substrate; 2-epitaxial layer; 3, trench; 4-field oxide layer; 5-shielding gate; 6-first isolation dielectric layer; 7-gate oxide layer; 8-control gate; 9-P well region; P1-first P well region; P2-second P well region; 10-N+ injection region; 11-second isolation dielectric layer; 12, CONT-contact hole; 13-hole bottom contact region. DETAILED DESCRIPTION

[0050] The following will be combined with the drawings in the embodiments of the present invention to clearly and completely describe the technical solutions in the embodiments of the present invention. Obviously, the described embodiments are only part of the embodiments of the present invention, not all of the embodiments. Based on the embodiments of the present invention, all other embodiments obtained by ordinary technicians in this field without creative work are within the scope of protection of the present invention.

[0051] It should be noted that, in the absence of conflict, the embodiments of the present invention and the features in the embodiments may be combined with each other.

[0052] The present invention will be further described below in conjunction with the accompanying drawings and specific embodiments, but they are not intended to limit the present invention.

[0053] See also Fig.13 The present invention provides a wide SOA shielded gate MOSFET device, comprising:

[0054] A substrate (1), an epitaxial layer (2) is grown on the surface of the substrate (1), a groove (3) is etched on the epitaxial layer (2), a shielding gate (5) is formed in the groove (3), a control gate (8) is provided on the shielding gate (5), the shielding gate (5) and the control gate (8) are separated by a first isolation dielectric layer (6), and a platform region is formed between the grooves (3);

[0055] A P-well region (9), and an N+ injection region (10) formed on the upper surface of the P-well region in the platform region, wherein the P-well region (9) includes a first P-well region (P1) formed only by general injection after forming the control gate (8);

[0056] A second isolation dielectric layer (11), covering the N+ implantation region (10);

[0057] A contact hole (12), the contact hole (12) penetrates the second isolation dielectric layer (11) and the N+ implantation region (10), and the bottom of the contact hole (12) forms a bottom contact region (13);

[0058] The MOSFET device is also characterized in that the P-well region (9) further includes a second P-well region (P2) formed by strip implantation after general implantation, and / or the distances between at least one contact hole (12) and the boundaries of adjacent trenches (3) are different.

[0059] The design concept proposed in this invention is to use the method of alternating heat conduction between hot and cold trench regions at the MOSFET cell level to enhance thermal stability, reduce the MOSFET ZTC point, thereby improving the linear mode working capability of the MOS tube and then expanding Figure 3 Coverage of the SOA Part 4 area is shown.

[0060] The present invention mainly has three design methods:

[0061] The first design method is to form a first P-well region (P1) and a second P-well region (P2) by two injections, one general injection and one strip injection, to form a cold and hot trench region design.

[0062] Generally, the second P-well region (P2) forms a cold trench region, and the first P-well region (P1) forms a hot trench region. The two PB injection methods are: one is a general injection method to form the total P-well region, and the second is a strip injection method, which further injects to form the second P-well region (P2). The total P-well region except the second P-well region (P2) is the first P-well region (P1). The doping concentration of the second P-well region (P2) is higher than that of the first P-well region (P1), forming a cold trench region.

[0063] The second design method is to form a cold and hot trench area design by offsetting the contact hole. The area with a smaller distance between the contact hole and the trench boundary forms a cold trench area, and the area with a larger distance between the contact hole and the trench boundary forms a hot trench area.

[0064] The third design method is to combine two injections, one general injection and one strip injection to form the first P-well region (P1) and the second P-well region (P2) and contact hole offset, that is, the combination of the first design method and the second design method, to form the design of cold trench region, secondary cold trench region, secondary hot trench region and hot trench region.

[0065] For example, the intersection area of ​​the second P-well region (P2) and the area with a smaller distance between the contact hole and the trench boundary forms a cold trench area, and the second P-well region (P2) and the area with a larger distance between the contact hole and the trench boundary form a secondary cold trench area. The intersection area of ​​the first P-well region (P1) and the area with a smaller distance between the contact hole and the trench boundary forms a secondary hot trench area, and the first P-well region (P1) and the area with a larger distance between the contact hole and the trench boundary form a hot trench area.

[0066] Specifically, the first and third design methods involve two P-well implantations, so the second P-well implantation requires an additional mask. The second design method only involves contact hole offset, and the original masking process can be used.

[0067] The hot channel region has a large transconductance (the degree of change of the voltage between the gate and the source to the drain current), the output current changes greatly with the voltage, and the threshold voltage (Vth) is the normal turn-on voltage. The cold channel region has a small transconductance, the output current changes little with the input voltage, and the threshold voltage (Vth) is relatively high. GS Under modulation, the conduction current I corresponding to the thermal trench area DS Large, large power consumption, so it is called hot channel, cold channel corresponding to the conduction current I DS The corresponding voltage is much smaller and the power consumption is small, so it is called cold channel. The area of ​​the fourth part of SOA, if the device is in the linear mode working area, the characteristic of this area is that the channel is not fully opened, and the device has to bear a large voltage drop V DS , but also have to bear a higher current I DS , the transient power consumption is particularly large.

[0068] The present invention forms a cold and hot trench area by design. The cold trench can provide uniform heat dissipation at the cell level for the hot trench, improve the thermal stability in the thermal design of the power device, and the cold trench area has a large threshold voltage Vth, which can reduce the zero temperature coefficient ZTC of the device. The cold and hot trenches work in parallel, and the overall turn-on voltage Vth of the device is still the low Vth of the hot trench, which does not affect the overall turn-on voltage customization of the device. Although the turn-on voltage of the cold trench part is high, the driving voltage V of the general device when it is normally turned on is GS It is about 3 times greater than the device threshold voltage Vth. When it is normally turned on, it has little effect on the on-voltage of the device, and it only exists in a certain small range, further compressing the impact on the on-resistance of the device.

[0069] In practical applications, the proportion of the cold trench area can be freely adjusted. The larger the proportion of the cold trench, the better the linear capability of the device. The larger the width of the fourth part SOA, the greater the impact on the on-resistance of the device. On the contrary, the smaller the proportion of the cold trench, the smaller the impact on the on-resistance of the device, but the improvement in linear capability is correspondingly reduced. In this way, we can adjust R according to different application requirements.DS It can freely and flexibly compromise with SOA and has good scalability of product series in segmented application fields.

[0070] Specifically, the substrate (1) is an N-type substrate, and the epitaxial layer (2) is an N-type epitaxial layer. Specifically, the bottom of the trench (3) formed by etching the epitaxial layer (2) remains in the epitaxial layer (2).

[0071] Specifically, a field oxide layer (4) is grown in the trench (3), and then polysilicon is filled in the trench and etched back to form a shielding gate (5).

[0072] Specifically, a first isolation dielectric layer (6) is formed in the groove (3) using HDP (High-Density Plasma) deposition technology, and the first isolation dielectric layer (6) is deposited on the upper surface of the shielding gate (5) and the upper surface of the field oxide layer (4). A gate oxide layer (7) is grown on the side surface and platform area of ​​the groove (3), and then polysilicon is filled in the groove (3) and etched back to form a control gate (8), and the first isolation dielectric layer (6) isolates the shielding gate (5) from the control gate (8).

[0073] After forming the control gate (8), a P-well general injection is performed, and then a P-well stripe injection is performed using a P-well mask to form a second P-well region (P2). The P-well region formed by the general injection except the second P-well region (P2) is the first P-well region (P1). After the two injections are completed, a P-well annealing is performed, or a first P-well general injection and annealing are performed, and a second P-well stripe injection and annealing are performed to form a P-well region.

[0074] Specifically, after the P well region is formed, NSD is implanted into the platform region between the two trenches (3) to form an N+ implant region (10), and after annealing, a second isolation dielectric (11) is deposited. NSD implantation belongs to the prior art and will not be described in detail here.

[0075] Specifically, after depositing the second isolation medium (11), photolithography and etching are performed using a hole mask to form a contact hole (12), and then hole injection and hole annealing are performed at the bottom of the contact hole (12) to form a hole bottom contact area (13).

[0076] After forming the hole bottom contact area (13), metal deposition, metal etching, passivation layer deposition and passivation layer etching are performed, which belong to the prior art and will not be described in detail here.

[0077] Specifically, Figure 5 and Figure 6 CONT in FIG. 1 represents a contact hole ( 12 ), and trench represents a groove ( 13 ).

[0078] like Figure 5As shown, further, when the MOSFET device has the characteristic that the distances between at least one contact hole (12) and the boundaries of the adjacent grooves (3) are different, and the cell of the MOSFET device is a strip-shaped cell, at least one contact hole (12) has the following characteristics: the distances between the contact hole (12) and the boundaries of the strip-shaped grooves (3) on the left and right sides are different.

[0079] Specifically, as the second design method, for a strip cell, the contact hole is cleverly offset in the MESA area (the platform area between the two grooves), and the area with a smaller distance between the contact hole and the groove boundary (narrow area) forms a cold groove area, and the area with a larger distance between the contact hole and the groove boundary (wide area) forms a cold groove area. The Mesa areas with different distance ratios (the distance ratio between the boundaries of the left and right grooves) are selected for contact hole offset to compromise R DS The balance relationship with SOA. The advantage of this design is that the process is simple and fully compatible with the original process. The disadvantage is that the Vth of the cold trench area is difficult to quantify.

[0080] To further conduct R DS Balanced relationship with SOA, such as Figure 6 As shown, in some cells, the contact holes are not offset to form a conventional groove region, that is, the distances between the contact holes and the boundaries of the adjacent grooves are equal, and in some cells, the contact holes are offset to form hot and cold groove regions.

[0081] In the strip-shaped cell, the lengths of the cold trench region and the hot trench region formed by contact hole offset are parallel to the length direction of the trench.

[0082] If the cell is a square cell, at least one contact hole in the device may be offset relative to the surrounding trenches. The specific number and position of the offset contact holes and the offset amount are determined according to actual applications.

[0083] Specifically, Figure 4 , Figure 14-17 Trench here stands for groove (13).

[0084] like Fig.14 As shown, further, when the characteristic of the MOSFET device includes a P-well region (9) and a second P-well region (P2) formed by strip injection after general injection, and the cell of the MOSFET device is a square cell, the boundary of the second P-well region (P2) is in the groove (3), and one second P-well region (P2) covers one or more complete cells.

[0085] For a square cell, the boundary of the second P-well region is always in the groove (3) (i.e. Fig.14 In the trench, one or more complete cells are enclosed, and the injection area can be arranged according to the design objectives. Figure 4As shown, six cells in one row are wrapped by the second P-well region (P2), and cells in the second row are not wrapped by the second P-well region (P2), that is, they are part of the first P-well region (P1), and the first P-well region P1 and the second P-well region P2 exist in an alternating manner.

[0086] like Figure 4 As shown, further, when the characteristic of the MOSFET device includes the P-well region (9) and also includes a second P-well region (P2) formed by strip implantation after the general implantation method, and the cell of the MOSFET device is a strip-shaped cell, the second P-well region (P2) is in the shape of a strip;

[0087] The length direction of each second P-well region (P2) is perpendicular to the length direction of the trench (3).

[0088] A plurality of second P-well regions (P2) in strip shape are arranged along the length direction of the trench (3), and can be arranged at equal intervals or at unequal intervals, and can be arranged evenly or non-uniformly.

[0089] The boundary of the second P-well region (P2) parallel to the length direction of the trench (3) (for example, the width boundary of the strip-shaped second P-well region) is in the trench (3).

[0090] like Fig.15 As shown, further, when the characteristic of the MOSFET device is that the P-well region (9) also includes a second P-well region formed by strip implantation after the general implantation method, and the cell of the MOSFET device is a strip-shaped cell, the second P-well region is a strip-like shape;

[0091] The length direction of each second P-well region is perpendicular to the length direction of the trench (3), and the second P-well region is divided into a plurality of sections along the length direction, and the widths of two adjacent sections are different.

[0092] Specifically, the widths of two segments separated by one segment are equal.

[0093] The widths of the two adjacent sections of the strip-shaped second P-well region are different, that is, there is a step-shaped boundary between the two adjacent sections, and the step-shaped boundary is parallel to the length direction of the groove (3). Specifically, the boundary of each second P-well region parallel to the length direction of the groove (3) is in the groove (3).

[0094] Specifically, a plurality of strip-shaped second P-well regions (P2) are arranged along the length direction of the trench (3), and may be arranged at equal intervals or at unequal intervals, and may be arranged evenly or non-evenly.

[0095] Figure 4 and Fig.15 The diagram shows a situation where the length direction of the second P-well region (P2) and the length direction of the trench (3) are designed to be perpendicular.

[0096] Figure 16-17 The diagram shows a case where the length direction of the second P-well region (P2) and the length direction of the trench (3) are designed to be parallel.

[0097] Furthermore, when the characteristic of the MOSFET device includes the P-well region (9) and also includes a second P-well region (P2) formed by strip implantation after general implantation, and the cell of the MOSFET device is a strip-shaped cell, the second P-well region (P2) is in the shape of a strip;

[0098] The length direction of each second P-well region (P2) is parallel to the length direction of the trench (3). Fig.16 As shown, further, a boundary on the second P-well region (P2) parallel to the length direction of the groove (3) is located in a platform region between two adjacent grooves (13).

[0099] Specifically, the boundary of the second P-well region (P2) in the length direction of the vertical trench (13) may be flush with both ends of the trench (13).

[0100] Specifically, a plurality of second P-well regions (P2) are arranged at a certain distance along the length direction of the groove (13). For example, a second P-well region (P2) surrounds a groove (13), and there are two grooves (13) between two adjacent second P-well regions (P2).

[0101] like Fig.17 As shown, further, a boundary on the second P-well region (P2) parallel to the length direction of the trench (3) is in the trench (13).

[0102] Specifically, the boundary of the second P-well region (P2) in the length direction of the vertical trench (13) may be flush with both ends of the trench (13).

[0103] Specifically, a plurality of second P-well regions (P2) are arranged at a certain distance along the length direction of the groove (13). For example, the second P-well region (P2) wraps the platform region of two adjacent grooves (13), and there is one groove (13) between two adjacent second P-well regions (P2).

[0104] Furthermore, when the characteristic of the MOSFET device exists in the P-well region (9) and also includes a second P-well region formed by performing strip implantation after the general implantation method;

[0105] The ratio between the total area of ​​the second P-well region and the total area of ​​the first P-well region is 1:4 to 1:3.

[0106] The window area of ​​the second layer of the tape injection method defines the corresponding ratio of the hot and cold grooves, and the preferred ratio of the hot and cold grooves is 1:3 to 1:4. DSThe impact on the linear capacity is <10%, and the improvement on the linear capacity is >20%.

[0107] See also Figure 7-Figure 13 , Fig.18 The present invention provides a method for preparing a wide SOA shielded gate MOSFET device, which is used to prepare the aforementioned wide SOA shielded gate MOSFET device, comprising:

[0108] Step A1, preparing a substrate (1), growing an epitaxial layer (2) on the surface of the substrate (1), etching grooves (3) on the epitaxial layer (2), and forming platform regions between the grooves (3);

[0109] Step A2, forming a shielding gate (5) in the trench (3);

[0110] Step A3, forming a first isolation dielectric layer (6) on the shielding grid (5);

[0111] Step A4, forming a control gate (8) on the first isolation dielectric layer (6);

[0112] Step A5, forming a P-well region (9), the P-well region (9) including a first P-well region formed only by general injection after forming the control gate (8);

[0113] Step A6, forming an N+ implantation region (10) on the upper surface layer of the P-well region of the platform region;

[0114] Step A7, forming a second isolation dielectric layer (11), wherein the second isolation dielectric layer (11) covers the N+ implantation region (10);

[0115] Step A8, forming a contact hole (12), wherein the contact hole (12) penetrates the second isolation dielectric layer (11) and the N+ implantation region (10), and the bottom of the contact hole (12) forms a bottom contact region (13);

[0116] The formed MOSFET device is also characterized by: the P-well region (9) further comprising a second P-well region formed by strip implantation after general implantation, and / or the distances between at least one contact hole (12) and the boundaries of adjacent trenches (3) are different.

[0117] Specifically, in step A1, the substrate (1) is an N-type substrate, and the epitaxial layer (2) is an N-type epitaxial layer. Specifically, the bottom of the trench (3) formed by etching the epitaxial layer (2) remains in the epitaxial layer (2).

[0118] Specifically, in step A2, a field oxide layer (4) is grown in the trench (3), and then polysilicon is filled in the trench and etched back to form a shielding gate (5).

[0119] Specifically, in step A3, a first isolation dielectric layer (6) is formed in the groove (3) using HDP (High-Density Plasma) deposition technology, and the first isolation dielectric layer (6) is deposited on the upper surface of the shielding gate (5) and the upper surface of the field oxide layer (4).

[0120] Specifically, in step A4, a gate oxide layer (7) is first grown on the side surface and platform area of ​​the trench (3), and then polysilicon is filled in the trench (3) and etched back to form a control gate (8), and a first isolation dielectric layer (6) isolates the shielding gate (5) from the control gate (8).

[0121] Specifically, in step A5, after forming the control gate (8), a P-well general injection is performed, and then a P-well stripe injection is performed using a P-well mask to form a second P-well region. The P-well region formed by the general injection except the second P-well region is the first P-well region. After the two injections are completed, a P-well annealing is performed, or a first P-well general injection and annealing are performed, and a second P-well stripe injection and annealing are performed to form a P-well region.

[0122] Specifically, in step A6, after the P well region is formed, NSD implantation is performed in the platform region between the two trenches (3) to form an N+ implantation region (10). After annealing, in step A7, a second isolation dielectric (11) is deposited.

[0123] Specifically, in step A8, after depositing the second isolation medium (11), photolithography and etching are performed using a hole mask to form a contact hole (12), and then hole injection and hole annealing are performed at the bottom of the contact hole (12) to form a hole bottom contact area (13).

[0124] After step A8, after the hole bottom contact area (13) is formed, metal deposition, metal etching, passivation layer deposition and passivation layer etching are performed, which belong to the prior art and will not be described in detail here.

[0125] For the technical solution with contact hole offset, the contact hole offset is completed in step A8, and a hole mask is used to perform photolithography and etching to form the contact hole.

[0126] The above are only preferred embodiments of the present invention, and are not intended to limit the implementation methods and protection scope of the present invention. Those skilled in the art should be aware that all solutions obtained by equivalent substitutions and obvious changes made using the description and illustrations of the present invention should be included in the protection scope of the present invention.

Claims

1. A wide SOA shielded gate MOSFET device, characterized in that: include: A substrate, wherein an epitaxial layer is grown on the surface of the substrate, a groove is etched on the epitaxial layer, a shielding gate is formed in the groove, a control gate is arranged on the shielding gate, the shielding gate and the control gate are separated by a first isolation dielectric layer, and a platform area is formed between the grooves; A P-well region, and an N+ injection region formed on the upper surface of the P-well region in the platform region, wherein the P-well region includes a first P-well region formed only by general injection after forming the control gate; A second isolation dielectric layer covering the N+ implantation region; A contact hole, wherein the contact hole penetrates the second isolation dielectric layer and the N+ implantation region, and the bottom of the contact hole forms a bottom contact region; The MOSFET device is also characterized in that: the P-well region further includes a second P-well region formed by strip implantation after general implantation, and / or the distances between at least one of the contact holes and the boundaries of the adjacent trenches are different.

2. A wide SOA shielded gate MOSFET device as claimed in claim 1, characterized in that: When the MOSFET device is characterized in that the distances between at least one contact hole and the boundary of the adjacent groove are different, and the cell of the MOSFET device is a strip cell, at least one contact hole has: the distances between the contact hole and the boundaries of the strip grooves on the left and right sides are different.

3. A wide SOA shielded gate MOSFET device as claimed in claim 1, characterized in that: When the characteristic of the MOSFET device is that the P-well region also includes a second P-well region formed by strip injection after general injection, and the cell of the MOSFET device is a square cell, the boundary of the second P-well region is in the groove, and one second P-well region covers one or more complete cells.

4. A wide SOA shielded gate MOSFET device as claimed in claim 1, characterized in that: When the MOSFET device is characterized in that the P-well region further includes a second P-well region formed by strip implantation after general implantation, and the cell of the MOSFET device is a strip-shaped cell, the second P-well region is in a strip shape; The length direction of each of the second P-well regions is perpendicular to the length direction of the trench.

5. A wide SOA shielded gate MOSFET device as claimed in claim 1, characterized in that: When the MOSFET device is characterized in that the P-well region further includes a second P-well region formed by performing strip implantation after general implantation, and the cell of the MOSFET device is a strip-shaped cell, the second P-well region is a strip-like shape; The length direction of each of the second P-well regions is perpendicular to the length direction of the trench, and the second P-well region is divided into a plurality of sections along the length direction, and the widths of two adjacent sections are different.

6. A wide SOA shielded gate MOSFET device as claimed in claim 1, characterized in that: When the MOSFET device is characterized in that the P-well region further includes a second P-well region formed by strip implantation after general implantation, and the cell of the MOSFET device is a strip-shaped cell, the second P-well region is in a strip shape; A length direction of each of the second P-well regions is parallel to a length direction of the trench.

7. A wide SOA shielded gate MOSFET device as claimed in claim 6, characterized in that: The boundary of the second P-well region parallel to the length direction of the trench is located in a platform region between two adjacent trenches.

8. A wide SOA shielded gate MOSFET device as claimed in claim 6, characterized in that: A boundary on the second P-well region parallel to the length direction of the trench is in the trench.

9. A wide SOA shielded gate MOSFET device as claimed in claim 1, characterized in that: When the characteristic of the MOSFET device is that the P-well region also includes a second P-well region formed by strip implantation after general implantation; The ratio between the total area of ​​the second P-well region and the total area of ​​the first P-well region is 1:4 to 1:

3.

10. A method for preparing a wide SOA shielded gate MOSFET device, characterized in that: A method for preparing a wide SOA shielded gate MOSFET device as claimed in any one of claims 1 to 9, comprising: Step A1, preparing a substrate, growing an epitaxial layer on the surface of the substrate, etching grooves on the epitaxial layer, and forming platform regions between the grooves; Step A2, forming a shielding gate in the trench; Step A3, forming a first isolation dielectric layer on the shielding grid; Step A4, forming a control gate on the first isolation dielectric layer; Step A5, forming a P-well region, wherein the P-well region includes a first P-well region formed only by general injection after forming the control gate; Step A6, forming an N+ implantation region on the upper surface layer of the P-well region in the platform region; Step A7, forming a second isolation dielectric layer, wherein the second isolation dielectric layer covers the N+ implantation region; Step A8, forming a contact hole, wherein the contact hole penetrates the second isolation dielectric layer and the N+ implantation region, and the bottom of the contact hole forms a bottom contact region; The features of the MOSFET device formed therein also include: the P-well region also includes a second P-well region formed by strip implantation after general implantation, and / or the distances between at least one of the contact holes and the boundaries of the adjacent trenches are different.

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