Radiation-proof SiC power MOSFET device and preparation method thereof

Abstract

The invention relates to the technical field of power devices, in particular to an anti-radiation SiC power MOSFET device and a preparation method thereof.The cellular structure of the device sequentially comprises a substrate and a drift layer from bottom to top, and the drift layer internally comprises a base buffer layer and a step buffer layer; the step buffer layer comprises a first step buffer layer and a second step buffer layer; the base buffer layer is arranged on the substrate and covers the substrate; at least two first step buffer layers are arranged on the substrate buffer layer side by side, and a second step buffer layer is arranged on each first step buffer layer; the width of the first step buffer layer is greater than that of the second step buffer layer; the doping concentration of the step buffer layer is larger than the doping concentration of the drift layer, smaller than or equal to the doping concentration of the base buffer layer and smaller than the doping concentration of the substrate. The step buffer layer is arranged in the drift layer, and the area of the step buffer layer is relatively smaller, so that the influence on the drop of breakdown voltage and the increase of leakage current is smaller, and the SEB threshold voltage is higher.

Description

Technical Field

[0001] The present invention relates to the technical field of power devices, and in particular to a radiation-resistant SiC power MOSFET device and a preparation method thereof. Background Art

[0002] At present, wide bandgap semiconductor materials have become a hot topic of research due to their excellent material properties. Among them, wide bandgap semiconductors represented by silicon carbide (SiC) have developed rapidly and have gradually replaced silicon-based semiconductor devices in some fields. Compared with traditional semiconductor materials, SiC materials have advantages such as wide bandgap, high thermal conductivity, high critical breakdown field strength and high carrier saturation velocity, so they are more suitable for working under high temperature, high pressure and high frequency.

[0003] Irradiation effect refers to the impact of radiation on devices. For power devices, radiation can change the working characteristics of power devices and even completely destroy the devices. In extreme working environments such as spacecraft and reactors, there are many high-energy particles and rays, such as protons, neutrons, electrons, alpha particles, heavy ions, gamma rays, etc., which will produce large radiation effects on power devices, such as single event effect (SEE) and total ionizing dose effect (TID).

[0004] As the application scope of SiC MOSFET devices is becoming increasingly wide, some SiC MOSFET devices are used in relatively harsh environments such as nuclear power and aerospace. SiC MOSFET devices are easily affected by radiation when operating in these environments, resulting in radiation effects such as single particle effects, causing performance degradation of SiC MOSFET devices and even catastrophic consequences. In order to ensure the stable and reliable operation of SiC MOSFET in an irradiated environment, it is required to have a high radiation resistance in the irradiated environment. Therefore, it is necessary to strengthen the cell structure of SiC MOSFET to improve its radiation resistance. Summary of the invention

[0005] In order to solve the above technical problems, a radiation-resistant SiC power MOSFET device and a preparation method thereof are provided. The present invention adopts a multi-layer step-type buffer layer structure to improve the radiation resistance of SiC MOSFET.

[0006] To achieve the above objectives, the present invention is implemented through the following technical solutions:

[0007] A radiation-resistant SiC power MOSFET device, wherein the cell structure of the device comprises, from bottom to top, an N+ substrate and an N-drift layer;

[0008] The N-drift layer includes a base buffer layer and a step buffer layer from bottom to top;

[0009] The step buffer layer includes a first step buffer layer and a second step buffer layer;

[0010] The base buffer layer is disposed on and covers the N+ substrate;

[0011] At least two first step buffer layers are arranged side by side on the base buffer layer, and one second step buffer layer is arranged on each of the first step buffer layers;

[0012] Let the width of the first step buffer layer be W st1 The width of the second step buffer layer is W st2 , then W is satisfied st1 >W st2 ;

[0013] The doping concentration of the step buffer layer is greater than the doping concentration of the N-drift layer, less than or equal to the doping concentration of the base buffer layer, and less than the doping concentration of the N+ substrate.

[0014] Furthermore, the W st1 The value range is 0.5-3μm, the W st2 The value of W st1 30% to 60% of the value of; the thickness of the first step buffer layer and the second step buffer layer are respectively in the range of 0.2-0.8μm, and preferably the thickness of both are 0.5μm.

[0015] Preferably, the W st1 The value of W is 1.4-2.6μm. st2 The value of W st1 More preferably, the W st1 The value of W is 1.8-2.4μm. st2 The value of W st1 50% of the value.

[0016] Furthermore, the doping concentration of the first stepped buffer layer is greater than or equal to the doping concentration of the second stepped buffer layer, and the doping concentration of the first stepped buffer layer is 8×10 16 cm -3 ~1.2×10 17 cm -3 .

[0017] Furthermore, the thickness of the N-drift layer is 8-20 μm, and the doping concentration of the N-drift layer is 8×10 15 cm -3～ 2×1016 cm -3 ; The doping concentration of the N+ substrate is 1×10 19 cm -3～ 5×10 19 cm -3 The thickness of the base buffer layer is 0.8-1.2 μm and the doping concentration is 1.5×10 17 cm -3～ 5.5×10 17 cm -3 .

[0018] Further, the cell structure further includes an oxide layer, a gate electrode G and a source electrode S arranged above the N-drift layer;

[0019] The gate electrode G is arranged inside the oxide layer, and the source electrode S is distributed on both sides of the oxide layer, that is, the oxide layer serves as an insulator to isolate the source electrode from the gate;

[0020] The cell structure further includes: a P-body region disposed on both sides of the N-drift layer, wherein an N+ source region is disposed in the P-body region on each side, and a portion of the P-body region excluding the N+ source region is the P+ source region;

[0021] The P-body region covers part of the oxide layer and part of the source electrode S and contacts both of them; and the N+ source region covers part of the oxide layer and part of the source electrode S and contacts both of them;

[0022] The internal space formed by the P-body regions on both sides forms a JFET region;

[0023] The cell structure further includes a drain electrode D disposed below the substrate. This part of the structure is the same as the conventional one.

[0024] Another aspect of the present invention provides a method for preparing the above-mentioned radiation-resistant SiC power MOSFET device, comprising the following steps:

[0025] Providing an N+ substrate, epitaxially growing a base buffer layer and a cache layer on the surface of the N+ substrate in sequence, performing ion implantation on the cache layer to form a step buffer layer, and then continuing epitaxial growth to form an N-drift layer;

[0026] The ion implantation is to form the cache layer into a first step buffer layer and a second step buffer layer with decreasing widths in sequence, wherein the first step buffer layer and the second step buffer layer constitute the step buffer layer; the doping concentration of the step buffer layer is greater than the doping concentration of the N-drift layer and less than the doping concentration of the N+ substrate;

[0027] The P-body region, the N+ source region, the oxide layer, the gate electrode G, the source electrode S and the drain electrode D are fabricated according to conventional methods.

[0028] Beneficial technical effects:

[0029] In the traditional SiC MOSFET structure, the electric field after the particle is incident is concentrated at the junction of the drift region and the substrate, and a high electric field area is formed at the junction of the drift region and the substrate on the particle incident trajectory. After adding the step buffer structure of the structure of the present invention, the electric field diffuses into the drift region and the buffer layer region, and the local high electric field at the junction of the drift region and the substrate on the incident trajectory disappears. The electric field of the device without a buffer layer forms a spike at the junction of the drift region and the substrate, which can easily lead to device breakdown. The peak of the electric field in the step buffer layer reinforcement structure of the present invention is reduced, and the electric field spike is transferred from the substrate to the buffer layer. Therefore, the step buffer reinforcement structure of the present invention can effectively change the electric field distribution and reduce the electric field peak. The present invention sets a step buffer structure in the drift layer. Since the area of ​​this buffer layer is smaller than that of the traditional double-layer buffer layer structure, it has less impact on the decrease of breakdown voltage and the increase of leakage current, has a higher SEB threshold voltage, and has better resistance to single radiation. BRIEF DESCRIPTION OF THE DRAWINGS

[0030] Figure 1 Schematic diagram of the cell structure of a radiation-resistant SiC power MOSFET device of the present invention, wherein 1: N+ substrate, 2: N-drift layer, 21: base buffer layer, 22: first step buffer layer, 23: second step buffer layer, 24: P-body region, 25: N+ source region, 3: oxide layer, 4: gate electrode G, 5: source electrode S, 6: drain D; W st1 : Width of the first step buffer layer, W st2 : The width of the second step buffer layer, L st1 : The thickness of the first step buffer layer, L st2 : The thickness of the second step buffer layer;

[0031] Figure 2 The present invention is a flow chart of a preparation process of a radiation-resistant SiC power MOSFET device; wherein N+Substrate represents an N+ substrate, N Buffer 1 represents a substrate buffer layer, N Buffer 2 represents a buffer layer, Step Buffer 1 represents a first step buffer layer, Step Buffer 2 represents a second step buffer layer, N-Drift represents an N-drift layer, P-body represents a P-body region, N+ represents an N+ source region, Oxide represents an oxide layer, Gate represents a gate electrode G, Source represents a source electrode S, and Drain represents a drain electrode D;

[0032] Figure 3The doping concentration of the first step buffer layer and the second step buffer layer is 1.2×10 17 cm -3 A curve diagram showing the influence of the width of the first step buffer layer on the SEB threshold voltage under the condition; wherein the abscissa represents the width of the first step buffer layer, and the ordinate represents the SEB threshold voltage of the device;

[0033] Figure 4 It is a curve diagram of the influence of the doping concentration of the first step buffer layer on the SEB threshold voltage under the conditions that the width of the first step buffer layer is 2 microns and the width of the second step buffer layer is 1 micron; wherein the abscissa represents the doping concentration of the first step buffer layer, and the ordinate represents the SEB threshold voltage of the device. DETAILED DESCRIPTION

[0034] The technical solutions in the embodiments of the present invention will be described clearly and completely below in combination with the embodiments of the present invention and the accompanying drawings. Obviously, the described embodiments are only part of the embodiments of the present invention, rather than all of the embodiments. The following description of at least one exemplary embodiment is actually only illustrative and is by no means intended to limit the present invention and its application or use. All other embodiments obtained by ordinary technicians in this field without creative work based on the embodiments of the present invention are within the scope of protection of the present invention.

[0035] Unless otherwise specifically stated, the numerical value set forth in these embodiments does not limit the scope of the present invention. The technology and method known to those of ordinary skill in the relevant art may not be discussed in detail, but in appropriate cases, the technology and method should be considered as a part of the specification. In all examples shown and discussed here, any specific value should be interpreted as being merely exemplary, rather than as a limitation. Therefore, other examples of exemplary embodiments may have different values.

[0036] The experimental methods in the following examples without specifying specific conditions are usually measured in accordance with national standards; if there is no corresponding national standard, the method is carried out in accordance with the general standard requirements or general methods.

[0037] Example 1

[0038] A radiation-resistant SiC power MOSFET device, the cell structure of the device is as follows Figure 1 As shown, it includes, from bottom to top: an N+ substrate 1 and an N- drift layer 2;

[0039] The N-drift layer 2 includes a base buffer layer 21 and a step buffer layer with doping concentrations decreasing from bottom to top;

[0040] The step buffer layer includes a first step buffer layer 22 and a second step buffer layer 23;

[0041] The base buffer layer 21 is disposed on the N+ substrate 1 and covers it; the thickness of the base buffer layer 21 is 1 μm, and the doping concentration of the base buffer layer is 1.8×10 17 cm -3 ;

[0042] Two first step buffer layers 22 are arranged side by side on the base buffer layer 21 , and one second step buffer layer 23 is arranged on each of the first step buffer layers 22 ;

[0043] W st1 represents the width of the first stepped buffer layer 22, L st1 represents the thickness of the first stepped buffer layer 22; W st2 represents the width of the second stepped buffer layer 23, L st2 represents the thickness of the second step buffer layer 23; respectively set W st1 =0.8μm, 1.0μm, 1.2μm, 1.4μm, 1.6μm, 1.8μm, 2.0μm, 2.2μm, 2.4μm, 2.6μm, 2.8μm, W st2 =1μm, L st1 =0.5μm, L st2 =0.5 μm; the ion doping concentration of the first step buffer layer 22 and the second step buffer layer 23 are both set to 1.2×10 17 cm -3 ;

[0044] The total thickness of the N-drift layer 2 is 11.5 μm (including each buffer layer), and the doping concentration of the N-drift layer 2 is 9.5×10 15 cm -3 ;

[0045] The doping concentration of the N+ substrate 1 is 1×10 19 cm -3 ;

[0046] The cell structure further includes an oxide layer 3, a gate electrode G4 and a source electrode S5 arranged above the N-drift layer 2; the gate electrode G4 is arranged inside the oxide layer 3, and the source electrode S5 is distributed on both sides of the oxide layer 3, that is, the oxide layer 3 acts as an insulator to isolate the source and the gate;

[0047] The cell structure further includes: a P-body region 24 disposed on both sides of the N-drift layer 2, wherein an N+ source region 25 is disposed in the P-body region 24 on each side, and the portion of the P-body region 24 excluding the N+ source region 25 is the P+ source region; the P-body region 24 covers a portion of the oxide layer 3 and a portion of the source electrode S5 and contacts the two; and the N+ source region 25 covers a portion of the oxide layer 3 and a portion of the source electrode S5 and contacts the two; the ion doping concentration of the P-body region is 1×10 16 cm -3 ~4×10 18 cm -3 , a width of 2.4 μm, a depth of 1.2 μm, and an ion doping concentration of the N+ source region of about 2×10 19 cm -3 , width 1.6μm, depth 0.35μm;

[0048] The internal space formed by the P-body regions 24 on both sides forms a JFET region;

[0049] The cell structure further includes a drain D 6 disposed below the substrate.

[0050] The preparation process of the radiation-resistant SiC power MOSFET device in this case is as follows, the flow chart is as follows Figure 2 As shown:

[0051] S1, as shown in Figure (a), firstly, epitaxial growth is performed on an N+ substrate to form a base buffer layer (i.e., N Buffer1), and P ions are implanted into it, and the ion doping concentration is controlled by controlling the time of ion implantation;

[0052] Then the buffer layer (i.e., N Buffer 2) is epitaxially grown again;

[0053] S2, as shown in Figure (b), the cache layer is then implanted with P ions, and the time of ion implantation and the width of the ion implantation area are controlled so that the cache layer is transformed into a W st1 and L st1 , W st2 and L st2 A step buffer layer with parameters, wherein the step buffer layer includes a first step buffer layer and a second step buffer layer, and the ion doping concentrations of the first step buffer layer and the second step buffer layer are the same;

[0054] Then, epitaxial growth is continued on the surface of the base buffer layer and the step buffer layer to obtain an N-drift layer (i.e., N-Drift);

[0055] S3, as shown in FIG. (c), a P-body region is first formed on both sides of the surface of the N-drift layer by ion implantation; an N+ source region is then formed by ion implantation in the P-body region, and the concentration, width and depth parameters of each layer are controlled by controlling the ion implantation time and the ion implantation area width;

[0056] S4, as shown in FIG. (d), a thin oxide layer (i.e., Oxide) is grown on the surface of the N-drift layer by oxidation;

[0057] S5, as shown in Figure (e), polysilicon is then deposited on the surface of the thin oxide layer, and the two sides of the polysilicon are etched away. After etching, a gate electrode G (i.e., Gate) is formed in the middle area of ​​the thin oxide layer. The width of the gate electrode G is sufficient to cover the N+ source regions on both sides;

[0058] The surface is oxidized again to form an oxide layer, which serves as an insulator to isolate the gate from the source formed by subsequent metallization;

[0059] S6. As shown in Figure (f), metal is evaporated on the surface of the oxide layer to form a metallization layer for front ohmic contact. After etching the metallization layer in the middle area, source electrodes S (i.e., Source) are obtained on both sides, and then metal is sputtered on the back to form a drain D.

[0060] Example 2

[0061] The device structure and preparation method of this case are the same as those of Example 1, except that W st1 =2.0 μm, and the doping concentration is controlled by controlling the ion implantation time, so that the doping concentration of the first stepped buffer layer 22 is 2.0×10 16 cm -3 4.0×10 16 cm -3 , 6.0×10 16 cm -3 8.0×10 16 cm -3 , 1.0×10 17 cm -3 , 1.2×10 17 cm -3 , 1.4×10 17 cm -3 , 1.6×10 17 cm -3 , 1.8×10 17 cm -3 .

[0062] Comparative Example 1

[0063] The device structure and preparation method of this case are the same as those of Example 1, except that: in terms of structure: there is no step buffer layer, in the preparation method: after forming the base buffer layer and the upper buffer layer in step S1, steps S3-S6 are directly performed, and the thickness of the N-drift region (including the base buffer layer and the cache layer) is 11.5 μm, and the doping concentration of the N-drift region is 9.5×10 15 cm -3 The thickness of the base buffer layer is 1 μm and the doping concentration is 1.8×10 17 cm -3 The thickness of the upper buffer layer is 1 μm and the doping concentration is 1.2×10 17 cm -3 .

[0064] The devices of the embodiment and the comparative example were subjected to SEB threshold voltage test, and the results are shown in Table 1. Figure 3 and Figure 4 This test was implemented through the TCAD simulation method. In the physical model, LET was added as 0.1pC / μm, the ion incident position was at the center of the gate, and the maximum incident distance was 12μm. By performing voltage test simulations on buffer layer devices with different widths and doping concentrations, the minimum voltage value of SEB occurring in different devices after the above ion incident was obtained, that is, the SEB threshold voltage was measured.

[0065] Table 1 SEB threshold voltage of each device

[0066]

[0067]

[0068] From Table 1, Figure 3 It can be seen that when the width of the first step buffer layer is small, the SEB threshold voltage increases as its width increases. However, when the width of the first step buffer layer exceeds 2.0μm, the SEB threshold voltage begins to gradually decrease. The highest SEB threshold voltage occurs when the width of the first step buffer layer is 2μm, reaching 670V. This is because at a smaller width, the step buffer layer (i.e., including the first step buffer layer and the second step buffer layer) can more effectively modulate the electric field and suppress the collision ionization rate, thereby increasing the SEB threshold voltage.

[0069] From Table 1, Figure 4 It can be seen that when the width of the step buffer layer is fixed, the SEB threshold voltage first increases and then decreases with the increase of the doping concentration of the first step buffer layer. The highest threshold voltage occurs when the doping concentration of the first step buffer layer is 1.2×10 17 cm -3 hour.

[0070] In summary, the SEB threshold voltage of the step buffer layer structure with the best reinforcement effect is 670 V, corresponding to the width of the first step buffer layer of 2 μm and 1.2×10 17 cm -3 These parameters can be used to improve radiation resistance during design and manufacturing.

[0071] The present invention significantly reduces the peak electric field intensity by designing a multi-layer buffer layer structure in the drift region, and due to the high electric field transfer caused by the base widening effect of the internal parasitic bipolar junction transistor, the electric field peak is transferred to the drift region and the buffer layer junction, and the high electric field area is dispersed, reducing the concentration of the electric field. In addition, the high electric field intensity of the set step buffer layer is more dispersed, especially the peak electric field, which will not be concentrated at one depth, but will present an "M" type distribution. This is because the peak electric field generally appears at the drift region and the buffer layer junction, and the steps of the step buffer layer make its junction with the drift region present an "M" type, which disperses the electric field peak, and further disperses the distribution of the electric field in the buffer layer, reducing the collision ionization rate. These features make the device have better radiation resistance and a higher SEB threshold voltage.

[0072] The above description is only a preferred specific implementation manner of the present invention, but the protection scope of the present invention is not limited thereto. Any technician familiar with the technical field can make equivalent replacements or changes according to the technical scheme and inventive concept of the present invention within the technical scope disclosed by the present invention, which should be covered by the protection scope of the present invention.

Claims

1. A radiation-resistant SiC power MOSFET device, wherein the cell structure of the device comprises an N+ substrate and an N-drift layer from bottom to top, characterized in that: The N-drift layer includes a base buffer layer and a step buffer layer from bottom to top; The step buffer layer includes a first step buffer layer and a second step buffer layer; The base buffer layer is disposed on and covers the N+ substrate; At least two first step buffer layers are arranged side by side on the base buffer layer, and one second step buffer layer is arranged on each of the first step buffer layers; Let the width of the first step buffer layer be W st1 The width of the second step buffer layer is W st2 , then W is satisfied st1 >W st2 ; The doping concentration of the step buffer layer is greater than the doping concentration of the N-drift layer, less than or equal to the doping concentration of the base buffer layer, and less than the doping concentration of the N+ substrate.

2. A radiation-resistant SiC power MOSFET device according to claim 1, characterized in that: The W st1 The value range is 0.5-3μm, the W st2 The value of W st1 30% to 60% of the value.

3. A radiation-resistant SiC power MOSFET device according to claim 2, characterized in that: The W st1 The value of W is 1.4-2.6μm. st2 The value of W st1 40% to 50% of the value.

4. The radiation-resistant SiC power MOSFET device according to claim 3, characterized in that: The W st1 The value of W is 1.8-2.4μm. st2 The value of W st1 50% of the value.

5. A radiation-resistant SiC power MOSFET device according to any one of claims 1 to 4, characterized in that: The doping concentration of the first stepped buffer layer is greater than or equal to the doping concentration of the second stepped buffer layer, and the doping concentration of the first stepped buffer layer is 8×10 16 cm -3 ~1.2×10 17 cm -3 .

6. The radiation-resistant SiC power MOSFET device according to claim 5, characterized in that: The thickness of the base buffer layer is 0.8-1.2 μm and the doping concentration is 1.5×10 17 cm -3～ 5.5×10 17 cm -3 .

7. The radiation-resistant SiC power MOSFET device according to claim 5, characterized in that: The cell structure further includes an oxide layer, a gate electrode G and a source electrode S disposed above the N-drift layer; The gate electrode G is disposed inside the oxide layer, and the source electrode S is distributed on both sides of the oxide layer, that is, the oxide layer serves as an insulator to isolate the source electrode from the gate electrode.

8. The radiation-resistant SiC power MOSFET device according to claim 5, characterized in that: The cell structure further includes a P-body region disposed on both sides of the N-drift layer, wherein an N+ source region is disposed in the P-body region on each side, and a portion of the P-body region excluding the N+ source region is the P+ source region; The P-body region covers part of the oxide layer and part of the source electrode S and contacts both of them; and the N+ source region covers part of the oxide layer and part of the source electrode S and contacts both of them; The internal space formed by the P-body regions on both sides forms a JFET region; The cell structure further includes a drain D disposed below the substrate.

9. The method for preparing a SiC power MOSFET device according to any one of claims 1 to 8, characterized in that: The steps include: Providing an N+ substrate, epitaxially growing a base buffer layer and a cache layer on the surface of the N+ substrate in sequence, performing ion implantation on the cache layer to form a step buffer layer, and then continuing epitaxial growth to form an N-drift layer; The ion implantation is to form the cache layer into a first step buffer layer and a second step buffer layer with successively decreasing widths, wherein the first step buffer layer and the second step buffer layer constitute the step buffer layer; The doping concentration of the step buffer layer is greater than the doping concentration of the N-drift layer and less than the doping concentration of the N+ substrate.

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