Method for manufacturing electrode in semiconductor functional area and semiconductor device

Abstract

The invention provides a method for manufacturing an electrode in a semiconductor functional area and a semiconductor device, and relates to the technical field of semiconductors, and according to the method, exposure of the side face of the functional area is prior to manufacturing of a first electrode, so that damage to the electrode caused by wet etching is avoided. On the basis, additional deposition of a medium protection layer before the second electrode layer is formed is avoided, and the condition that the contact between the second electrode layer and the side face of the exposed functional area is affected due to the fact that the medium protection layer grows on the side face of the exposed functional area is avoided. And by utilizing the etching selectivity of the second electrode layer and the first electrode, part of the second electrode layer is removed in the etching process, so that the remaining second electrode layer forms a second electrode, and meanwhile, the first electrode is also reserved, so that the second electrode is in contact with the side surface of the exposed functional area. Certainly, the process of firstly manufacturing the first electrode and then manufacturing the second electrode can be realized, and the influence of high-temperature annealing of the first electrode on the second electrode is effectively avoided.

Description

Technical Field

[0001] The present application relates to the field of semiconductor technology, and in particular to a method for manufacturing electrodes in a semiconductor functional region and a semiconductor device. Background Art

[0002] At present, when semiconductor devices are processed on wafers, the area used to realize the chip function (hereinafter referred to as the semiconductor functional area or functional area) is generally on the surface of the wafer. Therefore, the chip electrodes are usually made on the front side of the semiconductor functional area, such as Figure 1 The figure shows a conventional three-electrode semiconductor device, that is, a source electrode 2, a gate electrode 4 and a drain electrode 3 are formed on the top surface of the device in a horizontal direction at intervals.

[0003] However, with the gradual development of technology, such as Figure 1 The semiconductor device shown in the figure occupies a large area in the horizontal direction. In order to optimize the occupied area of ​​the semiconductor device, semiconductor devices with electrodes formed on different sides of the semiconductor functional area have been gradually developed. However, the electrodes in such semiconductor devices usually adopt the process of making the gate first and then the source, which is easy to affect the quality of the gate during the annealing process of the source, which is not conducive to the stability of the device performance. Summary of the invention

[0004] The purpose of the present application is to provide a method for manufacturing electrodes in a semiconductor functional region and a semiconductor device in view of the deficiencies in the above-mentioned prior art.

[0005] To achieve the above purpose, the technical solution adopted in the embodiment of the present application is as follows:

[0006] In one aspect of an embodiment of the present application, a method for manufacturing an electrode in a semiconductor functional region is provided, the method comprising:

[0007] Providing a semiconductor structure that exposes at least a portion of the top surface and side surfaces of the functional region;

[0008] forming an annealed first electrode on the top surface of the exposed functional region;

[0009] A second electrode layer is formed at least on the top surface and side surfaces of the exposed functional area, wherein a portion of the second electrode layer located on the top surface of the functional area extends above the first electrode;

[0010] By utilizing the etching selectivity of the second electrode layer and the first electrode, the first electrode is retained and at least the portion of the second electrode layer located on the top surface of the functional area is selectively removed so that the remaining second electrode layer forms a second electrode, which contacts the exposed side surface of the functional area.

[0011] Optionally, utilizing the etching selectivity of the second electrode layer and the first electrode, retaining the first electrode and selectively removing at least a portion of the second electrode layer located on the top surface of the functional area so that the remaining second electrode layer forms a second electrode, and the second electrode contacts the exposed side surface of the functional area comprises:

[0012] By utilizing the etching selectivity of the first electrode and the second electrode layer, the first electrode is retained and the second electrode layer is selectively etched through an anisotropic etching process so that the remaining second electrode layer forms a second electrode, and the second electrode is located on the side of the exposed functional area.

[0013] Optionally, the semiconductor structure has a groove, the side of the groove is the side of the exposed functional area, and the second electrode layer is formed at least on the top surface and the side of the exposed functional area, and the part of the second electrode layer located on the top surface of the functional area extends above the first electrode and includes:

[0014] A second electrode layer is formed at least on the exposed top surface of the functional area, the side surface and the bottom surface of the groove, and the portion of the second electrode layer located on the top surface of the functional area extends above the first electrode.

[0015] Optionally, utilizing the etching selectivity of the second electrode layer and the first electrode, retaining the first electrode and selectively removing at least a portion of the second electrode layer located on the top surface of the functional area so that the remaining second electrode layer forms a second electrode, and the second electrode contacts the exposed side surface of the functional area comprises:

[0016] forming a first photoresist layer located in the groove on the second electrode layer, wherein the first photoresist layer at least partially covers a portion of the second electrode layer located on the side and bottom of the groove;

[0017] By utilizing the etching selectivity of the second electrode layer and the first electrode, the first electrode is retained and the portion of the second electrode layer not covered by the first photoresist layer is selectively removed to form the second electrode of the remaining second electrode layer, and the second electrode contacts the side and bottom of the groove.

[0018] Optionally, before utilizing the etching selectivity of the second electrode layer and the first electrode, retaining the first electrode and selectively removing at least a portion of the second electrode layer located on the top surface of the functional area so that the remaining second electrode layer forms a second electrode, and the second electrode contacts the exposed side surface of the functional area, the method further comprises:

[0019] A first sidewall protection layer is formed on a portion of the second electrode layer located on a side of the exposed functional region.

[0020] Optionally, utilizing the etching selectivity of the second electrode layer and the first electrode, retaining the first electrode and selectively removing at least a portion of the second electrode layer located on the top surface of the functional area so that the remaining second electrode layer forms a second electrode, and the second electrode contacts the exposed side surface of the functional area comprises:

[0021] By utilizing the etching selectivity of the second electrode layer and the first electrode, the first electrode is retained and the portion of the second electrode layer not covered by the first sidewall protection layer is selectively removed so that the remaining second electrode layer forms a second electrode, which is located on the side of the exposed functional area.

[0022] Optionally, before utilizing the etching selectivity of the second electrode layer and the first electrode, retaining the first electrode and selectively removing at least a portion of the second electrode layer located on the top surface of the functional area so that the remaining second electrode layer forms a second electrode, and the second electrode contacts the exposed side surface of the functional area, the method further comprises:

[0023] forming a second protective layer on the second electrode layer, wherein the second protective layer covers the second electrode layer;

[0024] forming a second photoresist layer located in the groove on the second protective layer, wherein the second photoresist layer at least partially covers the portion of the second protective layer located on the side and bottom of the groove;

[0025] The second protective layer is etched by an anisotropic etching process so that at least part of the second protective layer retained on the side and bottom of the groove forms a second sidewall protective layer, and the height of the second sidewall protective layer on the side of the groove is greater than or equal to the height of the second photoresist layer.

[0026] Optionally, the first electrode includes an electrode body and an electrode protection layer covering the electrode body, wherein an etching selectivity ratio between the second electrode layer and the electrode protection layer is greater than an etching selectivity ratio between the second electrode layer and the electrode body.

[0027] Optionally, providing a semiconductor structure that exposes at least a portion of a top surface and a side surface of the functional region includes:

[0028] providing a substrate, wherein the substrate has a step;

[0029] Forming an epitaxial layer by epitaxy from the side of the step;

[0030] A gate dielectric layer is epitaxially formed from the side of the epitaxial layer to obtain a semiconductor structure, wherein the top surface of the epitaxial layer forms the top surface of the functional region, and the side of the gate dielectric layer forms the side of the functional region.

[0031] Optionally, an etching selectivity ratio between the second electrode layer and the gate dielectric layer is greater than 50.

[0032] Optionally, an etching selectivity ratio between the second electrode layer and the first electrode layer is greater than 5.

[0033] Optionally, the first electrode is a source electrode; and / or, the second electrode is a gate electrode.

[0034] Another aspect of an embodiment of the present application provides a semiconductor device, including:

[0035] A semiconductor structure having a functional region and at least partially exposing a top surface and a side surface of the functional region;

[0036] A first electrode, the first electrode is located on the top surface of the exposed functional area;

[0037] A second electrode, the second electrode is at least located on the side of the exposed functional area and in contact with the side of the functional area;

[0038] The first electrode and the second electrode are manufactured by using any of the above methods for manufacturing electrodes in a semiconductor functional region.

[0039] The beneficial effects of this application include:

[0040] The present application provides a method for making an electrode in a semiconductor functional area and a semiconductor device. The method exposes the side of the functional area before making the first electrode, thereby avoiding damage to the first electrode by wet etching (for example, in the wet etching process, HF acid and other corrosive solutions have a corrosive effect on commonly used ohmic contact metals such as TiAl, so the corrosion process will damage the first electrode, and the metal ions of the first electrode will also contaminate the solution of the corrosive medium, and the metal ions produced by the corrosion will remain on the surface of the dielectric layer. This residual contamination of metal ions may produce a leakage channel). On this basis, it also avoids the additional deposition of a dielectric protection layer before forming the second electrode layer, avoiding the growth of the dielectric protection layer on the side of the exposed functional area, affecting the contact between the second electrode layer and the exposed side of the functional area. The etching selectivity of the second electrode layer and the first electrode is utilized, so that part of the second electrode layer is removed during the etching process so that the remaining second electrode layer forms the second electrode, and the first electrode is also retained so that the second electrode is in contact with the exposed side of the functional area. Of course, it is also possible to implement a process in which the first electrode is made first and then the second electrode is made, effectively avoiding the influence of the high-temperature annealing of the first electrode on the second electrode. BRIEF DESCRIPTION OF THE DRAWINGS

[0041] In order to more clearly illustrate the technical solutions of the embodiments of the present application, the drawings required for use in the embodiments will be briefly introduced below. It should be understood that the following drawings only show certain embodiments of the present application and therefore should not be regarded as limiting the scope. For ordinary technicians in this field, other related drawings can be obtained based on these drawings without paying creative work.

[0042] Figure 1 It is a schematic diagram of the structure of a traditional three-electrode semiconductor device;

[0043] Figure 2 This is a flow chart of an existing preparation process of first making a gate and then forming a source;

[0044] Figure 3A flow chart of a preparation process for first making a gate and then forming a source provided in the present application;

[0045] Figure 4 One of the flow charts of a method for making an electrode in a semiconductor functional area provided in an embodiment of the present application;

[0046] Figure 5 A second flowchart of a method for making an electrode in a semiconductor functional area provided in an embodiment of the present application;

[0047] Figure 6 A third flowchart of a method for making an electrode in a semiconductor functional area provided in an embodiment of the present application;

[0048] Figure 7 A fourth flow chart of a method for making an electrode in a semiconductor functional area provided in an embodiment of the present application;

[0049] Figure 8 A fifth flowchart of a method for making an electrode in a semiconductor functional area provided in an embodiment of the present application;

[0050] Fig. 9 Flow chart six of a method for making an electrode in a semiconductor functional area provided in an embodiment of the present application.

[0051] Icon: 110-substrate; 120-epitaxial mask; 130-nucleation layer; 141-epitaxial layer; 142-gate dielectric layer; 150-third dielectric; 160-trench; 170-first electrode; 180-second electrode layer; 181-second electrode; 190-first photoresist layer; 210-first protective layer; 211-first sidewall protective layer; 220-second photoresist layer; 230-second protective layer; 231-second sidewall protective layer. DETAILED DESCRIPTION

[0052] In order to make the purpose, technical solution and advantages of the embodiments of the present application clearer, the technical solution in the embodiments of the present application will be clearly and completely described below in conjunction with the drawings in the embodiments of the present application. Obviously, the described embodiments are part of the embodiments of the present application, not all of the embodiments. It should be noted that, in the absence of conflict, the various features in the embodiments of the present application can be combined with each other, and the combined embodiments are still within the scope of protection of the present application.

[0053] In the description of the present application, it should be noted that the terms "center", "upper", "lower", "left", "right", "vertical", "horizontal", "inner", "outer", etc. indicate positions or positional relationships based on the positions or positional relationships shown in the accompanying drawings, or the positions or positional relationships in which the product of the application is usually placed when in use. They are only for the convenience of describing the present application and simplifying the description, and do not indicate or imply that the device or element referred to must have a specific position, be constructed and operated in a specific position, and therefore cannot be understood as a limitation on the present application. In addition, the terms "first", "second", "third", etc. are only used to distinguish the description, and cannot be understood as indicating or implying relative importance.

[0054] In the description of this application, it should also be noted that, unless otherwise clearly specified and limited, the terms "set", "install", "connect", and "connect" should be understood in a broad sense. For example, the connection can be a direct connection, or an indirect connection through an intermediate medium, or it can be the internal connection of two components. For ordinary technicians in this field, the specific meanings of the above terms in this application can be understood according to specific circumstances.

[0055] In order to optimize the device footprint, such as Figure 2 As shown in (b) in the figure, a semiconductor device is shown, which includes an epitaxial part and an electrode part. The epitaxial part includes a semiconductor layer 8 and a filling medium 6 filled around the semiconductor layer 8. The electrode part includes a gate 10 and a source 9. Of course, the electrode part may also include a drain (not shown). The surface of the semiconductor layer 8 serves as a semiconductor functional region, the top surface 81 of the semiconductor functional region is exposed, and the side surface 82 of the semiconductor functional region is partially exposed. The source 9 is located on the top surface 81 of the semiconductor functional region, and the gate 10 is in contact with the side surface 82 of the semiconductor functional region, which can reduce the occupied area of ​​the device in the horizontal direction.

[0056] Please refer to Figure 2 , providing a preparation process of first forming a gate and then forming a source, firstly as Figure 2 In (a), a gate 10 is formed on the side 82 of the semiconductor functional region, and then Figure 2 In (b), a source electrode 9 is then fabricated on the top surface 81 of the semiconductor functional region. Since the source electrode 9 needs to undergo a high temperature annealing stage during the fabrication process, the quality of the gate electrode 10 is affected, thereby reducing the stability of the semiconductor device.

[0057] When optimizing the problems existing in the above-mentioned process of first making the gate and then forming the source, such as Figure 3 As shown, a preparation process of first making a source and then forming a gate is provided, specifically:

[0058] Please refer to Figure 3As shown in (a), a semiconductor layer 8 is formed by epitaxy, and a filling medium 6 is formed around the semiconductor layer 8, and the top surface of the semiconductor layer 8 is flush with the top surface of the filling medium 6. As before, the surface of the semiconductor layer 8 is used as a semiconductor functional region, and a source electrode 9 is formed on the top surface of the semiconductor functional region. The source electrode 9 can be formed after high-temperature annealing. At this time, since there is no gate 10, the high-temperature annealing of the source electrode 9 will not affect the gate 10.

[0059] Then as Figure 3 As shown in (b) of Figure 3 A dielectric protection layer 11 is deposited on the top surface of the structure shown in (a) to cover the source electrode 9, so as to provide protection for the source electrode 9 in the subsequent etching process.

[0060] like Figure 3 As shown in (c) of FIG. 1 , using the photolithography process, Figure 3 A photoresist with a window is formed on the top surface of the structure shown in (b) (i.e., after the steps of coating, exposure, and development), and then the side of the semiconductor functional area is exposed by wet etching, that is, the filling medium 6 on the right side of the semiconductor layer 8 is etched. In this step, since the window needs to be accurately aligned with the boundary of the semiconductor layer 8, the requirements for photolithography accuracy are relatively high. It is also necessary to understand that in the process of exposing the side of the semiconductor functional area by wet etching, the source 9 located below the dielectric protection layer 11 may be damaged by the wet etching process (referring to the process of wet etching, HF acid and other solutions have a corrosive effect on commonly used ohmic contact metals such as TiAl, so the corrosion process will damage the source 9, and at the same time, the metal ions of the source 9 will also contaminate the solution of the corrosive medium, and the metal ions generated by the corrosion will remain on the surface of the medium, and this residual contamination of metal ions may produce leakage channels), thereby affecting the quality of the source 9.

[0061] like Figure 3 As shown in (d) in Figure 3 A metal layer 12 for making a gate is formed on the structure shown in (c) in the figure. The metal layer 12 covers the remaining dielectric protection layer 11, the side surfaces of the exposed semiconductor functional area, and the top surface of the filling dielectric 6 on the right side of the semiconductor layer 8 after the aforementioned etching.

[0062] like Figure 3 As shown in (e), the metal layer 12 is etched to remove the portion of the metal layer 12 located on the top surface of the semiconductor functional region, so that the remaining metal layer 12 forms the gate 10, so that the gate 10 can contact the side of the exposed semiconductor functional region.

[0063] Although the above process can realize the formation of the source electrode first and then the gate electrode to avoid the gate electrode being affected by the source electrode annealing, as mentioned above, this process not only requires high photolithography accuracy, but also easily causes the source electrode to be damaged during the etching process. In view of this, the present application continues to provide a method for forming an electrode in a semiconductor functional area to improve the above problem.

[0064] In one aspect of the present application, a method for manufacturing an electrode in a semiconductor functional region is provided. Figure 4 As shown, the method includes:

[0065] S100: providing a semiconductor structure that exposes at least a portion of a top surface and side surfaces of a functional region.

[0066] S200: forming an annealed first electrode on the top surface of the exposed functional region.

[0067] S300: forming a second electrode layer at least on the top surface and side surfaces of the exposed functional area, wherein a portion of the second electrode layer located on the top surface of the functional area extends above the first electrode.

[0068] S400: utilizing the etching selectivity of the second electrode layer and the first electrode, retaining the first electrode and selectively removing at least the portion of the second electrode layer located on the top surface of the functional area so that the remaining second electrode layer forms a second electrode, and the second electrode contacts the exposed side surface of the functional area.

[0069] like Figure 5 (a) shows a semiconductor structure, and the semiconductor structure has a functional area for forming current (ie, a semiconductor functional area), so that electrodes can be made on the surface of the functional area in cooperation with subsequent process steps to form a semiconductor device.

[0070] In order to facilitate the contact between the electrode and the functional area surface, the functional area needs to be exposed. Please continue to refer to Figure 5 The semiconductor structure shown in (a) has an exposed top surface A of the functional area. On this basis, the semiconductor structure also has a groove 160, so that a part of the side of the functional area can be exposed through the groove 160, so the exposed side B of the functional area can serve as the side of the groove 160.

[0071] In addition, in order to determine the position height of the electrode on the side of the functional area, the third dielectric 150 can be filled around the semiconductor structure, and a portion of the third dielectric 150 can be removed by etching to determine the exposed portion of the side of the functional area, thereby determining the final position height of the electrode on the side of the functional area. Figure 5As shown in (a), the trench 160 is constructed at least through the exposed side surface B of the functional area and the top surface of the third dielectric 150 on the right side of the semiconductor structure, and the bottom surface C of the trench 160 is the top surface of the third dielectric 150. Of course, the third dielectric 150 can also be selectively removed in the end, so that the electrode located on the side of the functional area is suspended.

[0072] like Figure 5 As shown in (b), the first electrode 170 is formed by depositing a first electrode 170 layer on the exposed top surface A of the functional area and patterning the first electrode 170 layer by photolithography, and then by high temperature annealing, so that the first electrode 170 forms a good contact, such as an ohmic contact, with the exposed top surface A of the functional area. Based on this, it can be understood that the exposure of the side surface of the functional area precedes the production of the first electrode 170, so that the aforementioned wet etching can avoid damage to the first electrode.

[0073] Next, the second electrode layer 180 is directly grown after the first electrode 170 is made, that is, the second electrode layer 180 is formed at least on the exposed top surface A of the functional area and the exposed side surface B of the functional area, for example Figure 5 As shown in (c) , the second electrode layer 180 is located on the exposed top surface A of the functional area, the exposed side surface B of the functional area, the bottom surface C of the trench 160 and the top surface of the third dielectric 150 on the left side of the semiconductor structure.

[0074] Continue to refer to Figure 5 In (c), the portion of the second electrode layer 180 located on the top surface of the functional area extends above the first electrode 170, so that the second electrode layer 180 can be in direct contact with the first electrode 170, and there is no need to deposit the aforementioned dielectric protection layer 11 before forming the second electrode layer 180, thereby avoiding the dielectric protection layer 11 growing on the exposed side surface B of the functional area, which affects the contact between the second electrode layer 180 and the exposed side surface B of the functional area. It should be understood that the second electrode layer 180 and the first electrode 170 should have a certain etching selectivity to meet the requirement that when selective etching is performed later, part of the second electrode layer 180 is removed while retaining the first electrode 170.

[0075] Then refer to Figure 5In (d), the second electrode layer 180 is selectively etched by utilizing the etching selectivity of the second electrode layer 180 and the first electrode 170, so that at least the portion of the second electrode layer 180 located on the top surface of the functional area is removed during the etching process, so that the remaining second electrode layer 180 forms the second electrode 181, and the first electrode 170 is also retained, so that the second electrode 181 can be separated from the first electrode 170, and the second electrode 181 can be in contact with the exposed side surface B of the functional area, forming, for example, an ohmic contact, a Schottky contact, etc., which can be reasonably set according to the device type. In this way, the process of first making the first electrode 170 and then making the second electrode 181 can also be realized, effectively avoiding the influence of the high-temperature annealing of the first electrode 170 on the second electrode 181.

[0076] It should be understood that wet etching, dry etching or a combination of wet etching and dry etching can be used when selectively etching the second electrode layer 180. In the process of dry etching, higher stability and uniformity can be achieved, while wet etching can achieve a higher etching selectivity.

[0077] based on Figure 4 In the method of manufacturing an electrode in a semiconductor functional area shown, a variety of different process methods can be used to form the second electrode 181 under different requirements and scenarios. For ease of understanding, some of the process methods will be described below in conjunction with the accompanying drawings.

[0078] Example 1 (please refer to Figure 6 )

[0079] S100: providing a semiconductor structure that exposes at least a portion of a top surface and side surfaces of a functional region.

[0080] S200: forming an annealed first electrode on the top surface of the exposed functional region.

[0081] S300: forming a second electrode layer at least on the top surface and side surfaces of the exposed functional area, wherein a portion of the second electrode layer located on the top surface of the functional area extends above the first electrode.

[0082] In this example, S100 to S300 can be combined Figure 6 (a) to (c) in the figure and the aforementioned steps are understood. As for the aforementioned S400, an anisotropic etching process can be specifically used to form the second electrode 181 located only on the side B of the exposed functional area, specifically:

[0083] S410: utilizing the etching selectivity of the first electrode and the second electrode layer, retaining the first electrode and selectively etching the second electrode layer through an anisotropic etching process so that the remaining second electrode layer forms a second electrode, and the second electrode is located on the side of the exposed functional area.

[0084] Please refer to Figure 6 In (d), since there is a certain etching selectivity between the first electrode 170 and the second electrode layer 180, the first electrode 170 can be retained when etching the second electrode layer 180. On this basis, the etching rate in the vertical direction can be controlled to be faster than the etching rate in other directions intersecting the vertical direction through an anisotropic etching process, thereby removing the portion of the second electrode layer 180 outside the exposed functional area side B, such as Figure 6 In (c) and (d), the second electrode layer 180 on the top surface of the functional area, the top surface of the third dielectric 150 on the left side of the semiconductor structure, and the bottom surface C of the groove 160 are removed, and the second electrode layer 180 retained on the exposed side surface B of the functional area is used as the second electrode 181. In this step of etching the second electrode layer 180, a dry etching method with strong anisotropy can be selected.

[0085] Example 2 (please refer to Figure 7 )

[0086] S100: providing a semiconductor structure that exposes at least a portion of a top surface and side surfaces of a functional region.

[0087] S200: forming an annealed first electrode on the top surface of the exposed functional region.

[0088] In this example, S100 to S200 can be combined Figure 7 (a) to (b) and the corresponding steps mentioned above are understood with reference to them. As for the above-mentioned S300 and S400, the second electrode layer 180 may first include a portion located at the bottom surface C of the groove 160, and then the second electrode 181 located at the exposed functional area side surface B and the bottom surface C of the groove 160 may be formed by using the first photoresist layer 190. Specifically:

[0089] S310: forming a second electrode layer at least on the exposed top surface of the functional area, the side surface and the bottom surface of the groove, wherein a portion of the second electrode layer located on the top surface of the functional area extends above the first electrode.

[0090] S421: forming a first photoresist layer on the second electrode layer and located in the groove, wherein the first photoresist layer at least partially covers a portion of the second electrode layer located on a side surface and a bottom surface of the groove.

[0091] S422: utilizing the etching selectivity of the second electrode layer and the first electrode, retaining the first electrode and selectively removing the portion of the second electrode layer not covered by the first photoresist layer so that the remaining second electrode layer forms a second electrode, the second electrode being in contact with the side and bottom of the groove.

[0092] Please refer to Figure 7In (c), the second electrode layer 180 needs to be located on the exposed top surface A of the functional area, the exposed side surface B of the functional area, the bottom surface C of the trench 160 and the top surface of the third dielectric 150 on the left side of the semiconductor structure.

[0093] On this basis, a first photoresist layer 190 is formed on the second electrode layer 180 and is located in the groove 160. The side surface of the first photoresist layer 190 should fully or partially cover the portion of the second electrode layer 180 located on the side surface of the exposed functional area, and the bottom surface of the first photoresist layer 190 should fully or partially cover the portion of the second electrode layer 180 located on the bottom surface C of the groove 160. The specific coverage amount can be reasonably set according to needs.

[0094] For ease of understanding, the process of forming the first photoresist layer 190 is described as follows: a photoresist is coated on the second electrode layer 180, and the photoresist is spin-coated to fill the groove 160 and have a certain thickness above the top surface of the functional area under a certain groove spacing, adhesive viscosity and spin-coating speed, and the entire photoresist upper surface (i.e., the top surface) is relatively flat. Then the photoresist is back-etched (usually using O plasma to react with the photoresist, so that the photoresist is uniformly etched on the entire surface). As the photoresist is gradually back-etched, especially when the photoresist is back-etched below the groove 160, the area of ​​the photoresist participating in the reaction will become smaller, thereby reducing the reactants participating in the etching, so the etching gas in the chamber will increase due to reduced consumption, and the etching product will decrease. In this way, the change in the content of the reactant or product during the etching process can be detected by the laser signal, and the time when the photoresist is back-etched to the position of the groove 160 can be accurately detected, thereby accurately controlling the height of the photoresist after back-etching. After the photoresist is etched back to the trench 160 , the photoresist remaining in the trench 160 can be used as the first photoresist layer 190 .

[0095] Please refer to Figure 7In (d), the first photoresist layer 190 formed in the groove 160 is used to protect the portion covered by the second electrode layer 180, and then based on the etching selectivity of the second electrode layer 180 and the first electrode 170, the second electrode layer 180 is selectively etched. During the etching process, the portion of the second electrode layer 180 not covered by the first photoresist layer 190 is removed, so that the remaining second electrode layer 180 forms the second electrode 181, and the first electrode 170 is also retained. In this etching process, wet etching, dry etching, or a combination of wet etching and dry etching can be used. In the process of using dry etching, it can have higher stability and uniformity, and when using wet etching, it can have a higher etching selectivity. The second electrode 181 formed in this way can contact the exposed side B of the functional area, and also contact the bottom surface C of the groove 160. When the second electrode 181 is formed by means of the first photoresist layer 190 , the height of the second electrode 181 can be accurately controlled by the height of the photoresist back-etching, and the formation of the second electrode 181 has a self-alignment characteristic, without the need for a photolithography process, thus simplifying the process steps and reducing the manufacturing cost.

[0096] After the second electrode 181 is finally formed, the first photoresist layer 190 in the trench 160 may be removed.

[0097] Example 3 (please refer to Figure 8 )

[0098] S100: providing a semiconductor structure that exposes at least a portion of a top surface and side surfaces of a functional region.

[0099] S200: forming an annealed first electrode on the top surface of the exposed functional region.

[0100] S300: forming a second electrode layer at least on the top surface and side surfaces of the exposed functional area, wherein a portion of the second electrode layer located on the top surface of the functional area extends above the first electrode.

[0101] In this example, S100 to S300 can be combined Figure 8 (a) to (c) in the figure and the aforementioned steps can be understood. After S300, the first sidewall protection layer 211 formed on the second electrode layer 180 can be used to combine S400 to form the second electrode 181 located only on the side of the exposed functional area. Specifically:

[0102] S500: forming a first sidewall protection layer on a portion of the second electrode layer located on a side of the exposed functional region.

[0103] S430: utilizing the etching selectivity of the second electrode layer and the first electrode, retaining the first electrode and selectively removing the portion of the second electrode layer not covered by the first sidewall protection layer so that the remaining second electrode layer forms a second electrode, and the second electrode is located on the side of the exposed functional area.

[0104] Please refer to Figure 8 In (c), the first protective layer 210, i.e., a thin layer dielectric, is continuously grown on the second electrode layer 180. Figure 8 In (d), the etching rate in the vertical direction is controlled to be faster than the etching rate in other directions intersecting the vertical direction by an anisotropic etching process, so that the first protective layer 210 outside the side B of the functional area is removed, and the portion of the first protective layer 210 located on the side of the functional area is retained, so that the portion of the first protective layer 210 remaining on the side of the functional area forms a first sidewall protective layer 211, and the formed first sidewall protective layer 211 can cover the second electrode layer 180 located on the side of the functional area. The anisotropic etching process used here can be a dry etching process with strong anisotropy.

[0105] Please refer to Figure 8 In (e), the first sidewall protection layer 211 is used to protect the portion covered by the second electrode layer 180, and then based on the etching selectivity of the second electrode layer 180 and the first electrode 170, the second electrode layer 180 is selectively etched. During the etching process, the portion of the second electrode layer 180 not covered by the first sidewall protection layer 211 is removed, so that the second electrode layer 180 covered by the first sidewall protection layer 211 forms the second electrode 181, while the first electrode 170 is also retained. During the etching process, either dry etching with strong anisotropy or isotropic wet etching can be used (the first sidewall protection layer 211 can provide protection). The second electrode 181 formed in this way can be located only on the side B of the exposed functional area.

[0106] It is understandable that the first protective layer 210 is a thin layer dielectric, so compared with the height control method of photoresist back etching, the use of thin layer dielectrics can further control the accuracy of etching height. Therefore, the height controllability of the second electrode 181 exposed after etching the first protective layer 210 through thin layer dielectrics is better than that of photoresist back etching.

[0107] Example 4 (refer to Fig. 9 )

[0108] S100: providing a semiconductor structure that exposes at least a portion of a top surface and side surfaces of a functional region.

[0109] S200: forming an annealed first electrode on the top surface of the exposed functional region.

[0110] S300: forming a second electrode layer at least on the top surface and side surfaces of the exposed functional area, wherein a portion of the second electrode layer located on the top surface of the functional area extends above the first electrode.

[0111] In this example, S100 to S300 can be combined Fig. 9(a) to (c) in the figure and the aforementioned steps can be understood. After S300, the second sidewall protection layer 231 and the second photoresist layer 220 formed on the second electrode layer 180 can also be used to form the second electrode 181 located on the exposed functional area side B and the bottom surface C of the groove 160. Specifically:

[0112] S600: forming a second protective layer on the second electrode layer, wherein the second protective layer covers the second electrode layer.

[0113] S700: forming a second photoresist layer on the second protective layer and located in the groove, wherein the second photoresist layer at least partially covers a portion of the second protective layer located on a side surface and a bottom surface of the groove.

[0114] S800: etching the second protective layer by anisotropic etching process, so that at least a portion of the second protective layer retained on the side and bottom of the groove forms a second sidewall protective layer, and the height of the second sidewall protective layer on the side of the groove is greater than or equal to the height of the second photoresist layer.

[0115] S400: utilizing the etching selectivity of the second electrode layer and the first electrode, retaining the first electrode and selectively removing at least the portion of the second electrode layer located on the top surface of the functional area so that the remaining second electrode layer forms a second electrode, and the second electrode contacts the exposed side surface of the functional area.

[0116] Please refer to Fig. 9 In (c), the second protective layer 230, i.e., a thin layer dielectric, continues to grow on the second electrode layer 180. Then, a second photoresist layer 220 located in the groove 160 is formed on the second protective layer 230. The side of the second photoresist layer 220 should fully or partially cover the part of the second protective layer 230 located on the side of the functional area, and the bottom of the second photoresist layer 220 should fully or partially cover the part of the second protective layer 230 located on the bottom surface C of the groove 160. The specific coverage can be reasonably set according to demand. The formation of the second photoresist layer 220 can refer to the formation process of the first photoresist layer 190, which will not be repeated here. It should be understood that the production of the second photoresist layer 220 can cover and protect the part of the second electrode layer 180 located on the bottom surface C of the groove 160, so that the second electrode 181 can be conveniently contacted with the bottom surface C of the groove 160.

[0117] Please refer to Fig. 9(d) in the figure, and then the etching rate in the vertical direction is controlled to be faster than the etching rate in other directions intersecting the vertical direction by an anisotropic etching process, so as to remove at least the second protective layer 230 outside the side of the functional area and the bottom surface C of the groove 160, and retain part or all of the second protective layer 230 located on the side of the functional area and the bottom surface of the groove 160, so that the part of the second protective layer 230 remaining on the side of the functional area and the bottom surface of the groove 160 forms a second sidewall protective layer 231, and the formed second sidewall protective layer 231 can cover the second electrode layer 180 located on the side of the functional area. The anisotropic etching process used here can be a dry etching process with strong anisotropy.

[0118] The height of the second sidewall protection layer 231 on the side of the groove 160 is greater than or equal to the height of the second photoresist layer 220, so that the high-precision control of the etching height of the second electrode layer 180 can be achieved through the thin layer dielectric. Fig. 9 (d) in the figure is the vertical distance from the top of the second sidewall protection layer 231 to the bottom surface C of the groove 160. Similarly, the height of the second photoresist layer 220 is the vertical distance from the top surface of the second photoresist layer 220 to the bottom surface C of the groove 160.

[0119] Please refer to Fig. 9 In (e), the second side wall protection layer 231 is used to cover the portion of the second electrode layer 180 located on the side of the groove 160, and the second side wall protection layer 231 and the second photoresist layer 220 are used to cover the portion of the second electrode layer 180 located on the bottom surface C of the groove 160. Then, based on the etching selectivity of the second electrode layer 180 and the first electrode 170, the second electrode layer 180 is selectively etched. During the etching process, the uncovered portion of the second electrode layer 180 is removed, so that the covered second electrode layer 180 forms the second electrode 181, and the first electrode 170 is also retained. During the etching process, both dry etching with strong anisotropy and isotropic wet etching can be used.

[0120] Please refer to Fig. 9 In step (f), the second photoresist layer 220 in the trench 160 can be finally removed.

[0121] In summary, electrodes can be made in semiconductor functional regions through the four examples shown.

[0122] In some possible implementations, the first electrode 170 is a source electrode.

[0123] In some possible implementations, the material of the first electrode 170 may be Ti / Al, Ti / Al / Ni / Au, Ti / Al / Ti, Cr, etc.

[0124] In some possible implementations, the second electrode 181 is a gate electrode.

[0125] In some possible implementations, the first electrode 170 is a source electrode, and the second electrode 181 is a gate electrode.

[0126] In some possible implementations, the etching selectivity of the second electrode layer 180 and the first electrode 170 is greater than 5. For example, the material of the source electrode may be Ti / Al / Ti, and the material of the gate electrode may be TiN (the material TiN here refers to titanium nitride; Ti / Al / Ti is a composite titanium / aluminum / titanium three-layer metal film layer), so that the gate electrode can form an etching selectivity greater than 5 with the source electrode after annealing in a nitrogen atmosphere (it should be understood that the dry and wet etching selectivity between TiN and Ti / Al / Ti can both achieve >5); for another example, the material of the gate electrode may be Al / Cu, and the material of the source electrode may be Ti / Al / Ti, and a wet etching selectivity greater than 100 may be formed between the two.

[0127] The first protective layer 210 and / or the second protective layer 230 may be a dielectric or metal film layer that can play a role in protecting the sidewall. In some possible implementations, the first protective layer 210 and / or the second protective layer 230 may be a dielectric layer, such as silicon oxide or silicon nitride grown by plasma enhanced chemical vapor deposition (PECVD) or low pressure chemical vapor deposition (LPCVD), aluminum oxide, silicon oxide, hafnium oxide, zirconium oxide and other materials grown by atomic layer deposition (ALD). In some possible implementations, the role played by the first protective layer 210 and / or the second protective layer 230 may also be achieved by a non-dielectric film layer, such as a metal film layer such as Al, Ni, Cu, Ti and the like.

[0128] In some possible implementations, the first electrode 170 includes an electrode body and an electrode protection layer covering the electrode body, wherein the etching selectivity ratio between the second electrode layer 180 and the electrode protection layer is greater than the etching selectivity ratio between the second electrode layer 180 and the electrode body. In other words, by providing the electrode protection layer, the etching selectivity ratio between the electrode body and the second electrode layer 180 can be increased, thereby better retaining the first electrode 170. For example, the electrode protection layer can be made into a metal layer, such as Cr, Au, Ni, Ta, etc., which are easy to achieve high etching selectivity ratios, thereby increasing the dry etching selectivity ratio to more than 100.

[0129] For some possible implementations, please refer to Figures 5 to 9 As shown, providing a semiconductor structure that exposes at least a portion of the top surface and side surfaces of the functional region includes:

[0130] S110: providing a substrate, wherein the substrate has a step.

[0131] S120: forming an epitaxial layer by epitaxial growth from the side surfaces of the step.

[0132] S130: epitaxially forming a gate dielectric layer from the side of the epitaxial layer to obtain a semiconductor structure, wherein the top surface of the epitaxial layer forms the top surface of the functional region, and the side of the gate dielectric layer forms the side of the functional region.

[0133] The substrate 110 has a step, and the step forms a first table and a second table with a height difference, and a step side connecting the first table and the second table. The substrate 110 in this embodiment can be any one of silicon, sapphire, silicon carbide or gallium nitride, for example, the side of the step can be the (0001) plane of gallium nitride, or the (111) plane of silicon.

[0134] A vertical epitaxial layer 141 is formed by epitaxial growth on the side of the step. The epitaxial layer 141 can be made of materials such as gallium nitride. Then, a gate dielectric layer 142 is formed by epitaxial growth on the side of the epitaxial layer 141, for example, the gate dielectric layer 142 is formed on the left and right sides of the epitaxial layer 141. Therefore, the exposed side B of the functional area is the exposed side of the gate dielectric layer 142, and the exposed top surface A of the functional area is the exposed top surface of the gate dielectric layer 142 and the epitaxial layer 141. Then, a first electrode 170 (source electrode) can be made on the top surface of the epitaxial layer 141 by any of the aforementioned process methods, and the made second electrode 181 (gate electrode) contacts the exposed side of the gate dielectric layer 142.

[0135] In some possible implementations, the etching selectivity of the second electrode layer 180 and the gate dielectric layer 142 is greater than 50, so as to reduce damage to the gate dielectric layer 142 when etching the second electrode layer 180. For example, when the second electrode layer 180 material such as Ti / N, Ti, Al, etc. is dry-etched or wet-etched, an etching selectivity greater than 100 can be achieved with MOSiN (gate dielectric layer 142), where MOSiN refers to SiN grown in situ by MOCVD.

[0136] In some possible implementations, an epitaxial mask 120 such as silicon oxide may be formed on the first and second mesas to facilitate epitaxial formation of a semiconductor structure on the side of the step.

[0137] In some possible implementations, when the epitaxial layer 141 matches the side lattice of the step, a semiconductor structure can be formed directly by epitaxy on the side of the step. However, when the epitaxial layer 141 is greatly different from the side lattice of the step, a nucleation layer 130 can be first formed on the side of the step, and then the semiconductor structure can be formed by epitaxy from the nucleation layer 130. For example, when the substrate 110 is GaN, the lattice of the substrate 110 matches the lattice of the epitaxial layer 141 that also uses GaN. At this time, the epitaxial layer 141 can be directly epitaxially grown on the side of the step. When the substrate 110 is silicon, since its lattice is greatly different from the lattice of the epitaxial layer 141 that uses GaN, the nucleation layer 130 can be first deposited from the side of the step. The nucleation layer 130 can be AlN, and then the epitaxial layer 141 can be epitaxially grown from the nucleation layer 130.

[0138] Another aspect of the present application embodiment provides a semiconductor device. Figures 5 to 9 , including: a semiconductor structure, the semiconductor structure has a functional area, and at least a portion of the top surface and the side surface of the functional area are exposed; a first electrode 170, the first electrode 170 is located on the exposed top surface of the functional area; a second electrode 181, the second electrode 181 is at least located on the side surface of the exposed functional area and contacts the side surface of the functional area; the first electrode 170 and the second electrode 181 are manufactured by any of the above-mentioned methods for manufacturing electrodes in a semiconductor functional area.

[0139] The above description is only the preferred embodiment of the present application and is not intended to limit the present application. For those skilled in the art, the present application may have various modifications and variations. Any modification, equivalent replacement, improvement, etc. made within the spirit and principle of the present application shall be included in the protection scope of the present application.

Claims

1. A method for making an electrode in a semiconductor functional area, characterized in that: The method comprises: Providing a semiconductor structure that exposes at least a portion of the top surface and side surfaces of the functional region; forming an annealed first electrode on the exposed top surface of the functional area; forming a second electrode layer at least on the exposed top surface and side surface of the functional area, wherein a portion of the second electrode layer located on the top surface of the functional area extends above the first electrode; By utilizing the etching selectivity of the second electrode layer and the first electrode, the first electrode is retained and at least the portion of the second electrode layer located on the top surface of the functional area is selectively removed so that the remaining second electrode layer forms a second electrode, and the second electrode contacts the exposed side surface of the functional area.

2. The method according to claim 1, characterized in that The method of utilizing the etching selectivity of the second electrode layer and the first electrode to retain the first electrode and selectively remove at least a portion of the second electrode layer located on the top surface of the functional area so that the remaining second electrode layer forms a second electrode, wherein the second electrode contacts the exposed side surface of the functional area, comprises: By utilizing the etching selectivity of the first electrode and the second electrode layer, the first electrode is retained and the second electrode layer is selectively etched through an anisotropic etching process so that the remaining second electrode layer forms the second electrode, and the second electrode is located on the side of the exposed functional area.

3. The method according to claim 1, characterized in that The semiconductor structure has a trench, the side of the trench is the exposed side of the functional area, the second electrode layer is formed at least on the top surface and the side of the exposed functional area, and the part of the second electrode layer located on the top surface of the functional area extends above the first electrode, including: The second electrode layer is formed at least on the exposed top surface of the functional area, the side surface and the bottom surface of the groove, and the portion of the second electrode layer located on the top surface of the functional area extends above the first electrode.

4. The method according to claim 3, characterized in that The method of utilizing the etching selectivity of the second electrode layer and the first electrode to retain the first electrode and selectively remove at least a portion of the second electrode layer located on the top surface of the functional area so that the remaining second electrode layer forms a second electrode, wherein the second electrode contacts the exposed side surface of the functional area, comprises: forming a first photoresist layer located in the groove on the second electrode layer, wherein the first photoresist layer at least partially covers a portion of the second electrode layer located on a side surface and a bottom surface of the groove; By utilizing the etching selectivity of the second electrode layer and the first electrode, the first electrode is retained and the portion of the second electrode layer not covered by the first photoresist layer is selectively removed so that the remaining second electrode layer forms the second electrode, and the second electrode contacts the side and bottom of the groove.

5. The method according to claim 1, characterized in that Before utilizing the etching selectivity of the second electrode layer and the first electrode to retain the first electrode and selectively remove at least a portion of the second electrode layer located on the top surface of the functional area so that the remaining second electrode layer forms a second electrode, and the second electrode contacts the exposed side surface of the functional area, the method further includes: A first sidewall protection layer is formed on a portion of the second electrode layer located on the exposed side of the functional area.

6. The method according to claim 5, characterized in that The method of utilizing the etching selectivity of the second electrode layer and the first electrode to retain the first electrode and selectively remove at least a portion of the second electrode layer located on the top surface of the functional area so that the remaining second electrode layer forms a second electrode, wherein the second electrode contacts the exposed side surface of the functional area, comprises: By utilizing the etching selectivity of the second electrode layer and the first electrode, the first electrode is retained and the portion of the second electrode layer not covered by the first sidewall protection layer is selectively removed so that the remaining second electrode layer forms the second electrode, and the second electrode is located on the side of the exposed functional area.

7. The method according to claim 3, characterized in that Before utilizing the etching selectivity of the second electrode layer and the first electrode to retain the first electrode and selectively remove at least a portion of the second electrode layer located on the top surface of the functional area so that the remaining second electrode layer forms a second electrode, and the second electrode contacts the exposed side surface of the functional area, the method further includes: forming a second protective layer on the second electrode layer, wherein the second protective layer covers the second electrode layer; forming a second photoresist layer located in the groove on the second protective layer, wherein the second photoresist layer at least partially covers a portion of the second protective layer located on a side surface and a bottom surface of the groove; The second protective layer is etched by an anisotropic etching process so that at least a portion of the second protective layer retained on the side and bottom of the groove forms a second sidewall protective layer, and the height of the second sidewall protective layer on the side of the groove is greater than or equal to the height of the second photoresist layer.

8. The method according to any one of claims 1 to 7, characterized in that The first electrode includes an electrode body and an electrode protection layer covering the electrode body, wherein an etching selectivity ratio between the second electrode layer and the electrode protection layer is greater than an etching selectivity ratio between the second electrode layer and the electrode body.

9. The method according to any one of claims 1 to 7, characterized in that: The semiconductor structure for exposing at least a portion of the top surface and side surfaces of the functional region comprises: providing a substrate, wherein the substrate has a step; Forming an epitaxial layer by epitaxy from the side surface of the step; A gate dielectric layer is epitaxially formed from the side surface of the epitaxial layer to obtain the semiconductor structure, wherein the top surface of the epitaxial layer forms the top surface of the functional region, and the side surface of the gate dielectric layer forms the side surface of the functional region.

10. The method according to claim 9, characterized in that The etching selectivity ratio between the second electrode layer and the gate dielectric layer is greater than 50.

11. The method according to any one of claims 1 to 7, characterized in that: An etching selectivity ratio between the second electrode layer and the first electrode layer is greater than 5.

12. The method according to any one of claims 1 to 7, characterized in that: The first electrode is a source electrode; and / or the second electrode is a gate electrode.

13. A semiconductor device, characterized in that: include: A semiconductor structure having a functional region, wherein at least a portion of a top surface and a side surface of the functional region are exposed; A first electrode, wherein the first electrode is located on the exposed top surface of the functional area; a second electrode, the second electrode being at least located on the exposed side of the functional area and in contact with the side of the functional area; The first electrode and the second electrode are manufactured by the method for manufacturing electrodes in a semiconductor functional region as described in any one of claims 1 to 12.

Images