Protection of gate dielectrics using molybdenum-containing material layers

Abstract

The present disclosure relates to protecting gate dielectric using a layer of molybdenum-containing material. Techniques are provided for forming an integrated circuit having a gate electrode including at least one molybdenum-containing layer. The transistor includes a gate structure having a gate electrode on a gate dielectric. A gate structure extends around a fin of semiconductor material or any number of nanowires (or nanoribbons or nanosheets). The gate electrode includes one or more conductive layers on a gate dielectric, at least one of the conductive layers including molybdenum (e.g., molybdenum nitride). A conductive layer having molybdenum may be used during formation of the gate dielectric (e.g., during an annealing process), thus resulting in a higher quality gate dielectric.

Description

Background Art

[0001] As the size of integrated circuits continues to shrink, many challenges arise. For example, it becomes increasingly difficult to reduce the size of memory and logic cells within the interconnect structure, as does reducing the device spacing at the device layer. Maintaining a certain level of quality between various transistor elements can be a challenge due to the many different manufacturing processes that the various transistor elements may undergo. Therefore, there are still many challenges that cannot be ignored with respect to forming such high-density semiconductor devices. BRIEF DESCRIPTION OF THE DRAWINGS

[0002] Figure 1A and Figure 1B are different cross-sectional views of an integrated circuit including a gate structure according to an embodiment of the present disclosure, wherein the gate structure includes at least one layer including molybdenum.

[0003] Figure 2A and Figure 2B is a cross-sectional view illustrating a stage in an example process for forming an integrated circuit configured with a gate structure including at least one layer having molybdenum according to an embodiment of the present disclosure.

[0004] Figure 3A and Figure 3B is a cross-sectional view illustrating another stage in an example process for forming an integrated circuit configured with a gate structure including at least one layer including molybdenum according to an embodiment of the present disclosure.

[0005] Figure 4A and Figure 4B is a cross-sectional view illustrating another stage in an example process for forming an integrated circuit configured with a gate structure including at least one layer including molybdenum according to an embodiment of the present disclosure.

[0006] Figure 5A and Figure 5B is a cross-sectional view illustrating another stage in an example process for forming an integrated circuit configured with a gate structure including at least one layer including molybdenum according to an embodiment of the present disclosure.

[0007] Fig. 6A and Figure 6B is a cross-sectional view illustrating another stage in an example process for forming an integrated circuit configured with a gate structure including at least one layer including molybdenum according to an embodiment of the present disclosure.

[0008] Fig. 7A and Figure 7B is a cross-sectional view illustrating another stage in an example process for forming an integrated circuit configured with a gate structure including at least one layer including molybdenum according to an embodiment of the present disclosure.

[0009] Fig. 8A and Figure 8B is a cross-sectional view illustrating another stage in an example process for forming an integrated circuit configured with a gate structure including at least one layer including molybdenum according to an embodiment of the present disclosure.

[0010] Fig.9A and Fig. 9B is a cross-sectional view illustrating another stage in an example process for forming an integrated circuit configured with a gate structure including at least one layer including molybdenum according to an embodiment of the present disclosure.

[0011] Fig. 10A and Fig. 10B is a cross-sectional view illustrating another stage in an example process for forming an integrated circuit configured with a gate structure including at least one layer including molybdenum according to an embodiment of the present disclosure.

[0012] Fig.11A and Fig. 11B is a cross-sectional view illustrating another stage in an example process for forming an integrated circuit configured with a gate structure including at least one layer including molybdenum according to an embodiment of the present disclosure.

[0013] Fig. 12A and Fig. 12B is a cross-sectional view illustrating another stage in an example process for forming an integrated circuit configured with a gate structure including at least one layer including molybdenum according to an embodiment of the present disclosure.

[0014] Fig.13A and Fig. 13B is a cross-sectional view illustrating another stage in an example process for forming an integrated circuit configured with a gate structure including at least one layer including molybdenum according to an embodiment of the present disclosure.

[0015] Fig.14A and Fig. 14B is a cross-sectional view illustrating another stage in an example process for forming an integrated circuit configured with a gate structure including at least one layer including molybdenum according to an embodiment of the present disclosure.

[0016] Fig.15A and Fig. 15B is a cross-sectional view illustrating another stage in an example process for forming an integrated circuit configured with a gate structure including at least one layer including molybdenum according to an embodiment of the present disclosure.

[0017] Fig.16 is a cross-sectional view of another example semiconductor device configured with a gate structure including at least one layer including molybdenum according to an embodiment of the present disclosure.

[0018] Fig.17A cross-sectional view of a chip package including one or more semiconductor dies according to some embodiments of the present disclosure is shown.

[0019] Fig.18 is a flow chart of a process for manufacturing an integrated circuit including a gate structure according to an embodiment of the present disclosure, wherein the gate structure includes at least one layer including molybdenum.

[0020] Fig.19 A computing system including one or more integrated circuits as variously described herein is shown according to an embodiment of the present disclosure.

[0021] Although the following detailed description will be made with reference to illustrative embodiments, many alternatives, modifications and variations thereof will be apparent in light of the present disclosure. As will be further understood, the drawings are not necessarily drawn to scale or intended to limit the present disclosure to the particular configurations shown. For example, although some of the figures generally illustrate perfectly straight lines, right angles, and smooth surfaces, actual implementations of integrated circuit structures may have less than perfect straight lines, right angles (e.g., some features may have tapered sidewalls and / or rounded corners), and some features may have surface topography or otherwise appear to be non-smooth, given the real-world limitations of the processing equipment and techniques used. DETAILED DESCRIPTION

[0022] Provided herein is a technique for forming an integrated circuit having a gate electrode including at least one molybdenum-containing layer. The technique can be used in any number of integrated circuit applications, and is particularly useful relative to logic and memory cells (e.g., those using FinFETs or full-ring gate transistors (e.g., ribbon FETs and nanowire FETs)). In one such example, a FET (field effect transistor) includes a gate structure having a gate electrode on a gate dielectric. The gate structure extends around a fin or any number of nanowires (or nanobelts or nanosheets, as the case may be) of a semiconductor material. The semiconductor material may extend in a first direction between a source region and a drain region, and the gate structure extends in a second direction substantially orthogonal to the first direction over the semiconductor material. The gate electrode includes one or more conductive layers on the gate dielectric, at least one of which has molybdenum and nitrogen (e.g., molybdenum nitride). A conductive layer having molybdenum may be used during the formation of the gate dielectric to protect the gate dielectric during the annealing step, thereby obtaining a higher quality gate dielectric. Many variations and embodiments will be apparent from the present disclosure.

[0023] General Overview

[0024] As mentioned above, there are still many challenges that cannot be ignored regarding integrated circuit manufacturing. In more detail, the gate dielectric of a FET is an important element that separates the gate electrode from the semiconductor material of the transistor. Any degradation of the quality of the gate dielectric may have a negative impact on the performance of the transistor. A given gate dielectric may be subjected to an annealing process to enhance the integrity of the gate dielectric and drive certain desired elements into the gate dielectric. Additional material layers may be deposited on the gate dielectric before annealing, which may provide a certain degree of protection for the gate dielectric during the annealing process. However, the deposition of these additional layers may actually damage the underlying gate dielectric and cause it to be partially removed during later manufacturing. For example, a titanium nitride layer is usually deposited on the gate dielectric before the annealing operation. However, the deposition of titanium nitride uses a chlorine-based precursor (precursor) (TiCl4) at high temperatures, which may produce byproducts that attack the gate dielectric and make it easier to remove during a later gate patterning process.

[0025] Therefore, and in accordance with embodiments of the present disclosure, techniques for protecting gate dielectrics during device manufacturing are provided herein. For example, these techniques can be used to replace titanium nitride (TiN) layers or other layers that may damage the underlying gate dielectric. Such potentially destructive layers (e.g., TiN) can be replaced with molybdenum-containing layers. For example, a molybdenum-containing layer can be deposited on top of the gate dielectric to effectively protect the gate dielectric during an annealing process. Then, the molybdenum-containing layer can be retained on top of the gate dielectric as one of the conductive layers within the gate electrode. According to some embodiments, the gate dielectric includes at least one high-k dielectric layer (e.g., a material having a dielectric constant higher than that of silicon dioxide or higher than 3.9), such as hafnium dioxide. The conductive layer used on the gate dielectric can include, for example, molybdenum nitride. During the formation of the gate electrode, an additional conductive layer can be formed on the molybdenum nitride layer to produce a work function metal layer and a metal filler on the work function metal layer. The material type and relative thickness of the various work function metal layers can vary depending on whether the transistor is n-type or p-type and depending on the desired threshold voltage of the transistor. Typically, the threshold voltage of a device decreases as the thickness of a given work function layer increases. In some embodiments, a p-type FET includes a plurality of work function layers having a material layer containing molybdenum nitride, a material layer containing tantalum nitride, and a material layer containing titanium nitride. In some embodiments, an n-type FET includes a plurality of work function layers having a material layer containing molybdenum nitride and a material layer containing tantalum nitride (e.g., without titanium nitride). In some embodiments, for some n-type FET devices, the layer containing molybdenum nitride is removed so that those n-type FET devices do not include a work function layer having molybdenum, but still obtain the benefits of an improved gate dielectric. An example fill metal on one or more work function layers is tungsten. The quality of the gate dielectric can be determined using measurements of parameters such as gate leakage, threshold voltage, and maximum voltage before transistor breakdown (VMAX).

[0026] According to an embodiment, a method for forming an integrated circuit includes: forming a fin including one or more semiconductor layers, the fin extending in a first direction above a substrate; forming a sacrificial gate, the sacrificial gate extending in a second direction above the fin, the second direction being different from the first direction; removing an exposed portion of the fin adjacent to the sacrificial gate to form a recess passing through the fin; forming a source or drain region from ends of the one or more semiconductor layers and within the recess; removing the sacrificial gate from around the fin; forming one or more dielectric layers on the one or more semiconductor layers of the fin; forming a conductive layer on the one or more dielectric layers, wherein the conductive layer includes molybdenum and nitrogen; after forming the conductive layer, annealing the one or more dielectric layers; and forming one or more additional conductive layers above the conductive layer.

[0027] According to another embodiment, an integrated circuit includes a semiconductor region extending from a source or drain region in a first direction, and a gate structure extending over the semiconductor region in a second direction different from the first direction. The gate structure includes one or more dielectric layers on the semiconductor region and one or more conductive layers on the one or more dielectric layers. The one or more conductive layers include a conductive layer containing molybdenum and nitrogen. The source or drain region may include, for example, silicon, germanium, or silicon germanium (SiGe) doped with an n-type dopant.

[0028] According to another embodiment, an electronic device includes a chip package having one or more tube cores. At least one tube core of the one or more tube cores includes a semiconductor device, the semiconductor device having a semiconductor region extending from a source or drain region in a first direction, and a gate structure extending above the semiconductor region in a second direction different from the first direction. The gate structure includes one or more dielectric layers on the semiconductor region and one or more conductive layers on the one or more dielectric layers. The one or more conductive layers include a conductive layer containing molybdenum and nitrogen. The source or drain region may include, for example, silicon, germanium, or silicon germanium (SiGe) doped with an n-type dopant.

[0029] These techniques can be used with any type of planar or non-planar transistor, including FinFETs (sometimes called dual-gate transistors or tri-gate transistors), or nanowire and nanoribbon transistors (sometimes called full-ring gate transistors), or forksheet transistors, to name a few examples. More generally, the techniques described herein can benefit any transistor architecture with a gate dielectric layer that is subjected to relatively high temperature annealing (e.g., 500°C to 700°C). The source region and the drain region can be, for example, doped portions of a given fin or substrate, or epitaxial regions deposited during etching and replacement source / drain formation processes. The type of dopant in the source region and the drain region will depend on the polarity of the corresponding transistor. The gate structure can be implemented with a gate-first process or a gate-last process (sometimes called a replacement metal gate or RMG process) or any other gate formation process. Any number of semiconductor materials can be used to form transistors, such as Group IV materials (e.g., silicon, germanium, silicon germanium) or Group III-V materials (e.g., gallium arsenide, indium gallium arsenide).

[0030] The use of the techniques and structures provided herein can be detected using tools such as electron microscopy, including scanning / transmission electron microscopy (SEM / TEM), scanning transmission electron microscopy (STEM), nanobeam electron diffraction (NBD or NBED), and reflection electron microscopy (REM); composition mapping; X-ray crystallography or diffraction (XRD); energy dispersive X-ray spectroscopy (EDX); secondary ion mass spectrometry (SIMS); time-of-flight SIMS (ToF-SIMS); atom probe imaging or tomography; local electrode atom probe (LEAP) technology; 3D tomography; or high-resolution physical or chemical analysis, to name just a few suitable example analysis tools. For example, in some example embodiments, such a tool can indicate the presence of a metal layer having molybdenum as part of a gate electrode of a transistor. In some embodiments, the layer having molybdenum also includes nitrogen and is arranged between the gate dielectric and one or more other metal layers as part of the gate electrode. The layer having molybdenum can be observed directly on the gate dielectric.

[0031] It should be readily understood that the meaning of "above" and "on" in the present disclosure should be interpreted in the broadest manner, so that "above" and "on" not only mean "directly on something", but also include the meaning of being on something with intermediate features or layers therebetween. In addition, for ease of description, spatially relative terms (e.g., "below", "below", "lower", "above", "up", "top", "bottom", etc.) may be used herein to describe the relationship between an element or feature as shown in the figure and another one or more elements or features. In addition to the orientations shown in the figures, spatially relative terms are intended to cover different orientations of the device in use or operation. The device may be oriented in other ways (rotated 90 degrees or in other orientations), and the spatially relative descriptors used herein may also be interpreted accordingly.

[0032] As used herein, the term "layer" refers to a portion of a material including an area having a thickness. A monolayer is a layer consisting of a single layer of atoms of a given material. A layer may extend over the entire underlying or superstructure, or may have an extent that is less than the extent of the underlying or superstructure. In addition, a layer may be an area of ​​a homogeneous or heterogeneous continuous structure, wherein the thickness of the layer is less than the thickness of the continuous structure. For example, a layer may be located between or between any pair of horizontal planes between the top and bottom surfaces of a continuous structure. A layer may extend horizontally, vertically, and / or along a tapered surface. A layer may be conformal to a given surface (whether flat or curved) and have a relatively uniform thickness over the entire layer.

[0033] As used herein, "compositionally different" or "compositionally dissimilar" materials refer to two materials having different chemical compositions. This compositional difference can be, for example, due to an element in one material that is not in the other material (e.g., SiGe is compositionally different from silicon), or by one material having all of the same elements as the second material, but at least one of these elements is intentionally provided in a different concentration in one material relative to the other material (e.g., SiGe with 70 atomic percent germanium is compositionally different from SiGe with 25 atomic percent germanium). In addition to this chemical composition diversity, the materials can also have different dopants (e.g., gallium and magnesium) or have the same dopants but in different concentrations. In other embodiments, compositionally different materials can further refer to two materials having different crystallographic orientations. For example, (110) silicon is compositionally dissimilar or different from (100) silicon. The creation of stacks of different orientations can be achieved, for example, using a blanket wafer layer transfer. If two materials are elementally different, one of the materials has an element that is not in the other material.

[0034] Architecture

[0035] Figure 1A is a cross-sectional view taken through each semiconductor device 101 along a “fin” direction according to an embodiment of the present disclosure, illustrating a semiconductor body extending between a source region or a drain region of each semiconductor device 101 . Figure 1B Shown parallel to Figure 1A A cross-sectional view is taken from a cross-section of a transistor and into the page (or out of the page, as the case may be) so that it is away from the semiconductor body of the transistor but still intersects with the gate structure extending above the semiconductor body. Each semiconductor device can be, for example, a non-planar metal oxide semiconductor (MOS) transistor, such as a tri-gate (e.g., FinFET) or a gate-all-around (GAA) transistor, but other transistor topologies and types can also benefit from the techniques provided herein. The examples herein show semiconductor devices having a GAA structure (e.g., having nanoribbons, nanowires, or nanosheets extending between a source region and a drain region). Other examples can have a fork-sheet structure having a p-type device and an n-type device separated by a dielectric spine or structure.

[0036] The semiconductor material used in each semiconductor device can be formed by a semiconductor substrate 102. Substrate 102 can be, for example, a bulk substrate including a Group IV semiconductor material (such as silicon, germanium, or SiGe), a Group III-V semiconductor material (such as gallium arsenide, indium gallium arsenide, or indium phosphide), and / or any other suitable material on which a transistor can be formed. Alternatively, the substrate can be a semiconductor-on-insulator substrate having a desired semiconductor layer above a buried insulator layer (e.g., silicon on silicon dioxide). Alternatively, the substrate can be a multilayer substrate or superlattice suitable for forming nanowires or nanoribbons (e.g., alternating layers of silicon and SiGe, or alternating layers of indium gallium arsenide and indium phosphide). Any number of substrates can be used. In some embodiments, substrate 102 is removed and replaced with one or more back-side interconnect layers to form back-side signal and power wiring.

[0037] One or more semiconductor regions of the device may include fins that may be native (formed by the substrate itself), for example, relative to the substrate 102, such as silicon fins etched from a bulk silicon substrate. Alternatively, the fins may be formed from a material deposited onto the substrate 102. In one such example case, a blanket layer of SiGe may be deposited onto a silicon substrate and then patterned and etched to form a plurality of SiGe fins extending from the substrate. In further other embodiments, the fins include alternating layers of material (e.g., alternating layers of silicon and SiGe) that facilitate the formation of nanowires and nanoribbons and nanosheets during a gate formation process, wherein one type of alternating layers is selectively etched away to release another type of alternating layers in the channel region so that a full-all-around gate process or a fork-sheet gate process may then be performed. Again, in some examples, the alternating layers may be blanket deposited and then etched into fins or deposited into fin-shaped trenches.

[0038] According to some embodiments, semiconductor device 101 further includes a sub-fin region 103 extending in the first direction below semiconductor device 101. According to some embodiments, sub-fin region 103 is a portion of a corresponding semiconductor fin that remains after forming each transistor, and may be formed by substrate 102. Thus, sub-fin region 103 may include the same semiconductor material as substrate 102 (or any semiconductor material if substrate 102 is removed).

[0039] Each semiconductor device 101 includes one or more semiconductor regions (also referred to as channel regions), such as one or more nanoribbons 104 extending between epitaxial source or drain regions 106 in a first direction. A gate structure extends over the one or more semiconductor regions (e.g., nanoribbons 104) of a given semiconductor device 101 in a second direction (e.g., into and out of the page) to form a transistor gate. Sub-fin regions 103 may extend along the first direction under the one or more nanoribbons 104 and to the sides of the dielectric filler 105 in areas not located under the one or more nanoribbons 104, such as Figure 1B Thus, the dielectric filler 105 may act as a shallow trench isolation (STI) between adjacent sub-fins along the second direction (eg, in and out of the page).

[0040] Depending on the application and dopant distribution, any of the source or drain regions 106 can act as a source region or a drain region. Any semiconductor material suitable for source and drain regions (e.g., Group IV and Group III-V semiconductor materials) can be used for any of the source or drain regions 106 shown. In any such case, the composition and doping of the source or drain region 106 can be the same or different, depending on the polarity of the transistor. For example, any semiconductor device that is a p-channel transistor has a high concentration of p-type dopants in the associated source or drain region 106, and any semiconductor device that is an n-channel transistor has a high concentration of n-type dopants in the associated source or drain region 106. Example p-type dopants include boron, and example n-type dopants include phosphorus. Any number of source and drain configurations and materials can be used. In some examples, the n-type source or drain region includes silicon doped with phosphorus, and the p-type source or drain region includes silicon germanium doped with boron.

[0041] According to some embodiments, the gate structure may include a gate electrode composed of a conductive filler 108 and one or more metal work function layers 109. The gate structure also includes a gate dielectric 110, which may represent any number of dielectric layers. The conductive filler 108 may include any sufficiently conductive material, such as a metal, a metal alloy, or doped polysilicon. In some examples, the conductive filler 108 includes tungsten (W), but other metals or conductive materials may be used, such as aluminum (Al), ruthenium (Ru), cobalt (Co), or doped polysilicon. In some embodiments, one or both of the semiconductor devices 101 are p-channel devices, wherein one or more work function layers 109 include molybdenum nitride (MoN) layers. Other metal work function layers 109 of p-channel devices may include tantalum nitride (TaN) and titanium nitride (TiN). In some embodiments, one or both of the semiconductor devices 101 are n-channel devices, wherein one or more work function layers 109 include molybdenum nitride (MoN) layers. Other metal work function layers 109 of n-channel devices may include tantalum nitride (TaN). According to some embodiments, a MoN layer may be deposited on the gate dielectric 110 before the annealing process and remain on the gate dielectric 110 to serve as one of the gate electrode work function metals.

[0042] The gate dielectric 110 may include any suitable one or more gate dielectric materials. In some embodiments, the gate dielectric 110 includes a native oxide material (e.g., silicon dioxide, germanium dioxide, or SiGe oxide) layer on the nanoribbons 104 or other semiconductor regions, and a high-k dielectric material (e.g., hafnium oxide or aluminum oxide) layer on the native oxide. According to some embodiments, the spacer structure 112 and the internal spacer 114 exist along the sidewalls of the gate structure. The spacer structure 112 and the internal spacer 114 may be any suitable dielectric material, such as silicon nitride, and provide isolation between a given gate structure and an adjacent source or drain region 106. The internal spacer 114 may separate adjacent nanoribbons 104 from each other along a third direction (e.g., a vertical direction).

[0043] According to some embodiments, a dielectric cap layer 116 may be present over a gate electrode within a gate trench of the semiconductor device 101. A top surface of the dielectric cap layer 116 may be substantially coplanar with a top surface of the spacer structure 112. In some examples, the dielectric cap layer 116 may include the same dielectric material as the spacer structure 112.

[0044] According to some embodiments, a conductive contact 118 is disposed on the source or drain region 106. The conductive contact 118 may include any suitable conductive material, such as tungsten, molybdenum, ruthenium, cobalt, or other metals. The conductive contacts 118 may be formed together such that they all include the same conductive material.

[0045] like Figure 1B As shown, according to some embodiments, a dielectric plug 120 may be present within the source / drain trench to separate the source or drain region 106 from other source or drain regions along a second direction (e.g., in and out of the page). The dielectric plug 120 may be any suitable dielectric material, such as silicon dioxide, silicon oxynitride, or silicon oxycarbide.

[0046] Manufacturing method

[0047] Figure 2A-15A and 2B-15B include cross-sectional views that collectively illustrate an example process for forming an integrated circuit configured with a molybdenum-containing work function layer according to an embodiment of the present disclosure. Figure 2A-15A Represents the current passing through a series of semiconductor devices and Figure 1A The cross-sectional view is similar to the cross-sectional view, while Figure 2B-15B Indicates parallel to Figure 2A-15A view in the semiconductor device and away from the Figure 1B Each set of figures sharing the same letter shows an example structure resulting from the process flow up to that point in time, and thus the structures shown evolve as the process flow continues, ultimately forming Figures 15A-15B The structure shown is similar to Figure 1A and Figure 1B The structure shown. Such a structure may be part of an entire integrated circuit (e.g., for example, a processor or memory chip) that includes, for example, digital logic cells and / or memory cells and analog mixed signal circuits. Thus, the integrated circuit structure shown may be part of a larger integrated circuit that includes other integrated circuits not shown. Example materials and process parameters are given, but other materials and process parameters may also be used, as will be understood from the present disclosure.

[0048] Figure 2A and Figure 2B Each shows a cross-sectional view taken through a substrate 201 having a series of material layers formed on the substrate according to an embodiment of the present disclosure. Alternating material layers may be deposited on the substrate 201, including sacrificial layers 202 alternating with semiconductor layers 204. The alternating layers are used to form a GAA transistor structure. Any number of alternating sacrificial layers 202 and semiconductor layers 204 may be deposited on the substrate 201. The substrate 201 may be substantially similar to the substrate 102 described above.

[0049] According to some embodiments, semiconductor layer 204 has a different material composition than sacrificial layer 202. In some embodiments, semiconductor layer 204 includes a semiconductor material suitable for use as a nanoribbon, such as silicon (Si), SiGe, germanium, or a III-V material, such as indium phosphide (InP) or gallium arsenide (GaAs). Sacrificial layer 202 includes a material that can be selectively removed relative to semiconductor layer 204. In some examples, for example, semiconductor layer 204 is silicon and sacrificial layer 202 is SiGe, or vice versa. In some other examples where SiGe is used in each of semiconductor layer 204 and sacrificial layer 202, the germanium concentration between semiconductor layer 204 and sacrificial layer 202 is different to allow for etching selectivity. For example, semiconductor layer 204 can include a higher germanium content than sacrificial layer 202.

[0050] Although the dimensions may vary from example embodiment to example embodiment, in some examples, the thickness of each semiconductor layer 204 may be between about 5 nm and about 20 nm. In some embodiments, the thickness of each semiconductor layer 204 is substantially the same (e.g., within 1-2 nm). The thickness of each of the sacrificial layers 202 may be substantially the same as the thickness of each semiconductor layer 204 (e.g., about 5-20 nm). Any material deposition technique may be used to deposit each of the semiconductor layer 204 and the sacrificial layer 202, such as chemical vapor deposition (CVD), plasma enhanced chemical vapor deposition (PECVD), physical vapor deposition (PVD), or atomic layer deposition (ALD) or epitaxial growth.

[0051] Figure 3A and Figure 3B 3 and 4 respectively show the structure of the substrate after forming the cover layer 302 and then forming a fin under the cover layer 302 according to an embodiment. Figure 2A and Figure 2B . The capping layer 302 may be any suitable hard mask material, such as a carbon hard mask (CHM) or silicon nitride. The capping layer 302 is patterned into rows to form corresponding rows of fins from alternating stacks of sacrificial layers 202 and semiconductor layers 204. The capping layer 302 extends along the top of each fin in a first direction, such as Figure 3A shown.

[0052] According to some embodiments, the anisotropic etching process through the layer stack continues into at least a portion of substrate 201. The portion of substrate 201 below the fin is not etched and a sub-fin region 304 is created, such as Figure 3A The etched portion of the substrate 201 that is not under the fin may be filled with a dielectric filler 306 that acts as a shallow trench isolation (STI) between adjacent fins, as shown in FIG. Figure 3BAs shown. Dielectric filler 306 may be any suitable dielectric material, such as silicon dioxide. According to some embodiments, sub-fin region 304 represents the remaining portion of substrate 201 at the side of dielectric filler 306 .

[0053] Figure 4A and Figure 4B FIG. 4 shows a schematic diagram of a structure after forming a sacrificial gate 402 and a spacer structure 404 according to some embodiments. Figure 3A and Figure 3B A cross-sectional view of the structure shown in . The gate mask layer may first be patterned into strips extending orthogonally (e.g., in the second direction) across each of the fins so as to form a corresponding strip-shaped sacrificial gate 402 beneath the gate mask layer. Thereafter, the gate mask layer may be removed or may be retained as a capping layer over each sacrificial gate 402. According to some embodiments, the sacrificial gate material is removed in all areas not protected by the gate mask layer. The sacrificial gate 402 may be any suitable material that can be selectively removed without damaging the semiconductor material of the fin. In some examples, the sacrificial gate 402 comprises polysilicon.

[0054] According to some embodiments, a spacer structure 404 is formed along the sidewalls of the sacrificial gate 402. The spacer structure 404 can be conformally deposited (e.g., CVD or ALD) and then etched back or otherwise removed from the horizontal surface (e.g., via anisotropic or directional etching) so that the spacer structure 404 remains mostly only on the sidewalls of any exposed structure. The width of the spacer structure 404 (along the first direction) can vary from example to example, but in some cases is in the range of 3nm to 20nm. According to some embodiments, the spacer structure 404 can be any suitable dielectric material, such as silicon nitride, silicon carbonitride, or silicon carbon nitride oxide. In one such embodiment, the spacer structure 404 includes a nitride and the dielectric fill 306 includes an oxide to provide a degree of etch selectivity during final gate processing. Other etch selective dielectric schemes (e.g., oxide / carbide, carbide / nitride) can also be used for the spacer structure 404 and the dielectric fill 306. In other embodiments, the spacer structure 404 and the dielectric fill 306 are identical or otherwise similar in composition, where etch selectivity is not employed.

[0055] Figure 5A and Figure 5B FIG. 4 shows a fin after removing exposed portions of the fin that are not protected by the sacrificial gate 402 and the spacer structure 404, according to some embodiments. Figure 4A and Figure 4B4. A cross-sectional view of the structure shown in . The exposed fin portion may be removed using any anisotropic etching process, such as reactive ion etching (RIE) or other directional etching process. According to some embodiments, removing the exposed fin portion produces source or drain trenches alternating with gate trenches (currently filled with sacrificial gate 402) along a first direction. In some embodiments, at least a portion of the sub-fin region 304 is also removed so that the top surface of the sub-fin region 304 is recessed below the top surface of the dielectric filler 306. The recessed area above the sub-fin region 304 may be filled with one or more dielectric materials.

[0056] Fig. 6A and Figure 6B FIG. 2 shows a schematic diagram of a structure of the sacrificial layer 202 after removing a portion of the sacrificial layer 202 according to an embodiment of the present disclosure. Figure 5A and Figure 5B An isotropic etching process may be used to selectively recess the exposed end of each sacrificial layer 202 (eg, while etching relatively few semiconductor layers 204).

[0057] Fig. 7A and Figure 7B FIG. 1 shows a schematic diagram of a circuit ... Fig. 6A and Figure 6B . The internal spacer 702 can have a material composition similar or identical to that of the spacer structure 404. Thus, the internal spacer 702 can be any suitable dielectric material that exhibits a high etch selectivity to semiconductor materials (such as silicon and / or silicon germanium). The internal spacer 702 can be conformally deposited over the sides of the fin structure, for example using a conformal deposition process (such as CVD or ALD), and then etched back using an isotropic etching process to expose the ends of the semiconductor layer 204. According to some embodiments, the internal spacer 702 has a width similar to that of the spacer structure 404 (e.g., along the first direction). Note that according to some embodiments, the internal spacer 702 can be formed only around the ends of the semiconductor layer 204, and not along other edges of the gate trench away from the semiconductor layer 204 (such as Figure 7B shown).

[0058] Fig. 8A and Figure 8B 8 and 9 respectively show the structure of the source or drain region 802 after forming the source or drain region 802 in the source / drain trench according to some embodiments. Fig. 7A and Figure 7B. A source or drain region 802 may be formed in an area previously occupied by an exposed fin between spacer structures 404. According to some embodiments, the source or drain region 802 is epitaxially grown from the exposed semiconductor material at the end of the semiconductor layer 204. In some example embodiments, the source or drain region 802 is an n-channel source or drain region (e.g., epitaxial silicon with an n-type dopant) or a p-channel source or drain region (e.g., epitaxial SiGe with a p-type dopant). A contact 804 may be formed above the top surface of the source or drain region 802. The contact 804 may include any suitable conductive material for making electrical contact with the underlying source or drain region 802, such as tungsten, cobalt, molybdenum, or ruthenium. In some embodiments, the area above the source or drain region 802 is filled with a dielectric that is replaced by the contact 804 after the sacrificial gate 402 is replaced with the gate structure.

[0059] According to some embodiments, a dielectric filler 806 is disposed between adjacent source or drain regions 802 along a given source / drain trench extending in the second direction. In some examples, the dielectric filler 806 occupies the remaining volume within the source / drain trench around and possibly above a portion of the source or drain region 802. The dielectric filler 806 can be any suitable dielectric material, such as silicon dioxide. In some examples, the dielectric filler 806 extends all the way to and is planar with the top surface of the spacer structure 404 (e.g., after a polishing process).

[0060] Fig.9A and Fig. 9B 4 and 40 respectively show the structure of the sacrificial gate 402 and the sacrificial layer 202 after removal according to some embodiments. Fig. 8A and Figure 8B 4. In the example where the gate mask layer is still present, the gate mask layer can be removed at this time. Once the sacrificial gate 402 is removed, the fin extending between the spacer structures 404 is exposed.

[0061] In the example where the fin includes alternating semiconductor layers 202 and 204, the sacrificial layer 202 is selectively removed to leave a nanoribbon 902 extending between the corresponding source or drain regions 802. Each vertical collection of nanoribbons 902 represents a semiconductor region (also referred to as a channel region) of a different semiconductor device. It should be understood that the nanoribbons 902 can also be nanowires or nanosheets. The sacrificial gate 402 and the sacrificial layer 202 can be removed using the same isotropic etching process or different isotropic etching processes.

[0062] Fig. 10A and Fig. 10Band FIG. 1 respectively show the gate dielectric 1002 after it is formed according to some embodiments. Fig.9A and Fig. 9B . A gate dielectric 1002 may be formed around the nanoribbon 902 and along any exposed surface within the gate trench (such as along the sidewalls of the spacer structure 404). The gate dielectric 1002 may include any suitable dielectric material (such as silicon dioxide and / or a high-k dielectric material). Examples of high-k dielectric materials include, for example, hafnium oxide, hafnium silicon oxide, lanthanum oxide, lanthanum aluminum oxide, zirconium oxide, zirconium silicon oxide, tantalum oxide, titanium oxide, barium strontium titanium oxide, barium titanium oxide, strontium titanium oxide, yttrium oxide, aluminum oxide, lead scandium tantalum oxide, and lead zinc niobate to provide some examples. According to some embodiments, the gate dielectric 1002 includes a hafnium oxide layer having a thickness between about 1 nm and about 5 nm. In some embodiments, the gate dielectric 1002 may include one or more silicates (e.g., titanium silicate, tungsten silicate, niobium silicate, and silicates of other transition metals). In some cases, the gate dielectric 1002 includes a first layer on the nanoribbon 902 and a second layer on the first layer. The first layer may be an oxide of the semiconductor material of, for example, nanoribbon 902 (e.g., silicon dioxide), and the second layer may be a high-k dielectric material (e.g., hafnium oxide or aluminum oxide). Any excess gate dielectric may be removed from the top surface of the structure, for example, via a polishing process (e.g., chemical mechanical planarization CMP).

[0063] Fig.11A and Fig. 11B 1 and 2 respectively show the structure of the gate dielectric 1002 after forming a material layer 1102 on all surfaces of the gate dielectric 1002 in the gate trench according to some embodiments. Fig. 10A and Fig. 10B . According to some embodiments, material layer 1102 includes molybdenum, such as molybdenum nitride (MoN). Material layer 1102 may be deposited using ALD at a temperature between about 380° C. and about 390° C. using molybdenum and an ammonia (NH3) precursor. In some examples, material layer 1102 has a thickness between about 1 nm and 2 nm (e.g., to about According to some embodiments, the deposition conditions used to form the material layer 1102 do not damage the underlying gate dielectric 1002.

[0064] Fig. 12A and Fig. 12B The diagrams respectively show the structure of the protective layer 1202 after forming the protective layer 1202 on the material layer 1102 according to some embodiments. Fig.11A and Fig. 11B. The protective layer 1202 may include, for example, amorphous silicon or amorphous silicon germanium, and may be provided to protect the gate dielectric 1002 during the annealing process. After forming the protective layer 1202, an annealing process is performed to improve the quality of the gate dielectric 1002. The temperature and duration of the annealing may vary from example to example, but in some cases range from about 550° C. to about 650° C. for about 30 seconds to about 90 seconds.

[0065] Fig.13A and Fig. 13B 1 and 10, respectively, show the gate dielectric 1002 after forming one or more additional conductive layers to form a work function layer 1302 on top of the gate dielectric 1002 according to some embodiments. Fig. 12A and Fig. 12B . After the annealing process, the protective layer 1202 can be removed, and one or more additional conductive layers (e.g., one or more metal layers) can be formed over the material layer 1102 to provide a stack of work function layers 1302. In some embodiments, the work function layer 1302 fills the area between adjacent nanoribbons 902. The work function layer 1302 can be deposited using electroplating, electroless plating, CVD, PECVD, ALD, or PVD, to name a few examples.

[0066] The type and thickness of different work function layers 1302 depend on the type of transistor (n-type or p-type) and the desired threshold voltage of the transistor. For example, an n-channel transistor may have a work function layer 1302 that includes a material layer 1102 directly on the gate dielectric 1002 and a first work function layer 1304 on the material layer 1102, such as Fig. 13B . The first work function layer 1304 may include, for example, tantalum nitride. In another example, a p-channel transistor may have a work function layer 1302 including a material layer 1102 directly on the gate dielectric 1002, a first work function layer 1304 on the material layer 1102, and a second work function layer 1306 on the first work function layer 1304, as shown in FIG. Fig. 13B . The second work function layer 1306 may include, for example, titanium nitride. Other work function materials may also be used for each of the first work function layer 1304 and the second work function layer 1306. In some examples, an additional work function metal layer including aluminum-doped titanium carbide (TiAlC) is provided within the work function layer 1302. According to some embodiments, the thickness of the second work function layer 1306 may be used to adjust the threshold voltage of the p-channel transistor. For example, the threshold voltage of the p-channel transistor generally decreases as the thickness of the second work function layer 1306 increases.

[0067] Fig.14A and Fig. 14B 1402 after forming a conductive filler 1402 in the remaining volume of the gate trench according to some embodiments. Fig.13A and Fig. 13B . The conductive filler 1402 may include any suitable conductive metal material, such as tungsten, cobalt, or ruthenium. According to some embodiments, the conductive filler 1402 also includes one or more conductive adhesion layers to promote better adhesion to the underlying work function layer 1302. An example adhesion layer includes titanium nitride. According to some embodiments, the conductive filler 1402 and the work function layer 1302 together constitute a gate electrode disposed on the gate dielectric 1002. Other examples may not include any conductive filler 1402, where the work function layer 1302 uses up the entire space remaining after depositing the first work function layer 1304 or the second work function layer 1306.

[0068] Fig.15A and Fig. 15B and FIG. 1502 respectively show the gate cap 1502 after it is formed according to some embodiments. Fig.14A and Fig. 14B . The top portion of the gate electrode can be recessed using any suitable metal etching process, wherein the recessed area is filled with a dielectric material to form a gate cap 1502. Thus, the gate cap 1502 can be any suitable dielectric material, such as silicon nitride. In some examples, the gate cap 1502 includes the same dielectric material as the spacer structure 404. Other examples may not include the gate cap 1502.

[0069] Fig.16 Another example integrated circuit having a FinFET architecture in contrast to a GAA architecture is shown. Thus, the semiconductor region extending between the source region and the drain region has the shape of a fin 1602 extending above the substrate 201 . Fig.16 The cross section is taken across the gate trench (along the second direction) through different fins 1602. The same process described above for the GAA architecture can be used in the FinFET architecture to form a gate structure having a gate dielectric 1002, a work function layer 1302, and a conductive filler 1402 on the fin 1602. The work function layer 1302 may include different metal layers as described above, depending on whether the fin 1602 is part of an n-channel device or a p-channel device. But in either case, the work function layer 1302 includes a layer having molybdenum.

[0070] Fig.17An example embodiment of a chip package 1700 according to an embodiment of the present disclosure is shown. As can be seen, the chip package 1700 includes one or more dies 1702. The one or more dies 1702 may include at least one integrated circuit having a semiconductor device (e.g., any of the semiconductor devices disclosed herein). In some example configurations, the one or more dies 1702 may include any other circuitry for interfacing with other devices formed on the die or connected to the chip package 1700.

[0071] As can be further seen, the chip package 1700 includes a housing 1704 bonded to a package substrate 1706. The housing 1704 can be any standard or proprietary housing and can provide, for example, electromagnetic shielding and environmental protection for the components of the chip package 1700. One or more dies 1702 can be conductively coupled to the package substrate 1706 using connections 1708, which can be implemented using any number of standard or proprietary connection mechanisms, such as solder bumps, ball grid arrays (BGA), pins, or wire bonds, to name a few examples. The package substrate 1706 can be any standard or proprietary package substrate, but in some cases includes a dielectric material with conductive paths (e.g., including conductive vias and lines) that extend through the dielectric material between the faces of the package substrate 1706 or between different locations on each face. In some embodiments, the package substrate 1706 can have a thickness of less than 1 mm (e.g., between 0.1 mm and 0.5 mm), but any number of package geometries can be used. Additional conductive contacts 1712 may be provided at the opposite side of the package substrate 1706 for conductively contacting, for example, a printed circuit board (PCB). One or more vias 1710 extend through the thickness of the package substrate 1706 to provide a conductive path between one or more connections 1708 and one or more contacts 1712. For ease of illustration, the via 1710 is shown as a single straight column passing through the package substrate 1706, but other configurations may be used (e.g., inlays, dual inlays, through-silicon vias, or interconnect structures that meander through the thickness of the substrate 1706 to contact one or more intermediate locations therein). In further other embodiments, the via 1710 is made of multiple smaller stacked vias, or is staggered at different locations on the package substrate 1706. In the illustrated embodiment, the contacts 1712 are solder balls (e.g., for bump-based connections or ball grid array arrangements), but any suitable package engagement mechanism may be used (e.g., pins in a pin grid array arrangement, or lands in a land grid array arrangement). In some embodiments, solder resist is disposed between contacts 1712 to inhibit short circuits.

[0072] In some embodiments, molding material 1714 may be disposed around one or more dies 1702 included within housing 1704 (e.g., as an underfill material between die 1702 and package substrate 1706, and as an overfill material between die 1702 and housing 1704). Although the size and quality of molding material 1714 may vary from embodiment to embodiment, in some embodiments, molding material 1714 has a thickness of less than 1 millimeter. Example materials that may be used for molding material 1714 include epoxy molding material, if appropriate. In some cases, in addition to being electrically insulating, molding material 1714 is also thermally conductive.

[0073] method

[0074] Fig.18 is a flow chart of a method 1800 for forming at least a portion of an integrated circuit according to an embodiment. Figure 2A-15A and Figure 2B-15B The various operations of method 1800 are shown in the figure. However, the correlation of the various operations of method 1800 with the specific components shown in the aforementioned figures is not intended to imply any structural and / or use limitations. Instead, the aforementioned figures provide an example embodiment of method 1800. Other operations may be performed before, during, or after any operation of method 1800. For example, method 1800 does not explicitly describe various standard processes that are typically performed to form transistor structures. Some operations of method 1800 may be performed in an order different from the order shown.

[0075] According to some embodiments, method 1800 begins at operation 1802, where a plurality of parallel semiconductor fins are formed. The semiconductor material in the fins may be formed from a substrate such that the fins are an integral part of the substrate (e.g., etched from a bulk silicon substrate). Alternatively, the fins may be formed from a material deposited onto an underlying substrate. In one such example case, a blanket layer of SiGe may be deposited onto a silicon substrate, and then the blanket layer of SiGe may be patterned and etched to form a plurality of SiGe fins extending from the substrate. In another such example, non-native fins may be formed in a so-called aspect ratio trapping-based process, in which the native fins are etched away to leave fin-shaped trenches, which may then be filled with an alternative semiconductor material (e.g., a group IV or group III-V material). In further other embodiments, the fins include alternating material layers (e.g., alternating silicon layers and SiGe layers) that facilitate formation of nanowires and nanoribbons during a gate formation process, wherein one type of alternating layers is selectively etched away to release another type of alternating layers within the channel region so that a full-surround gate (GAA) process can then be performed. Again, according to some examples, the alternating layers can be blanket deposited and then etched into fins, or deposited into fin-shaped trenches. The fins may also include a capping structure over each fin that is used to define the position of the fin during, for example, an RIE process. The capping structure may be a dielectric material, such as silicon nitride.

[0076] According to some embodiments, a dielectric filler is formed around a sub-fin portion of one or more fins. In some embodiments, the dielectric filler extends between each pair of adjacent parallel fins and extends longitudinally in the same direction as the fins. In some embodiments, the anisotropic etching process that forms the fins also etches into a portion of the substrate, and the dielectric filler can be formed within a recessed portion of the substrate. Thus, the dielectric filler acts as a shallow trench isolation (STI) between adjacent fins. The dielectric filler can be any suitable dielectric material, such as silicon dioxide. The lower portion of the fin adjacent to the dielectric filler can be identified as a sub-fin.

[0077] Method 1800 continues with operation 1804, where a sacrificial gate is formed over the fin. The sacrificial gate may be patterned using a strip-shaped gate mask layer that extends orthogonally and parallel to each other over the fin (e.g., forming an intersecting hatch pattern). The gate mask layer may be any suitable hard mask material, such as CHM or silicon nitride. The sacrificial gate itself may be formed of any suitable material that may be selectively removed at a later time without damaging the semiconductor material of the fin. In one example, the sacrificial gate comprises polysilicon.

[0078] In accordance with some embodiments, a spacer structure is also formed on at least the sidewalls of the sacrificial gate. The spacer structure may be deposited and then etched back such that the spacer structure remains mostly only on the sidewalls of any exposed structure. In some cases, the spacer structure may also be formed along the sidewalls of the exposed fins extending orthogonally between the sacrificial gate strips. In accordance with some embodiments, the spacer structure may be any suitable dielectric material, such as silicon nitride or silicon oxynitride.

[0079] The method 1800 continues with operation 1806, where exposed portions of the fin are removed to form source / drain trenches. Any exposed portions of the fin not covered by the sacrificial gate or spacer structure may be removed using any anisotropic etching process, such as reactive ion etching (RIE). The sacrificial layer of the fin may be recessed (e.g., via an isotropic etching process), followed by deposition of an internal spacer (e.g., silicon nitride), as described above.

[0080] Method 1800 continues with operation 1808, where a source or drain region is formed at the opposite end of the fin within the source / drain trench. The source or drain region may be formed in an area previously occupied by the exposed fin between the spacer structures. According to some embodiments, the source or drain region is epitaxially grown from the exposed semiconductor material of the fin (or nanobelt, nanowire, or nanosheet, as the case may be) along the outer wall of the spacer structure. In some example embodiments, the source or drain region is an NMOS source or drain region (e.g., epitaxial silicon with n-type dopants) or a PMOS source or drain region (e.g., epitaxial SiGe with p-type dopants). A dielectric filler may be formed between and above the source or drain region along a given source / drain trench. The dielectric filler may be any suitable dielectric material, such as silicon dioxide. In some examples, the dielectric filler extends over the source or drain region to the top surface of the spacer structure and is in plane with the top surface of the spacer structure. The dielectric fill also acts as an electrical insulator between adjacent source or drain regions, but some adjacent source or drain regions may merge together during their growth.

[0081] Method 1800 continues with operation 1810 where the sacrificial gate is removed. According to some embodiments, the sacrificial gate may be removed along with any sacrificial layer within the exposed fins between the spacer structures (in the case of a GAA structure). The sacrificial gate and / or sacrificial layer may be removed using any suitable isotropic etching process.

[0082] The method 1800 continues with operation 1812, where a gate dielectric is formed within the gate trench (e.g., the area previously occupied by the sacrificial gate). The gate dielectric may include any number of dielectric layers deposited using an oxidation process and / or a conformal deposition process such as ALD. The gate dielectric may include at least one high-k dielectric material layer, such as a layer having hafnium oxide or aluminum oxide.

[0083] Method 1800 continues with operation 1814, where a conductive layer including molybdenum is formed on the gate dielectric. According to some embodiments, the conductive layer includes molybdenum nitride, and the conductive layer can be deposited using ALD with a molybdenum and ammonia (NH3) precursor at a temperature between about 380° C. and about 390° C. In some examples, the conductive layer including molybdenum nitride has a thickness of about to about The thickness of the molybdenum nitride layer is between 100 and 1000 nm. The precursors and temperatures used during the formation of the molybdenum nitride layer do not cause any significant damage to the gate dielectric. In some embodiments, the protective layer is deposited over the conductive layer including molybdenum. The protective layer may include amorphous silicon or any other similar amorphous semiconductor material.

[0084] The method 1800 continues with operation 1816, where an annealing process is performed on the gate dielectric using the molybdenum nitride layer. The annealing may be performed to strengthen the gate dielectric and improve its electrical properties. For example, the annealing may reduce charge traps within the gate dielectric. The temperature and duration of the annealing may vary from example to example, but in some cases range from about 550° C. to 650° C. for about 30 seconds to 90 seconds. After the annealing process, if a protective layer is present, the protective layer may be removed.

[0085] Method 1800 continues with operation 1818, where one or more additional conductive layers are formed over the molybdenum-containing layer to complete the formation of a gate electrode on the gate dielectric. According to some embodiments, the one or more additional conductive layers include a metal work function layer and a metal filler on the metal work function layer. The metal work function layer may be different depending on whether the transistor is an n-channel device or a p-channel device. The metal filler may be any suitable conductive material, such as tungsten. In some examples, the metal work function layer includes at least one tantalum nitride layer and at least one titanium nitride layer for a p-channel device and at least one tantalum nitride layer for an n-channel device. In some examples, the metal work function layer also includes a TiAlC layer.

[0086] In some embodiments, operation 1818 includes removing the molybdenum-containing layer before forming one or more additional conductive layers. Some n-channel devices (e.g., n-channel devices with relatively low threshold voltages) may not use a molybdenum-containing layer as one of their work function layers. According to some embodiments, an n-channel device without a molybdenum-containing layer may instead include a titanium nitride work function layer. Since the molybdenum-containing layer is present during the annealing process in operation 1816, the n-channel device that removes the molybdenum-containing layer still benefits from the improved gate dielectric.

[0087] Example System

[0088] Fig.19 1900 is an example computing system implemented using one or more of the integrated circuit structures as disclosed herein according to some embodiments of the present disclosure. As can be seen, computing system 1900 accommodates motherboard 1902. Motherboard 1902 may include multiple components, including but not limited to processor 1904 and at least one communication chip 1906, each of which may be physically and electrically coupled to motherboard 1902, or otherwise integrated therein. As will be appreciated, motherboard 1902 may be, for example, any printed circuit board (PCB), whether a motherboard, a daughterboard mounted on a motherboard, or the only board of system 1900, etc.

[0089] Depending on its application, the computing system 1900 may include one or more other components that may or may not be physically and electrically coupled to the motherboard 1902. These other components may include, but are not limited to, volatile memory (e.g., DRAM), non-volatile memory (e.g., ROM), a graphics processor, a digital signal processor, a cryptographic processor, a chipset, an antenna, a display, a touch screen display, a touch screen controller, a battery, an audio codec, a video codec, a power amplifier, a global positioning system (GPS) device, a compass, an accelerometer, a gyroscope, a speaker, a camera, and a mass storage device (such as a hard drive, a compact disk (CD), a digital versatile disk (DVD), etc.). Any component included in the computing system 1900 may include one or more integrated circuit structures or devices configured according to example embodiments (e.g., a module including an integrated circuit device on a substrate having one or more semiconductor devices including a gate structure including at least one layer having molybdenum as provided in various ways herein). In some embodiments, multiple functions may be integrated into one or more chips (eg, for example, note that the communication chip 1906 may be part of or otherwise integrated into the processor 1904).

[0090] The communication chip 1906 implements wireless communication to transmit data to and from the computing system 1900. The term "wireless" and its derivatives can be used to describe circuits, devices, systems, methods, technologies, communication channels, etc. that can transfer data via non-solid media using modulated electromagnetic radiation. The term does not mean that the associated device does not contain any wires, although in some embodiments they may not. The communication chip 1906 can implement any of a variety of wireless standards or protocols, including but not limited to Wi-Fi (IEEE 802.11 series), WiMAX (IEEE 802.16 series), IEEE802.20, Long Term Evolution (LTE), Ev-DO, HSPA+, HSDPA+, HSUPA+, EDGE, GSM, GPRS, CDMA, TDMA, DECT, Bluetooth, its derivatives, and any other wireless protocols named 3G, 4G, 5G and above. The computing system 1900 may include multiple communication chips 1906. For example, the first communication chip 1906 can be dedicated to shorter-range wireless communications such as Wi-Fi and Bluetooth, while the second communication chip 1906 can be dedicated to longer-range wireless communications such as GPS, EDGE, GPRS, CDMA, WiMAX, LTE, Ev-DO, etc.

[0091] The processor 1904 of the computing system 1900 includes an integrated circuit die packaged within the processor 1904. In some embodiments, the integrated circuit die of the processor includes on-board circuitry implemented using one or more semiconductor devices as described in various ways herein. The term "processor" may refer to any device or portion of a device that processes electronic data, such as from registers and / or memory, to transform the electronic data into other electronic data that may be stored in registers and / or memory.

[0092] The communication chip 1906 may also include an integrated circuit die packaged within the communication chip 1906. According to some such example embodiments, the integrated circuit die of the communication chip includes one or more semiconductor devices as described in various ways herein. As will be understood in light of the present disclosure, note that multi-standard wireless capabilities may be integrated directly into the processor 1904 (e.g., where the functionality of any chip 1906 is integrated into the processor 1904, rather than having a separate communication chip). Further note that the processor 1904 may be a chipset with such wireless capabilities. In short, any number of processors 1904 and / or communication chips 1906 may be used. Likewise, any one chip or chipset may have multiple functions integrated therein.

[0093] In various embodiments, computing system 1900 may be a laptop computer, a netbook, a notebook, a smart phone, a tablet computer, a personal digital assistant (PDA), an ultra-mobile PC, a mobile phone, a desktop computer, a server, a printer, a scanner, a monitor, a set-top box, an entertainment control unit, a digital camera, a portable music player, a digital video recorder, or any other electronic device that processes data or employs one or more integrated circuit structures or devices formed using the disclosed techniques and as described in various ways herein.

[0094] It will be appreciated that in some embodiments, the various components of computing system 1900 may be combined or integrated in a system-on-chip (SoC) architecture. In some embodiments, the components may be hardware components, firmware components, software components, or any suitable combination of hardware, firmware, or software.

[0095] Additional Example Embodiments

[0096] The following examples relate to additional embodiments from which numerous permutations and configurations will be apparent.

[0097] Example 1 is a method for forming an integrated circuit, the method comprising: forming a fin comprising one or more semiconductor layers, the fin extending in a first direction over a substrate; forming a sacrificial gate, the sacrificial gate extending in a second direction over the fin, the second direction being different from the first direction; removing an exposed portion of the fin adjacent to the sacrificial gate to form a groove passing through the fin; forming a source or drain region from ends of the one or more semiconductor layers and within the groove; removing the sacrificial gate from around the fin; forming one or more dielectric layers on the one or more semiconductor layers of the fin; forming a conductive layer on the one or more dielectric layers, wherein the conductive layer comprises molybdenum and nitrogen; after forming the conductive layer, annealing the one or more dielectric layers; and forming one or more additional conductive layers over the conductive layer.

[0098] Example 2 includes the method of Example 1, wherein forming the conductive layer includes forming the conductive layer using an atomic layer deposition (ALD) process.

[0099] Example 3 includes the method of Example 2, wherein the conductive layer includes molybdenum and nitrogen, and the ALD process uses molybdenum with an ammonia (NH 3 ) precursor gas.

[0100] Example 4 includes the method of any one of Examples 1-3, wherein forming the conductive layer comprises forming the conductive layer to be approximately to about The thickness between.

[0101] Example 5 includes the method of any of Examples 1-4, wherein forming the conductive layer includes forming the conductive layer at a temperature below 400°C.

[0102] Example 6 includes the method of any of Examples 1-5, wherein the one or more dielectric layers include at least one layer having a high-k dielectric material.

[0103] Example 7 includes the method of Example 6, wherein the high-k dielectric material includes hafnium and oxygen.

[0104] Example 8 includes the method of any of Examples 1-7, wherein forming the one or more additional conductive layers includes forming at least one additional conductive layer including nitrogen and one of tantalum or titanium.

[0105] Example 9 includes the method of any one of Examples 1-8, wherein forming the sacrificial gate includes forming spacers on sidewalls of the sacrificial gate, and removing the sacrificial gate includes removing the sacrificial gate between the spacers so as to expose the one or more semiconductor layers between the spacers.

[0106] Example 10 includes the method of any of Examples 1-9, further comprising removing the conductive layer and the one or more additional conductive layers to expose the one or more dielectric layers.

[0107] Example 11 includes the method of Example 10, further comprising forming another conductive layer including titanium and nitrogen on the one or more dielectric layers.

[0108] Example 12 is an integrated circuit comprising a semiconductor region extending from a source or drain region in a first direction, and a gate structure extending over the semiconductor region in a second direction different from the first direction. The gate structure comprises one or more dielectric layers on the semiconductor region and one or more conductive layers on the one or more dielectric layers. The one or more conductive layers comprise a conductive layer containing molybdenum and nitrogen. The source or drain region comprises silicon, germanium, or silicon germanium (SiGe) doped with an n-type dopant.

[0109] Example 13 includes the integrated circuit of Example 12, wherein the conductive layer is directly on the one or more dielectric layers.

[0110] Example 14 includes the integrated circuit of Example 12 or 13, wherein the conductive layer further comprises nitrogen and has a thickness of about to about The thickness between.

[0111] Example 15 includes the integrated circuit of any of Examples 12-14, wherein the one or more dielectric layers include at least one layer having a high-k dielectric material.

[0112] Example 16 includes the integrated circuit of Example 15, wherein the high-k dielectric material includes hafnium and oxygen.

[0113] Example 17 includes the integrated circuit of any of Examples 12-16, wherein the semiconductor region includes one or more semiconductor nanoribbons.

[0114] Example 18 includes the integrated circuit of Example 17, wherein the one or more semiconductor nanoribbons include germanium, silicon, or any combination thereof.

[0115] Example 19 includes the integrated circuit of any of Examples 12-18, wherein the conductive layer is a first conductive layer, and the one or more conductive layers include a second conductive layer on the first conductive layer, the second conductive layer including nitrogen and one of tantalum or titanium.

[0116] Example 20 is a printed circuit board comprising the integrated circuit of any one of Examples 12-19.

[0117] Example 21 is an electronic device, the electronic device including a chip package having one or more tube cores. At least one tube core of the one or more tube cores includes a semiconductor device, the semiconductor device having a semiconductor region extending from a source or drain region in a first direction, and a gate structure extending above the semiconductor region in a second direction different from the first direction. The gate structure includes one or more dielectric layers on the semiconductor region and one or more conductive layers on the one or more dielectric layers. The one or more conductive layers include a conductive layer containing molybdenum and nitrogen. The source or drain region includes silicon, germanium, or silicon germanium (SiGe) doped with an n-type dopant.

[0118] Example 22 includes the electronic device of Example 21, wherein the conductive layer is directly on the one or more dielectric layers.

[0119] Example 23 includes the electronic device of Example 21 or 22, wherein the conductive layer has a thickness of about to about The thickness between.

[0120] Example 24 includes the electronic device of any of Examples 21-23, wherein the one or more dielectric layers include at least one layer having a high-k dielectric material.

[0121] Example 25 includes the electronic device of Example 24, wherein the high-k dielectric material includes hafnium and oxygen.

[0122] Example 26 includes the electronic device of any of Examples 21-25, wherein the semiconductor region comprises one or more semiconductor nanoribbons.

[0123] Example 27 includes the electronic device of Example 26, wherein the one or more semiconductor nanoribbons include germanium, silicon, or any combination thereof.

[0124] Example 28 includes the electronic device of any of Examples 21-27, wherein the conductive layer is a first conductive layer, and the one or more conductive layers include a second conductive layer on the first conductive layer, the second conductive layer including tantalum and nitrogen.

[0125] Example 29 includes an electronic device of any one of Examples 21-28, wherein the semiconductor device is a first semiconductor device, the semiconductor region is a first semiconductor region, the source or drain region is a first source or drain region, the gate structure is a first gate structure, the one or more dielectric layers are first one or more dielectric layers, and the one or more conductive layers are first one or more conductive layers. At least one of the one or more dies also includes a second semiconductor device having a second semiconductor region extending from a second source or drain region in the first direction and a second gate structure extending over the second semiconductor region in the second direction. The second gate structure includes one or more second dielectric layers on the second semiconductor region and one or more second conductive layers on the one or more second dielectric layers. The one or more second conductive layers include a conductive layer containing molybdenum and nitrogen. The second source or drain region includes silicon, germanium, or SiGe doped with a p-type dopant.

[0126] Example 30 includes the electronic device of any of Examples 21-29, further comprising a printed circuit board (PCB), wherein the chip package is attached to the PCB.

[0127] Example 31 is a method of forming an integrated circuit, the method comprising: forming a fin comprising one or more semiconductor layers, the fin extending in a first direction over a substrate; forming a sacrificial gate, the sacrificial gate extending in a second direction over the fin, the second direction being different from the first direction; removing an exposed portion of the fin adjacent to the sacrificial gate to form a groove passing through the fin; forming a source or drain region from ends of the one or more semiconductor layers and within the groove, the source or drain region comprising silicon doped with an n-type dopant; removing the sacrificial gate from around the fin; forming one or more dielectric layers over the one or more semiconductor layers of the fin; forming a conductive layer over the one or more dielectric layers, wherein the conductive layer comprises molybdenum and nitrogen; and forming one or more additional conductive layers over the conductive layer.

[0128] Example 32 includes the method of Example 31, further comprising annealing the one or more dielectric layers after forming the conductive layer.

[0129] Example 33 includes the method of Example 31 or 32, wherein forming the conductive layer includes forming the conductive layer at a temperature below 400°C.

[0130] Example 34 includes the method of any of Examples 31-33, further comprising removing the conductive layer and the one or more additional conductive layers to expose the one or more dielectric layers.

[0131] Example 35 includes the method of Example 34, further comprising forming another conductive layer comprising titanium and nitrogen on the one or more dielectric layers.

[0132] Example 36 includes the method of any of Examples 1-11, wherein the annealing includes annealing the one or more dielectric layers at about 550° C. to about 650° C. for about 30 seconds to about 90 seconds.

[0133] For the purpose of illustration and description, the above description of the embodiments of the present disclosure has been presented. It is not intended to be exhaustive or to limit the present disclosure to the precise form described. Many modifications and variations are possible based on the present disclosure. The scope of the present disclosure is not intended to be limited by this specific embodiment, but is limited by the appended claims.

Claims

1. A method of forming an integrated circuit, comprising: forming a fin including one or more semiconductor layers, the fin extending in a first direction; forming a sacrificial gate extending over the fin in a second direction, the second direction being different from the first direction; removing an exposed portion of the fin adjacent to the sacrificial gate to form a groove passing through the fin; forming a source or drain region from an end of the one or more semiconductor layers and within the recess; removing the sacrificial gate from around the fin; forming one or more dielectric layers on the one or more semiconductor layers of the fin; forming a conductive layer on the one or more dielectric layers, wherein the conductive layer comprises molybdenum; annealing the one or more dielectric layers after forming the conductive layer; as well as One or more additional conductive layers are formed over the conductive layer.

2. The method according to claim 1, wherein: Forming the conductive layer includes forming the conductive layer using an atomic layer deposition (ALD) process.

3. The method according to claim 2, wherein: The conductive layer includes molybdenum and nitrogen, and the ALD process uses molybdenum and ammonia (NH 3 ) precursor gases.

4. The method according to claim 1, wherein: Forming the conductive layer includes forming the conductive layer to be approximately to about The thickness between.

5. The method according to claim 1, wherein: Forming the conductive layer includes forming the conductive layer at a temperature below 400°C.

6. The method according to claim 1, wherein: The one or more dielectric layers include at least one layer having a high-k dielectric material.

7. The method according to claim 6, wherein: The high-k dielectric material includes hafnium and oxygen.

8. The method according to any one of claims 1 to 7, wherein: Forming the one or more additional conductive layers includes forming at least one additional conductive layer including nitrogen, and one of tantalum or titanium.

9. The method according to any one of claims 1 to 7, wherein: Forming the sacrificial gate includes forming spacers on sidewalls of the sacrificial gate, and removing the sacrificial gate includes removing the sacrificial gate between the spacers so as to expose the one or more semiconductor layers between the spacers.

10. The method of any one of claims 1-7, further comprising removing the conductive layer and the one or more additional conductive layers to expose the one or more dielectric layers.

11. The method of claim 10, further comprising forming another conductive layer comprising titanium and nitrogen on the one or more dielectric layers.

12. The method according to any one of claims 1 to 7, wherein: The annealing includes annealing the one or more dielectric layers at about 550° C. to about 650° C. for about 30 seconds to about 90 seconds.

13. An integrated circuit comprising: a semiconductor region extending from a source or drain region in a first direction, wherein the source or drain region comprises one or both of silicon and germanium and is doped with an n-type dopant; and a gate structure extending over the semiconductor region in a second direction different from the first direction, wherein the gate structure comprises: one or more dielectric layers on the semiconductor region, and One or more conductive layers on the one or more dielectric layers, wherein the one or more conductive layers include a conductive layer containing molybdenum and nitrogen.

14. The integrated circuit of claim 13, wherein: The conductive layer is directly on the one or more dielectric layers.

15. The integrated circuit of claim 13, wherein: The conductive layer has a to about The thickness between.

16. The integrated circuit of claim 13, wherein: The one or more dielectric layers include at least one layer having a high-k dielectric material.

17. The integrated circuit of claim 16, wherein: The high-k dielectric material includes hafnium and oxygen.

18. The integrated circuit of claim 13, wherein: The semiconductor region includes one or more semiconductor nanoribbons.

19. An integrated circuit according to any one of claims 13 to 18, wherein: The conductive layer is a first conductive layer, and the one or more conductive layers include a second conductive layer on the first conductive layer, the second conductive layer including nitrogen, and one of tantalum or titanium.

20. The integrated circuit according to any one of claims 13 to 18, wherein: The semiconductor region is a first semiconductor region, the source or drain region is a first source or drain region, the gate structure is a first gate structure, the one or more dielectric layers are first one or more dielectric layers, the one or more conductive layers are first one or more conductive layers, and at least one of the one or more dies further comprises: a second semiconductor region extending from a second source or drain region in the first direction, wherein the second source or drain region comprises silicon doped with a p-type dopant, and A second gate structure extending above the second semiconductor region in the second direction, wherein the second gate structure comprises: one or more second dielectric layers on the second semiconductor region, and One or more second conductive layers on the one or more second dielectric layers, wherein the one or more second conductive layers include a conductive layer containing molybdenum and nitrogen.

21. A method of forming an integrated circuit, comprising: forming a fin including one or more semiconductor layers, the fin extending in a first direction; forming a sacrificial gate extending over the fin in a second direction, the second direction being different from the first direction; removing an exposed portion of the fin adjacent to the sacrificial gate to form a groove passing through the fin; forming a source or drain region from an end of the one or more semiconductor layers and within the recess, the source or drain region comprising silicon doped with an n-type dopant; removing the sacrificial gate from around the fin; forming one or more dielectric layers on the one or more semiconductor layers of the fin; forming a conductive layer on the one or more dielectric layers, wherein the conductive layer comprises molybdenum; and One or more additional conductive layers are formed over the conductive layer.

22. The method of claim 21, further comprising annealing the one or more dielectric layers after forming the conductive layer.

23. The method according to claim 21, wherein: Forming the conductive layer includes forming the conductive layer at a temperature below 400°C.

24. The method of any one of claims 21-23, further comprising removing the conductive layer and the one or more additional conductive layers to expose the one or more dielectric layers.

25. The method of claim 24, further comprising forming another conductive layer comprising titanium and nitrogen on the one or more dielectric layers.

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