Method for forming embedded interconnection structure

Abstract

The invention provides a method for forming a semiconductor device. The method comprises the following steps: forming a groove for an embedded interconnection structure between a first fin structure and a second fin structure; lining the trench with a dielectric layer; etching a contact opening in a first portion of the dielectric layer adjacent a first region of the first fin structure while masking a second portion of the dielectric layer adjacent a second region of the second fin structure directly opposite the first region; forming a local interconnect trench extending between the first region and the second region, where the second portion of the dielectric layer divides the local interconnect trench into a first trench portion and a second trench portion; and forming a first local interconnect and a second local interconnect in the first trench portion and the second trench portion, wherein the first local interconnect and the second local interconnect are spaced apart by a second portion of the dielectric layer.

Description

Technical Field

[0001] The present disclosure generally relates to a method for forming a buried interconnect structure. Background Art

[0002] Integrated circuits often include power rails (e.g., for VSS and VDD supply voltage distribution). Traditionally, the power rails are packaged within a back-end-of-line (BEOL) interconnect structure located above the level of the active physical devices (e.g., transistors such as FinFETs or nanosheet FETs). In contrast, a "buried" power rail (BPR) is at least partially lowered into the substrate so that the power rail can be located at a level below the active physical devices. This allows for reduced routing congestion in the BEOL. In addition, the BPR can be formed with an increased cross-section, thereby enabling reduced line resistance without taking up valuable space in the BEOL.

[0003] Local interconnects for active devices (e.g., MOAs) can be connected to BPRs through so-called vias to BPRs or power vias (PVs). Low resistance BPR connections facilitate large contact interfaces between PVs and BPRs and between PVs and local interconnects, thereby enlarging PVs and local interconnects along the critical dimension (CD), i.e., along the dimension parallel to the substrate and lateral to the BPRs. This reduces the spacing along the CD between local interconnects of laterally adjacent active devices (e.g., which may be disposed on opposite sides along a standard cell boundary).

[0004] Therefore, low resistance BPR connections reduce the process margin of PV and local interconnect formation and thus increase the sensitivity to random errors in the integration process, such as overlay error and over-etching. Summary of the invention

[0005] It is an object of the present invention to provide a method capable of forming a low resistance connection between a local interconnect and a BPR (or more generally, a buried interconnect structure such as a buried metal line) with improved reliability and process margin. Additional and alternative objects may be understood from the following.

[0006] Therefore, according to one aspect of the present invention, there is provided a method for forming a semiconductor device, the method comprising:

[0007] Forming a trench for a buried interconnect structure at a position between a first fin structure and a second fin structure extending in parallel along the substrate, wherein the trench extends through an isolation layer structure embedded in the first fin structure and the second fin structure;

[0008] lining the trench with a dielectric layer, the dielectric layer comprising a first portion and a second portion formed along opposing first and second sidewalls of the trench;

[0009] etching a contact opening in a first portion of the dielectric layer adjacent to a first region of the first fin structure while masking a second portion of the dielectric layer adjacent to a second region of the second fin structure, the second region directly opposite the first region;

[0010] After etching the contact opening, filling the trench with a dielectric material to restore the isolation layer structure over the buried interconnect structure;

[0011] forming a local interconnect trench in the isolation layer structure, the local interconnect trench extending between the first region and the second region and across the buried interconnect structure, wherein the local interconnect trench is formed by: selectively etching the isolation layer structure to the dielectric layer so that a second portion of the dielectric layer is retained to divide the local interconnect trench into a first trench portion for a first local interconnect and a second trench portion for a second local interconnect, wherein the first trench portion extends through a contact opening in the first portion of the dielectric layer; and

[0012] A first local interconnect is formed in the first trench portion and a second local interconnect is formed in the second trench portion, wherein the first local interconnect and the second local interconnect are separated by a second portion of the dielectric layer, wherein the second local interconnect contacts a source / drain formed in a second region of the second fin structure, and wherein the first local interconnect includes a source / drain contact portion contacting the source / drain formed in the first region of the first fin structure, a through-hole portion contacting the buried interconnect structure, and a bridge portion extending through the contact opening between the source / drain contact portion and the through-hole portion.

[0013] The method facilitates providing a low resistance via connection to a buried interconnect structure (such as a BPR) by allowing a contact interface between first local interconnects to extend along a width dimension of the buried interconnect structure (ie, across the buried interconnect structure).

[0014] The method involves selectively opening a dielectric layer lining a trench for a buried interconnect structure along one lateral sidewall of the trench, which enables interconnection of a first source / drain portion and a via portion of a first local interconnect through a bridge portion, while a second portion of the dielectric layer directly opposite the contact opening is retained to ensure a minimum isolation margin between the first local interconnect and the second local interconnect.

[0015] The method therefore allows the first local interconnect (specifically the bridging portion of the first local interconnect) to extend laterally toward the second local interconnect, thereby enabling the isolation margin and CD (i.e., tip-to-tip spacing) between adjacent local interconnects (e.g., M0A) to be reduced while reducing the risk of short circuits.

[0016] Since the source / drain contact portions, bridge portions and via portions are all formed in the first trench portion of the local interconnect trench extending through the contact opening, the location of the via connection can be formed in a self-aligned manner relative to the source / drain in the first region.

[0017] The corresponding source / drain formed in the first and second regions of the first and second fin structures, respectively, may generally be formed after restoring the isolation layer structure over the buried interconnect structure (eg, after restoring the isolation layer structure and before forming the local interconnect trench).

[0018] The term "buried metal line" refers herein to an interconnect structure (dummy or conductive) that is at least partially located below the active level of a transistor device (to be formed). Typically, the interconnect structure can be at least partially encapsulated in a shallow trench isolation (STI) structure embedded in the lower portion of the fin structure, and / or at least partially encapsulated in the substrate. The interconnect structure can be an elongated structure extending parallel to the fin structure. The term "first region" of the first fin structure refers herein to the region where the source / drain of the transistor will be or has been formed, or alternatively (and equivalently) refers to the region where the source / drain contact portion of the first local interconnect will be formed.

[0019] The term “second region” of the first fin structure refers herein to a region where the source / drain of the transistor will be or has been formed, or alternatively (and equivalently) refers to a region where the second local interconnect will be or has been formed.

[0020] The term "fin structure" refers herein to a pair of elongated semiconductor structures, such as semiconductor fins (eg, for finFETs) or horizontally oriented nanosheet stacks (eg, alternating stacks of sacrificial nanosheets and channel nanosheets).

[0021] In some embodiments, the buried interconnect structure is a buried conductive interconnect. The buried conductive interconnect may in particular be a buried conductive line, typically a buried metal line. The buried interconnect may for example be a buried power rail (BPR).

[0022] In some embodiments, the buried interconnect structure is a buried dummy interconnect, and the method includes replacing the buried dummy interconnect with a buried conductive interconnect during backside processing. The method can thus be compatible with a "replacement method" for forming a buried conductive interconnect (e.g., a buried wire). The replacement method can reduce the risk of adversely affecting the first region of the first fin structure due to metal contamination and metal etching during metal deposition and metal etchback when forming a conductive (e.g., metal) interconnect in a non-replacement flow.

[0023] In some embodiments, forming a local interconnect trench includes: forming an initial local interconnect trench by etching back an isolation layer structure through a first mask opening overlapping the buried interconnect structure, wherein the etching stops before exposing the buried interconnect structure; and forming a local interconnect trench by etching back the isolation layer structure through a second mask opening overlapping the initial interconnect trench and the first region and the second region.

[0024] The local interconnect trench can thus be formed in two consecutive etch-back steps, thereby allowing control of the width and height dimensions of the bottom of the first trench portion (which will accommodate the via portion) to be decoupled from the depth dimension of the upper portions of the first and second trench portions. The first mask opening can be defined to overlap the buried interconnect structure, but not the first and second regions.

[0025] In some embodiments, the first mask opening also overlaps the second portion of the dielectric layer.The first trench portion, and thus the first local interconnect, may thus extend laterally to abut / terminate at the second portion of the dielectric layer.

[0026] In some embodiments, the first mask opening also overlaps a contact opening in the dielectric layer.The vertical dimensions (ie, depth and height, respectively) of the first trench portion and thus the first local interconnect may thereby extend at the location of the contact opening.

[0027] In some embodiments, the buried interconnect structure is formed before forming the contact opening in the dielectric layer. Therefore, when forming a conductive (e.g., metal) interconnect in a non-replacement flow, the first region of the first fin structure can be protected from metal contamination and metal etching to a greater extent during metal deposition and metal etchback. In this case, when forming the contact opening in the dielectric layer, the dielectric layer can be masked by the buried interconnect structure at the bottom of the trench. Therefore, the dielectric layer can be retained along the sidewalls of the buried interconnect structure.

[0028] In some embodiments, the buried interconnect structure is formed after forming the contact opening in the dielectric layer. In this case, the dielectric layer can be masked by a temporary barrier layer at the bottom of the trench when forming the contact opening in the dielectric layer. Therefore, the dielectric layer can be retained along the bottom of the buried interconnect structure.

[0029] In some embodiments, the isolation layer structure includes a shallow trench isolation structure embedded in a lower portion of the fin structure and an interlayer dielectric layer covering the shallow trench isolation structure and embedded in an upper portion of the fin structure.

[0030] In some embodiments, the trench extends further into the substrate.

[0031] In some embodiments, the method further includes processing the first fin structure and the second fin structure to form a gate across the channel region of the first fin structure and the second fin structure and a source / drain in the first region and the second region of the first fin structure and the second fin structure, wherein the contact opening is formed before processing the first fin structure and the second fin structure. The buried interconnect structure and the contact opening can therefore be formed before the gate patterning and source / drain module of the front-end line processing. Therefore, the method can be integrated into the conventional integration method for FinFET and nanosheet FET manufacturing in a pipeline manner without any complex adjustments to the existing process steps. BRIEF DESCRIPTION OF THE DRAWINGS

[0032] This and other aspects of the present invention will now be described in more detail, with reference to the appended drawings showing embodiments of the invention.

[0033] Figure 1 A schematic cross-section of a semiconductor device including a BPR and a PV is shown, which device may be formed using conventional techniques.

[0034] Figure 2 A schematic cross-section of a semiconductor device including a BPR and a PV is shown, which device may be formed using embodiments of the present invention.

[0035] Figure 3 A schematic cross-section of an initial or precursor structure for a method of forming a buried interconnect structure according to an embodiment is shown.

[0036] Figure 4 The structure is shown after a trench for a buried interconnect structure is formed in the isolation layer structure and the trench is lined with a dielectric layer.

[0037] Figure 5 The structure is shown after forming a buried interconnect structure in the trench.

[0038] Figure 6 The structure is shown after forming an etch mask for etching contact openings in the dielectric layer.

[0039] Figure 7 The structure is shown after forming contact openings.

[0040] Figure 8 The structure is shown after filling the trench with a dielectric material to restore the isolation layer structure over the buried interconnect structure.

[0041] Fig. 9 is a schematic top view of the structure after forming contact openings in the dielectric layer.

[0042] Figure 10-12Process steps for forming local interconnect trenches in an isolation layer structure are shown.

[0043] Fig.13 The structure is shown after forming a first local interconnect in the first trench and the second trench portions of the local interconnect trench.

[0044] Fig.14 The structure is shown after the substrate is flipped over and backside processing is used to form backside interconnect structures.

[0045] Fig.15 The structure is shown after forming contact openings according to another method. DETAILED DESCRIPTION

[0046] Example embodiments and methods for forming buried interconnect structures will be described below with reference to the accompanying drawings. The accompanying drawings are schematic diagrams only, and the relative sizes of certain structures and layers may be exaggerated and not drawn to scale. Instead, the dimensions may be adjusted to make the illustration clear and easy to understand. When present in the figures, the indicated axes X, Y, and Z refer to the first horizontal or lateral, second horizontal or lateral, and vertical directions, respectively. As used herein, the terms "horizontal" and "lateral" refer to directions parallel to the (main surface of) the supporting substrate of the memory structure. The term "vertical" refers to a direction parallel to the normal direction of the substrate (main surface), i.e., transverse to the substrate.

[0047] Figure 1 A schematic cross section of a semiconductor or integrated circuit (IC) device 100 including a BPR and a PV is shown. The device 100 further includes a backside interconnect structure including a backside metal layer (BSM1) connected to the BPR via a through silicon via (TSV). The BPR and the PV can be formed using conventional techniques. As shown, an additional lateral spacing or margin (dashed line enclosed area) is provided between the local interconnect MOA at the top of the PV and the adjacent MOA. As a result, the width dimension of the PV (along the X-axis) is relatively small compared to the corresponding width dimension of the BPR. The PV can therefore provide a relatively high resistance connection between the local interconnect MOA and the BPR. In a standard unit circuit, the additional spacing can usually be placed at the boundary between two adjacent circuit units.

[0048] Figure 2 A schematic cross section of a corresponding semiconductor device 200 including a BPR and a PV is shown, which may be formed using embodiments of the present invention. As seen in the dashed enclosed area, additional lateral spacing or margin is provided here with Figure 1 That is, the local interconnect MOA extends further laterally (along the X-axis) toward the adjacent MOA. As a result, the width dimension of the PV (along the X-axis) is enlarged and can match or even exceed the corresponding width dimension of the BPR. Figure 1, PV can therefore provide a relatively low resistance connection between the local interconnect M0A and the BPR.

[0049] Figure 3 Shown is a schematic cross section of an initial or precursor structure 1 which is to undergo the processing steps of the method disclosed below.

[0050] The structure 1 includes a substrate 2 and first and second fin structures 4, 5 (interchangeably referred to as "fins"). The structure 1 is shown at a stage prior to front-side device processing such as gate patterning and source / drain formation.

[0051] The substrate 2 may be a conventional substrate, for example a semiconductor substrate such as a Si substrate, a Ge substrate or a SiGe substrate. Other examples include a silicon-on-insulator (SOI) substrate, a GeOI substrate or a SiGeOI substrate.

[0052] The fins 4 and 5 protrude from the substrate 2, that is, vertically protrude along the Z axis. The fins 4 and 5 extend parallel to the Y direction (see Fig. 9 ).

[0053] According to the example shown, the fins 4, 5 (as shown in fin 5) each include an alternating stack of channel nanosheets 5c and sacrificial nanosheets 5s (e.g., made of Si and SiGe, respectively). Therefore, the fins 4, 5 are suitable precursors for forming nanosheet FETs. However, the method is also applicable to fins 4, 5 formed as single semiconductor material bodies, which are suitable precursors for forming FinFETs (e.g., fins patterned in a single continuous layer of Si or SiGe). Fins for nanosheet-based FETs (e.g., nanosheet FETs, fork sheet FETs, CFETs) or FinFETs can be formed using any suitable conventional techniques known in the art.

[0054] The method will be described for a single pair of fins 4, 5 and used to form a single buried interconnect structure. However, it will be appreciated that the structure 1 may include multiple parallel fins 4, 5 and the method may be applied at multiple locations along the substrate 2 to form buried interconnect structures between multiple pairs of different fins.

[0055] An isolation layer structure 6 has been further formed to embed the fins 4, 5. The isolation layer structure 6 may include one or more dielectrics, for example, including oxides, such as SiO2 or other low-k dielectrics. As shown, the isolation layer structure 6 may include an STI structure or portion 6a embedded in the lower portion of the fins 4, 5, and an interlayer dielectric (ILD) layer 6b covering the STI structure 6a and embedded in the upper portion of the fins 4, 5. Although not shown separately, the isolation structure 6 may also include one or more dielectric liners and / or dummy oxides covering the fins as known in the art.

[0056] In any case, as shown in the figure, the thickness of the isolation layer structure 6 can exceed the height of the fins 4 and 5 on the substrate 2 (along the Z axis), so that the top surface of the isolation layer structure 6 (which can be flattened) is located above the fins 4 and 5, so that the fins 4 and 5 are completely embedded in the isolation layer structure 6.

[0057] Figure 4 The structure 1 is shown after forming a trench for a buried interconnect structure in the isolation layer structure 6 and then lining the trench with a dielectric layer (interchangeably referred to as a "liner"). As shown, the trench 8 can thus extend through the isolation layer structure 6 and optionally further into the substrate 2. The trench 8 can be elongated (e.g., along the Y axis, see FIG. 1 ). Fig. 9 ), and is parallel to the fins 4, 5 and extends along at least a portion of the length of the fins 4, 5. The trench 8 can be formed by photolithography and etching. Any etching process suitable for forming the trench 8 (which typically has a high aspect ratio) can be used, including, for example, anisotropic dry etching, such as reactive ion etching (RIE) or ion beam etching (IBE).

[0058] The liner 10 may be conformally deposited on the structure 1 using, for example, atomic layer deposition (ALD). The liner 10 may include one or more insulating materials, such as SiN, SiO2, SiC, SiCO, or SiOCN. The liner material(s) may typically be selected to be one or more materials that can be selectively etched to the material(s) of the isolation layer structure 6, so that the local interconnect trench 24 can be etched in the isolation layer structure 6 without causing any significant etching of the liner 10.

[0059] The dielectric layer / liner 10 lines (ie, covers) the sidewalls and bottom of the trench 8. The liner 10 includes a first portion 10a and a second portion 10b formed along first and second opposing sidewalls of the trench 8.

[0060] Figure 5 The structure 1 is shown after a buried interconnect structure 12 is formed in the trench 8. As shown, the buried interconnect structure 12 can fill the bottom of the trench 8. . As shown, the top surface of the buried interconnect structure 12 can be located at a level below the top of the corresponding fins 4, 5. In the example shown, the top surface of the buried interconnect structure 12 is approximately coincident with the base of the fins 4, 5. However, in another example, the trench 8 can extend deeper into the substrate 2, and the thickness of the buried interconnect structure 12 can be such that the top surface of the buried interconnect structure 12 is located below the fins 4, 5 (i.e., the buried interconnect structure 2 can be completely immersed in the thickness of the substrate 2). In any case, as seen along the Z axis, the height of the buried interconnect structure 12 will generally be less than the depth of the trench 8 (after being lined with the liner 10).

[0061] The buried interconnect structure 12 can be a conductive interconnect (e.g., a buried conductive interconnect line) comprising one or more conductive materials, such as one or more metals. Example metals include Cu, W, Ru, Ni, and Al. The metal(s) can be deposited by conventional deposition techniques such as chemical vapor deposition (CVD) or ALD. The conductive interconnect can also include barrier metals such as TiN. The deposited conductive material (e.g., metal) can then be recessed (e.g., by metal etching back) to a desired level. The buried interconnect structure 12 can be a BPR in particular and is therefore configured to deliver power to active devices in a finished circuit. However, other use cases for the buried interconnect structure 12 are also possible, such as for routing analog or digital signals.

[0062] Figure 6 The process for etching the contact opening 18 in the liner 10 is shown. Figure 7 ) as shown. The etch mask 14 can be a conventional photolithography layer stack, including, for example, a fill layer (e.g., spin-on carbon), a patterned film, and a photoresist on top. The etch mask 14 is patterned to define an opening 15 along a portion of the first portion 10a of the liner 10. More specifically, the opening 15 is defined along a portion of the first portion 10a adjacent to the first region 4a of the first fin 4 (i.e., selectively). At the same time, the etch mask 14 covers the second portion 10b along a portion of the liner 10 adjacent to the second region 5a of the second fin 5, the second region 5a being directly opposite to the first region 4a (i.e., along a direction across the trench 8, i.e., as seen along the X-axis). The first region 4a is a region where the source / drain contact portion 26a of the first local interconnect 26 will be formed, and the second region 5a is a region where the second local interconnect 28 will be formed (see, e.g., Fig.13 ). In addition, the first region 4a is a region where the source / drain 41 for the first FET will be formed, and the second region 5a is a region where the source / drain 51 for the second FET will be formed (see, for example Fig.10 ).

[0063] Figure 7 The structure 1 is shown after forming a contact opening 18 by etching the liner 10 through the opening 15 in the etching mask 14. The contact opening 18 is formed in a first portion 10a of the dielectric layer 10 adjacent to the first region 4a. Any suitable etching process, whether wet or dry, may be used. The opening 18 exposes the sidewall 6c of the isolation layer structure 6a along the first region 4a. While forming the contact opening 18, the buried interconnect structure 12 shields the dielectric layer 10 at the bottom of the trench 8.

[0064] Fig. 9 is a schematic top view of the structure 1 after forming the contact opening 18 and removing the etching mask 14. Fig. 9 As shown, corresponding contact openings 18' may be selectively formed in one or more other portions of the liner 10, including portions of the second portion 10b of the liner 10. Specifically, openings 18, 18' may be formed in the liner 10 along the trench 8 at each location where a through-hole connection between a local interconnect and a buried interconnect structure 12 is desired.

[0065] Figure 8 The structure 1 is shown after removing the etch mask 14 and filling the trench 8 with one or more dielectrics (e.g., one or more oxides, such as SiO2 or other low-k dielectrics) to restore the isolation layer structure 6 above the buried interconnect structure 12. After depositing the dielectric, the deposited dielectric may be recessed and / or planarized (e.g., by CMP and / or etch-back) so that the top of the liner 10 (e.g., the second portion 10b) is exposed, as shown in FIG. Figure 8 shown.

[0066] Figure 10-12 The process steps for forming the local interconnect trench 24 in the isolation layer structure 6 are shown. As shown in the figure, Figure 10-12 The process steps can be performed at a stage after the structure 1 is subjected to gate patterning and source / drain formation (e.g., including fin recesses and source-drain epitaxy). Therefore, reference numerals 41 and 51 respectively represent source / drain electrodes that have been formed in the first and second regions 4a, 5a of the fins 4 and 5. The dotted outline G schematically indicates the approximate location of the gate. One or more gates can be cut to form disconnected gates on the first and second fins 4 and 5. Gate patterning and source / drain formation can be performed according to conventional front-end line processing.

[0067] exist Fig.10 , an etch mask 20 has been formed on the isolation layer structure 6. The etch mask 20 defines a first mask opening having a width W1. The opening in the etch mask 20 can be formed along the contact opening 18 in the first portion 10a of the liner 10. That is, the opening in the etch mask 20 can be substantially aligned with the contact opening 18 along the longitudinal dimension (along the Y dimension) of the trench 8. The opening in the etch mask 20 can, for example, be substantially coextensive with the contact opening 18. The etch mask 20 can be formed as a conventional photolithography layer stack.

[0068] exist Fig.11 In the embodiment, by etching back the isolation layer structure 6 through the first mask opening in the etching mask 20, the opening in the etching mask 20 has been transferred to the upper thickness portion of the isolation layer structure 6, thereby forming an initial local interconnect trench 22 having a width dimension substantially matching W1.

[0069] exist Fig.12, an etching mask 23 has been formed on the isolation layer structure 6. The etching mask 23 defines a second mask opening of width W2, which overlaps the initial interconnect trench 22 and the first and second regions 4a, 5a (i.e., in the vertical direction, i.e., as seen along the Z axis). Subsequently, a local interconnect trench 24 is formed by (further) etching back the isolation layer structure 6 through the second mask opening in the etching mask 23, thereby forming a local interconnect trench having a width dimension substantially matching W2.

[0070] The local interconnect trench 24 extends between the first and second regions 4a, 5a and across the buried interconnect structure 12. The local interconnect trench 24 is formed by selectively etching the isolation layer structure 6 to the liner 10 so that the second portion 10b of the liner 10 is retained in the local interconnect trench 24, thereby dividing the local interconnect trench 24 into a first trench portion 24a and a second trench portion 24b. The etch back may continue until the top surface of the buried interconnect structure 12 (e.g., conductive interconnect) is exposed and at least the top of the source / drain 41, 51 is exposed. The first trench portion 24a includes a bottom portion 24aa having a bottom surface at least partially defined by the top surface of the buried interconnect structure 12.

[0071] The first trench portion 24a defines a portion for accommodating a first local interconnect 26 for connecting the source / drain 41 and the buried interconnect structure 12. Correspondingly, the second trench portion 24b defines a portion for accommodating a second local interconnect 28 for contacting the source / drain 51. The connection between the source / drain 41 and the buried interconnect structure 12 is facilitated by the contact opening 18 in the first portion 10a of the liner 10. That is, the first trench portion 24a extends through the contact opening 18.

[0072] like Figure 10-11 As shown, the opening in the etch mask 20 and the initial local interconnect trench 22 can already be defined to overlap with the second portion 10b of the liner 10. This can provide overlay compensation to ensure that even if overlay errors occur when patterning the etch mask 20, the first trench portion 24a can expose the buried interconnect structure 12 along its full width dimension.

[0073] like Figure 10-11 As further shown, the first mask opening W1 in the etch mask 20 may also overlap the contact opening 18 in the liner 10. That is, the first mask opening W1 may extend across the first portion 10a of the liner 10 and the contact opening 18. This allows the bridge portion 26b (see FIG. 24) of the first local interconnect 26 formed in the first trench portion 24a to be overlapped. Fig.13 ) extends in height dimension and advantageously matches the depth / height of the contact opening 18 .

[0074] exist Fig.12In the embodiment, the width dimension W2 of the second opening in the etch mask 23 corresponds approximately to the pitch of the fins 4, 5. However, in another example, the width dimension W2 of the second opening can span across one or more additional fins, thereby allowing "merged lithography" (i.e., simultaneous etching through a common second mask opening) of local interconnect trenches for three or more fins.

[0075] Due to the two-step etch-back method used to form the local interconnect trench 24, the bottom surface of the bottom 24aa of the first trench portion 24a is located at a level below the bottom surface portion of the local interconnect trench 24a surrounding the source / drain 41, 51. Therefore, the two-step etch-back method allows the depth of the local interconnect trench 24 at the first and second regions 4a, 5a to be controlled independently of the depth at the buried interconnect structure 12, at least to some extent. Although this may be beneficial in some cases to reduce the risk of over-etching the isolation layer structure 6 at the first and second regions 4a, 5a (potentially exposing the substrate 2), when there is sufficient vertical etching margin, a single-step etch can be used instead of the two-step etch-back method to directly form the local interconnect trench 24.

[0076] Fig.13 The structure 1 is shown after removing the etch mask 23 and forming first and second local interconnects 26 , 28 in the first and second trench portions 24 a - b of the local interconnect trench 24 .

[0077] The first and second local interconnects 26, 28 are separated by the second portion 10b of the liner 10. The second local interconnect 28 contacts the source / drain 51 formed in the second region 5a of the second fin 5. The first local interconnect 26 includes: a source / drain contact portion 26a, which contacts the source / drain electrode 41 formed in the first region 4a of the fin 4; a through-hole portion 26c (e.g., formed in the bottom 24aa of the first trench portion 24a), which contacts the buried interconnect structure 12; and a bridge portion 26b, which extends between the source / drain contact portion 26a and the through-hole portion 26c through the contact opening 18. Therefore, the first local interconnect 26 interconnects the source / drain 41 and the buried interconnect structure 12. Due to the lateral isolation margin provided by the second portion 10b of the liner 10, both the bridge portion 26b and the through-hole portion 26c can extend laterally (along the X-axis) to cross and thus connect with the full width dimension of the buried interconnect structure 12. This enables low resistance connections between the source / drain 41 and the buried interconnect structure 12 even with aggressive contact and fin pitches.

[0078] The first and second local interconnects 26, 28 may be formed by depositing one or more contact metals that fill the first and second trench portions 24a-b. Examples of contact metals include metals commonly used for source / drain contacts, such as W and Al, optionally preceded by a metal liner, such as TiN. The contact metal(s) may be deposited by CVD and / or ALD. After metal deposition, the blanket metal may be removed by a planarization and metal recessing process (e.g., CMP and / or metal etch back) to stop at the top of the second portion 10b of the liner 10 to separate the metal(s) into discrete local interconnects 26, 28.

[0079] As reference Figure 2 It can be understood that the source / drain contact portion 28, the source / drain contact portion 26a and the bridge portion 26b can form part of the MOA local interconnect layer, and the through-hole contact portion 26c can correspond to the PV of the distance between the vertical bridge MOA layer and the buried interconnect structure 12 (such as BPR).

[0080] Although reference numerals 26a-c refer to different portions of the first local interconnect 26, the first local interconnect 26 forms a continuum of one or more metals. Fig.13 The dashed lines indicating the divisions between the portions 26 a - c do not represent any physical boundaries or partitions of the first local interconnect 26 , but are merely added to facilitate understanding of the physical extension of the first local interconnect 26 .

[0081] Fig.14 The structure 1 is shown after the substrate 2 is flipped over and backside processing is used to form a backside interconnect structure. The backside processing may include thinning the substrate 2 from the backside to expose the backside or underside of the buried interconnect structure 12. Thereafter, the backside processing may continue to form one or more backside interconnect layers, including, for example, depositing an ILD 30 and forming TSVs 32 for contacting the buried interconnect structure 12, and a backside interconnect 34 (e.g., using a dual damascene process).

[0082] Those skilled in the art realize that the present invention is by no means limited to the embodiments described above. On the contrary, many modifications and variations are possible within the scope of the appended claims.

[0083] For example, in the above, the method steps have been described for a buried interconnect structure 12 in the form of a conductive interconnect (e.g., a BPR). However, the method is also compatible with an alternative method in which the buried interconnect structure 12 can be formed as a dummy structure of a dummy material (e.g., amorphous silicon) and then removed and replaced with a final conductive interconnect (e.g., any of the example metals discussed above for the buried interconnect structure 12) using selective etching after substrate thinning for backside processing.

[0084] Fig.15 A structure 1 according to yet another variation of the above method is shown, in which a contact opening 18 is formed before forming a buried interconnect structure 12 (which may be a conductive interconnect or a dummy interconnect). In this case, a dedicated temporary barrier layer 36 may be formed to fill the bottom of the trench 8 before forming the etching mask 14. Thus, when etching the contact opening 18, the temporary barrier layer 36 may mask the liner 10 formed along the sidewalls and bottom of the bottom of the trench 8. The barrier layer 36 may then be removed and replaced with the final conductive interconnect, i.e., it may be a dummy structure of dummy material, as discussed above. The temporary barrier layer 36 may be formed, for example, of a spin-on carbon material or some other material that has sufficient etching contrast with the material of the liner 10, good filling properties, and may be easily removed from the trench 8 without leaving any substantial residue.

Claims

1. A method for forming a semiconductor device, the method comprising: Forming a trench for a buried interconnect structure at a position between a first fin structure and a second fin structure extending in parallel along the substrate, wherein the trench extends through an isolation layer structure embedded in the first fin structure and the second fin structure; lining the trench with a dielectric layer, the dielectric layer comprising a first portion and a second portion formed along opposing first and second sidewalls of the trench; After lining the trench, forming a buried interconnect structure in the trench; etching a contact opening in the first portion of the dielectric layer adjacent to a first region of the first fin structure while masking the second portion of the dielectric layer adjacent to a second region of the second fin structure, the second region being directly opposite the first region; After etching the contact opening, filling the trench with a dielectric material to restore the isolation layer structure over the buried interconnect structure; forming a local interconnect trench in the isolation layer structure, the local interconnect trench extending between the first region and the second region and across the buried interconnect structure, wherein the local interconnect trench is formed by: selectively etching the isolation layer structure to the dielectric layer so that the second portion of the dielectric layer is retained to divide the local interconnect trench into a first trench portion for a first local interconnect and a second trench portion for a second local interconnect, wherein the first trench portion extends through the contact opening in the first portion of the dielectric layer; as well as A first local interconnect is formed in the first trench portion and a second local interconnect is formed in the second trench portion, wherein the first local interconnect and the second local interconnect are separated by the second portion of the dielectric layer, wherein the second local interconnect contacts a source / drain formed in the second region of the second fin structure, and wherein the first local interconnect includes a source / drain contact portion contacting the source / drain formed in the first region of the first fin structure, a through-hole portion contacting the buried interconnect structure, and a bridge portion extending through the contact opening between the source / drain contact portion and the through-hole portion.

2. The method of claim 1, wherein the buried interconnect structure is a buried conductive interconnect.

3. The method of claim 1, wherein the buried interconnect structure is a buried dummy interconnect, and the method includes replacing the buried dummy interconnect with a buried conductive interconnect during backside processing. The method of claim 1 , wherein the buried conductive interconnect is a buried power rail.

5. The method of claim 1 , wherein forming the local interconnect trench comprises: forming an initial local interconnect trench by etching back the etched isolation layer structure through a first mask opening overlapping the buried interconnect structure, wherein the etching back stops before exposing the buried interconnect structure; as well as The local interconnect trench is formed by etching back the isolation layer structure through a second mask opening overlapping the initial interconnect trench and the first region and the second region. The method of claim 5 , wherein the first mask opening also overlaps the second portion of the dielectric layer.

7. The method of claim 6, wherein the first mask opening also overlaps the contact opening in the dielectric layer.

8. The method of claim 1, wherein the buried interconnect structure is formed before forming the contact opening in the dielectric layer.

9. The method of claim 8, wherein when forming the contact opening in the dielectric layer, the dielectric layer is masked by the buried interconnect structure at the bottom of the trench.

10. The method of claim 1, wherein the buried interconnect structure is formed after forming the contact opening in the dielectric layer. 11 . The method of claim 10 , wherein when forming the contact opening in the dielectric layer, the dielectric layer is masked by a temporary barrier layer at the bottom of the trench. 12 . The method according to claim 1 , wherein the isolation layer structure comprises a shallow trench isolation structure embedded in a lower portion of the fin structure and an interlayer dielectric layer covering the shallow trench isolation structure and embedded in an upper portion of the fin structure.

13. The method of claim 1, wherein the trench extends further into the substrate.

14. The method of claim 1 further comprises processing the first fin structure and the second fin structure to form a gate across the channel region of the first fin structure and the second fin structure and a source / drain in the first region and the second region of the first fin structure and the second fin structure, wherein the contact opening is formed before processing the first fin structure and the second fin structure.

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