Semiconductor device including backside power supply network

Abstract

A semiconductor device including a backside power supply network (BSPDN) is provided. The semiconductor device includes: a substrate; a first active pattern extending in a first direction on a top surface of the substrate; a second active pattern extending in the first direction on the top surface of the substrate and spaced apart from the first active pattern in a second direction crossing the first direction; a gate structure extending in a second direction on the first active pattern and the second active pattern; a first source / drain pattern connected to the first active pattern on a side surface of the gate structure; a second source / drain pattern connected to the second active pattern on a side surface of the gate structure; a backside source / drain contact penetrating the substrate; and a first power line connected to the backside source / drain contact on the bottom surface of the substrate.

Description

Technical Field

[0001] The present disclosure relates to a semiconductor device including a backside power supply network. Background Art

[0002] Semiconductor devices include, for example, semiconductor memory devices for storing logic data, semiconductor logic devices for processing calculations of logic data, hybrid semiconductor devices including storage elements and logic elements, etc. The demand for high reliability, high speed and / or versatility, etc. for semiconductor devices is increasing. In order to meet these demands, the structures in semiconductor devices are becoming more and more complex and highly integrated. As semiconductor devices become more highly integrated, the width of wiring patterns and path patterns that implement semiconductor devices is decreasing. Summary of the invention

[0003] Aspects of the present disclosure provide semiconductor devices with improved power, performance, area, cost (PPAC).

[0004] Aspects of the present disclosure also provide methods for fabricating semiconductor devices having improved PPAC.

[0005] However, aspects of the present disclosure are not limited to the aspects set forth herein. The above and other aspects of the present disclosure will become more apparent to those skilled in the art to which the present disclosure pertains by referring to the detailed description of the present disclosure given below.

[0006] According to some aspects of the present disclosure, a semiconductor device is provided, comprising: a substrate; a first active pattern extending in a first direction on a top surface of the substrate; a second active pattern extending in the first direction on the top surface of the substrate and spaced apart from the first active pattern in a second direction intersecting the first direction; a gate structure extending in the second direction on the first active pattern and the second active pattern; a first source / drain pattern connected to the first active pattern on a side surface of the gate structure; a second source / drain pattern connected to the second active pattern on a side surface of the gate structure; a first back source / drain contact penetrating the substrate to be connected to the first source / drain pattern; a second back source / drain contact penetrating the substrate to be connected to the second source / drain pattern, and Spaced apart from the first back source / drain contact in the second direction; and a first power line extending in the first direction on the bottom surface of the substrate and connected to the first back source / drain contact and the second back source / drain contact, wherein the first back source / drain contact includes a first side surface facing the second back source / drain contact and a second side surface opposite to the first side surface, the second back source / drain contact includes a third side surface facing the first back source / drain contact and a fourth side surface opposite to the third side surface, at the bottom surface of the substrate, the second side surface and the fourth side surface are spaced apart from each other by a first distance in the second direction, and at the bottom surface of the first power line, at least a portion of the first power line has a first width in the second direction that is less than the first distance.

[0007] According to some aspects of the present disclosure, a semiconductor device is provided, comprising: a first substrate pattern extending in a first direction; a second substrate pattern extending in the first direction and spaced apart from the first substrate pattern in a second direction intersecting the first direction; a first active pattern extending in the first direction on a top surface of the first substrate pattern; a second active pattern extending in the first direction on a top surface of the second substrate pattern; a gate structure extending in the second direction on the first active pattern and the second active pattern; a first source / drain pattern connected to the first active pattern on a side surface of the gate structure; a second source / drain pattern connected to the second active pattern on a side surface of the gate structure; a first back source / drain contact connected to the first source / drain pattern in the first substrate pattern; A second back source / drain contact, connected to the second source / drain pattern in the second substrate pattern; and a first power line, extending in a first direction on a bottom surface of the first substrate pattern and on a bottom surface of the second substrate pattern and connected to the first back source / drain contact and the second back source / drain contact, wherein the first substrate pattern includes a first side surface facing the second substrate pattern and a second side surface opposite to the first side surface, the second substrate pattern includes a third side surface facing the first substrate pattern and a fourth side surface opposite to the third side surface, at the bottom surface of the first substrate pattern, the second side surface and the fourth side surface are spaced apart from each other by a first distance in the second direction, and at the bottom surface of the first power line, at least a portion of the first power line has a first width in the second direction that is less than the first distance.

[0008] According to some aspects of the present disclosure, a semiconductor device is provided, comprising: a substrate; first to third active patterns, each of the first to third active patterns extending in a first direction on a top surface of the substrate and arranged in sequence along a second direction intersecting the first direction; a gate structure extending in a second direction, each of the first to third active patterns penetrating the gate structure; a first back source / drain contact penetrating the substrate to be connected to a first source / drain pattern of the first active pattern; a second back source / drain contact penetrating the substrate to be connected to a second source / drain pattern of the second active pattern; a third back source / drain contact penetrating the substrate to be connected to a third source / drain pattern of the third active pattern; a first power line extending in the first direction on a bottom surface of the substrate and connected to the first back source / drain; The first back source / drain contact and the second back source / drain contact are in contact and a first power supply voltage is applied to them; and a second power supply line extends in the first direction on the bottom surface of the substrate, is connected to the third back source / drain contact and a second power supply voltage different from the first power supply voltage is applied to them, wherein the first back source / drain contact includes a first side surface facing the second back source / drain contact and a second side surface opposite to the first side surface, the second back source / drain contact includes a third side surface facing the first back source / drain contact and a fourth side surface opposite to the third side surface, at the bottom surface of the substrate, the second side surface and the fourth side surface are spaced apart from each other by a first distance in the second direction, and at the bottom surface of the first power line, at least a portion of the first power line has a first width in the second direction that is less than the first distance. BRIEF DESCRIPTION OF THE DRAWINGS

[0009] The above and other aspects and features of the present disclosure will become more apparent by describing in detail examples of the present disclosure with reference to the accompanying drawings, in which:

[0010] Figure 1 is a layout diagram illustrating a semiconductor device according to some implementations.

[0011] Figure 2 It is along Figure 1 A schematic cross-sectional view taken along line AA.

[0012] Figure 3 It is along Figure 1 A schematic cross-sectional view taken along line BB of FIG.

[0013] Figure 4 It is shown Figure 3 Magnified view of region R1.

[0014] Figure 5 It is along Figure 1 A schematic cross-sectional view taken along line CC of FIG.

[0015] Figure 6 It is shown Figure 5 Magnified view of region R2.

[0016] Figure 7 It is along Figure 1 A schematic cross-sectional view taken along line DD.

[0017] Figure 8 is a schematic cross-sectional view illustrating a semiconductor device according to some implementations.

[0018] Fig. 9 It is shown Figure 8 An enlarged view of region R3.

[0019] Fig.10 is a schematic cross-sectional view illustrating a semiconductor device according to some implementations.

[0020] Fig.11 It is shown Fig.10 An enlarged view of region R4.

[0021] Fig.12 is a layout diagram illustrating a semiconductor device according to some implementations.

[0022] Fig.13 It is along Fig.12 A schematic cross-sectional view taken along line EE.

[0023] Fig.14 is a layout diagram illustrating a semiconductor device according to some implementations.

[0024] Fig.15 It is along Fig.14 A schematic cross-sectional view taken along line FF.

[0025] Fig.16 is a layout diagram illustrating a semiconductor device according to some implementations.

[0026] Fig.17 It is along Fig.16 A schematic cross-sectional view taken along line GG.

[0027] Fig.18 is a layout diagram illustrating a semiconductor device according to some implementations.

[0028] Fig.19 It is along Fig.18 A schematic cross-sectional view taken along line HH of FIG.

[0029] FIG. 20A to FIG. 21B is a layout diagram illustrating a semiconductor device according to some implementations.

[0030] Figures 22 to 39are diagrams illustrating intermediate steps of a method for manufacturing a semiconductor device according to some implementations. DETAILED DESCRIPTION

[0031] Although the terms first, second, etc. can be used to describe various elements or components here, these elements or components should not be limited by these terms. These terms are used to distinguish an element or component from another element or component. Therefore, the first element or component discussed below can be referred to as the second element or component without departing from the teaching of the present disclosure.

[0032] The reduced width of the wiring patterns and via patterns can be associated with an increased voltage drop of the power delivery network (PDN). For example, the "IR" drop of the power supply voltage of the integrated circuit may increase. Aspects of the present disclosure provide semiconductor devices, systems, and methods that can provide improved power, performance, area, and / or cost in this context.

[0033] In the following, reference will be made to Figures 1 to 22 Semiconductor devices according to some implementations are described.

[0034] Figure 1 is a layout diagram illustrating a semiconductor device according to some implementations. Figure 2 It is along Figure 1 A schematic cross-sectional view taken along line AA. Figure 3 It is along Figure 1 A schematic cross-sectional view taken along line BB of FIG. Figure 4 It is shown Figure 3 Magnified view of region R1. Figure 5 It is along Figure 1 A schematic cross-sectional view taken along line CC of FIG. Figure 6 It is shown Figure 5 Magnified view of region R2. Figure 7 It is along Figure 1 A schematic cross-sectional view taken along line DD.

[0035] Reference Figures 1 to 7 According to some implementations, a semiconductor device includes a substrate 100, a plurality of active patterns A1 to A4, a plurality of gate structures G1 to G8, a plurality of source / drain patterns 160A to 160D (such as Figure 5 As shown), a first interlayer insulating layer 172, a second interlayer insulating layer 174, a plurality of front source / drain contacts FC1 to FC4, a front wiring structure FS, a plurality of back source / drain contacts BC1 to BC4 and a back wiring structure BS.

[0036] The substrate 100 may include a top surface and a bottom surface opposite to each other. In this specification, the top surface of the substrate 100 may also be referred to as a front surface, and the bottom surface of the substrate 100 may also be referred to as a back surface.

[0037] The substrate 100 may include a first cell region CR1 and a second cell region CR2 adjacent to each other. For example, the first cell region CR1 and the second cell region CR2 may each extend in a first direction X, and may be arranged along a second direction Y intersecting (e.g., orthogonal to) the first direction X. At least one integrated circuit may be provided in each of the first cell region CR1 and the second cell region CR2. The integrated circuit provided in the first cell region CR1 and the second cell region CR2 may include various logic elements (such as inverters, AND gates, OR gates, NAND gates, NOR gates, and XOR gates) or static random access memory (SRAM) devices, but is not limited thereto.

[0038] In some implementations, the substrate 100 may include an insulating material. For example, the substrate 100 may be an insulating substrate including at least one of silicon oxide, silicon oxynitride, silicon oxycarbon nitride, and combinations thereof.

[0039] In some implementations, the substrate 100 may include a plurality of base patterns 102 and a field insulation layer 105 .

[0040] The base patterns 102 may extend side by side while being spaced apart from each other. For example, the base patterns 102 may each extend in a first direction X and may be spaced apart from each other in a second direction Y. In some implementations, each base pattern 102 may include an insulating material. For example, each base pattern 102 may include at least one of silicon oxide, silicon nitride, silicon carbide oxide, silicon oxynitride oxide, silicon oxycarbon nitride, and combinations thereof, but the present disclosure is not limited thereto.

[0041] The field insulating layer 105 may cover at least a portion of the side surface of each base pattern 102. For example, the field insulating layer 105 may fill the space between the base patterns 102. The field insulating layer 105 may include, for example, at least one of silicon oxide, silicon nitride, silicon carbon oxide, silicon nitride oxide, silicon oxycarbon nitride, and a combination thereof, but is not limited thereto. The field insulating layer 105 may include the same material as the base pattern 102, or may include a material different from the material of the base pattern 102. In some implementations, the bottom surface of the field insulating layer 105 may be disposed on the same plane as the bottom surface of the base pattern 102. In some implementations, the top surface of the field insulating layer 105 may be disposed on the same plane as the top surface of the base pattern 102.

[0042] A plurality of active patterns A1 to A4 may be disposed on the top surface of the substrate 100. The active patterns A1 to A4 may extend side by side while being spaced apart from each other. For example, the active patterns A1 to A4 may include a first active pattern A1, a second active pattern A2, a third active pattern A3, and a fourth active pattern A4 sequentially arranged along the second direction Y. The active patterns A1 to A4 may each extend in the first direction X and may be spaced apart from each other in the second direction Y. The first active pattern A1 and the second active pattern A2 may be disposed on the first cell region CR1, and the third active pattern A3 and the fourth active pattern A4 may be disposed on the second cell region CR2.

[0043] Each of the active patterns A1 to A4 may include silicon (Si) or germanium (Ge) which is an elemental semiconductor material. For example, each of the active patterns A1 to A4 may include a silicon pattern. Each of the active patterns A1 to A4 may include a compound semiconductor, such as a group IV-IV compound semiconductor or a group III-V compound semiconductor. The group IV-IV compound semiconductor may be a binary compound or a ternary compound including at least two elements selected from the group consisting of carbon (C), silicon (Si), germanium (Ge), and tin (Sn), or the above compound doped with a group IV element. The group III-V compound semiconductor may be, for example, a binary compound, a ternary compound, or a quaternary compound formed by combining at least one of aluminum (Al), gallium (Ga), and indium (In) as group III elements with at least one of phosphorus (P), arsenic (As), and antimony (Sb) as group V elements.

[0044] In some implementations, the active patterns A1 to A4 may be disposed on a top surface of the base pattern 102. For example, the active patterns A1 to A4 and the base pattern 102 may overlap in a third direction Z crossing the top surface of the substrate 100.

[0045] In some implementations, each of the active patterns A1 to A4 may include a plurality of bridge patterns (e.g., first to third bridge patterns 111, 112, and 113) sequentially stacked on the base pattern 102 and spaced apart from each other. These active patterns A1 to A4 may be used as a multi-bridge channel metal oxide semiconductor field effect transistor (MBCFET) including a multi-bridge channel. ® The number of bridge patterns included in each of the active patterns A1 to A4 is only an example and is not limited thereto.

[0046] A plurality of gate structures G1, G2, G3, G4, G5, G6, G7, and G8 may be disposed on the substrate 100 and the active patterns A1 to A4. The gate structures G1 to G8 may extend side by side while being spaced apart from each other. In addition, the gate structures G1 to G8 may intersect the active patterns A1 to A4. For example, the gate structures G1 to G8 may be elongated in the second direction Y and may be spaced apart from each other in the first direction X.

[0047] In some implementations, the active patterns A1 to A4 penetrate the gate structures G1 to G8 while extending along the first direction X. For example, the bridge patterns 111 to 113 may penetrate the gate structures G1 to G8 while extending along the first direction X. The gate structures G1 to G8 may surround the perimeters of the bridge patterns 111 to 113 .

[0048] Each of the gate structures G1 to G8 (eg, Figure 3 The illustrated G6) may include a gate dielectric layer 120 and a gate electrode 130. The gate dielectric layer 120 and the gate electrode 130 may be sequentially stacked on the active patterns A1 to A4.

[0049] The gate dielectric layer 120 may be formed on each of the active patterns A1 to A4. The gate dielectric layer 120 may be interposed between each of the active patterns A1 to A4 and the gate electrode 130. For example, the gate dielectric layer 120 may surround the periphery of the active patterns A1 to A4. In some implementations, the gate dielectric layer 120 may conformally extend along the periphery of the bridge patterns 111 to 113.

[0050] The gate dielectric layer 120 may include, for example, at least one of silicon oxide, silicon oxynitride, silicon nitride, and a high-k material having a higher dielectric constant than silicon oxide. The high-k material may include, for example, hafnium oxide (HfO 2 ), zirconium oxide (ZrO 2 ), lanthanum oxide (La 2 O 3 ), aluminum oxide (Al 2 O 3 ), titanium oxide (TiO 2 ), strontium titanium oxide (SrTiO 3 ), lanthanum aluminum oxide (LaAlO 3 ), yttrium oxide (Y 2 O 3 ), hafnium oxide nitride (HfO x N y )、Zirconium oxynitride(ZrO x N y ), lanthanum nitride (La 2 O x N y), aluminum nitride oxide (Al 2 O x N y ), titanium oxide nitride (TiO x N y ), Strontium Titanium Oxynitride (SrTiO x N y ), lanthanum aluminum oxynitride (LaAlO x N y ), yttrium nitride oxide (Y 2 O x N y ) and at least one of a combination thereof, but not limited thereto.

[0051] The semiconductor device according to some implementations may include a negative capacitor FET using a negative capacitor.For example, the gate dielectric layer 120 may include a ferroelectric material layer having a ferroelectric property and a paraelectric material layer having a paraelectric property.

[0052] The ferroelectric material layer may have a negative capacitance, and the paraelectric material layer may have a positive capacitance. For example, when two or more capacitors are connected in series and the capacitance of each capacitor has a positive value, the total capacitance becomes smaller than the capacitance of each capacitor. On the other hand, when at least one of the capacitances of two or more capacitors connected in series has a negative value, the total capacitance may have a positive value and may be greater than the absolute value of each capacitance.

[0053] When a ferroelectric material layer having negative capacitance and a paraelectric material layer having positive capacitance are connected in series, the total capacitance value of the ferroelectric material layer and the paraelectric material layer connected in series can be increased. By utilizing the increase in the total capacitance value, a transistor including the ferroelectric material layer can have a subthreshold swing (SS) of less than about 60 mV / decade at room temperature.

[0054] The ferroelectric material layer may have ferroelectric properties. The ferroelectric material layer may include, for example, at least one of hafnium oxide, hafnium zirconium oxide, barium strontium titanium oxide, barium titanium oxide, and lead zirconium titanium oxide. In this case, as an example, the hafnium zirconium oxide may be a material containing hafnium oxide doped with zirconium (Zr). As another example, the hafnium zirconium oxide may be a compound of hafnium (Hf), zirconium (Zr), and oxygen (O).

[0055] The ferroelectric material layer may further include a dopant incorporated therein. For example, the dopant may include at least one of aluminum (Al), titanium (Ti), niobium (Nb), lanthanum (La), yttrium (Y), magnesium (Mg), silicon (Si), calcium (Ca), cerium (Ce), dysprosium (Dy), erbium (Er), gadolinium (Gd), germanium (Ge), scandium (Sc), strontium (Sr), and tin (Sn). The type of dopant included in the ferroelectric material layer may vary depending on the ferroelectric material included in the ferroelectric material layer.

[0056] When the ferroelectric material layer includes hafnium oxide, the dopant included in the ferroelectric material layer may include, for example, at least one of gadolinium (Gd), silicon (Si), zirconium (Zr), aluminum (Al), and yttrium (Y).

[0057] When the dopant is aluminum (Al), the ferroelectric material layer may include about 3 atomic percent (at%) to about 8 at% of aluminum. In this case, the ratio of the dopant may be a ratio of aluminum to the sum of hafnium and aluminum.

[0058] When the dopant is silicon (Si), the ferroelectric material layer may include about 2 at% to about 10 at% silicon. When the dopant is yttrium (Y), the ferroelectric material layer may include 2 at% to 10 at% yttrium. When the dopant is gadolinium (Gd), the ferroelectric material layer may include 1 at% to 7 at% gadolinium. When the dopant is zirconium (Zr), the ferroelectric material layer may include 50 at% to 80 at% zirconium.

[0059] The paraelectric material layer may have paraelectric properties. The paraelectric material layer may include, for example, at least one of silicon oxide and a metal oxide having a high dielectric constant. The metal oxide included in the paraelectric material layer may include, for example, at least one of hafnium oxide, zirconium oxide, and aluminum oxide, but is not limited thereto.

[0060] The ferroelectric material layer and the paraelectric material layer may include the same material. The ferroelectric material layer may have ferroelectric properties, but the paraelectric material layer may not have ferroelectric properties. For example, when the ferroelectric material layer and the paraelectric material layer include hafnium oxide, the crystal structure of the hafnium oxide included in the ferroelectric material layer is different from the crystal structure of the hafnium oxide included in the paraelectric material layer.

[0061] The ferroelectric material layer may have a thickness that exhibits ferroelectric properties. The thickness of the ferroelectric material layer may be, for example, in the range of 0.5 nm to 10 nm, but is not limited thereto. Because the critical thickness at which each ferroelectric material exhibits ferroelectric properties may be different, the thickness of the ferroelectric material layer may vary depending on the ferroelectric material.

[0062] In one example, the gate dielectric layer 120 may include one ferroelectric material layer. In another example, the gate dielectric layer 120 may include a plurality of ferroelectric material layers spaced apart from each other. The gate dielectric layer 120 may have a stacked structure in which a plurality of ferroelectric material layers and a plurality of paraelectric material layers are alternately stacked.

[0063] The gate electrode 130 may be formed on the gate dielectric layer 120. The gate electrode 130 may be formed, for example, by a replacement process, but is not limited thereto.

[0064] Although the gate electrode 130 is shown as a single layer, this is only an example, and the gate electrode 130 can be formed by stacking a plurality of conductive layers. For example, the gate electrode 130 may include a work function adjustment layer for adjusting the work function and a filling conductive layer for filling the space formed by the work function adjustment layer. The work function adjustment layer may include, for example, at least one of TiN, TaN, TiC, TaC, TiAlC, and a combination thereof. The filling conductive layer may include, for example, W or Al.

[0065] In some implementations, the gate spacer 140 (eg Figure 2 The gate dielectric layer 120 may be formed on the side surface of each of the gate structures G1 to G8. The gate spacer 140 may be formed on the substrate 100. In addition, the gate spacer 140 may extend along the side surface of the gate electrode 130. In some implementations, a portion of the gate dielectric layer 120 may be interposed between the gate electrode 130 and the gate spacer 140. For example, the gate dielectric layer 120 may further extend along the inner side surface of the gate spacer 140. The gate dielectric layer 120 may be formed by a replacement process, but is not limited thereto.

[0066] The gate spacer 140 may include an insulating material, for example, at least one of silicon nitride, silicon oxynitride, silicon oxycarbide, silicon boron nitride, silicon boron carbon nitride, silicon oxycarbon nitride, and combinations thereof, but is not limited thereto. For example, the gate spacer 140 may include a silicon nitride layer.

[0067] In some implementations, the gate capping layer 150 may be formed on the top surface of each of the gate structures G1 to G8. The gate capping layer 150 may extend along the top surface of the gate electrode 130. Figure 2 FIG. 4 shows that the top surface of the gate capping layer 150 is disposed on the same plane as the top surface of the gate spacer 140 , but this is only exemplary. For another example, the gate capping layer 150 may cover the top surface of the gate spacer 140 .

[0068] The gate capping layer 150 may include an insulating material, for example, at least one of silicon nitride, silicon oxynitride, silicon oxycarbide, silicon boron nitride, silicon boron carbon nitride, silicon oxycarbon nitride, and combinations thereof, but is not limited thereto. For example, the gate capping layer 150 may include a silicon nitride layer.

[0069] In some implementations, a gate cutting pattern 135 extending through / cutting the gate structures G1 to G8 may be formed. For example, the gate cutting pattern 135 may extend in the first direction X to extend through / cutting the gate structures G1 to G8. In some implementations, at least a portion of the gate cutting pattern 135 may be interposed between the second active pattern A2 and the third active pattern A3. The gate cutting pattern 135 may separate the gate structures G1 to G8 on the first cell region CR1 from the gate structures G1 to G8 on the second cell region CR2.

[0070] The gate cutting pattern 135 may include an insulating material, for example, at least one of silicon nitride (SiN), silicon oxynitride (SiON), silicon oxycarbon nitride (SiOCN), and a combination thereof, but is not limited thereto.

[0071] The source / drain patterns 160A to 160D may be disposed on side surfaces of the active patterns A1 to A4. In addition, the source / drain patterns 160A to 160D may be disposed on at least one side surface (e.g., two side surfaces) of each of the gate structures G1 to G8. The source / drain patterns 160A to 160D may be connected to the active patterns A1 to A4. For example, the source / drain patterns 160A to 160D may include a first source / drain pattern 160A connected to the first active pattern A1, a second source / drain pattern 160B connected to the second active pattern A2, a third source / drain pattern 160C connected to the third active pattern A3, and a fourth source / drain pattern 160D connected to the fourth active pattern A4.

[0072] In some implementations, the active patterns A1 to A4 may be connected to the source / drain patterns 160A to 160D while penetrating / extending through the gate structures G1 to G8. The source / drain patterns 160A to 160D may be electrically separated from the gate electrode 130 by the gate dielectric layer 120 and / or the gate spacer 140. The source / drain patterns 160A to 160D may be provided as source / drain regions of a field effect transistor including the active patterns A1 to A4 and the gate structures G1 to G8.

[0073] In some implementations, each of the source / drain patterns 160A to 160D may include an epitaxial layer. For example, the source / drain patterns 160A to 160D may be formed by an epitaxial growth process using the active patterns A1 to A4 as a seed layer. Figures 5 to 7 , the cross section of the source / drain patterns 160A to 160D crossing the first direction X is shown to be hexagonal, but this is only exemplary. Depending on the conditions of the epitaxial growth process, the cross section of the source / drain patterns 160A to 160D crossing the first direction X may have various shapes, such as a pentagonal shape, a diamond shape, etc.

[0074] When the field effect transistor including the active patterns A1 to A4 and the gate structures G1 to G8 is an NFET, the source / drain patterns 160A to 160D may include n-type impurities or impurities for preventing the diffusion of n-type impurities. For example, the source / drain patterns 160A to 160D may include at least one of P, Sb, As, and combinations thereof.

[0075] In some implementations, the source / drain patterns 160A to 160D may include a tensile stress material. For example, when the active patterns A1 to A4 are silicon (Si) patterns, the source / drain patterns 160A to 160D may include a material having a lattice constant smaller than that of silicon (Si) (e.g., silicon carbide (SiC)). The tensile stress material may apply tensile stress to the active patterns A1 to A4 to improve carrier mobility in the channel region.

[0076] When the field effect transistor including the active patterns A1 to A4 and the gate structures G1 to G8 is a PFET, the source / drain patterns 160A to 160D may include p-type impurities or impurities for preventing the diffusion of p-type impurities. For example, the source / drain patterns 160A to 160D may include at least one of B, C, In, Ga, Al, and combinations thereof.

[0077] In some implementations, the source / drain patterns 160A to 160D may include a compressive stress material. For example, when the active patterns A1 to A4 are silicon patterns, the source / drain patterns 160A to 160D may include a material having a lattice constant greater than that of silicon (Si) (e.g., silicon germanium (SiGe)). The compressive stress material may apply compressive stress to the active patterns A1 to A4 to improve carrier mobility in the channel region.

[0078] In some implementations, the first active pattern A1 and the second active pattern A2 may form field effect transistors of different conductivity types, and the third active pattern A3 and the fourth active pattern A4 may form field effect transistors of different conductivity types. In addition, in some embodiments, the second active pattern A2 and the third active pattern A3 may form field effect transistors of the same conductivity type.

[0079] For example, the second source / drain pattern 160B and the third source / drain pattern 160C may include impurities of a first conductivity type, and the first source / drain pattern 160A and the fourth source / drain pattern 160D may include impurities of a second conductivity type different from the first conductivity type. For example, the second source / drain pattern 160B and the third source / drain pattern 160C may include n-type impurities, and the first source / drain pattern 160A and the fourth source / drain pattern 160D may include p-type impurities. For another example, the second source / drain pattern 160B and the third source / drain pattern 160C may include p-type impurities, and the first source / drain pattern 160A and the fourth source / drain pattern 160D may include n-type impurities.

[0080] In some implementations (e.g., Figure 2 As shown in the figure), each of the source / drain patterns 160A to 160D may include a first epitaxial layer 162 and a second epitaxial layer 164. The first epitaxial layer 162 may be formed on the side surfaces of the active patterns A1 to A4. For example, the first epitaxial layer 162 may extend along the top surface of the substrate pattern 102, the outer surface of the inner spacer 145, and the side surfaces of the bridge patterns 111 to 113. The second epitaxial layer 164 may be stacked on the first epitaxial layer 162. The first epitaxial layer 162 may be provided as a seed layer for growing the second epitaxial layer 164.

[0081] The first epitaxial layer 162 and the second epitaxial layer 164 may include impurities at different concentrations. For example, the first epitaxial layer 162 and the second epitaxial layer 164 may include germanium (Ge) as a compressive stress material at different concentrations. For example, when the field effect transistor including the active patterns A1 to A4 and the gate structures G1 to G8 is a PFET, the germanium concentration of the second epitaxial layer 164 may be higher than the germanium concentration of the first epitaxial layer 162.

[0082] In some implementations, an inner spacer 145 may be further formed on the side surface of the gate electrode 130. The inner spacer 145 may be formed on the side surface of the gate electrode 130 between the bridge patterns 111 to 113. The gate electrode 130 between the bridge patterns 111 to 113 may be electrically separated from the source / drain patterns 160A to 160D by the gate dielectric layer 120 and the inner spacer 145. In some implementations, the inner spacer 145 may be omitted.

[0083] The inner spacer 145 may include an insulating material, for example, at least one of silicon nitride, silicon oxynitride, silicon oxycarbide, silicon boron nitride, silicon boron carbon nitride, silicon oxycarbon nitride, and a combination thereof, but is not limited thereto. For example, the inner spacer 145 may include a silicon nitride layer. The inner spacer 145 may include the same material as the gate spacer 140, or may include a material different from the gate spacer 140. Although the thickness of the inner spacer 145 is shown to be the same as the thickness of the gate spacer 140, this is only exemplary.

[0084] The first interlayer insulating layer 172 may be formed to fill a space on an outer surface of the gate spacer 140. For example, the first interlayer insulating layer 172 may cover the field insulating layer 105 and the source / drain patterns 160A to 160D.

[0085] The second interlayer insulating layer 174 may be formed on the first interlayer insulating layer 172. For example, the second interlayer insulating layer 174 may cover top surfaces of the first interlayer insulating layer 172, the gate spacer 140, and the gate capping layer 150.

[0086] Each of the first interlayer insulating layer 172 and the second interlayer insulating layer 174 may include, for example, at least one of silicon oxide, silicon nitride, silicon oxynitride, silicon oxycarbide, silicon boron nitride, silicon carbon nitride, silicon oxycarbon nitride, and a low-k material having a dielectric constant smaller than that of silicon oxide. The low-k material may include, for example, at least one of flowable oxide (FOX), east-burning silazane (TOSZ), undoped silicate glass (USG), borosilicate glass (BSG), phosphosilicate glass (PSG), borophosphosilicate glass (BPSG), plasma-enhanced tetraethyl orthosilicate (PETEOS), fluoride silicate glass (FSG), carbon-doped silicon oxide (CDO), dry gel, aerogel, amorphous fluorinated carbon, organic silicate glass (OSG), polyparaxylene, bisbenzocyclobutene (BCB), SiLK, polyimide, porous polymer material, and combinations thereof, but is not limited thereto.

[0087] A plurality of front source / drain contacts FC1 to FC4 may be disposed on top surfaces of the source / drain patterns 160A to 160D. The front source / drain contacts FC1 to FC4 may penetrate / extend through the second interlayer insulating layer 174 and the first interlayer insulating layer 172 while extending in the third direction Z, and may be connected to upper portions of the source / drain patterns 160A to 160D. For example, the front source / drain contacts FC1 to FC4 may include a first front source / drain contact FC1 connected to the first source / drain pattern 160A, a second front source / drain contact FC2 connected to the second source / drain pattern 160B, a third front source / drain contact FC3 connected to the third source / drain pattern 160C, and a fourth front source / drain contact FC4 connected to the fourth source / drain pattern 160D.

[0088] The width of the front source / drain contacts FC1 to FC4 may decrease toward the source / drain patterns 160A to 160D. Here, the width refers to the width on a plane (e.g., an XY plane) intersecting the third direction Z. This may be caused by performing an etching process for forming the front source / drain contacts FC1 to FC4 on the top surfaces of the source / drain patterns 160A to 160D.

[0089] In some implementations, the front-side source / drain contacts FC1 to FC4 may include a first silicide layer 182 and a first metal layer 184 sequentially stacked on the source / drain patterns 160A to 160D.

[0090] The first metal layer 184 may include a conductive metal, for example, at least one of cobalt (Co), titanium (Ti), tantalum (Ta), ruthenium (Ru), tungsten (W), cobalt tungsten phosphide (CoWP), and combinations thereof, but is not limited thereto. For example, the first metal layer 184 may include a cobalt layer.

[0091] The first silicide layer 182 may be interposed between the source / drain patterns 160A to 160D and the first metal layer 184. The first silicide layer 182 may be formed by a reaction of an element included in the first metal layer 184 with the source / drain patterns 160A to 160D. The first silicide layer 182 may include a metal silicide, such as at least one of nickel silicide, cobalt silicide, tungsten silicide, titanium silicide, niobium silicide, tantalum silicide, and combinations thereof, but is not limited thereto. For example, the first silicide layer 182 may include a titanium silicide layer.

[0092] The front wiring structure FS may be disposed on the top surface (or front surface) of the substrate 100 . For example, the front wiring structure FS may be formed on the top surface of the second interlayer insulating layer 174 .

[0093] The front wiring structure FS may include a plurality of front wiring inter-insulating layers 210, 220, 230, 240, 250, 260, a plurality of front wiring patterns FM1, FM2, and FM3, and a plurality of front via patterns FV1, FV2, and FV3. The front wiring patterns FM1 to FM3 may be sequentially stacked on the second interlayer insulating layer 174. The front via patterns FV1 to FV3 may connect the front wiring patterns FM1 to FM3 to each other. The front wiring patterns FM1 to FM3 and the front via patterns FV1 to FV3 may be formed in the front wiring inter-insulating layers 210 to 260. The front wiring patterns FM1 to FM3 and the front via patterns FV1 to FV3 may be insulated from each other by the front wiring inter-insulating layers 210 to 260, respectively. The number of layers, the number, and the arrangement of the front wiring inter-insulating layers 210 to 260, the front wiring patterns FM1 to FM3, and the front via patterns FV1 to FV3 are only examples and are not limited to the number of layers, the number, and the arrangement shown.

[0094] Each of the front wiring patterns FM1 to FM3 and each of the front path patterns FV1 to FV3 may include a blocking conductive layer and a filling conductive layer. The blocking conductive layer may include a metal or metal nitride for preventing diffusion of the filling conductive layer. For example, the blocking conductive layer may include at least one of titanium (Ti), tantalum (Ta), tungsten (W), nickel (Ni), cobalt (Co), platinum (Pt), an alloy thereof, and a nitride thereof, but is not limited thereto. For example, the filling conductive layer may include at least one of aluminum (Al), copper (Cu), tungsten (W), molybdenum (Mo), cobalt (Co), ruthenium (Ru), and an alloy thereof, but is not limited thereto.

[0095] The front wiring structure FS may provide signal lines and / or power lines for various integrated circuits (e.g., field effect transistors) formed on the substrate 100. For example, the first front via pattern FV1 of the front wiring structure FS may be connected to the front source / drain contacts FC1 to FC4. Therefore, the front wiring structure FS may be electrically connected to the source / drain patterns 160A to 160D.

[0096] In some implementations, a gate contact 185 may be formed on the gate structures G1 to G8. The gate contact 185 may be connected to the gate electrode 130 while sequentially penetrating / extending through the second interlayer insulating layer 174, the first interlayer insulating layer 172, and the gate capping layer 150. The gate contact 185 may connect the gate electrode 130 and the first front wiring pattern FM1. Therefore, the front wiring structure FS may be electrically connected to the gate electrode 130. In some implementations, the gate contact 185 may connect the gate electrode 130 and the first front via pattern FV1.

[0097] A plurality of back source / drain contacts BC1 to BC4 may be disposed on the bottom surfaces of the source / drain patterns 160A to 160D. The back source / drain contacts BC1 to BC4 may penetrate / extend through the substrate 100 while extending in the third direction Z, and may be connected to the lower portions of the source / drain patterns 160A to 160D. For example, the back source / drain contacts BC1 to BC4 may include a first back source / drain contact BC1 connected to the first source / drain pattern 160A, a second back source / drain contact BC2 connected to the second source / drain pattern 160B, a third back source / drain contact BC3 connected to the third source / drain pattern 160C, and a fourth back source / drain contact BC4 connected to the fourth source / drain pattern 160D.

[0098] In some implementations, backside source / drain contacts BC1 to BC4 may be formed in the base pattern 102. For example, Figure 2 As shown, the back source / drain contacts BC1 to BC4 may penetrate the base pattern 102 while extending along the third direction Z. The field insulating layer 105 may cover at least a portion of the side surface of each of the back source / drain contacts BC1 to BC4. Figures 5 to 7 As shown, the field insulating layer 105 may fill the space between the back source / drain contacts BC1 to BC4 and / or between the back source / drain contacts BC1 to BC4 and the base pattern 102 .

[0099] The width of the back source / drain contacts BC1 to BC4 may decrease toward the source / drain patterns 160A to 160D. Here, the width refers to a width on a plane (e.g., an XY plane) intersecting the third direction Z. This may be caused by performing an etching process for forming the back source / drain contacts BC1 to BC4 on the bottom surfaces of the source / drain patterns 160A to 160D.

[0100] In some implementations, the back-side source / drain contacts BC1 to BC4 may include a second silicide layer 192 and a second metal layer 194 sequentially stacked on the source / drain patterns 160A to 160D.

[0101] The second metal layer 194 may include a conductive metal, for example, at least one of cobalt (Co), titanium (Ti), tantalum (Ta), ruthenium (Ru), tungsten (W), cobalt tungsten phosphide (CoWP), and combinations thereof, but is not limited thereto. For example, the second metal layer 194 may include a cobalt layer.

[0102] The second silicide layer 192 may be interposed between the source / drain patterns 160A to 160D and the second metal layer 194. The second silicide layer 192 may be formed by a reaction of an element included in the second metal layer 194 with the source / drain patterns 160A to 160D. The second silicide layer 192 may include a metal silicide, such as at least one of nickel silicide, cobalt silicide, tungsten silicide, titanium silicide, niobium silicide, tantalum silicide, and combinations thereof, but is not limited thereto. For example, the second silicide layer 192 may include a titanium silicide layer.

[0103] The back side wiring structure BS may be disposed on a bottom surface (or rear surface) of the substrate 100 . For example, the back side wiring structure BS may be formed on a bottom surface of the base pattern 102 and a bottom surface of the field insulating layer 105 .

[0104] The back wiring structure BS may include a plurality of back wiring inter-insulating layers 310, 320, 340, 350, a plurality of back wiring patterns BM1 and BM2, and a plurality of back via patterns BV1 and BV2. The back wiring patterns BM1 and BM2 may be sequentially stacked on the bottom surface of the base pattern 102 and the bottom surface of the field insulating layer 105. The back via patterns BV1 and BV2 may connect the back wiring patterns BM1 and BM2 to each other. The back wiring patterns BM1 and BM2 and the back via patterns BV1 and BV2 may be formed in the back wiring inter-insulating layers 310 to 350. The back wiring patterns BM1 and BM2 and the back via patterns BV1 and BV2 may be insulated from each other by the back wiring inter-insulating layers 310 to 350. The number of layers, the number, and the arrangement of the back wiring inter-insulating layers 310 to 350, the back wiring patterns BM1 and BM2, and the back via patterns BV1 and BV2 are only examples and are not limited to the number of layers, the number, and the arrangement shown.

[0105] Each of the back wiring patterns BM1 and BM2 and each of the back via patterns BV1 and BV2 may include a blocking conductive layer and a filling conductive layer. The blocking conductive layer may include a metal or a metal nitride for preventing the filling conductive layer from diffusing. For example, the blocking conductive layer may include at least one of titanium (Ti), tantalum (Ta), tungsten (W), nickel (Ni), cobalt (Co), platinum (Pt), an alloy thereof, and a nitride thereof, but is not limited thereto. For example, the filling conductive layer may include at least one of aluminum (Al), copper (Cu), tungsten (W), molybdenum (Mo), cobalt (Co), ruthenium (Ru), and an alloy thereof, but is not limited thereto.

[0106] The backside wiring structure BS may include a plurality of power lines PW1 to PW3. The power lines PW1 to PW3 may extend side by side while being spaced apart from each other. For example, the power lines PW1 to PW3 may include a first power line PW1, a second power line PW2, and a third power line PW3 sequentially arranged along the second direction Y. The power lines PW1 to PW3 may each extend in the first direction X and may be spaced apart from each other in the second direction Y.

[0107] The power lines PW1 to PW3 may extend along the bottom surface of the substrate 100. In addition, the power lines PW1 to PW3 may be connected to the back source / drain contacts BC1 to BC4. For example, the first power line PW1 may be connected to the first back source / drain contact BC1, and the third power line PW3 may be connected to the fourth back source / drain contact BC4. In some implementations, the second power line PW2 may be connected to both the second back source / drain contact BC2 and the third back source / drain contact BC3. That is, the first cell region CR1 and the second cell region CR2 may share the second power line PW2.

[0108] In some implementations, a first power supply voltage may be applied to the first power supply line PW1 and the third power supply line PW3, and a second power supply voltage different from the first power supply voltage may be applied to the second power supply line PW2. SS can be applied to the second power line PW2, the drain voltage V DD It can be applied to the first power line PW1 and the third power line PW3. For another example, the drain voltage V DD Can be applied to the second power line PW2, the source voltage V SS It can be applied to the first power line PW1 and the third power line PW3.

[0109] The backside wiring structure BS including the power lines PW1 to PW3 may provide a power supply network (PDN) for various integrated circuits (eg, field effect transistors) formed on the substrate 100. For example, a power supply voltage (eg, source voltage V SS Or drain voltage V DD ) may be transmitted to the outermost wiring of the back side wiring structure BS (eg, the second back side wiring pattern BM2), and may be provided to the source / drain patterns 160A to 160D through the power lines PW1 to PW3 and the back side source / drain contacts BC1 to BC4.

[0110] The second back source / drain contact BC2 may include a first side surface BC2a and a second side surface BC2b opposite to each other crossing the second direction Y. For example, the first side surface BC2a may face the third back source / drain contact BC3, and the second side surface BC2b may face the first back source / drain contact BC1.

[0111] The third back source / drain contact BC3 may include a third side surface BC3a and a fourth side surface BC3b that cross the second direction Y and are opposite to each other. For example, the third side surface BC3a may face the second back source / drain contact BC2, and the fourth side surface BC3b may face the fourth back source / drain contact BC4.

[0112] like Figure 1 , Figure 5 and Figure 6 As shown, at the bottom surface of the substrate 100, the second side surface BC2b and the fourth side surface BC3b may be spaced apart from each other by a first distance DS in the second direction Y. In this case, at the bottom surface of the second power line PW2, at least a portion of the second power line PW2 may have a first width W1 less than the first distance DS in the second direction Y. For example, the second power line PW2 may overlap with a portion of the second back source / drain contact BC2 and a portion of the third back source / drain contact BC3 in the third direction Z. For example, one side surface of the second power line PW2 may overlap with the second back source / drain contact BC2 in the third direction Z, and the other side surface of the second power line PW2 may overlap with the third back source / drain contact BC3 in the third direction Z.

[0113] In some implementations, the size of the area where the second back source / drain contact BC2 and / or the third back source / drain contact BC3 overlap with the second power line PW2 may be different from the size of the area where they do not overlap with the second power line PW2. For example, a central axis that bisects the second back source / drain contact BC2 in the second direction Y may be defined. In this case, a side surface of the second power line PW2 that overlaps with the second back source / drain contact BC2 may not be aligned with the central axis in the third direction Z.

[0114] In some implementations, the size of the area where the second back source / drain contact BC2 and / or the third back source / drain contact BC3 overlap with the second power line PW2 may be larger than the size of the area where they do not overlap with the second power line PW2. For example, one side surface of the second power line PW2 may overlap with the second back source / drain contact BC2 between the central axis and the second side surface BC2b.

[0115] In some implementations, the width of the back source / drain contacts BC1 to BC4 in the second direction Y may be the same as the width of the base pattern 102 in the second direction Y. The term "same" as used herein means not only completely the same, but also includes slight differences that may occur due to process margins, etc. For example, Figure 4As shown, the base pattern 102 may include a first base pattern 1021 and a second base pattern 1022. The width of the first base pattern 1021 in the second direction Y and the width of the second base pattern 1022 in the second direction Y may decrease toward the source / drain patterns 160A to 160D.

[0116] The first base pattern 1021 may include a fifth side surface 1021a and a sixth side surface 1021b that cross the second direction Y and are opposite to each other. The fifth side surface 1021a may be disposed on the same plane as the first side surface BC2a of the second back source / drain contact BC2, and the sixth side surface 1021b may be disposed on the same plane as the second side surface BC2b of the second back source / drain contact BC2.

[0117] The second base pattern 1022 may include a seventh side surface 1022a and an eighth side surface 1022b that are opposite to each other and intersect the second direction Y. The seventh side surface 1022a may be disposed on the same plane as the third side surface BC3a of the third back source / drain contact BC3, and the eighth side surface 1022b may be disposed on the same plane as the fourth side surface BC3b of the third back source / drain contact BC3.

[0118] like Figure 1 , Figure 3 and Figure 4 As shown, at the bottom surface of the substrate 100, the sixth side surface 1021b and the eighth side surface 1022b may be spaced apart from each other by a first distance DS in the second direction Y. In this case, at the bottom surface of the second power line PW2, at least a portion of the second power line PW2 may have a first width W1 less than the first distance DS in the second direction Y. For example, the second power line PW2 may overlap a portion of the first base pattern 1021 and a portion of the second base pattern 1022 in the third direction Z.

[0119] In some implementations, such as Figure 7 As shown, the second power line PW2 may overlap a portion of the second back source / drain contact BC2 and a portion of the substrate pattern 102 in the third direction Z. For example, one side surface of the second power line PW2 may overlap the second back source / drain contact BC2 in the third direction Z, and the other side surface of the second power line PW2 may overlap the second substrate pattern 1022 in the third direction Z.

[0120] like Figure 1As shown, in the second direction Y, the first power line PW1 can be spaced apart from the second power line PW2 by a second distance S1, and the third power line PW3 can be spaced apart from the second power line PW2 by a third distance S2. Here, the second distance S1 and the third distance S2 can be defined, for example, at the bottom surface of the second power line PW2 (or the bottom surface of the first back-side wiring insulation layer 310) in the second direction Y (e.g., measured at the bottom surface of the second power line PW2 (or the bottom surface of the first back-side wiring insulation layer 310)). In some implementations, the ratio of the second distance S1 to the first width W1 of the second power line PW2 and / or the ratio of the third distance S2 to the first width W1 of the second power line PW2 can be approximately 0.5 to approximately 1.2. Within the above range, process defects caused by maximum density violations of wiring patterns can be effectively prevented. In some implementations, a ratio of the second distance S1 to the first width W1 of the second power line PW2 and / or a ratio of the third distance S2 to the first width W1 of the second power line PW2 may be about 0.8 to about 1.1. Within the above range, process defects caused by maximum density violations of wiring patterns may be effectively prevented.

[0121] By providing a so-called back side power supply network (BSPDN), a semiconductor device according to some implementations may have a reduced voltage drop. For example, as described above, a back side wiring structure BS providing a power supply network (PDN) may be provided on a bottom surface (or rear surface) of a substrate 100 on which no integrated circuit (e.g., field effect transistor) is provided. Therefore, compared to a case where a power supply network (PDN) is provided on a top surface (or front surface) of the substrate 100, a semiconductor device according to some implementations may reduce device size and improve (e.g., reduce) voltage drop by reducing or minimizing routing crosstalk.

[0122] For connection between a back side power supply network (BSPDN) and an integrated circuit, a contact for directly connecting the back side power supply network (BSPDN) and the integrated circuit (hereinafter, referred to as a back side direct contact) has been proposed. The back side direct contact can connect the back side power supply network (BSPDN) and the integrated circuit through the shortest path, and thus is beneficial in terms of power, performance, area, and cost (PPAC).

[0123] However, the back direct contact may be associated with alignment with active patterns (e.g., active patterns A1 to A4) of the integrated circuit in a vertical direction (e.g., a third direction Z), and thus may impose restrictions on the back side power supply network (BSPDN). For example, for efficient power supply voltage transmission, a merged power rail may be provided in which adjacent cell areas share a power line. The merged power rail may be connected to all back direct contacts of different cell areas, and thus may be formed to have a relatively large width. In this case, if the width of the merged power rail becomes too large compared to the space with another adjacent power line, it causes a process defect (e.g., dishing, etc.) due to a maximum density violation of the wiring pattern.

[0124] The semiconductor device according to some implementations can provide a more efficiently merged power rail by using a second power line PW2 having a reduced width. Specifically, as described above, the second power line PW2 can be provided as a merged power rail connected to both the back direct contact of the first cell region CR1 (e.g., the second back source / drain contact BC2) and the back direct contact of the second cell region CR2 (e.g., the third back source / drain contact BC3), for example, as Figure 5 As shown. In addition, the first width W1 of the second power line PW2 may be smaller than the first distance DS at the bottom surface of the second power line PW2, and the first width W1 may be reduced to be similar to the spacing to another adjacent power line (e.g., the second distance S1 or the third distance S2). Therefore, process defects caused by maximum density violation of the wiring pattern may be prevented, thereby providing a semiconductor device with improved power, performance, area, and cost (PPAC).

[0125] Figure 8 is a schematic cross-sectional view illustrating a semiconductor device according to some implementations. Fig. 9 It is shown Figure 8 For reference, Figure 8 It is along Figure 1 Another schematic cross-sectional view taken along line CC of FIG. Figures 1 to 7 Redundant portions of the description may be briefly restated or omitted. Unless otherwise stated, Figure 8 The device can have a Figures 1 to 7 Describe the characteristics.

[0126] Reference Figure 8 and Fig. 9 In the semiconductor device according to some implementations, the widths of the power lines PW1 to PW3 may gradually increase toward the substrate 100. For example, in the second direction Y, the lengths of the top surfaces of the power lines PW1 to PW3 may be greater than the lengths of the bottom surfaces of the power lines PW1 to PW3.

[0127] For example, Fig. 9 As shown, the first inner angle θ1 formed by the top surface of the second power line PW2 and the side surface of the second power line PW2 may be an acute angle, and the second inner angle θ2 formed by the bottom surface of the second power line PW2 and the side surface of the second power line PW2 may be an obtuse angle.

[0128] Each of the power lines PW1 to PW3 may be formed by, for example, a reverse tapered etching process. Thus, the power lines PW1 to PW3 each having a reverse trapezoidal shape may be provided.

[0129] In some implementations, at the top surface of the second power line PW2, the width of the second power line PW2 may be the same as or greater than the first distance DS (i.e., greater than or equal to the first distance DS). For example, the second back source / drain contact BC2 and the third back source / drain contact BC3 may completely overlap the second power line PW2 in the third direction Z. In this case, the contact area between the second back source / drain contact BC2 and the third back source / drain contact BC3 and the second power line PW2 may be increased, thereby providing a back side power supply network (BSPDN) with reduced resistance.

[0130] The bottom surface of the second power line PW2 may have a first width W1 less than the first distance DS in the second direction Y. For example, the bottom surface of the second power line PW2 may overlap a portion of the second back source / drain contact BC2 and a portion of the third back source / drain contact BC3 in the third direction Z. In some implementations, the top surface of the second power line PW2 may have a width in the second direction Y less than the first distance DS and greater than the first width W1.

[0131] Fig.10 is a schematic cross-sectional view illustrating a semiconductor device according to some implementations. Fig.11 It is shown Fig.10 For reference, Fig.10 It is along Figure 1 In order to simplify the description, refer to Figures 1 to 7 Redundant portions of the description may be briefly restated or omitted. Unless otherwise stated, Fig.10 The device can have a Figures 1 to 7 Describe the characteristics.

[0132] Reference Fig.10 and Fig.11 , in the semiconductor device according to some implementations, the widths of the power lines PW1 to PW3 may gradually increase toward the substrate 100 .

[0133] For example, Fig.11 As shown, the second power line PW2 may include a first layer 312, a second layer 314, and a third layer 316 sequentially stacked on the bottom surface of the substrate 100. In the second direction Y, the width of the second layer 314 may be smaller than the width of the first layer 312, and the width of the third layer 316 may be smaller than the width of the second layer 314. The first layer 312, the second layer 314, and the third layer 316 are represented as divided regions having different widths in the second direction Y, and they may be integrally formed.

[0134] Each of the power lines PW1 to PW3 may be formed by, for example, a step etching process. Thus, the power lines PW1 to PW3 each having a step shape may be provided.

[0135] In some implementations, at the top surface of the second power line PW2, the width of the second power line PW2 may be greater than or equal to the first distance DS. For example, the second back source / drain contact BC2 and the third back source / drain contact BC3 may completely overlap the second power line PW2 in the third direction Z. In this case, the contact area between the second back source / drain contact BC2 and the third back source / drain contact BC3 and the second power line PW2 may be increased, thereby providing a back side power supply network (BSPDN) with reduced resistance.

[0136] The bottom surface of the second power line PW2 may have a first width W1 less than the first distance DS in the second direction Y. For example, the bottom surface of the second power line PW2 may overlap a portion of the second back source / drain contact BC2 and a portion of the third back source / drain contact BC3 in the third direction Z. In some implementations, the top surface of the second power line PW2 may have a width in the second direction Y less than the first distance DS and greater than the first width W1.

[0137] Fig.12 is a layout diagram illustrating a semiconductor device according to some implementations. Fig.13 It is along Fig.12 In order to simplify the description, refer to Figures 1 to 11 Redundant portions of the description may be briefly restated or omitted. Unless otherwise stated, Fig.12 The device can have a Figures 1 to 11 Describe the characteristics.

[0138] Reference Fig.12 and Fig.13 In a semiconductor device according to some implementations, the second power line PW2 may include a first portion P1a and a second portion P1b.

[0139] At the bottom surface of the second power line PW2, the third width W22 of the second portion P1b may be smaller than the first distance DS. In addition, the third width W22 of the second portion P1b may be smaller than the second width W21 of the first portion P1a. For example, the first power line PW1 may be spaced apart from the first portion P1a of the second power line PW2 by a fourth distance S21, and the third power line PW3 may be spaced apart from the first portion P1a of the second power line PW2 by a fifth distance S22. In addition, the first power line PW1 may be spaced apart from the second portion P1b of the second power line PW2 by a fourth distance S21, and the third power line PW3 may be spaced apart from the second portion P1b of the second power line PW2 by a sixth distance S23 greater than the fifth distance S22.

[0140] In some implementations, the second width W21 of the second power line PW2 may be greater than or equal to the first distance DS.

[0141] In some implementations, the ratio of the sixth distance S23 to the third width W22 of the second power line PW2 may be about 0.5 to about 1.2. In some implementations, the ratio of the sixth distance S23 to the third width W22 of the second power line PW2 may be about 0.8 to about 1.1. Within the above range, process defects caused by maximum density violations of wiring patterns can be effectively prevented.

[0142] In some implementations, the first portion P1a may overlap the second back source / drain contact BC2 and the third back source / drain contact BC3 in the third direction Z. In some implementations, one side surface of the first portion P1a may be aligned with the side surface of the second back source / drain contact BC2, and the other side surface of the first portion P1a may be aligned with the side surface of the third back source / drain contact BC3.

[0143] In addition, the first portion P1a may overlap with two adjacent base patterns 102 in the third direction Z. For example, the first portion P1a may overlap with the base pattern 102 (eg, Figure 4 The first base pattern 1021 of FIG. 1 and the base pattern 102 (eg, the first base pattern 1021 of FIG. 1 ) in which the third back source / drain contact BC3 is formed Figure 4 In some implementations, both side surfaces of the first portion P1a may be aligned with side surfaces of the base pattern 102.

[0144] In some implementations, the second portion P1b may overlap the second back source / drain contact BC2 and the field insulating layer 105 in the third direction Z, and may not overlap the base pattern 102 (eg, Figure 4In some implementations, one side surface of the second portion P1b may be aligned with the side surface of the second back source / drain contact BC2, and the other side surface of the second portion P1b may be aligned with the side surface of the base pattern 102 facing the second back source / drain contact BC2. In some implementations, the other side surface of the second portion P1b may not be aligned with the side surface of the base pattern 102 facing the second back source / drain contact BC2.

[0145] Fig.14 is a layout diagram illustrating a semiconductor device according to some implementations. Fig.15 It is along Fig.14 In order to simplify the description, refer to Figures 1 to 11 Redundant portions of the description may be briefly restated or omitted. Unless otherwise stated, Fig.14 The device can have a Figures 1 to 11 Describe the characteristics.

[0146] Reference Fig.14 and Fig.15 , in the semiconductor device according to some implementations, the second power line PW2 may include third to sixth portions P2a to P2d.

[0147] The fifth portion P2c and the sixth portion P2d may each extend in the first direction X to connect the third portion P2a and the fourth portion P2b. In addition, the fifth portion P2c and the sixth portion P2d may be spaced apart from each other in the second direction Y. In some implementations, the second power line PW2 may include a first opening P2o defined by the third portion P2a to the sixth portion P2d. The first opening P2o may extend in the first direction X.

[0148] At the bottom surface of the second power line PW2, the fifth width W32 of the fifth portion P2c and the sixth width W33 of the sixth portion P2d may be smaller than the first distance DS. In addition, the fifth width W32 of the fifth portion P2c and the sixth width W33 of the sixth portion P2d may be smaller than the fourth width W31 of the third portion P2a and the fourth portion P2b. For example, the first power line PW1 may be spaced apart from the second power line PW2 by a seventh distance S31, and the third power line PW3 may be spaced apart from the second power line PW2 by an eighth distance S32. In addition, the fifth portion P2c of the second power line PW2 and the sixth portion P2d of the second power line PW2 may be spaced apart from each other by a ninth distance S33.

[0149] In some implementations, the fourth width W31 of the second power line PW2 may be greater than or equal to the first distance DS.

[0150] In some implementations, each of the ratio of the seventh distance S31 to the fifth width W32 of the second power line PW2, the ratio of the seventh distance S31 to the sixth width W33 of the second power line PW2, the ratio of the eighth distance S32 to the fifth width W32 of the second power line PW2, and the ratio of the eighth distance S32 to the sixth width W33 of the second power line PW2 may be about 0.5 to about 1.2. In some implementations, each of the ratio of the seventh distance S31 to the fifth width W32 of the second power line PW2, the ratio of the seventh distance S31 to the sixth width W33 of the second power line PW2, the ratio of the eighth distance S32 to the fifth width W32 of the second power line PW2, and the ratio of the eighth distance S32 to the sixth width W33 of the second power line PW2 may be about 0.8 to about 1.1. Within the above range, process defects caused by maximum density violations of wiring patterns can be effectively prevented.

[0151] Fig.16 is a layout diagram illustrating a semiconductor device according to some implementations. Fig.17 It is along Fig.16 In order to simplify the description, refer to Figures 1 to 11 Redundant portions of the description may be briefly restated or omitted. Unless otherwise stated, Fig.16 The device can have a Figures 1 to 11 Describe the characteristics.

[0152] Reference Fig.16 and Fig.17 , in the semiconductor device according to some implementations, the second power line PW2 may include seventh to ninth portions P3a to P3c.

[0153] The seventh portion P3a and the eighth portion P3b may each extend in the first direction X. The ninth portion P3c may extend in the second direction Y to connect the seventh portion P3a and the eighth portion P3b. In some implementations, the second power line PW2 may include a plurality of second openings P3o defined by the seventh portion P3a to the ninth portion P3c. The second openings P3o may be arranged along the first direction X while being spaced apart from each other by the ninth portion P3c.

[0154] At the bottom surface of the second power line PW2, the seventh width W41 of the seventh portion P3a and the eighth width W42 of the eighth portion P3b may be less than the first distance DS. For example, the first power line PW1 may be spaced apart from the second power line PW2 by a tenth distance S41, and the third power line PW3 may be spaced apart from the second power line PW2 by an eleventh distance S42. In addition, the seventh portion P3a of the second power line PW2 and the eighth portion P3b of the second power line PW2 may be spaced apart from each other by a twelfth distance S43.

[0155] In some implementations, each of the ratio of the tenth distance S41 to the seventh width W41 of the second power line PW2, the ratio of the tenth distance S41 to the eighth width W42 of the second power line PW2, the ratio of the eleventh distance S42 to the seventh width W41 of the second power line PW2, and the ratio of the eleventh distance S42 to the eighth width W42 of the second power line PW2 may be about 0.5 to about 1.2. In some implementations, each of the ratio of the tenth distance S41 to the seventh width W41 of the second power line PW2, the ratio of the tenth distance S41 to the eighth width W42 of the second power line PW2, the ratio of the eleventh distance S42 to the seventh width W41 of the second power line PW2, and the ratio of the eleventh distance S42 to the eighth width W42 of the second power line PW2 may be about 0.8 to about 1.1. Within the above range, process defects caused by maximum density violations of wiring patterns can be effectively prevented.

[0156] In some implementations, each of the ratio of the twelfth distance S43 to the seventh width W41 of the second power line PW2 and the ratio of the twelfth distance S43 to the eighth width W42 of the second power line PW2 may be about 0.5 to about 1.2. In some implementations, each of the ratio of the twelfth distance S43 to the seventh width W41 of the second power line PW2 and the ratio of the twelfth distance S43 to the eighth width W42 of the second power line PW2 may be about 0.8 to about 1.1. Within the above range, process defects caused by maximum density violations of wiring patterns can be effectively prevented.

[0157] Fig.18 is a layout diagram illustrating a semiconductor device according to some implementations. Fig.19 It is along Fig.18 For simplicity of description, refer to Figures 1 to 11 Redundant portions of the description may be briefly restated or omitted. Unless otherwise stated, Fig.18 The device can have a Figures 1 to 11 Describe the characteristics.

[0158] Reference Fig.18 and Fig.19 , in the semiconductor device according to some implementations, the second power line PW2 may include a tenth portion P4a and an eleventh portion P4b.

[0159] At the bottom surface of the second power line PW2, the tenth width W52 of the eleventh portion P4b may be smaller than the first distance DS. In addition, the tenth width W52 of the eleventh portion P4b may be smaller than the ninth width W51 of the tenth portion P4a. For example, the first power line PW1 may be spaced apart from the tenth portion P4a of the second power line PW2 by a thirteenth distance S51, and the third power line PW3 may be spaced apart from the tenth portion P4a of the second power line PW2 by a fourteenth distance S52. In addition, the first power line PW1 may be spaced apart from the eleventh portion P4b of the second power line PW2 by a fifteenth distance S53 greater than the thirteenth distance S51, and the third power line PW3 may be spaced apart from the eleventh portion P4b of the second power line PW2 by a sixteenth distance S54 greater than the fourteenth distance S52.

[0160] In some implementations, the ninth width W51 of the second power line PW2 may be greater than or equal to the first distance DS.

[0161] In some implementations, each of the ratio of the fifteenth distance S53 to the tenth width W52 of the second power line PW2 and the ratio of the sixteenth distance S54 to the tenth width W52 of the second power line PW2 may be about 0.5 to about 1.2. In some implementations, each of the ratio of the fifteenth distance S53 to the tenth width W52 of the second power line PW2 and the ratio of the sixteenth distance S54 to the tenth width W52 of the second power line PW2 may be about 0.8 to about 1.1. Within the above range, process defects caused by maximum density violations of wiring patterns can be effectively prevented.

[0162] In some implementations, the eleventh portion P4b of the second power line PW2 may not be connected to the back source / drain contacts BC1 to BC4. For example, as shown, the eleventh portion P4b of the second power line PW2 may not overlap with the back source / drain contacts BC1 to BC4 in the third direction Z, and may overlap with the front source / drain contacts FC2 and FC3.

[0163] FIG. 20A to FIG. 21B are various layout diagrams for illustrating semiconductor devices according to some implementations. Figures 1 to 19 Redundant portions of the description may be briefly restated or omitted. Unless otherwise stated, FIG. 20A to FIG. 21B The device can have a Figures 1 to 19 Describe the characteristics.

[0164] Reference Fig. 20A , in the semiconductor device according to some implementations, the second power line PW2 may include twelfth to fourteenth portions P5a to P5c.

[0165] The twelfth to fourteenth portions P5a to P5c may be arranged in sequence along the first direction X. The thirteenth portion P5b may connect the twelfth portion P5a and the fourteenth portion P5c in the first direction X. At the bottom surface of the second power line PW2, the twelfth width W62 of the fourteenth portion P5c may be smaller than the eleventh width W61 of the twelfth portion P5a. For example, the first power line PW1 may be spaced apart from the twelfth portion P5a of the second power line PW2 by a seventeenth distance S61, and the third power line PW3 may be spaced apart from the twelfth portion P5a of the second power line PW2 by an eighteenth distance S62. In addition, the first power line PW1 may be spaced apart from the fourteenth portion P5c of the second power line PW2 by a nineteenth distance S63 greater than the seventeenth distance S61, and the third power line PW3 may be spaced apart from the fourteenth portion P5c of the second power line PW2 by a twentieth distance S64 greater than the eighteenth distance S62.

[0166] At the bottom surface of the second power line PW2, the width of the thirteenth portion P5b may gradually decrease from the twelfth portion P5a toward the fourteenth portion P5c. That is, the thirteenth portion P5b may have a tapered shape whose width decreases in the first direction X.

[0167] In some implementations, the eleventh width W61 of the second power line PW2 may be greater than or equal to the first distance DS.

[0168] In some implementations, each of the ratio of the nineteenth distance S63 to the twelfth width W62 of the second power line PW2 and the ratio of the twentieth distance S64 to the twelfth width W62 of the second power line PW2 may be about 0.5 to about 1.2. In some implementations, each of the ratio of the nineteenth distance S63 to the twelfth width W62 of the second power line PW2 and the ratio of the twentieth distance S64 to the twelfth width W62 of the second power line PW2 may be about 0.8 to about 1.1. Within the above range, process defects caused by maximum density violations of wiring patterns can be effectively prevented.

[0169] In some implementations, the second active pattern A2 and / or the third active pattern A3 may have a shape corresponding to the shape of the second power line PW2. For example, the width of the portion of the second active pattern A2 overlapping the fourteenth portion P5c of the second power line PW2 may be smaller than the width of the portion of the second active pattern A2 overlapping the twelfth portion P5a of the second power line PW2. The portion of the second active pattern A2 overlapping the thirteenth portion P5b of the second power line PW2 may have a tapered shape whose width decreases in the first direction X. In addition, for example, the width of the portion of the third active pattern A3 overlapping the fourteenth portion P5c of the second power line PW2 may be smaller than the width of the portion of the third active pattern A3 overlapping the twelfth portion P5a of the second power line PW2. In addition, the portion of the third active pattern A3 overlapping the thirteenth portion P5b of the second power line PW2 may have a tapered shape whose width decreases in the first direction X.

[0170] Reference Fig. 20B In the semiconductor device according to some implementations, the second power line PW2 may include a first sub wiring line PW2 a and a second sub wiring line PW2 b .

[0171] The first sub wiring PW2 a may be connected to the second back-side source / drain contact BC2 , and the second sub wiring PW2 b may be connected to the third back-side source / drain contact BC3 .

[0172] In some implementations, at least a portion of the first sub-wiring PW2a and at least a portion of the second sub-wiring PW2b may each have a tapered shape whose width decreases in the first direction X. For example, at least a portion of the first sub-wiring PW2a may have the same shape as described above with reference to Fig. 20A At least a portion of the second sub wiring PW2b may have a shape corresponding to the shape of the second active pattern A2 described above. Fig. 20A The shape of the third active pattern A3 described above corresponds to the shape of .

[0173] Reference Fig.21A , in the semiconductor device according to some implementations, the second power line PW2 may include fifteenth to seventeenth portions P6a to P6c.

[0174] The fifteenth to seventeenth portions P6a to P6c may be arranged in sequence along the first direction X. The sixteenth portion P6b may connect the fifteenth portion P6a and the seventeenth portion P6c in the first direction X. When viewed in a plan view, the bottom surface of the sixteenth portion P6b of the second power line PW2 may have a curved shape. For example, the first power line PW1 may be spaced apart from the fifteenth portion P6a of the second power line PW2 by a twenty-first distance S71, and the third power line PW3 may be spaced apart from the fifteenth portion P6a of the second power line PW2 by a twenty-second distance S72. In addition, the first power line PW1 may be spaced apart from the seventeenth portion P6c of the second power line PW2 by a twenty-third distance S73 greater than the twenty-first distance S71, and the third power line PW3 may be spaced apart from the seventeenth portion P6c of the second power line PW2 by a twenty-fourth distance S74 less than the twenty-second distance S72. In some implementations, at the bottom surface of the second power line PW2 , the thirteenth width W71 of the fifteenth portion P6 a and the fourteenth width W72 of the seventeenth portion P6 c may be the same.

[0175] In some implementations, the second active pattern A2 and / or the third active pattern A3 may have a shape corresponding to the shape of the second power line PW2. For example, the width of the portion of the second active pattern A2 overlapping the seventeenth portion P6c of the second power line PW2 may be less than the width of the portion of the second active pattern A2 overlapping the fifteenth portion P6a of the second power line PW2. The portion of the second active pattern A2 overlapping the sixteenth portion P6b of the second power line PW2 may have a tapered shape whose width decreases in the first direction X. In addition, for example, the width of the portion of the third active pattern A3 overlapping the seventeenth portion P6c of the second power line PW2 may be greater than the width of the portion of the third active pattern A3 overlapping the fifteenth portion P6a of the second power line PW2. In addition, the portion of the third active pattern A3 overlapping the sixteenth portion P6b of the second power line PW2 may have a tapered shape whose width decreases in the direction -X opposite to the first direction X.

[0176] Reference Fig. 21B In the semiconductor device according to some implementations, the second power line PW2 may include a first sub wiring line PW2 a and a second sub wiring line PW2 b .

[0177] The first sub wiring PW2 a may be connected to the second back-side source / drain contact BC2 , and the second sub wiring PW2 b may be connected to the third back-side source / drain contact BC3 .

[0178] In some implementations, at least a portion of the first sub-wiring PW2a may have a tapered shape whose width decreases in the first direction X, and at least a portion of the second sub-wiring PW2b may have a tapered shape whose width decreases in a direction -X opposite to the first direction X. For example, at least a portion of the first sub-wiring PW2a may have the same tapered shape as described above with reference to Fig.21A At least a portion of the second sub wiring PW2b may have a shape corresponding to the shape of the second active pattern A2 described above. Fig.21A The shape of the third active pattern A3 described above corresponds to the shape of .

[0179] In the following, reference will be made to Figures 1 to 7 and Figures 22 to 39 Methods for fabricating semiconductor devices according to some implementations are described.

[0180] Figures 22 to 39 is a diagram showing an intermediate step of a method for manufacturing a semiconductor device according to some implementations. Figures 1 to 21B Redundant parts of the description may be briefly restated or omitted.

[0181] Reference Fig. 22 , a fin pattern 101 , a sacrificial pattern 410 , and bridge patterns 111 to 113 are formed on a base substrate 100B.

[0182] The base substrate 100B may be bulk silicon or silicon on insulator (SOI). Alternatively, the base substrate 100B may be a silicon substrate, or may include other materials such as silicon germanium, silicon germanium on insulator (SGOI), indium antimonide, lead telluride, indium arsenide, indium phosphide, gallium arsenide, or gallium antimonide, but the present disclosure is not limited thereto. To simplify the description, hereinafter, it is assumed that the base substrate 100B is a silicon substrate.

[0183] The base substrate 100B may include a top surface and a bottom surface opposite to each other. In this specification, the top surface of the base substrate 100B may also be referred to as a front surface, and the bottom surface of the base substrate 100B may also be referred to as a back surface.

[0184] The fin pattern 101 may protrude from the top surface of the base substrate 100B and extend in the first direction X. The fin pattern 101 may be a portion of the base substrate 100B, and may include an epitaxial layer grown from the base substrate 100B.

[0185] Sacrificial patterns 410 and bridge patterns 111 to 113 may be alternately stacked on the fin pattern 101. Each of the sacrificial patterns 410 and each of the bridge patterns 111 to 113 may extend in the first direction X. Thus, active patterns A1 to A4 including bridge patterns 111 to 113 sequentially stacked and spaced apart from each other may be provided.

[0186] The sacrificial pattern 410 may have an etch selectivity with respect to the bridge patterns 111 to 113. For example, when each of the bridge patterns 111 to 113 includes a silicon (Si) layer, each of the sacrificial patterns 410 may include a silicon germanium (SiGe) layer.

[0187] The fin pattern 101, the sacrificial pattern 410, and the bridge patterns 111 to 113 may be formed by a patterning process using a mask layer extending in the first direction X as an etching mask. Although not specifically shown, after the fin pattern 101, the sacrificial pattern 410, and the bridge patterns 111 to 113 are formed, a field insulating layer 105 (see FIG. 1 ) covering at least a portion of a side surface of the fin pattern 101 may be formed. Figure 3 ).

[0188] Reference Fig.23 , a dummy gate DG and a gate spacer 140 are formed on the sacrificial pattern 410 and the bridge patterns 111 to 113 .

[0189] The dummy gate DG may cross the sacrificial pattern 410 and the bridge patterns 111 to 113. For example, the dummy gate DG may be elongated in the second direction Y. The dummy gate DG may have an etching selectivity with respect to the sacrificial pattern 410 and the bridge patterns 111 to 113. For example, the dummy gate DG may include a polysilicon (poly Si) layer.

[0190] The gate spacer 140 may extend along the side surface of the dummy gate DG. The gate spacer 140 may include an insulating material, such as at least one of silicon nitride, silicon oxynitride, silicon oxycarbide, silicon boron nitride, silicon boron carbon nitride, silicon oxycarbon nitride, and combinations thereof, but is not limited thereto. For example, the gate spacer 140 may include a silicon nitride layer.

[0191] Reference Fig.24 , source / drain recesses 160 r are formed in the sacrificial pattern 410 and the bridge patterns 111 to 113 at the side of the dummy gate DG.

[0192] For example, a first recess process may be performed on the sacrificial pattern 410 and the bridge patterns 111 to 113 using the dummy gate DG and the gate spacer 140 as an etching mask. By performing the first recess process, a portion of each of the sacrificial patterns 410 and a portion of each of the bridge patterns 111 to 113 may be removed to form the source / drain recesses 160r.

[0193] Reference Fig.25 , inner spacers 145 are formed on side surfaces of the sacrificial pattern 410 .

[0194] For example, the second recess process may be performed on the sacrificial pattern 410 exposed by the source / drain recess 160r. By performing the second recess process, the side surface of the sacrificial pattern 410 may be recessed. Next, the inner spacer 145 may be formed on the side surface of the recessed sacrificial pattern 410.

[0195] The inner spacer 145 may include an insulating material, for example, at least one of silicon nitride, silicon oxynitride, silicon oxycarbide, silicon boron nitride, silicon boron carbon nitride, silicon oxycarbon nitride, and combinations thereof, but is not limited thereto. For example, the inner spacer 145 may include a silicon nitride layer.

[0196] In some implementations, the formation of inner spacers 145 can be omitted.

[0197] Reference Fig.26 , a first contact recess 101 r is formed in the fin pattern 101 .

[0198] For example, a third recess process may be performed on at least a portion of the fin pattern 101 exposed by the source / drain recess 160r. By performing the third recess process, at least a portion of the fin pattern 101 may be removed to form a first contact recess 101r. The first contact recess 101r may define a region in which back source / drain contacts BC1 to BC4, which will be described later, are formed.

[0199] Reference Fig. 27 , a sacrificial contact 190S is formed on the base substrate 100B.

[0200] Sacrificial contact 190S can be filled Fig.26 The top surface of the sacrificial contact 190S may be formed lower than the bottom surface of the lowermost bridge pattern 111. For example, a sacrificial material may be deposited to fill the first contact recess 101r and the source / drain recess 160r, and an etch-back process may be performed on the sacrificial material.

[0201] The sacrificial contact 190S may have an etch selectivity with respect to the fin pattern 101. For example, when the fin pattern 101 includes a silicon (Si) layer, the sacrificial contact 190S may include a silicon germanium (SiGe) layer.

[0202] Reference Fig.28 , source / drain patterns 160A to 160D are formed on the fin pattern 101 and the sacrificial contact 190S.

[0203] The source / drain patterns 160A to 160D may be filled with Fig. 27For example, an epitaxial growth process using the fin pattern 101, the sacrificial contact 190S, and the bridge patterns 111 to 113 as a seed layer may be performed. Thus, source / drain patterns 160A to 160D connected to the bridge patterns 111 to 113 may be formed.

[0204] Reference Fig.29 , the sacrificial pattern 410 and the dummy gate DG are removed.

[0205] For example, a first interlayer insulating layer 172 may be formed on the dummy gate DG, the gate spacer 140, and the source / drain patterns 160A to 160D. The first interlayer insulating layer 172 may be formed to fill the space on the outer surface of the gate spacer 140. Next, a planarization process may be performed on the first interlayer insulating layer 172 to expose the top surface of the dummy gate DG. Next, the exposed dummy gate DG may be removed. As described above, the dummy gate DG may have an etching selectivity relative to the sacrificial pattern 410 and the bridge patterns 111 to 113, so that the dummy gate DG may be selectively removed. Because the dummy gate DG is removed, a plurality of sacrificial patterns 410 may be exposed.

[0206] Next, the exposed plurality of sacrificial patterns 410 may be removed. As described above, the sacrificial patterns 410 may have an etching selectivity with respect to the bridge patterns 111 to 113, so that the sacrificial patterns 410 may be selectively removed.

[0207] Reference Fig.30 , forming gate structures G1 to G8.

[0208] For example, the gate dielectric layer 120 and the gate electrode 130 may be sequentially stacked on the bridge patterns 111 to 113. Thus, the gate structures G1 to G8 crossing the active patterns A1 to A4 may be formed to replace the dummy gate DG.

[0209] In some implementations, upper portions of the gate structures G1 to G8 may be recessed. Next, a gate capping layer 150 may be formed on top surfaces of the recessed gate structures G1 to G8.

[0210] Reference Fig.31 , front source / drain contacts FC1 to FC4 are formed on the source / drain patterns 160A to 160D.

[0211] For example, a second interlayer insulating layer 174 may be formed covering the first interlayer insulating layer 172, the gate spacer 140, and the gate capping layer 150. Next, front source / drain contacts FC1 to FC4 connected to the source / drain patterns 160A to 160D while penetrating the second interlayer insulating layer 174 and the first interlayer insulating layer 172 may be formed.

[0212] Reference Fig.32 , a front wiring structure FS is formed on the second interlayer insulating layer 174 and the front source / drain contacts FC1 to FC4.

[0213] The front wiring structure FS may include a plurality of front inter-wiring insulating layers 210 to 260 , a plurality of front wiring patterns FM1 to FM3 , and a plurality of front via patterns FV1 to FV3 . The front wiring structure FS may be electrically connected to the front source / drain contacts FC1 to FC4 .

[0214] Reference Fig.33 , the front wiring structure FS is attached to the carrier substrate 500 .

[0215] For example, the carrier substrate 500 may be attached to Fig.32 After attaching the carrier substrate 500, the Fig.32 For example, the back side of the base substrate 100B may face upward. In some implementations, the front wiring structure FS may be attached to the carrier substrate 500 by an oxide-oxide bonding process.

[0216] Reference Fig.34 , removing the base substrate 100B.

[0217] For example, a grinding process and / or a planarization process may be performed on the base substrate 100B. Since the base substrate 100B is removed, the fin pattern 101 and the sacrificial contact 190S may be exposed.

[0218] Reference Fig.35 , the fin pattern 101 is removed.

[0219] As described above, the fin pattern 101 may have an etching selectivity with respect to the sacrificial contact 190S, so that the fin pattern 101 may be selectively removed. Since the fin pattern 101 is removed, the source / drain patterns 160A to 160D and / or the sacrificial contact 190S may be exposed. Although not specifically shown, during the process of removing the fin pattern 101, the field insulating layer 105 (see FIG. 1 ) may be removed. Figure 3 ) can be retained and not removed.

[0220] Reference Fig.36 , forming a base pattern 102.

[0221] The base pattern 102 may fill the region where the fin pattern 101 has been removed. For example, the base pattern 102 may cover the source / drain patterns 160A to 160D. In addition, the base pattern 102 may cover the side surface of the sacrificial contact 190S and may expose the top surface of the sacrificial contact 190S. Thus, the substrate 100 including the base pattern 102 and the field insulating layer 105 may be formed.

[0222] Reference Fig.37 , remove the sacrificial contact 190S.

[0223] The sacrificial contacts 190S may be removed selectively with respect to the base pattern 102 and / or the field insulating layer 105. As the sacrificial contacts 190S are removed, second contact recesses 190r exposing the source / drain patterns 160A to 160D in regions overlapping the sacrificial contacts 190S may be formed.

[0224] Reference Fig.38 , back side source / drain contacts BC1 to BC4 are formed on the source / drain patterns 160A to 160D.

[0225] Backside source / drain contacts BC1 to BC4 can be filled Fig.37 Thus, back-side source / drain contacts BC1 to BC4 connected to the source / drain patterns 160A to 160D while penetrating the substrate 100 may be formed.

[0226] Reference Fig.39 , power lines PW1 to PW3 are formed on the substrate 100 .

[0227] The power lines PW1 to PW3 may be electrically connected to backside source / drain contacts BC1 to BC4 .

[0228] Next, refer to Figure 2 , forming a backside wiring structure BS including a plurality of backside wiring patterns BM1 and BM2 and a plurality of backside via patterns BV1 and BV2. Thus, the above reference can be manufactured Figures 1 to 7 A semiconductor device is described.

[0229] Although the present disclosure includes many specific implementation details, these details should not be interpreted as limitations on what can be claimed. Certain features described in the present disclosure in the context of separate implementations may also be implemented in combination in a single implementation. On the contrary, various features described in the context of a single implementation may also be implemented separately in multiple implementations or in any suitable sub-combination. In addition, although features may be described above as working in certain combinations, one or more features from a combination may be deleted from the combination in some cases, and the combination may be directed to a sub-combination or a variant of a sub-combination.

[0230] While aspects of the disclosure have been particularly shown and described with reference to implementations thereof, it will be understood by those skilled in the art that various changes in form and details may be made therein without departing from the spirit and scope of the disclosure as defined by the appended claims.

[0231] This application claims the priority of Korean Patent Application No. 10-2023-0130091 filed in the Korean Intellectual Property Office on September 27, 2023 and all rights arising therefrom, the contents of which are incorporated herein by reference in their entirety.

Claims

1. A semiconductor device, comprising: substrate; a first active pattern extending in a first direction on a top surface of the substrate; a second active pattern extending in the first direction on the top surface of the substrate and spaced apart from the first active pattern in a second direction crossing the first direction; a gate structure extending in the second direction on the first active pattern and the second active pattern; a first source / drain pattern connected to the first active pattern and disposed on a side surface of the gate structure; a second source / drain pattern connected to the second active pattern and disposed on the side surface of the gate structure; a first back source / drain contact extending through the substrate and connected to the first source / drain pattern; a second back source / drain contact extending through the substrate and connected to the second source / drain pattern, wherein the second back source / drain contact is spaced apart from the first back source / drain contact in the second direction; and a first power supply line extending in the first direction on the bottom surface of the substrate and connected to the first back source / drain contact and the second back source / drain contact, wherein the first back source / drain contact comprises a first side surface facing the second back source / drain contact and a second side surface opposite to the first side surface, wherein the second back source / drain contact comprises a third side surface facing the first back source / drain contact and a fourth side surface opposite to the third side surface, wherein, at the bottom surface of the substrate, the second side surface and the fourth side surface are spaced apart from each other by a first distance in the second direction, and Wherein, at a bottom surface of the first power line, at least a portion of the first power line has a first width in the second direction that is smaller than the first distance.

2. The semiconductor device according to claim 1, wherein The first active pattern and the second active pattern each extend in the first direction to extend through the gate structure.

3. The semiconductor device according to claim 1, wherein The first source / drain pattern and the second source / drain pattern include impurities of the same conductivity type.

4. The semiconductor device according to claim 1, wherein: A width of the first back source / drain contact in the second direction and a width of the second back source / drain contact in the second direction each decrease with increasing distance from the first power line.

5. The semiconductor device according to claim 1 , further comprising a second power supply line extending in the first direction on the bottom surface of the substrate and spaced apart from the first power supply line in the second direction, in, The first power supply line is configured to provide a first power supply voltage in the semiconductor device, and The second power supply line is configured to provide a second power supply voltage different from the first power supply voltage in the semiconductor device.

6. The semiconductor device according to claim 5, wherein: The first power line and the second power line are spaced apart from each other by a second distance in the second direction at the bottom surface of the first power line, and Wherein, a ratio of the second distance to the first width is in a range from 0.5 to 1.

2.

7. The semiconductor device according to claim 1, wherein The width of the first power line in the second direction increases toward the substrate.

8. The semiconductor device according to claim 7, wherein: At a top surface of the first power line, the width of the first power line in the second direction is greater than or equal to the first distance.

9. The semiconductor device according to claim 1, wherein: The first power line includes a first portion and a second portion arranged along the first direction, wherein, at the bottom surface of the first power line, the first portion has the first width in the second direction, and Wherein, at the bottom surface of the first power line, the second portion has a second width in the second direction that is greater than the first width.

10. The semiconductor device according to claim 9, wherein The second width is greater than or equal to the first distance.

11. The semiconductor device according to claim 1, further comprising: a first front source / drain contact on the top surface of the substrate, the first front source / drain contact connected to the first source / drain pattern; as well as A second front side source / drain contact is formed on the top surface of the substrate, the second front side source / drain contact being connected to the second source / drain pattern.

12. The semiconductor device according to claim 11, wherein In the second direction, the gate structure is interposed between the first back source / drain contact and the first front source / drain contact and between the second back source / drain contact and the second front source / drain contact.

13. A semiconductor device comprising: a first base pattern extending in a first direction; a second base pattern extending in the first direction and spaced apart from the first base pattern in a second direction intersecting the first direction; a first active pattern extending in the first direction on a top surface of the first base pattern; a second active pattern extending in the first direction on a top surface of the second base pattern; a gate structure extending in the second direction on the first active pattern and the second active pattern; a first source / drain pattern connected to the first active pattern and disposed on a side surface of the gate structure; a second source / drain pattern connected to the second active pattern and disposed on the side surface of the gate structure; a first back source / drain contact connected to the first source / drain pattern and disposed in the first substrate pattern; a second back source / drain contact connected to the second source / drain pattern and disposed in the second base pattern; as well as a first power line extending in the first direction and connected to the first back source / drain contact and the second back source / drain contact, wherein the first power line is disposed on a bottom surface of the first substrate pattern and a bottom surface of the second substrate pattern, wherein the first base pattern includes a first side surface facing the second base pattern and a second side surface opposite to the first side surface, wherein the second base pattern includes a third side surface facing the first base pattern and a fourth side surface opposite to the third side surface, wherein, at the bottom surface of the first base pattern, the second side surface and the fourth side surface are spaced apart from each other by a first distance in the second direction, and Wherein, at a bottom surface of the first power line, at least a portion of the first power line has a first width in the second direction that is smaller than the first distance.

14. The semiconductor device according to claim 13, wherein: The first base pattern and the second base pattern each include an insulating material.

15. The semiconductor device according to claim 13, further comprising a field insulating layer, the field insulating layer covering the first side surface, the second side surface, the third side surface and the fourth side surface, in, The gate structure extends along the top surface of the first base pattern, the top surface of the second base pattern, and a top surface of the field insulation layer.

16. The semiconductor device according to claim 13, wherein: A width of the first base pattern in the second direction and a width of the second base pattern in the second direction each decrease as a distance from the first power line increases.

17. The semiconductor device according to claim 13, wherein: The first back side source / drain contact and the second back side source / drain contact are arranged along the second direction.

18. A semiconductor device comprising: substrate; a first active pattern, a second active pattern, and a third active pattern, each of the first active pattern, the second active pattern, and the third active pattern extending in a first direction on a top surface of the substrate, wherein the first active pattern, the second active pattern, and the third active pattern are sequentially arranged along a second direction crossing the first direction; a gate structure extending in the second direction, wherein the first active pattern, the second active pattern, and the third active pattern each extend through the gate structure; a first back source / drain contact extending through the substrate and connected to a first source / drain pattern of the first active pattern; a second back source / drain contact extending through the substrate and connected to the second source / drain pattern of the second active pattern; a third back source / drain contact extending through the substrate and connected to a third source / drain pattern of the third active pattern; a first power supply line extending in the first direction on the bottom surface of the substrate and connected to the first back source / drain contact and the second back source / drain contact, wherein the first power supply line is configured to provide a first power supply voltage; and a second power supply line extending in the first direction on the bottom surface of the substrate and connected to the third back source / drain contact, wherein the second power supply line is configured to provide a second power supply voltage different from the first power supply voltage, wherein the first back source / drain contact comprises a first side surface facing the second back source / drain contact and a second side surface opposite to the first side surface, wherein the second back source / drain contact comprises a third side surface facing the first back source / drain contact and a fourth side surface opposite to the third side surface, wherein, at the bottom surface of the substrate, the second side surface and the fourth side surface are spaced apart from each other by a first distance in the second direction, and Wherein, at a bottom surface of the first power line, at least a portion of the first power line has a first width in the second direction that is smaller than the first distance.

19. The semiconductor device according to claim 18, wherein: The first source / drain pattern and the second source / drain pattern include impurities of a first conductivity type, and The third source / drain pattern includes impurities of a second conductivity type different from the first conductivity type.

20. The semiconductor device according to claim 18, wherein The first power line and the second power line are spaced apart from each other by a second distance in the second direction at the bottom surface of the first power line, and Wherein, a ratio of the second distance to the first width is in a range from 0.8 to 1.1.

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