Semiconductor device and manufacturing method thereof
By introducing an insulated isolation structure and doped semiconductor structure into the ring gate transistor, the problems of poor quality and poor electrical performance of the ring gate transistor in the prior art are solved, and the effect of effectively preventing parasitic channel leakage is achieved.
Patent Information
- Application Number
- CN202411877160.4
- Authority / Receiving Office
- CN · China
- Patent Type
- Applications(China)
- Current Assignee / Owner
- Filing Date
- 2024-12-18
- Publication Date
- 2025-03-28
AI Technical Summary
The existing manufacturing method for suppressing parasitic channel leakage results in poor quality of the ring gate transistor, affecting its electrical performance.
By introducing an insulating isolation structure and a doped semiconductor structure into the semiconductor device, the insulating isolation structure is arranged under the at least one layer of nanostructure, and self-aligning therewith, the conductivity type of the doped semiconductor structure is opposite to the source region and the drain region to prevent parasitic channel leakage.
Effectively prevent parasitic channel leakage, improve the electrical performance of the first ring gate transistor, simplify the manufacturing process, and reduce the yield requirements.
Smart Images
Figure CN119730376A_ABST
Abstract
Description
Technical Field
[0001] The present invention relates to the field of semiconductor technology, and in particular to a semiconductor device and a manufacturing method thereof. Background Art
[0002] With the development of semiconductor technology, the ring-gate transistor has emerged. Because the gate stack structure of the ring-gate transistor is not only formed on the top and sidewalls of the channel region, but also on the bottom of the channel region, compared with the planar transistor and the fin field effect transistor, the ring-gate transistor has a stronger gate control capability, which is conducive to suppressing the short channel effect.
[0003] However, the quality of the all-around gate transistor formed by the existing manufacturing method for suppressing parasitic channel leakage is poor, which is not conducive to improving the electrical performance of the all-around gate transistor. Summary of the invention
[0004] The object of the present invention is to provide a semiconductor device and a method for manufacturing the same, which are used to prevent parasitic channel leakage and help improve the operating performance of the semiconductor device including a first all-round gate transistor.
[0005] In order to achieve the above-mentioned object, in a first aspect, the present invention provides a semiconductor device, which includes: a substrate, and a first ring-gate transistor and an insulating isolation structure arranged on the substrate. The first ring-gate transistor includes a source region, a drain region, at least one layer of nanostructure, a gate stack structure and a doped semiconductor structure. At least one layer of nanostructure is located between the source region and the drain region, and is in contact with the source region and the drain region respectively. The gate stack structure surrounds the periphery of at least a portion of the region of each layer of nanostructure along the length direction. The insulating isolation structure is arranged between the substrate and the source region, the drain region and the gate stack structure respectively. The doped semiconductor structure is arranged between the insulating isolation structure and the source region and the drain region respectively, and the conductivity type of the doped semiconductor structure is opposite to the conductivity type of the source region and the drain region respectively. Among them, the insulating isolation structure is arranged in a portion below at least one layer of nanostructure, and is self-aligned with at least one layer of nanostructure. The thickness of the portion of the insulating isolation structure arranged below at least one layer of nanostructure is H1, and the thickness of the portion of the insulating isolation structure arranged below the source region and the drain region is H2, and H2 is less than H1.
[0006] In the case of adopting the above technical solution, the semiconductor device provided by the present invention includes an insulating isolation structure arranged between the substrate and the source region, the drain region and the gate stack structure respectively. Since the insulating isolation structure is a non-conductive structure, and the thickness H1 of the portion of the insulating isolation structure located below the at least one layer of nanostructure is relatively large, the insulating isolation structure can separate the substrate from at least part of the gate stack structure. At the same time, the portion of the insulating isolation structure arranged below the at least one layer of nanostructure is self-aligned with the at least one layer of nanostructure, so that when a suitable voltage is applied to the gate stack structure, the source region and the drain region are prevented from being turned on through the semiconductor material located below the gate stack structure, that is, parasitic channel leakage is prevented, so that the first ring-gate transistor has good electrical performance.
[0007] In addition, although the thickness H2 of the portion of the insulating isolation structure disposed below the source region and the drain region is relatively small, the manufacturing material of the insulating isolation structure is an insulating material, so the portion of the insulating isolation structure disposed below the source region and the drain region also has a certain electrical isolation effect. In addition, the semiconductor device provided by the present invention also includes an impurity-doped semiconductor structure disposed between the insulating isolation structure and the source region and the drain region, respectively, and having a conductivity type opposite to that of the source region and the drain region, respectively, and the impurity-doped semiconductor structure can form a reverse-biased PN junction with the source region and the drain region, respectively, so as to further suppress parasitic channel leakage through the reverse-biased PN junction. In addition, the area of the gate in the gate stack structure facing the source region and the drain region can be reduced, which is conducive to reducing the parasitic capacitance between the gate and the source region and the drain region, respectively. Furthermore, the semiconductor device provided by the present invention prevents parasitic channel leakage through the above-mentioned insulating isolation structure and doped semiconductor structure. There is no need to use ion implantation and precisely control the implantation parameters to only dope the top silicon layer or the middle and lower parts of the fin structure as in the existing manufacturing method, which makes manufacturing more difficult. This is beneficial to improving the yield of the first ring-gate transistor, and further improving the working performance of the semiconductor device including the first ring-gate transistor.
[0008] In one example, a top of the doped semiconductor structure is flush with a top of a portion of the insulating isolation structure disposed below the at least one layer of nanostructures.
[0009] In one example, surfaces of regions of the insulating isolation structure close to the substrate are flush.
[0010] In one example, when the conductivity type of the first gate-all-around transistor is N-type, the doping concentration of the P-type impurities in the doped semiconductor structure is greater than or equal to 1E17 cm -3 , and less than or equal to 5E18cm -3 , and / or, the material of the doped semiconductor structure includes silicon. Alternatively, when the conductivity type of the first gate-all-around transistor is P-type, the doping concentration of N-type impurities in the doped semiconductor structure is less than or equal to 3E18 cm -3, and / or, the material of the doped semiconductor structure includes germanium silicon.
[0011] In one example, the difference between H2 and H1 is greater than or equal to 15 nm.
[0012] In one example, H2 is less than or equal to 30 nm.
[0013] In one example, the insulating isolation structure includes an isolation portion and a bonding portion, wherein the isolation portion is disposed between two doped semiconductor structures, and the bonding portion is disposed between the substrate and the doped semiconductor structure and the isolation portion, respectively; or, the isolation portion is disposed below the source region, the drain region, and the gate stack structure, and the bonding portion is located between the isolation portion and the substrate.
[0014] In one example, the portions of the insulating isolation structure are integrally continuous.
[0015] In one example, the semiconductor device is a three-dimensional monolithic integrated device. Alternatively, the semiconductor device includes a vertical complementary field effect transistor, the vertical complementary field effect transistor includes a second transistor and a first ring-gate transistor disposed above the second transistor. The second transistor and the first ring-gate transistor have opposite conductivity types.
[0016] In a second aspect, the present invention provides a method for manufacturing a semiconductor device, the method for manufacturing a semiconductor device comprising: first, providing a first semiconductor substrate. Next, forming a first ring-gate transistor on the first semiconductor substrate. The first ring-gate transistor comprises a source region, a drain region, at least one layer of nanostructure, a gate stack structure and a doped semiconductor structure. At least one layer of nanostructure is located between the source region and the drain region, and is in contact with the source region and the drain region respectively. The gate stack structure surrounds the periphery of at least a portion of the region of each layer of nanostructure along the length direction. Next, removing the first semiconductor substrate; and forming an insulating isolation structure on the side of the first ring-gate transistor having the doped semiconductor structure. Next, forming a substrate on the side of the insulating isolation structure away from the first ring-gate transistor. The insulating isolation structure is disposed between the substrate and the source region, the drain region and the gate stack structure respectively. The doped semiconductor structure is disposed between the insulating isolation structure and the source region and the drain region respectively, and the conductivity type of the doped semiconductor structure is opposite to the conductivity type of the source region and the drain region respectively. Wherein, the insulating isolation structure is disposed in a portion below at least one layer of nanostructure and is self-aligned with at least one layer of nanostructure. The thickness of the portion of the insulating isolation structure disposed under at least one layer of the nanostructure is H1, and the thickness of the portion of the insulating isolation structure disposed under the source region and the drain region is H2, and H2 is smaller than H1.
[0017] In one example, a first ring-gate transistor is formed on a first semiconductor substrate, including: forming a fin structure on the first semiconductor substrate. Along the thickness direction of the first semiconductor substrate, the fin structure includes a sacrificial layer and a channel layer that are alternately arranged. Among the alternating sacrificial layers and channel layers, the film layer located at the bottom is a sacrificial layer. Next, a mask structure is formed across the fin structure. Next, the portion of the fin structure exposed outside the mask structure is removed; and the first semiconductor substrate of a partial thickness is continuously etched downward. The protruding portion of the first semiconductor substrate remaining under the fin structure after etching is a layer to be removed. Next, doped semiconductor structures are formed on both sides of the layer to be removed. Next, a source region and a drain region are formed on the doped semiconductor structure and on both sides of the remaining fin structure. Next, at least a portion of the mask structure is removed; and the remaining sacrificial layer is removed so that the remaining channel layer forms a nanostructure. Next, a gate stack structure is formed around the periphery of at least a portion of the area of each layer of nanostructure along the length direction.
[0018] In one example, before removing the portion of the fin structure exposed outside the mask structure and forming a source region and a drain region on the doped semiconductor structure and on both sides of the remaining fin structure, the method for manufacturing a semiconductor device further includes: removing the edge portions on both sides of each remaining sacrificial layer along the length direction to form a recess; and forming an inner side wall in the recess.
[0019] In one example, after removing the portion of the fin-shaped structure exposed outside the mask structure, and before continuing to etch downward a portion of the first semiconductor substrate, the edge portions of both sides of each remaining sacrificial layer along the length direction are removed to form a notch; and an inner sidewall is formed in the notch. Alternatively, after forming doped semiconductor structures on both sides of the layer to be removed, and before forming a source region and a drain region on the doped semiconductor structure and on both sides of the remaining fin-shaped structure, the edge portions of both sides of each remaining sacrificial layer along the length direction are removed to form a notch; and an inner sidewall is formed in the notch.
[0020] In one example, the first semiconductor substrate is removed; and an insulating isolation structure is formed on a side of the first all-round gate transistor having the doped semiconductor structure, including: bonding a second semiconductor substrate on a side of the first all-round gate transistor away from the first semiconductor substrate. Next, the remaining first semiconductor substrate and the layer to be removed are removed. Next, an insulating isolation structure is formed on a side of the first all-round gate transistor away from the second semiconductor substrate.
[0021] The beneficial effects of the second aspect of the present invention and its various implementations can be analyzed by referring to the beneficial effects of the first aspect and its various implementations, and will not be repeated here. BRIEF DESCRIPTION OF THE DRAWINGS
[0022] The drawings described herein are used to provide a further understanding of the present invention and constitute a part of the present invention. The exemplary embodiments of the present invention and their descriptions are used to explain the present invention and do not constitute an improper limitation of the present invention. In the drawings:
[0023] Figure 1 A schematic diagram of the structure of a semiconductor device during the manufacturing process provided by an embodiment of the present invention Figure 1 ;
[0024] Figure 2 A schematic diagram of the structure of a semiconductor device during the manufacturing process provided by an embodiment of the present invention Figure 2 ;
[0025] Figure 3 A schematic diagram of the structure of a semiconductor device during the manufacturing process provided by an embodiment of the present invention Figure 3 ;
[0026] Figure 4 A schematic diagram of the structure of a semiconductor device during the manufacturing process provided by an embodiment of the present invention Figure 4 ;
[0027] Figure 5 A schematic diagram of the structure of a semiconductor device during the manufacturing process provided by an embodiment of the present invention Figure 5 ;
[0028] Figure 6 A schematic diagram of the structure of a semiconductor device during the manufacturing process provided by an embodiment of the present invention Figure 6 ;
[0029] Figure 7 A schematic diagram of the structure of a semiconductor device during the manufacturing process provided by an embodiment of the present invention Figure 7 ;
[0030] Figure 8 A schematic diagram of the structure of a semiconductor device during the manufacturing process provided by an embodiment of the present invention Figure 8 ;
[0031] Fig. 9 A schematic diagram of the structure of a semiconductor device during the manufacturing process provided by an embodiment of the present invention Figure 9 ;
[0032] Fig.10 A schematic diagram of the structure of a semiconductor device during the manufacturing process provided by an embodiment of the present invention Figure 10 ;
[0033] Fig.11 A schematic diagram of the structure of a semiconductor device during the manufacturing process provided by an embodiment of the present invention Figure 10 one;
[0034] Fig.12A schematic diagram of the structure of a semiconductor device during the manufacturing process provided by an embodiment of the present invention Figure 10 two;
[0035] Fig.13 A schematic diagram of the structure of a semiconductor device during the manufacturing process provided by an embodiment of the present invention Figure 10 three;
[0036] Fig.14 A schematic diagram of the structure of a semiconductor device during the manufacturing process provided by an embodiment of the present invention Figure 10 Four;
[0037] Fig.15 A schematic diagram of the structure of a semiconductor device during the manufacturing process provided by an embodiment of the present invention Figure 10 five;
[0038] Fig.16 A schematic diagram of the structure of a semiconductor device during the manufacturing process provided by an embodiment of the present invention Figure 10 six;
[0039] Fig.17 A schematic diagram of the structure of a semiconductor device during the manufacturing process provided by an embodiment of the present invention Figure 10 seven;
[0040] Fig.18 A schematic diagram of the structure of a semiconductor device during the manufacturing process provided by an embodiment of the present invention Figure 10 eight;
[0041] Fig.19 A schematic diagram of the structure of a semiconductor device during the manufacturing process provided by an embodiment of the present invention Figure 10 Nine;
[0042] Fig. 20 A schematic diagram of the structure of a semiconductor device during the manufacturing process provided by an embodiment of the present invention Figure 2 ten;
[0043] Fig.21 A schematic diagram of the structure of a semiconductor device during the manufacturing process provided by an embodiment of the present invention Figure 2 eleven;
[0044] Fig. 22 A schematic diagram of the structure of a semiconductor device during the manufacturing process provided by an embodiment of the present invention Figure 2 twelve;
[0045] Fig.23 A schematic diagram of the structure of a semiconductor device during the manufacturing process provided by an embodiment of the present invention Figure 2 Thirteen;
[0046] Fig.24 A schematic diagram of the structure of a semiconductor device during the manufacturing process provided by an embodiment of the present invention Figure 2fourteen;
[0047] Fig.25 A schematic diagram of the structure of a semiconductor device during the manufacturing process provided by an embodiment of the present invention Figure 2 fifteen;
[0048] Fig.26 A schematic diagram of the structure of a semiconductor device during the manufacturing process provided by an embodiment of the present invention Figure 2 sixteen;
[0049] Fig. 27 A schematic diagram of the structure of a semiconductor device during the manufacturing process provided by an embodiment of the present invention Figure 2 XVII;
[0050] Fig.28 A schematic diagram of the structure of a semiconductor device during the manufacturing process provided by an embodiment of the present invention Figure 2 eighteen;
[0051] Fig.29 A schematic diagram of the structure of a semiconductor device during the manufacturing process provided by an embodiment of the present invention Figure 2 nineteen;
[0052] Fig.30 A schematic diagram of the structure of a semiconductor device during the manufacturing process provided by an embodiment of the present invention Figure 3 ten;
[0053] Fig.31 A schematic diagram of the structure of a semiconductor device during the manufacturing process provided by an embodiment of the present invention Figure 3 eleven;
[0054] Fig.32 A schematic diagram of the structure of a semiconductor device during the manufacturing process provided by an embodiment of the present invention Figure 3 twelve;
[0055] Fig.33 A schematic diagram of the structure of a semiconductor device during the manufacturing process provided by an embodiment of the present invention Figure 3 Thirteen;
[0056] Fig.34 A schematic diagram of the structure of a semiconductor device during the manufacturing process provided by an embodiment of the present invention Figure 3 fourteen;
[0057] Fig.35 A schematic diagram of the structure of a semiconductor device during the manufacturing process provided by an embodiment of the present invention Figure 3 fifteen;
[0058] Fig.36 A schematic diagram of the structure of a semiconductor device during the manufacturing process provided by an embodiment of the present invention Figure 3 sixteen;
[0059] Fig.37 A schematic diagram of the structure of a semiconductor device during the manufacturing process provided by an embodiment of the present invention Figure 3 Seventeen.
[0060] Figure numerals: 11 is a substrate, 12 is a first ring-gate transistor, 13 is an insulating isolation structure, 14 is a source region, 15 is a drain region, 16 is a nanostructure, 17 is a gate stack structure, 18 is a doped semiconductor structure, 19 is an isolation portion, 20 is a bonding portion, 21 is an inner side wall, 22 is a shallow trench isolation structure, 23 is a gate side wall, 24 is an interlayer dielectric layer, 25 is a first semiconductor substrate, 26 is a fin structure, 27 is a sacrificial layer, 28 is a channel layer, 29 is a mask structure, 30 is a layer to be removed, 31 is a recess, and 32 is a second semiconductor substrate. DETAILED DESCRIPTION
[0061] Hereinafter, embodiments of the present invention will be described with reference to the accompanying drawings. However, it should be understood that these descriptions are exemplary only and are not intended to limit the scope of the present invention. In addition, in the following description, descriptions of known structures and technologies are omitted to avoid unnecessary confusion of the concept of the present invention.
[0062] Various structural schematic diagrams according to embodiments of the present invention are shown in the accompanying drawings. These figures are not drawn to scale, and some details are magnified and some details may be omitted for a clearer expression. The shapes of various regions and layers shown in the figures and the relative sizes and positional relationships therebetween are only exemplary, and may deviate in practice due to manufacturing tolerances or technical limitations, and those skilled in the art may additionally design regions / layers with different shapes, sizes, and relative positions according to actual needs.
[0063] In the context of the present invention, when a layer / element is referred to as being "on" another layer / element, the layer / element may be directly on the other layer / element, or there may be an intermediate layer / element between them. In addition, if a layer / element is "on" another layer / element in one orientation, then when the orientation is reversed, the layer / element may be "under" the other layer / element. In order to make the technical problems, technical solutions and beneficial effects to be solved by the present invention clearer, the present invention is further described in detail below in conjunction with the accompanying drawings and embodiments. It should be understood that the specific embodiments described herein are only used to explain the present invention and are not used to limit the present invention.
[0064] In addition, the terms "first" and "second" are used for descriptive purposes only and should not be understood as indicating or implying relative importance or implicitly indicating the number of the indicated technical features. Therefore, the features defined as "first" and "second" may explicitly or implicitly include one or more of the features. In the description of the present invention, the meaning of "multiple" is two or more, unless otherwise clearly and specifically defined. The meaning of "several" is one or more, unless otherwise clearly and specifically defined.
[0065] In the description of the present invention, it should be noted that, unless otherwise clearly specified and limited, the terms "installed", "connected", and "connected" should be understood in a broad sense, for example, it can be a fixed connection, a detachable connection, or an integral connection; it can be a mechanical connection or an electrical connection; it can be a direct connection or an indirect connection through an intermediate medium, it can be the internal connection of two elements or the interaction relationship between two elements. For ordinary technicians in this field, the specific meanings of the above terms in the present invention can be understood according to specific circumstances.
[0066] With the development of semiconductor technology, the ring-gate transistor has emerged. Compared with the fin field effect transistor, the gate-all-around transistor has a gate stack structure formed not only on the top and sidewalls of the channel, but also on the bottom of the channel, which can enhance the gate control ability of the ring-gate transistor, suppress the short channel effect, and make the ring-gate transistor have higher working performance.
[0067] However, the gate-all-around transistor has a parasitic channel leakage problem during actual operation. To solve this problem, those skilled in the art mainly use the following two methods to improve it:
[0068] The first type uses a semiconductor substrate with a buried oxide layer, such as a silicon-on-insulator substrate. The parasitic channel leakage is mainly suppressed by injecting doping into the top silicon layer before the stacked material layer of the epitaxial sacrificial layer / channel layer.
[0069] Second, an anti-punch-through injection process is used to inject impurity ions into the middle and lower part of the formed fin structure to suppress parasitic channel leakage. Specifically, in the process of manufacturing the ring-gate transistor, after the fin structure and the shallow trench isolation structure are formed on the substrate, the anti-punch-through injection process is used to inject impurity ions of a conductivity type opposite to that of the impurities doped in the source region and the drain region into at least the fin structure to form a barrier layer in the middle and lower part of the fin structure, thereby using the highly doped barrier layer to suppress the parasitic channel.
[0070] However, in the semiconductor substrate with buried oxide layer such as silicon on insulator used in the first method, the thickness and uniformity of the top silicon layer are difficult to be guaranteed. Specifically, in the process of manufacturing the semiconductor layer substrate on insulator, the thickness of the top silicon layer itself varies after thinning or epitaxy. Different thicknesses have strict requirements on the concentration of impurity injection, and the thickness of the top silicon layer is usually small (about 20nm), resulting in a higher control accuracy of impurity injection into the thinner top silicon layer, that is, it is more difficult to suppress parasitic channel leakage. In the second method, the process fluctuation (for example: injection depth, source and drain etching depth, etc.) of the anti-punch-through injection process has a greater impact, resulting in poor effect of suppressing parasitic channel leakage. In addition, when the width of the channel region included in the ring gate transistor is large, the fin structure formed on the substrate also has a wider width. Based on this, when the anti-punch-through injection process is used to inject ion impurities into the fin structure, it is difficult for the ion impurities to enter the central area of the fin structure along its width direction, that is, the central area of the fin structure along its width direction does not fully form a barrier layer. In this case, after an appropriate voltage is loaded on the gate stack structure of the ring-gate transistor, the source and drain regions can not only be connected through the channel, but also the central area has a parasitic channel leakage problem, thereby reducing the electrical performance of the ring-gate transistor.
[0071] In order to solve the above technical problems, an embodiment of the present invention provides a semiconductor device and a method for manufacturing the same. The semiconductor device provided in the embodiment of the present invention prevents parasitic channel leakage through an insulating isolation structure and a doped semiconductor structure, and does not need to be implanted by ion implantation and precisely control the implantation parameters to only dope the top silicon layer or the middle and lower parts of the fin structure as in the existing manufacturing method, which leads to greater manufacturing difficulty. This is conducive to improving the yield of the first ring-gate transistor, thereby improving the working performance of the semiconductor device including the first ring-gate transistor.
[0072] Specifically, in a first aspect, an embodiment of the present invention provides a semiconductor device. Figure 35 to Figure 37As shown, the semiconductor device includes: a substrate 11, and a first all-around gate transistor 12 and an insulating isolation structure 13 disposed on the substrate 11. The first all-around gate transistor 12 includes a source region 14, a drain region 15, at least one layer of nanostructure 16, a gate stack structure 17 and a doped semiconductor structure 18. At least one layer of nanostructure 16 is located between the source region 14 and the drain region 15, and is in contact with the source region 14 and the drain region 15 respectively. The gate stack structure 17 surrounds the periphery of at least a portion of the region of each layer of nanostructure 16 along the length direction. The insulating isolation structure 13 is disposed between the substrate 11 and the source region 14, the drain region 15 and the gate stack structure 17 respectively. The doped semiconductor structure 18 is disposed between the insulating isolation structure 13 and the source region 14 and the drain region 15 respectively, and the conductivity type of the doped semiconductor structure 18 is opposite to the conductivity type of the source region 14 and the drain region 15 respectively. Among them, the insulating isolation structure 13 is disposed in the portion below the at least one layer of nanostructure 16, and is self-aligned with the at least one layer of nanostructure 16. The thickness of the portion of the insulating isolation structure 13 disposed under at least one layer of the nanostructure 16 is H1 , and the thickness of the portion of the insulating isolation structure 13 disposed under the source region 14 and the drain region 15 is H2 , and H2 is smaller than H1 .
[0073] When the above technical solution is adopted, Figure 35 to Figure 37 As shown, the semiconductor device provided by the embodiment of the present invention includes an insulating isolation structure 13 disposed between the substrate 11 and the source region 14, the drain region 15 and the gate stack structure 17. Since the insulating isolation structure 13 is a non-conductive structure, and the thickness H1 of the portion of the insulating isolation structure 13 located below the at least one layer of nanostructure 16 is relatively large, the insulating isolation structure 13 can separate the substrate 11 from at least part of the gate stack structure 17. At the same time, the portion of the insulating isolation structure 13 disposed below the at least one layer of nanostructure 16 is self-aligned with the at least one layer of nanostructure 16, so that when a suitable voltage is applied to the gate stack structure 17, the source region 14 and the drain region 15 can be prevented from being turned on through the semiconductor material located below the gate stack structure 17, that is, parasitic channel leakage is prevented, so that the first ring-gate transistor 12 has good electrical performance.
[0074] In addition, if Figure 35 to Figure 37As shown, although the thickness H2 of the portion of the insulating isolation structure 13 disposed below the source region 14 and the drain region 15 is relatively small, the manufacturing material of the insulating isolation structure 13 is an insulating material, so the portion of the insulating isolation structure 13 disposed below the source region 14 and the drain region 15 also has a certain electrical isolation effect. In addition, the semiconductor device provided by the embodiment of the present invention also includes an impurity-doped semiconductor structure 18 disposed between the insulating isolation structure 13 and the source region 14 and the drain region 15, respectively, and the conductivity type is opposite to the conductivity type of the source region 14 and the drain region 15, respectively. The impurity-doped semiconductor structure 18 can form a reverse-biased PN junction with the source region 14 and the drain region 15, respectively, so as to further suppress parasitic channel leakage through the reverse-biased PN junction. In addition, the area facing each other between the gate in the gate stack structure 17 and the source region 14 and the drain region 15, respectively, can also be reduced, which is conducive to reducing the parasitic capacitance between the gate and the source region 14 and the drain region 15, respectively. Furthermore, as Figures 1 to 37 As shown, the semiconductor device provided by the embodiment of the present invention prevents parasitic channel leakage through the above-mentioned insulating isolation structure 13 and the doped semiconductor structure 18. There is no need to use ion implantation and accurately control the implantation parameters to only dope the top silicon layer or the middle and lower parts of the fin structure as in the existing manufacturing method, which makes manufacturing more difficult. This is beneficial to improving the yield of the first ring-gate transistor 12, and further improving the working performance of the semiconductor device including the first ring-gate transistor 12.
[0075] In actual application, the embodiment of the present invention does not specifically limit the device type of the semiconductor device, as long as it can include the above-mentioned substrate, the first ring-gate transistor and the insulating isolation structure.
[0076] For example, the semiconductor device provided by the embodiment of the present invention may have only a single-layer transistor disposed on a substrate. The single-layer transistor may have only one or more first all-round gate transistors, and may also have one or more other transistors (such as fin field effect transistors or conventional all-round gate transistors) having a structure different from that of the first all-round gate transistor.
[0077] Alternatively, illustratively, the semiconductor device provided by the embodiment of the present invention may also be a three-dimensional monolithic integrated device. In this case, the first gate-all-around transistor and the insulating isolation structure may be arranged at any layer in the three-dimensional monolithic integrated device.
[0078] Alternatively, illustratively, the semiconductor device may further include a vertical complementary field effect transistor, and the vertical complementary field effect transistor includes a second transistor and a first ring-gate transistor disposed above the second transistor. The conductivity types of the second transistor and the first ring-gate transistor are opposite. The second transistor may be a fin field effect transistor or a ring-gate transistor, etc.; as for the structure of the second transistor, it may be determined according to the device type of the second transistor, and no specific limitation is made here. The conductivity type of the second transistor may be N-type or P-type. The embodiment of the present invention does not specifically limit the device type and conductivity type of the second transistor, as long as it can be applied to the semiconductor device provided in the embodiment of the present invention.
[0079] For the above-mentioned substrate, the specific structure of the above-mentioned substrate can be set according to the device type of the semiconductor device and the actual application scenario, and is not specifically limited here. For example, the substrate provided in the embodiment of the present invention can be a semiconductor substrate such as silicon, silicon germanium, germanium, etc. without any structure formed. Alternatively, the substrate can also be a semiconductor substrate formed with some structures. For example: when the first ring-gate transistor in the embodiment of the present invention is a transistor of the second layer or higher layer in the semiconductor device, the substrate includes a semiconductor structure located below the first ring-gate transistor, etc.
[0080] For the first ring-gate transistor, from the structural point of view, Figure 35 to Figure 37 As shown, the first ring-gate transistor 12 includes a source region 14, a drain region 15, at least one layer of nanostructure 16, a gate stack structure 17 and a doped semiconductor structure 18. At least one layer of nanostructure 16 is located between the source region 14 and the drain region 15, and is in contact with the source region 14 and the drain region 15 respectively. The first ring-gate transistor 12 may include only a single layer of nanostructure, or may include multiple layers of nanostructure 16 spaced apart along the thickness direction of the substrate 11; the number of layers of nanostructure 16 included in the first ring-gate transistor 12 may be set according to the actual application scenario, and is not specifically limited here. Secondly, the gate stack structure 17 surrounds the periphery of at least a portion of the area of each layer of nanostructure 16 along the length direction. The gate stack structure 17 may include a gate dielectric layer and a gate. The gate dielectric layer surrounds the periphery of at least a portion of the area of each layer of nanostructure 16, and covers the portion of the substrate 11 corresponding to the gate formation area. The gate is located on the gate dielectric layer. The doped semiconductor structure 18 is disposed between the insulating isolation structure 13 and the source region 14 and the drain region 15, respectively, and the conductivity type of the doped semiconductor structure 18 is opposite to the conductivity type of the source region 14 and the drain region 15. For example, when the conductivity type of the first all-around gate transistor 12 is N-type, P-type impurities are doped in the doped semiconductor structure 18. When the conductivity type of the first all-around gate transistor 12 is P-type, N-type impurities are doped in the doped semiconductor structure 18.
[0081] From the material aspect, the source region, the drain region and the nanostructure may include any semiconductor material such as silicon, silicon germanium or germanium.
[0082] As for the material of the gate stack structure, the material of the gate dielectric layer included in the gate stack structure can be HfO 2 、ZrO 2 、TiO 2 or Al 2 O 3 The gate may be made of a conductive material such as TiN, TaN or TiSiN.
[0083] As for the doped semiconductor structure, its material can be determined according to actual needs and actual manufacturing process. It is understandable that in the actual manufacturing process, such as Figures 6 to 37 As shown, after the source and drain etching operation, the first semiconductor substrate 25 can be overetched to form a layer 30 to be removed below the remaining fin structure 26 for manufacturing the nanostructure 16, and then the doped semiconductor structure 18 can be formed in the space released by overetching the first semiconductor substrate 25. In addition, after the first ring-gate transistor 12 is formed, the formed structure will be inverted to remove the remaining first semiconductor substrate 25 and the layer 30 to be removed to achieve self-aligned etching of the parasitic channel. Based on this, when the first semiconductor substrate 25 and the layer 30 to be removed are selectively removed, the etchant will also contact the formed doped semiconductor structure 18, so the material and / or doping of the doped semiconductor structure 18 need to be considered to be able to prevent being affected by the above-mentioned etchant later.
[0084] For example, when the conductivity type of the first gate-all-around transistor is N-type, the doping concentration of the P-type impurities in the doped semiconductor structure may be greater than or equal to 1E17 cm -3 , and less than or equal to 5E18cm -3 , and / or, the material of the doped semiconductor structure includes silicon. Alternatively, when the conductivity type of the first gate-all-around transistor is P-type, the doping concentration of N-type impurities in the doped semiconductor structure is less than or equal to 3E18 cm -3 , and / or, the material of the doped semiconductor structure includes germanium silicon. In the above case, the doped semiconductor structure has a good parasitic channel leakage suppression effect, and can also improve the formation quality of the doped semiconductor structure by doping P-type impurities such as boron, or setting it to a semiconductor material such as germanium silicon different from the first semiconductor substrate material, and further improve the yield of the first ring-gate transistor.
[0085] In terms of appearance, Figure 35 to Figure 37As shown, the top of the doped semiconductor structure 18 can be flush with the top of the portion of the insulating isolation structure 13 disposed below at least one layer of the nanostructure 16. At this time, the side of the source region 14 and the drain region 15 close to the substrate 11 is flush with the bottom of the gate stack structure 17, so that the first all-around gate transistor 12 has a higher working performance.
[0086] Alternatively, the top of the doped semiconductor structure may be lower or higher than the top of the portion of the insulating isolation structure disposed below the at least one layer of nanostructure, so as to reduce the difficulty of the manufacturing process of the first all-around gate transistor.
[0087] In addition, in some cases, such as Figures 6 to 37 As shown, the first ring-gate transistor 12 may also include at least one of a shallow trench isolation structure 22, a gate sidewall 23, an interlayer dielectric layer 24 and an inner sidewall. The shallow trench isolation structure 22 is located on the substrate 11, and is used to isolate different active areas of the substrate 11 to prevent leakage. The thickness of the shallow trench isolation structure 22 can be set according to actual conditions. The gate sidewall 23 is located on both sides of the gate stack structure 17 along its own length direction to isolate the gate stack structure 17 from other conductive structures to ensure that the first ring-gate transistor 12 has stable electrical characteristics. The interlayer dielectric layer 24 covers the substrate 11, and its top is flush with the top of the gate stack structure 17, and is used to protect the source region 14 and the drain region 15 from being affected by operations such as etching and cleaning when removing at least part of the mask structure 29. The inner sidewall 21 is arranged between the gate stack structure 17 and the source region 14 and the drain region 15, respectively, to limit the length of the gate stack structure 17 and improve the yield and working performance of the first ring-gate transistor 12.
[0088] At least one of the gate sidewall, shallow trench isolation structure, interlayer dielectric layer and inner sidewall may be made of SiN, Si 3 N 4 、SiO 2 Or insulating materials such as SiCO.
[0089] It should be noted that, when the first all-around gate transistor does not include the above-mentioned gate sidewalls and inner sidewalls, the gate stack structure may surround the periphery of each region of each layer of nanostructure along the length direction. When the first all-around gate transistor includes the above-mentioned gate sidewalls and / or inner sidewalls, the gate stack structure may only surround the periphery of a portion of the region of each layer of nanostructure along the length direction.
[0090] For the above-mentioned insulating isolation structure, the insulating isolation structure is arranged between the substrate and the source region, the drain region and the gate stack structure respectively. Among them, the surfaces of each region of the insulating isolation structure close to the substrate side can be flush. In addition, the thickness H1 of the portion of the insulating isolation structure arranged under at least one layer of nanostructure and the thickness H2 of the portion of the insulating isolation structure arranged under the source region and the drain region can be determined according to the requirements for the dielectric isolation characteristics of the portion of the insulating isolation structure in the actual application scenario, and the actual manufacturing process, and are not specifically limited here.
[0091] Exemplarily, the difference between H2 and H1 may be greater than or equal to 15 nm, so as to ensure that the portion of the insulating isolation structure located below the nanostructure has a higher insulating property and prevent parasitic channel leakage.
[0092] Exemplarily, H2 may be less than or equal to 30 nm, so as to reduce the amount of consumables used in manufacturing the insulating isolation structure, thereby facilitating the control of the manufacturing cost of the semiconductor device.
[0093] From a structural perspective, Fig.35 As shown, the insulating isolation structure 13 may be a single-layer structure, and in this case, each part of the insulating isolation structure 13 may be continuous as a whole.
[0094] Alternatively, the insulating isolation structure may also be a stacked structure. Fig.36 and Fig.37 As shown, the insulating isolation structure 13 may include an isolation portion 19 and a bonding portion 20. In this case, the presence of the bonding portion 20 can further improve the bonding strength between the insulating isolation structure 13 and the substrate 11, especially the bonding strength between the portion of the insulating isolation structure 13 corresponding to the source region 14 and the drain region 15 and the substrate 11, thereby ensuring that the semiconductor device has a high structural stability.
[0095] Specifically, Fig.36 As shown, the isolation portion 19 may be disposed between two doped semiconductor structures 18, and the bonding portion 20 may be disposed between the substrate 11 and the doped semiconductor structure 18 and the isolation portion 19, respectively. Fig.37 As shown, the isolation portion 19 may also be disposed below the source region 14, the drain region 15 and the gate stack structure 17, and the bonding portion 20 is located between the isolation portion 19 and the substrate 11. In this case, the thickness of the isolation portion 19 and the bonding portion 20 corresponding to the source region 14 and the drain region 15 may be set according to actual needs, and no specific limitation is made here.
[0096] In terms of materials, the material of the insulating isolation structure can be set according to the specific structure of the insulating isolation structure and actual needs, and is not specifically limited here. For example, the material of the insulating isolation structure may include silicon oxide, silicon nitride, silicon oxynitride or silicon oxycarbide.
[0097] In a second aspect, an embodiment of the present invention provides a method for manufacturing a semiconductor device. Figures 1 to 37 The manufacturing process is described in the perspective view or cross-sectional view of the operation shown. Specifically, the manufacturing method of the semiconductor device includes the following steps:
[0098] First, a first semiconductor substrate is provided, which can be any semiconductor substrate such as a silicon substrate, a silicon germanium substrate or a germanium substrate, as long as it can be applied to the manufacturing method provided in the embodiment of the present invention.
[0099] Next, if Figures 1 to 37 As shown, a first all-around gate transistor 12 is formed on a first semiconductor substrate 25. The first all-around gate transistor 12 includes a source region 14, a drain region 15, at least one layer of nanostructure 16, a gate stack structure 17, and a doped semiconductor structure 18. At least one layer of nanostructure 16 is located between the source region 14 and the drain region 15, and is respectively in contact with the source region 14 and the drain region 15. The gate stack structure 17 surrounds the periphery of at least a portion of each layer of nanostructure 16 along the length direction.
[0100] Specifically, the structure and materials of the above-mentioned first all-round gate transistor can refer to the information on the structure and materials of the first all-round gate transistor in the semiconductor device provided in the first aspect above, and will not be repeated here.
[0101] In an actual manufacturing process, illustratively, the above-mentioned step of forming the first gate-all-around transistor on the first semiconductor substrate may include the following steps:
[0102] like Figures 1 to 3 As shown, a fin structure 26 is formed on a first semiconductor substrate 25. Along the thickness direction of the first semiconductor substrate 25, the fin structure 26 includes alternately arranged sacrificial layers 27 and channel layers 28. Among the alternately arranged sacrificial layers 27 and channel layers 28, the film layer at the bottom is the sacrificial layer 27.
[0103] Specifically, the channel layer is used to manufacture the nanostructure included in the first ring-gate transistor, so the material, thickness and number of layers of the channel layer included in the fin structure can be determined based on the material, thickness and number of layers of the nanostructure included in the first ring-gate transistor, which will not be repeated here. In addition, the nanostructure will be released later by removing the portion of the sacrificial layer corresponding to the gate formation area, and the gate stack structure is surrounded by the gap released by removing the portion of the sacrificial layer corresponding to the gate formation area around the periphery of each layer of the nanostructure, so the thickness of the sacrificial layer can be determined based on the thickness of the gate stack structure, and the material of the sacrificial layer can be any semiconductor material different from the channel layer and the first semiconductor substrate.
[0104] For example, when the material of the channel layer and the first semiconductor substrate is silicon or silicon germanium, the material of the sacrificial layer may include silicon germanium or germanium with a higher germanium content.
[0105] For another example, when the materials of the channel layer and the first semiconductor substrate are germanium silicon or germanium with a relatively high germanium content, the material of the sacrificial layer may include germanium silicon or silicon with a relatively low germanium content.
[0106] In the actual manufacturing process, Figure 1 As shown, epitaxy or other processes may be used to form a sacrificial layer 27 and a channel layer 28 on the first semiconductor substrate 25 according to the relative position relationship of each film layer in the fin structure. Figure 2 As shown, the sacrificial layer 27, the channel layer 28 and a portion of the first semiconductor substrate 25 may be etched by photolithography and etching to form a fin. Figure 3 As shown, a shallow trench isolation structure 22 is formed on a first semiconductor substrate 25 by using processes such as deposition and etching. The material of the shallow trench isolation structure 22 can refer to the above. Secondly, the top height of the shallow trench isolation structure 22 is less than or equal to the bottom height of the sacrificial layer 27, and the part of the fin exposed outside the shallow trench isolation structure 22 is a fin-shaped structure 26.
[0107] Next, if Figure 4 As shown, a mask structure 29 is formed across the fin structure 26 .
[0108] In the actual manufacturing process, a deposition process can be used to form a mask material covering the first semiconductor substrate. Then, processes such as photolithography and etching are used to selectively etch the mask material to form the above-mentioned mask structure. As for the material of the mask structure, it can be set according to actual needs, as long as it can play a role in mask protection in the future.
[0109] Exemplarily, the mask structure may include a sacrificial gate. The material of the sacrificial gate may include a material that is easy to remove, such as polysilicon. Secondly, the mask structure may also include a gate oxide layer, and a sacrificial gate located on the gate oxide layer. The material of the gate oxide layer may include materials such as silicon oxide. In addition, the mask structure may also include a sacrificial gate, and gate sidewalls located at least on both sides of the sacrificial gate along the length direction. The material of the gate sidewall can be referred to in the above text and will not be repeated here.
[0110] Next, if Figures 5 to 7 As shown, dry etching or wet etching can be used to remove the portion of the fin structure exposed outside the mask structure 29, and then continue to etch down a portion of the thickness of the first semiconductor substrate 25. The protruding portion of the first semiconductor substrate 25 remaining below the fin structure after etching is the layer 30 to be removed.
[0111] It should be noted that after removing the portion of the fin structure exposed outside the mask structure, the first semiconductor substrate is etched downward to a certain thickness. Figure 8 As shown, a doped semiconductor structure 18 will be subsequently formed in the area released by etching a partial thickness of the first semiconductor substrate 25. Therefore, the thickness of the doped semiconductor structure 18 can be determined according to the actual application scenario, and the etching thickness of the first semiconductor substrate 25 can be determined, and no specific limitation is made here.
[0112] Next, if Figure 8 As shown, epitaxy or other processes can be used to form doped semiconductor structures 18 on both sides of the layer to be removed 30. The material and doping conditions of the doped semiconductor structure 18 can be referred to above and will not be described again here.
[0113] Exemplarily, before removing the portion of the fin structure exposed outside the mask structure and forming a source region and a drain region on the doped semiconductor structure and on both sides of the remaining fin structure, the method for manufacturing the semiconductor device further includes: Fig. 9 As shown, dry etching or wet etching is used to remove the edge portions of both sides of each remaining sacrificial layer 27 along the length direction to form a notch 31; as shown Fig.10 As shown, deposition and etching processes are used to form inner sidewalls 21 in the recess.
[0114] Next, if Fig.11 As shown, epitaxy or other processes may be used to form a source region 14 and a drain region 15 on the doped semiconductor structure 18 and on both sides of the remaining fin structure.
[0115] It should be noted that if Figures 5 to 11 As shown, after removing the portion of the fin-shaped structure exposed outside the mask structure 29, the first semiconductor substrate 25 is etched downward to form a layer to be removed 30. At this time, if the manufactured semiconductor device also includes an inner sidewall 21, after forming the doped semiconductor structure 18 on both sides of the layer to be removed 30, and before forming the source region 14 and the drain region 15 on the doped semiconductor structure 18 and on both sides of the remaining fin-shaped structure, the edge portions of both sides of each remaining sacrificial layer 27 along the length direction are removed to form a notch 31; and the inner sidewall 21 is formed in the notch.
[0116] Or, if Figure 5 , Figures 12 to 17 As shown, after removing the portion of the fin structure exposed outside the mask structure 29 and before continuing to etch downward a portion of the first semiconductor substrate 25, the remaining edge portions of each sacrificial layer 27 on both sides along the length direction may be removed to form a recess 31; and an inner sidewall 21 may be formed in the recess.
[0117] Among them, the specific formation order of the inner wall can be set according to actual needs and is not specifically limited here.
[0118] Next, if Fig.18 As shown, deposition and chemical mechanical polishing processes can be used to form an interlayer dielectric layer 24 covering the first semiconductor substrate 25. The top of the interlayer dielectric layer 24 is flush with the top of the mask structure 29. The material of the interlayer dielectric layer 24 can be referred to above and will not be repeated here.
[0119] Next, if Fig.19 As shown, a dry etching or wet etching process is used to remove at least a portion of the mask structure; and the remaining sacrificial layer is removed, so that the remaining channel layer forms a nanostructure 16.
[0120] Specifically, whether to completely remove the mask structure can be determined according to the specific structure of the mask structure. For example, when the mask structure only includes a gate oxide layer and a sacrificial gate, the mask structure needs to be completely removed. For another example, when the mask structure includes a sacrificial gate and a gate sidewall, only the sacrificial gate needs to be removed, that is, only part of the mask structure needs to be removed.
[0121] Next, if Fig. 20 As shown, atomic layer deposition and other processes can be used to form a gate stack structure 17 surrounding at least a portion of the periphery of each layer of nanostructure 16 along the length direction. The specific structure and material of the gate stack structure 17 can be referred to above and will not be repeated here.
[0122] Next, if Figures 21 to 28 As shown, the first semiconductor substrate is removed; and an insulating isolation structure 13 is formed on the side of the first all-around gate transistor 12 having the doped semiconductor structure 18 .
[0123] Specifically, the operations of removing the first semiconductor substrate and forming the insulating isolation structure may be performed after forming the gate stack structure, or after performing the back-end interconnection process.
[0124] Exemplarily, the above-mentioned removing the first semiconductor substrate; and forming an insulating isolation structure on the side of the first all-around gate transistor having the doped semiconductor structure may include the following steps: Fig.21 As shown, a second semiconductor substrate 32 is bonded to the side of the first gate-all-around transistor 12 away from the first semiconductor substrate 25. The second semiconductor substrate 32 can be any semiconductor substrate with a supporting function, such as a silicon substrate, a silicon germanium substrate, or a germanium substrate, as long as it can be applied to the method for manufacturing a semiconductor device provided in an embodiment of the present invention. Next, as Fig. 22 and Fig.23As shown, the remaining first semiconductor substrate and the layer to be removed are removed. The remaining first semiconductor substrate and the layer to be removed can be removed by at least one process selected from dry etching, wet etching and chemical mechanical polishing. Alternatively, the remaining first semiconductor substrate can be removed by a smart cut (nano knife) process, and then the layer to be removed can be removed by dry etching or wet etching.
[0125] Next, if Figures 24 to 28 As shown, deposition and chemical mechanical polishing processes can be used to form an insulating isolation structure 13 on the side of the first all-around gate transistor 12 away from the second semiconductor substrate 32. The specific material and structure of the insulating isolation structure 13 can be referred to above and will not be repeated here.
[0126] Next, if Figure 29 to Figure 31 As shown, a bonding process or the like can be used to form a substrate 11 on the side of the insulating isolation structure 13 away from the first ring-gate transistor 12. The insulating isolation structure 13 is disposed between the substrate 11 and the source region 14, the drain region 15 and the gate stack structure 17 respectively. The doped semiconductor structure 18 is disposed between the insulating isolation structure 13 and the source region 14 and the drain region 15 respectively, and the conductivity type of the doped semiconductor structure 18 is opposite to the conductivity type of the source region 14 and the drain region 15 respectively. Among them, the insulating isolation structure 13 is disposed in a portion below at least one layer of nanostructure 16, and is self-aligned with at least one layer of nanostructure 16. The thickness of the portion of the insulating isolation structure 13 disposed below at least one layer of nanostructure 16 is H1, and the thickness of the portion of the insulating isolation structure 13 disposed below the source region 14 and the drain region 15 is H2, and H2 is less than H1.
[0127] Next, if Figure 32 to Figure 37 As shown, a debonding process is adopted to remove the second semiconductor substrate to obtain a semiconductor device.
[0128] The beneficial effects of the second aspect and its various implementations in the embodiments of the present invention can be analyzed with reference to the beneficial effects of the first aspect and its various implementations, and will not be repeated here.
[0129] In the above description, the technical details of the patterning and etching of each layer are not described in detail. However, those skilled in the art should understand that various technical means can be used to form layers, regions, etc. of desired shapes. In addition, in order to form the same structure, those skilled in the art can also design methods that are not completely the same as the methods described above. In addition, although the various embodiments are described above separately, this does not mean that the measures in the various embodiments cannot be used in combination to advantage.
[0130] The embodiments of the present invention are described above. However, these embodiments are only for a clearer description and are not intended to limit the scope of the present invention. The scope of the present invention is defined by the appended claims and their equivalents. Without departing from the scope of the present invention, a person skilled in the art may make various substitutions and modifications, which should all fall within the scope of the present invention.
Claims
1. A semiconductor device, characterized in that: The invention comprises: a substrate, and a first ring-gate transistor and an insulating isolation structure arranged on the substrate; The first all-around gate transistor comprises a source region, a drain region, at least one layer of nanostructure, a gate stack structure and a doped semiconductor structure; the at least one layer of nanostructure is located between the source region and the drain region, and is in contact with the source region and the drain region respectively; The gate stack structure surrounds the periphery of at least a portion of each layer of the nanostructure along the length direction; The insulating isolation structure is disposed between the substrate and the source region, the drain region and the gate stack structure respectively; the doped semiconductor structure is disposed between the insulating isolation structure and the source region and the drain region respectively, and the conductivity type of the doped semiconductor structure is opposite to the conductivity type of the source region and the drain region respectively; Wherein, the insulating isolation structure is disposed at a portion below the at least one layer of nanostructures and is self-aligned with the at least one layer of nanostructures; The thickness of the portion of the insulating isolation structure disposed under the at least one layer of nanostructure is H1, and the thickness of the portion of the insulating isolation structure disposed under the source region and the drain region is H2, and H2 is smaller than H1.
2. The semiconductor device according to claim 1, wherein: The top of the doped semiconductor structure is flush with the top of the portion of the insulating isolation structure disposed below the at least one layer of nanostructures; And / or, surfaces of regions of the insulating isolation structure close to one side of the substrate are flush.
3. The semiconductor device according to claim 1, wherein: When the conductivity type of the first all-around gate transistor is N-type, the doping concentration of the P-type impurities in the doped semiconductor structure is greater than or equal to 1E17 cm -3 , and less than or equal to 5E18cm -3 , and / or, the material of the doped semiconductor structure includes silicon; Or, when the conductivity type of the first all-around gate transistor is P-type, the doping concentration of the N-type impurities in the doped semiconductor structure is less than or equal to 3E18 cm -3 , and / or, the material of the doped semiconductor structure includes germanium silicon.
4. The semiconductor device according to claim 1, wherein: The difference between H2 and H1 is greater than or equal to 15nm; And / or, H2 is less than or equal to 30 nm.
5. The semiconductor device according to claim 1, wherein: The insulating isolation structure includes an isolation portion and a bonding portion; wherein the isolation portion is arranged between the two doped semiconductor structures, and the bonding portion is arranged between the substrate and the doped semiconductor structure and the isolation portion respectively; or, the isolation portion is arranged below the source region, the drain region and the gate stack structure, and the bonding portion is located between the isolation portion and the substrate; Alternatively, the various parts of the insulating isolation structure are continuous as one.
6. The semiconductor device according to any one of claims 1 to 5, characterized in that: The semiconductor device is a three-dimensional monolithic integrated device; Alternatively, the semiconductor device includes a vertical complementary field effect transistor, the vertical complementary field effect transistor includes a second transistor and the first ring-gate transistor arranged above the second transistor; the second transistor and the first ring-gate transistor have opposite conductivity types.
7. A method for manufacturing a semiconductor device, characterized in that: include: Providing a first semiconductor substrate; forming a first gate-all-around transistor on the first semiconductor substrate; The first all-around gate transistor comprises a source region, a drain region, at least one layer of nanostructure, a gate stack structure and a doped semiconductor structure; the at least one layer of nanostructure is located between the source region and the drain region, and is in contact with the source region and the drain region respectively; The gate stack structure surrounds the periphery of at least a portion of the region of each layer of the nanostructure along the length direction; removing the first semiconductor substrate; and forming an insulating isolation structure on a side of the first gate-all-around transistor having the doped semiconductor structure; forming a substrate on a side of the insulating isolation structure away from the first all-around gate transistor; The insulating isolation structure is disposed between the substrate and the source region, the drain region and the gate stack structure respectively; the doped semiconductor structure is disposed between the insulating isolation structure and the source region and the drain region respectively, and the conductivity type of the doped semiconductor structure is opposite to the conductivity type of the source region and the drain region respectively; Wherein, the insulating isolation structure is disposed at a portion below the at least one layer of nanostructures and is self-aligned with the at least one layer of nanostructures; The thickness of the portion of the insulating isolation structure disposed under the at least one layer of nanostructure is H1, and the thickness of the portion of the insulating isolation structure disposed under the source region and the drain region is H2, and H2 is smaller than H1.
8. The method for manufacturing a semiconductor device according to claim 7, wherein: The step of forming a first gate-all-around transistor on the first semiconductor substrate comprises: A fin-shaped structure is formed on the first semiconductor substrate; along the thickness direction of the first semiconductor substrate, the fin-shaped structure includes sacrificial layers and channel layers that are alternately arranged; among the sacrificial layers and channel layers that are alternately arranged, the film layer located at the bottom is the sacrificial layer; forming a mask structure spanning over the fin-shaped structure; Removing the portion of the fin-shaped structure exposed outside the mask structure; and continuing to etch downward a portion of the thickness of the first semiconductor substrate; the protruding portion of the first semiconductor substrate remaining below the fin-shaped structure after etching is the layer to be removed; forming the doped semiconductor structure on both sides of the layer to be removed respectively; forming the source region and the drain region on the doped semiconductor structure and on both sides of the remaining fin structure; removing at least a portion of the mask structure; and removing the remaining sacrificial layer, so that the remaining channel layer forms the nanostructure; The gate stack structure is formed around at least a portion of the periphery of each layer of the nanostructure along the length direction.
9. The method for manufacturing a semiconductor device according to claim 8, wherein: Before removing the portion of the fin-shaped structure exposed outside the mask structure and forming the source region and the drain region on the doped semiconductor structure and on both sides of the remaining fin-shaped structure, the method for manufacturing the semiconductor device further includes: The edge portions on both sides of each remaining sacrificial layer along the length direction are removed to form a notch; and an inner sidewall is formed in the notch.
10. The method for manufacturing a semiconductor device according to claim 9, wherein: After removing the portion of the fin structure exposed outside the mask structure and before continuing to etch downward a portion of the first semiconductor substrate, removing both side edge portions of each remaining sacrificial layer along the length direction to form the notch; and forming the inner side wall in the recess; Or, after the doped semiconductor structure is formed on both sides of the layer to be removed, and before the source region and the drain region are formed on the doped semiconductor structure and on both sides of the remaining fin structure, the edge portions on both sides of each remaining sacrificial layer along the length direction are removed to form the recess; and the inner side wall is formed in the recess.
11. The method for manufacturing a semiconductor device according to any one of claims 8 to 10, characterized in that: removing the first semiconductor substrate; An insulating isolation structure is formed on a side of the first gate-all-around transistor having the doped semiconductor structure, comprising: Bonding a second semiconductor substrate to a side of the first gate-all-around transistor facing away from the first semiconductor substrate; removing the remaining first semiconductor substrate and the layer to be removed; The insulating isolation structure is formed on a side of the first gate-all-around transistor facing away from the second semiconductor substrate.