TFT (Thin Film Transistor) substrate manufacturing method and low-temperature polycrystalline silicon TFT substrate
By forming a heavily doped region on the polysilicon layer of a low-temperature polysilicon display and covering the light doped photoresist pattern, LDD ions are directly implanted within the gap distance, solving the problem of difficult control of the ion implantation uniformity and gap width of the light doped leakage region, and improving the display performance.
Patent Information
- Application Number
- CN202411872646.9
- Authority / Receiving Office
- CN · China
- Patent Type
- Applications(China)
- Current Assignee / Owner
- Filing Date
- 2024-12-18
- Publication Date
- 2025-03-28
AI Technical Summary
When existing low-temperature polysilicon displays perform ion implantation in light doped drain region, it is difficult to ensure the uniformity of ions and the gap width of the drain region, affecting the display performance.
After forming the heavily doped region by ND ion implantation, a light doped photoresist pattern is covered on the polycrystalline silicon layer to form two gap distances, and LDD ions are directly implanted within these gap distances to form a light doped region.
This method solves the problem that the light-doped drain region needs to pass through the insulating layer during ion implantation, improves the uniformity and gap width control of the light-doped drain region ions, and improves the display performance of low-temperature polysilicon displays.
Smart Images
Figure CN119730380A_ABST
Abstract
Description
Technical Field
[0001] The invention relates to the technical field of ion implantation of low-temperature polysilicon displays, and in particular to a method for manufacturing a TFT substrate and a low-temperature polysilicon TFT substrate. Background Art
[0002] Most of the liquid crystal display devices on the current market are backlight type liquid crystal display devices, which include a housing, a liquid crystal panel disposed in the housing, and a backlight module disposed in the housing. The structure of a traditional liquid crystal panel is composed of a color filter substrate, a thin film transistor array substrate (TFT array substrate), and a liquid crystal layer disposed between the two substrates. Its working principle is to control the rotation of the liquid crystal molecules of the liquid crystal layer by applying a driving voltage on the two glass substrates, so as to refract the light of the backlight module to produce a picture.
[0003] Low Temperature Poly-silicon (LTPS) technology is a new generation of TFT substrate manufacturing technology. The biggest difference between it and traditional amorphous silicon (a-Si) technology is that low temperature poly-silicon displays have faster response speeds and have the advantages of high brightness, high resolution and low power consumption.
[0004] The uniformity and width of ion implantation in the lightly doped drain region (LDD doping) of low-temperature polysilicon have a great influence on the leakage current of low-temperature polysilicon display devices. Therefore, controlling the uniformity and CD width of the lightly doped drain region (LDD doping) has a great influence on the device characteristics.
[0005] However, the existing low-temperature polysilicon displays need to pass through the insulating layer when performing lightly doped ion implantation. Since the uniformity of the insulating layer is very difficult to control, it is difficult to ensure the uniformity of the lightly doped drain region ions and the gap width of the lightly doped drain region, which affects the display performance of the low-temperature polysilicon display device. Summary of the invention
[0006] When performing ion implantation in existing low-temperature polysilicon displays, it is difficult to control the uniformity of ions and the gap width of the lightly doped drain region, thereby failing to ensure that the low-temperature polysilicon display device achieves the specified display performance.
[0007] In view of the above problems, a TFT substrate manufacturing method and a low-temperature polysilicon TFT substrate are proposed. After a heavily doped area is formed by ND ion implantation, a lightly doped photoresist pattern is covered on the polysilicon layer. The pattern and the heavily doped photoresist pattern form two gap distances. LDD ions are directly implanted in the two gap distances to form a lightly doped area. This solves the problem in the prior art that when LDD ions are implanted, it is necessary to pass through an insulating layer. Since the uniformity of the insulating layer is very controlled, it is difficult to ensure the uniformity of the lightly doped drain area ions and the gap width of the lightly doped drain area, which affects the display performance of the low-temperature polysilicon display device.
[0008] In a first aspect, a method for manufacturing a TFT substrate is provided, which is used to manufacture a TFT substrate for a low-temperature polysilicon display, comprising:
[0009] Step 100: fabricating a polysilicon layer on a glass substrate;
[0010] Step 200, covering the polysilicon layer with a heavily doped ND photoresist pattern, and forming active regions on both sides of the polysilicon layer by ion implantation;
[0011] Step 300, removing the ND heavily doped photoresist pattern, covering the polysilicon layer with a lightly doped photoresist pattern, wherein the lightly doped photoresist pattern and two sides corresponding to the position of the ND heavily doped photoresist pattern form two gap widths, and forming two drain regions in the polysilicon layer corresponding to the two gap widths by ion implantation, wherein the two drain regions are respectively adjacent to the active regions on both sides;
[0012] Step 400: Form a channel region between two drain regions of the polysilicon layer by ion implantation.
[0013] In combination with the TFT substrate manufacturing method described in the first aspect of the present invention, in a first possible implementation manner, the TFT substrate manufacturing method further includes:
[0014] Step 500, removing the lightly doped photoresist pattern, and forming a gate insulating layer on the polysilicon layer film;
[0015] Step 600: fabricating a gate layer on the gate insulating layer.
[0016] In combination with the first possible implementation of the first aspect of the present invention, in a second possible implementation, step 100 includes:
[0017] Step 110, decomposing the silicon source gas, and reacting and depositing on the glass substrate under the action of a radio frequency electric field;
[0018] Step 120 : Setting a specified silicon source gas flow rate and radio frequency power to form a uniform amorphous silicon thin film on the glass substrate.
[0019] In combination with the second possible implementation manner of the first aspect of the present invention, in a third possible implementation manner, step 100 further includes:
[0020] Step 130, irradiating the amorphous silicon thin film with a high energy density excimer laser beam;
[0021] Step 140 , scanning the amorphous silicon film with laser for multiple times to convert the amorphous silicon film into a polycrystalline silicon film.
[0022] In combination with the third possible implementation manner of the first aspect of the present invention, in a fourth possible implementation manner, step 200 includes:
[0023] Step 210, accelerating the ND doped ions to bombard the area of the polysilicon layer not covered by the photoresist under the action of the electric field;
[0024] Step 220: After the ND doping ions are implanted, the polysilicon layer is repaired by rapid thermal annealing.
[0025] In combination with the fourth possible implementation manner of the first aspect of the present invention, in a fifth possible implementation manner, step 300 includes:
[0026] Step 310: Under the action of an electric field, accelerate the LDD doping ions to bombard the regions corresponding to the two gap widths of the polysilicon layer;
[0027] Step 320: After the LDD dopant ion implantation, the polysilicon layer is repaired by rapid thermal annealing.
[0028] In a second aspect, a low temperature polysilicon TFT substrate is provided, using the TFT substrate manufacturing method described in the first aspect, comprising:
[0029] Glass substrate substrate;
[0030] Polysilicon layer;
[0031] The polysilicon layer is formed on the glass substrate by deposition, comprising:
[0032] Active region, drain region and channel region;
[0033] The active region is formed on both sides of the polysilicon layer by covering the polysilicon layer with a heavily doped ND photoresist pattern and by ion implantation;
[0034] The drain region is formed by removing the ND heavily doped photoresist pattern after the active region is formed, covering the polysilicon layer with a lightly doped photoresist pattern, wherein two gap widths are formed between the lightly doped photoresist pattern and the two sides corresponding to the position of the ND heavily doped photoresist pattern, and forming the drain region in the polysilicon layer corresponding to the two gap widths by ion implantation;
[0035] The channel region is formed between the two drain regions of the polysilicon layer by ion implantation after the drain region is formed;
[0036] The two drain regions are adjacent to the active regions on both sides respectively.
[0037] In conjunction with the low-temperature polysilicon TFT substrate described in the second aspect, in a first possible implementation manner, the polysilicon layer is further:
[0038] The silicon source gas is decomposed, and reacts and deposits on the glass substrate under the action of the radio frequency electric field, and a uniform amorphous silicon film is formed on the glass substrate according to the specified gas flow rate and radio frequency power.
[0039] Made.
[0040] In combination with the first possible implementation manner of the second aspect of the present invention, in a second possible implementation manner, the active region is further provided by:
[0041] Under the action of the electric field, the ND doping ions are accelerated to bombard the areas of the polysilicon layer not covered by the photoresist, and after the ND doping ions are implanted, the polysilicon layer is repaired by rapid thermal annealing.
[0042] Made.
[0043] In combination with the second possible implementation manner of the second aspect of the present invention, in a third possible implementation manner, the drain region is further provided by:
[0044] Under the action of the electric field, the LDD doping ions are accelerated to bombard the areas corresponding to the two gap widths of the polysilicon layer, and after the LDD doping ions are implanted, the polysilicon layer is repaired by rapid thermal annealing.
[0045] Made.
[0046] In the TFT substrate manufacturing method and the low-temperature polysilicon TFT substrate of the present invention, after forming a heavily doped region by ND ion implantation, a lightly doped photoresist pattern is covered on the polysilicon layer, and the pattern and the heavily doped photoresist pattern form two gap distances. LDD ions are directly implanted in the two gap distances to form a lightly doped region, which solves the problem in the prior art that when LDD ions are implanted, it is necessary to pass through the insulating layer. Since the uniformity of the insulating layer is very controlled, it is difficult to ensure the uniformity of the lightly doped drain region ions and the gap width of the lightly doped drain region, which affects the display performance of the low-temperature polysilicon display device. BRIEF DESCRIPTION OF THE DRAWINGS
[0047] In order to more clearly illustrate the scheme in the present application, a brief introduction is given below to the drawings required for use in the description of the embodiments of the present application. Obviously, the drawings described below are some embodiments of the present application. For ordinary technicians in this field, other drawings can be obtained based on these drawings without paying any creative work.
[0048] Figure 1 is a flow chart of an embodiment of a TFT substrate manufacturing method of the present application;
[0049] Figure 2 yes Figure 1 A flowchart of a specific implementation of S100;
[0050] Figure 3 yes Figure 2 A flowchart of a specific implementation method after S120;
[0051] Figure 4 yes Figure 1 A flowchart of a specific implementation of S200;
[0052] Figure 5 yes Figure 4 A flowchart of a specific implementation method after S220;
[0053] Figure 6 is a flow chart of another embodiment of a TFT substrate manufacturing method of the present application;
[0054] Figure 7 It is a schematic diagram of a TFT substrate manufacturing method in the prior art;
[0055] Figure 8 It is a schematic diagram of a TFT substrate manufacturing method in this application. DETAILED DESCRIPTION
[0056] The following will be combined with the accompanying drawings in the invention to clearly and completely describe the technical solutions in the present invention. Obviously, the described embodiments are only part of the embodiments of the present invention, not all of the embodiments. Based on the embodiments in the present invention, other embodiments obtained by ordinary technicians in this field without creative work are all within the scope of protection of the present invention.
[0057] Reference to "embodiments" herein means that a particular feature, structure, or characteristic described in conjunction with the embodiments may be included in at least one embodiment of the present application. The appearance of the phrase in various locations in the specification does not necessarily refer to the same embodiment, nor is it an independent or alternative embodiment that is mutually exclusive with other embodiments. It is explicitly and implicitly understood by those skilled in the art that the embodiments described herein may be combined with other embodiments.
[0058] Unless otherwise defined, all technical and scientific terms used herein have the same meaning as commonly understood by technicians in the technical field to which this application belongs; the terms used in the specification of the application are only for the purpose of describing specific embodiments and are not intended to limit this application; the terms "including" and "having" in the specification and claims of this application and the above-mentioned figure descriptions and any variations thereof are intended to cover non-exclusive inclusions.
[0059] In addition, the terms "first" and "second" are used for descriptive purposes only and should not be understood as indicating or implying relative importance or implicitly indicating the number of the indicated technical features. Thus, a feature defined as "first" or "second" may explicitly or implicitly include one or more of the features. In the description of this application, the meaning of "plurality" is two or more, unless otherwise clearly and specifically defined.
[0060] Explanation of the name:
[0061] When performing ion implantation in existing low-temperature polysilicon displays, it is difficult to control the uniformity of ions and the gap width of the lightly doped drain region, thereby failing to ensure that the low-temperature polysilicon display device achieves the specified display performance.
[0062] like Figure 7 , Figure 7 It is a schematic diagram of a TFT substrate manufacturing method in the prior art;
[0063] The process route of the existing technology is: laser slicing (LS) - polysilicon layer production (Poly-Si) - ND ion implantation - gate insulation layer production (GI CVD) - gate layer production (GATE) - LDD (lightly drain doped) ion implantation (LDD Doping).
[0064] The injection principle of the prior art is: the Poly Si part blocked by ND PR (ND heavily doped photoresist) will not be injected with ND ions. After the ND ion injection, the ND PR is removed, and the gate insulation layer (GI CVD) and the gate layer (GATE metal line) are made after cleaning. There is a left and right gap d1&d2 between the Poly-Si and the GATE line blocked by ND PR, which is the LDD width (gap distance). Finally, LDD ion injection is performed for light doping. Here, it is necessary to pass through GI CVD during injection. In actual production, the uniformity of GI CVD is difficult to control, and the etching of the GATE line after GI CVD is difficult to control, which affects the accuracy of the LDD width.
[0065] In view of the above problems, a TFT substrate manufacturing method and a low-temperature polysilicon display are proposed.
[0066] In a first aspect, a method for manufacturing a TFT substrate is provided. Figure 1 , Figure 1 This is a flow chart of an embodiment of a method for manufacturing a TFT substrate of the present application; the method is used to manufacture a TFT substrate for a low-temperature polysilicon display, comprising:
[0067] S100, manufacturing a polysilicon layer on a glass substrate.
[0068] In this embodiment, a large array substrate is divided into single array substrates by a laser scribing LS process, and a high energy density laser beam can be used for cutting to obtain a glass substrate.
[0069] In a preferred embodiment, if Figure 2 , Figure 2 yes Figure 1 A flowchart of a specific implementation method of S100; S100 includes: S110, decomposing the silicon source gas, and reacting and depositing on the glass substrate under the action of the radio frequency electric field; S120, setting a specified silicon source gas flow rate and radio frequency power to form a uniform amorphous silicon film on the glass substrate.
[0070] In this embodiment, plasma enhanced chemical vapor deposition (PECVD) technology is used to decompose the silicon source gas (SiH4) in a plasma environment. Under the action of the radio frequency electric field, the reaction gas is ionized to generate plasma, and the active radicals therein react with each other and are deposited on the substrate.
[0071] The temperature is controlled at 300-400° C. and parameters such as gas flow rate and radio frequency power are set according to specified values to form a uniform amorphous silicon film on the substrate.
[0072] In a preferred embodiment, if Figure 3 , Figure 3 yes Figure 2 A flowchart of a specific implementation method after S120 in FIG. 1 ; S100 also includes: S130, irradiating the amorphous silicon film with a high energy density excimer laser beam; S140, converting the amorphous silicon film into a polycrystalline silicon film by scanning the amorphous silicon film with the laser multiple times.
[0073] In this embodiment, the energy of the laser pulse can make amorphous silicon absorb enough energy in a short time, and the atoms can rearrange into polycrystalline silicon after obtaining enough kinetic energy. For example, a XeC excimer laser with a wavelength of 308nm is used to scan the surface of the amorphous silicon film multiple times, optimize the scanning interval and laser energy density of each time, and thus convert amorphous silicon into polycrystalline silicon.
[0074] S200 , covering the polysilicon layer with a heavily ND-doped photoresist pattern, and forming active regions on both sides of the polysilicon layer by ion implantation.
[0075] In a preferred embodiment, Figure 4 , Figure 4 yes Figure 1 A flowchart of a specific implementation method of S200; S200 includes: S210, under the action of an electric field, accelerating ND doped ions to bombard the polysilicon layer not covered by the photoresist; S220, after the ND doped ions are implanted, using rapid thermal annealing to repair the polysilicon layer.
[0076] In this embodiment, after the polysilicon layer is formed, heavy doping is required to change the electrical properties to form an active area. First, ND heavily doped photoresist is evenly coated on the polysilicon layer, and then a mask is used to migrate the mask pattern to the ND heavily doped photoresist after exposure and development to form an ND heavily doped photoresist pattern to protect the polysilicon layer area that does not require ND ion implantation.
[0077] In this embodiment, for the ND heavily doped region, the commonly used impurity element is phosphorus (P). Phosphorus ions are implanted into the target area of the polysilicon layer by ion implantation. After the ion implantation, annealing is performed to repair lattice damage and activate the implanted phosphorus ions.
[0078] S300, removing the ND heavily doped photoresist pattern, covering the polysilicon layer with a lightly doped photoresist pattern, forming two gap widths between the lightly doped photoresist pattern and the corresponding ND heavily doped photoresist pattern position on both sides, and forming two drain regions in the polysilicon layer corresponding to the two gap widths through ion implantation, and the two drain regions are respectively adjacent to the active regions on both sides.
[0079] In this embodiment, after the active area is formed, the ND heavily doped photoresist pattern is removed and a lightly doped photoresist pattern is covered on the polysilicon layer. At this time, it is necessary to refer to the original ND heavily doped photoresist pattern so that two gap distances are formed in the lightly doped photoresist pattern to facilitate LDD ion implantation into the polysilicon layer.
[0080] In a preferred embodiment, if Figure 5 , Figure 5 yes Figure 4 A flowchart of a specific implementation method after S220; S300 includes: S310, under the action of the electric field, accelerating the LDD doping ions to bombard the two gap widths corresponding to the polysilicon layer; S320, after the LDD doping ions are implanted, using rapid thermal annealing to repair the polysilicon layer.
[0081] In this embodiment, the LDD ion doping concentration is smaller than the ND ion concentration in the heavily doped region, for example, it may be one tenth of the heavily doped concentration.
[0082] S400 , forming a channel region between two drain regions of the polysilicon layer.
[0083] In a preferred embodiment, Figure 6 , Figure 6 1 is a flow chart of another embodiment of a TFT substrate manufacturing method of the present application; the TFT substrate manufacturing method further includes:
[0084] S500, remove the lightly doped photoresist pattern, and make a gate insulating layer on the polysilicon film; S600, make a gate layer on the gate insulating layer. After forming a heavily doped region through ND ion implantation, cover the polysilicon layer with a lightly doped photoresist pattern, and the pattern and the heavily doped photoresist pattern form two gap distances. LDD ions are directly implanted in the two gap distances to form a lightly doped region, which solves the problem in the prior art that when LDD ions are implanted, it is necessary to pass through the insulating layer. Since the uniformity of the insulating layer is very controlled, it is difficult to ensure the uniformity of the lightly doped drain region ions and the gap width of the lightly doped drain region, which affects the display performance of the low-temperature polysilicon display device.
[0085] like Figure 8 , Figure 8 Schematic diagram of a TFT substrate manufacturing method in this application. The ion implantation principle of the embodiment of this application is:
[0086] ND PR blocks the Ploy-Si part and ND ions will not be injected. After ND ion injection, a heavily doped area is obtained. After the active area is formed, the ND PR is removed, and LDD PHT PR (LDD post-annealing photoresist) is performed after cleaning. There is a left and right gap d1&d2 between the Ploy-Si part blocked by ND PR and the LDD PHT PR, which is the LDD width (gap distance). Then LDD ion injection is performed, and finally GI CVD and GATE lines are performed. Here, there is no need to pass through GI CVD during injection. Both ND ion injection and LDD ion injection are completed in the Poly-Si layer, which reduces the interference layer and injection depth, and is more conducive to improving the uniformity of LDD ion injection.
[0087] In a second aspect, a low-temperature polycrystalline silicon TFT substrate adopts the TFT substrate manufacturing method of the first aspect, including a glass substrate substrate and a polycrystalline silicon layer; the polycrystalline silicon layer is manufactured on the glass substrate substrate by deposition, and includes an active region, a drain region and a channel region; the active region is formed on both sides of the polycrystalline silicon layer by covering the polycrystalline silicon layer with an ND heavily doped photoresist pattern and by ion implantation; the drain region is formed by removing the ND heavily doped photoresist pattern after the active region is formed, and covering the polycrystalline silicon layer with a lightly doped photoresist pattern, the lightly doped photoresist pattern and the two sides of the corresponding ND heavily doped photoresist pattern position forming two gap widths, and by ion implantation, the polycrystalline silicon layer corresponding to the two gap widths is formed; the channel region is formed between the two drain regions of the polycrystalline silicon layer by ion implantation after the drain region is formed; wherein the two drain regions are respectively adjacent to the active regions on both sides.
[0088] Furthermore, the polysilicon layer is further made by decomposing the silicon source gas, reacting and depositing on the glass substrate under the action of the radio frequency electric field, and forming a uniform amorphous silicon film on the glass substrate according to the specified gas flow and radio frequency power.
[0089] Furthermore, the active region is further manufactured by accelerating ND doping ions to bombard the region of the polysilicon layer not covered by the photoresist under the action of an electric field, and repairing the polysilicon layer by rapid thermal annealing after the ND doping ions are implanted.
[0090] Furthermore, the drain region is further manufactured by accelerating LDD doping ions to bombard the regions corresponding to the two gap widths of the polysilicon layer under the action of an electric field, and repairing the polysilicon layer by rapid thermal annealing after the LDD doping ions are implanted.
[0091] In the TFT substrate manufacturing method and the low-temperature polysilicon TFT substrate of the present invention, after forming a heavily doped region by ND ion implantation, a lightly doped photoresist pattern is covered on the polysilicon layer, and the pattern and the heavily doped photoresist pattern form two gap distances. LDD ions are directly implanted in the two gap distances to form a lightly doped region, which solves the problem in the prior art that when LDD ions are implanted, it is necessary to pass through the insulating layer. Since the uniformity of the insulating layer is very controlled, it is difficult to ensure the uniformity of the lightly doped drain region ions and the gap width of the lightly doped drain region, which affects the display performance of the low-temperature polysilicon display device.
[0092] The above are only preferred embodiments of the present invention and are not intended to limit the present invention. Any modifications, equivalent substitutions, improvements, etc. made within the spirit and principles of the present invention should be included in the protection scope of the present invention.
Claims
1. A method for manufacturing a TFT substrate, characterized in that it is used to manufacture a TFT substrate for a low-temperature polysilicon display, comprising: Step 100: fabricating a polysilicon layer on a glass substrate; Step 200, covering the polysilicon layer with a heavily doped ND photoresist pattern, and forming active regions on both sides of the polysilicon layer by ion implantation; Step 300, removing the ND heavily doped photoresist pattern, covering the polysilicon layer with a lightly doped photoresist pattern, wherein the lightly doped photoresist pattern and two sides corresponding to the position of the ND heavily doped photoresist pattern form two gap widths, and forming two drain regions in the polysilicon layer corresponding to the two gap widths by ion implantation, wherein the two drain regions are respectively adjacent to the active regions on both sides; Step 400: Form a channel region between two drain regions of the polysilicon layer by ion implantation.
2. The method for manufacturing a TFT substrate according to claim 1, wherein: The TFT substrate manufacturing method further includes: Step 500, removing the lightly doped photoresist pattern, and forming a gate insulating layer on the polysilicon layer film; Step 600: fabricating a gate layer on the gate insulating layer.
3. The method for manufacturing a TFT substrate according to claim 2, wherein: The step 100 comprises: Step 110, decomposing the silicon source gas, and reacting and depositing on the glass substrate under the action of a radio frequency electric field; Step 120 : Setting a specified silicon source gas flow rate and radio frequency power to form a uniform amorphous silicon thin film on the glass substrate.
4. The method for manufacturing a TFT substrate according to claim 3, characterized in that: The step 100 further includes: Step 130, irradiating the amorphous silicon thin film with a high energy density excimer laser beam; Step 140 , scanning the amorphous silicon film with laser for multiple times to convert the amorphous silicon film into a polycrystalline silicon film.
5. The method for manufacturing a TFT substrate according to claim 4, characterized in that: The step 200 comprises: Step 210, accelerating the ND doped ions to bombard the area of the polysilicon layer not covered by the photoresist under the action of the electric field; Step 220: After the ND doping ions are implanted, the polysilicon layer is repaired by rapid thermal annealing.
6. The method for manufacturing a TFT substrate according to claim 5, characterized in that: The step 300 includes: Step 310: Under the action of an electric field, accelerate the LDD doping ions to bombard the regions corresponding to the two gap widths of the polysilicon layer; Step 320: After the LDD doping ions are implanted, the polysilicon layer is repaired by rapid thermal annealing.
7. A low temperature polysilicon TFT substrate, using the TFT substrate manufacturing method according to any one of claims 1 to 6, characterized in that: include: Glass substrate substrate; Polysilicon layer; The polysilicon layer is formed on the glass substrate by deposition, comprising: Active region, drain region and channel region; The active region is formed on both sides of the polysilicon layer by covering the polysilicon layer with a heavily doped ND photoresist pattern and by ion implantation; The drain region is formed by removing the ND heavily doped photoresist pattern after the active region is formed, covering the polysilicon layer with a lightly doped photoresist pattern, wherein two gap widths are formed between the lightly doped photoresist pattern and the two sides corresponding to the position of the ND heavily doped photoresist pattern, and forming the drain region in the polysilicon layer corresponding to the two gap widths by ion implantation; The channel region is formed between the two drain regions of the polysilicon layer by ion implantation after the drain region is formed; The two drain regions are adjacent to the active regions on both sides respectively.
8. The low-temperature polysilicon TFT substrate according to claim 7, characterized in that: The polysilicon layer is further passed through: The silicon source gas is decomposed, and reacts and deposits on the glass substrate under the action of the radio frequency electric field, and the specified gas flow rate and radio frequency power are set to form a uniform amorphous silicon film on the glass substrate. Made.
9. The low-temperature polysilicon TFT substrate according to claim 8, characterized in that: The active region is further provided by: Under the action of the electric field, the ND doping ions are accelerated to bombard the areas of the polysilicon layer not covered by the photoresist, and after the ND doping ions are implanted, the polysilicon layer is repaired by rapid thermal annealing. Made.
10. The low-temperature polysilicon TFT substrate according to claim 9, characterized in that: The drain region is further provided by: Under the action of the electric field, the LDD doping ions are accelerated to bombard the areas corresponding to the two gap widths of the polysilicon layer, and after the LDD doping ions are implanted, the polysilicon layer is repaired by rapid thermal annealing. Made.