Thin film transistor substrate and display device using the same

Abstract

Provided is a thin film transistor substrate including: a substrate; a first gate electrode on the substrate, the first gate electrode including a first portion and a second portion; an active layer on the first gate electrode; a second gate electrode on the active layer, the second gate electrode overlapping at least a first portion of the first gate electrode; a source electrode connected to a first side of the active layer; and a drain electrode connected to a second side of the active layer, in which a first portion overlaps the second gate electrode, a second portion protrudes from one end of the first portion in a direction toward the source electrode or the drain electrode, and a thickness of the second portion is smaller than a thickness of the first portion. A display device is provided that includes the thin film transistor substrate. The present invention can minimize or at least reduce high bonding stress regions.

Description

[0001] CROSS-REFERENCE TO RELATED APPLICATIONS

[0002] This application claims the benefit of Korean Patent Application No. 10-2023-0129520, filed on September 26, 2023, which is hereby incorporated by reference in its entirety. Technical Field

[0003] The present invention relates to a thin film transistor substrate and a display device using the thin film transistor substrate. Background Art

[0004] Since thin film transistors can be manufactured on glass or plastic substrates, they are widely used as switching elements or driving elements of display devices such as liquid crystal display devices or organic light emitting display devices.

[0005] According to the positional relationship between the gate electrode and the active layer, thin film transistors can be divided into a top gate structure in which the gate electrode is arranged above the active layer, a bottom gate structure in which the gate electrode is arranged below the active layer, and a double gate structure in which two or more gate electrodes are arranged above and below the active layer.

[0006] Among them, the thin film transistor with a dual-gate structure can be formed so that the width of the gate electrode arranged at the bottom is greater than the width of the gate electrode arranged at the top. In this case, the upper gate electrode and the lower gate electrode with different widths have different effects on the active layer, and thus high junction stress (junction stress) may be formed in the active layer. The area where high junction stress is formed in the active layer can be defined as a so-called high junction stress region (HJS region). When such an HJS region is generated, there is a problem that the threshold voltage Vth will change significantly during the driving (conduction) process of the thin film transistor, and as the threshold voltage Vth changes, the life of the device will be shortened. Therefore, it is important to minimize or at least reduce such an HJS region. Summary of the Invention

[0007] The present invention has been made in view of the above problems, and its object is to provide a thin film transistor substrate and a display device using the thin film transistor substrate, which minimizes or at least reduces the HJS area by adjusting the electric field strength of the upper gate electrode and the lower gate electrode to the active layer in the area where the upper gate electrode and the lower gate electrode do not overlap.

[0008] According to one or more embodiments of the present invention, the above and other purposes can be achieved by providing a thin film transistor substrate and a display device including the thin film transistor substrate, wherein the thin film transistor substrate includes: a substrate; a first gate electrode on the substrate, the first gate electrode including a first part and a second part; an active layer on the first gate electrode; a second gate electrode on the active layer, the second gate electrode overlapping at least the first part of the first gate electrode; a source electrode connected to a first side of the active layer; and a drain electrode connected to a second side of the active layer, wherein the second part protrudes from one end of the first part in a first direction toward one of the source electrode and the drain electrode, and the thickness of the second part is less than the thickness of the first part.

[0009] In addition, the above and other purposes can be achieved by providing a thin film transistor substrate and a display device including the thin film transistor substrate, wherein the thin film transistor substrate includes: a substrate; a first gate electrode on the substrate, the first gate electrode including a first portion and a plurality of second portions, the plurality of second portions being separated from each other with a plurality of first grooves sandwiched between the plurality of second portions; an active layer on the first gate electrode; a second gate electrode on the active layer, the second gate electrode overlapping with at least a portion of the first gate electrode; a source electrode connected to a first side of the active layer; and a drain electrode connected to a second side of the active layer, wherein the plurality of second portions protrude from a first end of the first portion in a first direction toward one of the source electrode and the drain electrode, and wherein one end of the second gate electrode overlaps with a region extending from the first end of the first portion to one end of the second portion.

[0010] In addition, the above and other purposes can be achieved by providing a thin film transistor substrate, which includes: a first gate electrode extending in a first direction, the first gate electrode including a first portion and a plurality of second portions protruding from a first end of the first portion along a second direction different from the first direction, the plurality of second portions being separated from each other; an active layer on the first gate electrode and extending in the second direction, the active layer partially overlapping with the first portion and a portion of the second portion among the plurality of second portions along the first direction; a source electrode connected to a first side of the active layer; a drain electrode connected to a second side of the active layer, the second side of the active layer being opposite to the first side of the active layer along the second direction; and a second gate electrode on the active layer and extending in the first direction, the second gate electrode partially overlapping with the first gate electrode along the second direction without overlapping with one end of the plurality of second portions. BRIEF DESCRIPTION OF THE DRAWINGS

[0011] The above and other objects, features and other advantages of the present invention will be more clearly understood from the following detailed description taken in conjunction with the accompanying drawings, in which:

[0012] Figure 1A FIG. 1 is a plan view of a thin film transistor substrate according to an embodiment of the present invention.

[0013] Figure 1B FIG. 1 is a plan view of a first gate electrode and a second gate electrode of a thin film transistor substrate according to an embodiment of the present invention.

[0014] Figure 2A is a cross-sectional view of a thin film transistor substrate according to one embodiment of the present invention. In this case, Figure 2A The cross-section in the figure corresponds to the Figure 1A The cross section is taken along line II'.

[0015] Figure 2B is a cross-sectional view of a thin film transistor substrate according to one embodiment of the present invention. In this case, Figure 2B The cross-section in the figure corresponds to the Figure 1A A cross section taken along line II-II'.

[0016] Figure 2C is a cross-sectional view of a thin film transistor substrate according to one embodiment of the present invention. In this case, Figure 2C The cross-section in the figure corresponds to the Figure 1A A cross section taken along line III-III'.

[0017] Figure 3A is a cross-sectional view of a thin film transistor substrate according to another embodiment of the present invention. In this case, Figure 3A The cross-section in the figure corresponds to the Figure 1A A cross section taken along line II'.

[0018] Figure 3B is a cross-sectional view of a thin film transistor substrate according to another embodiment of the present invention. In this case, Figure 3B The cross-section in the figure corresponds to the Figure 1A A cross section taken along line II-II'.

[0019] Figure 4 is a plan view of a thin film transistor substrate according to another embodiment of the present invention.

[0020] Figure 5A is a cross-sectional view of a thin film transistor substrate according to another embodiment of the present invention. In this case, Figure 5A The cross-section in the figure corresponds to the Figure 4 A cross section taken along line IV-IV'.

[0021] Figure 5B is a cross-sectional view of a thin film transistor substrate according to another embodiment of the present invention. In this case, Figure 5B The cross-section in the figure corresponds to the Figure 4 The cross section is taken along line V-V'.

[0022] Figure 6 is a plan view of a thin film transistor substrate according to another embodiment of the present invention.

[0023] Figure 7A is a cross-sectional view of a thin film transistor substrate according to another embodiment of the present invention. In this case, Figure 7A The cross-section in the figure corresponds to the Figure 6 A cross section taken along line VI-VI'.

[0024] Figure 7B is a cross-sectional view of a thin film transistor substrate according to another embodiment of the present invention. In this case, Figure 7B The cross-section in the figure corresponds to the Figure 6 A cross section taken along line VII-VII'.

[0025] Figure 8 is a plan view of a thin film transistor substrate according to another embodiment of the present invention.

[0026] Figure 9 is a plan view of a thin film transistor substrate according to another embodiment of the present invention.

[0027] Figure 10 FIG. 1 is a cross-sectional view of a display device including a thin film transistor substrate according to an embodiment of the present invention.

[0028] Figure 11 is a schematic diagram of a display device according to an embodiment of the present invention.

[0029] Figure 12 is a circuit diagram of a pixel included in a display device according to an embodiment of the present invention. DETAILED DESCRIPTION

[0030] The advantages and features of the present invention, as well as their implementation methods, will be illustrated by the following embodiments described with reference to the accompanying drawings. However, the present invention may be embodied in various forms and should not be construed as limited to the embodiments listed herein. Rather, these embodiments are provided so that this disclosure will be thorough and complete and will fully convey the scope of the present invention to those skilled in the art. Furthermore, the present invention is limited only by the scope of the claims.

[0031] The shapes, sizes, proportions, angles, and quantities disclosed in the drawings for describing the embodiments of the present invention are merely examples, and the present invention is therefore not limited to the illustrated details. The same reference numerals refer to the same elements throughout. In the following description, when it is determined that a detailed description of a related known function or structure would unnecessarily obscure the key points of the present invention, such detailed description will be omitted.

[0032] Where “including,” “having,” and “comprising” are used in the description of the present application, other parts may also be present unless “only” is used. Terms in the singular form may include plural forms unless otherwise indicated.

[0033] When interpreting an element, although not explicitly described, the element is interpreted as including a range of error.

[0034] When describing a positional relationship, for example, when the positional order is described as "on," "above," "below," "under," and "after," the case where there is no contact between them may be included unless "just" or "directly" is used.

[0035] If a first element is referred to as being "on" a second element, this does not necessarily mean that the first element is above the second element in the drawing. The upper and lower parts of the objects referred to may vary depending on the positioning of the objects. Thus, a first element being "on" a second element includes both the case where the first element is "below" the second element in the drawing or in actual construction, as well as the case where the first element is "above" the second element.

[0036] When describing a temporal relationship, for example, when a temporal order relationship is described as "after," "subsequently," "next," and "before," discontinuous cases may be included unless "just" or "directly" is used.

[0037] It will be understood that although the terms "first," "second," etc. may be used herein to describe various elements, these elements should not be limited by these terms. These terms are merely used to distinguish one element from another. For example, a first element may be referred to as a second element, and similarly, a second element may be referred to as a first element.

[0038] It should be understood that the term "at least one" includes all combinations related to any one item. For example, "at least one of a first element, a second element, and a third element" includes all combinations of two or more elements selected from the first element, the second element, and the third element, as well as each of the first element, the second element, and the third element.

[0039] The features of the various embodiments of the present invention may be combined or combined with each other in part or in whole, and may interoperate and drive each other in various technical aspects. The embodiments of the present invention may be implemented independently of each other, or implemented together in a mutually dependent relationship.

[0040] In the drawings, the same or similar elements are denoted by the same reference numerals even though they are depicted in different drawings.

[0041] In the embodiments of the present invention, the source electrode and the drain electrode are distinguished from each other for ease of description. However, the source electrode and the drain electrode can be used interchangeably. Thus, the source electrode can be a drain electrode, and the drain electrode can be a source electrode. In addition, the source electrode in any one embodiment of the present invention can be a drain electrode in another embodiment of the present invention, and the drain electrode in any one embodiment of the present invention can be a source electrode in another embodiment of the present invention.

[0042] In one or more embodiments of the present invention, for ease of description, the source region is separated from the source electrode, and the drain region is separated from the drain electrode. However, embodiments of the present invention are limited to this structure. For example, the source region may be the source electrode, and the drain region may be the drain electrode. Alternatively, the source region may be the drain electrode, and the drain region may be the source electrode.

[0043] Figure 1A FIG. 1 is a plan view of a thin film transistor substrate according to an embodiment of the present invention. Figure 1B FIG. 1 is a plan view of a first gate electrode and a second gate electrode of a thin film transistor substrate according to an embodiment of the present invention.

[0044] First, if Figure 1A As shown in , a thin film transistor substrate according to an embodiment of the present invention may include a first gate electrode 120 , an active layer 140 , a second gate electrode 160 , a source electrode 181 , and a drain electrode 182 .

[0045] The active layer 140 may extend in a first direction X, for example, a horizontal direction. In this case, the first direction X may be defined as a direction toward the source electrode 181 and the drain electrode 182 .

[0046] A first contact hole CH1 may be provided on one side, for example, the left side, of the active layer 140, and a second contact hole CH2 may be provided on the other side, for example, the right side, of the active layer 140. In this case, one side of the active layer 140 may be electrically connected to the source electrode 181 through the first contact hole CH1, and the other side of the active layer 140 may be electrically connected to the drain electrode 182 through the second contact hole CH2.

[0047] Each of the first gate electrode 120 and the second gate electrode 160 may extend in a second direction Y, for example, a longitudinal direction. In this case, the second direction Y may be defined as a direction orthogonal to the first direction X. Alternatively, the longitudinal direction may be referred to as the first direction Y, and the horizontal direction may be referred to as the second direction Y.

[0048] Each of the first gate electrode 120 and the second gate electrode 160 may overlap the active layer 140 , and the first gate electrode 120 and the second gate electrode 160 may at least partially overlap each other.

[0049] The first gate electrode 120 and the second gate electrode 160 may be provided in different shapes. Figure 1B The different shapes of the first gate electrode 120 and the second gate electrode 160 are described in more detail.

[0050] like Figure 1B As shown in FIG, the first gate electrode 120 may include a first portion 121, a plurality of second portions 122a, and a plurality of third portions 122b. In this case, the first portion 121 is a main portion of the first gate electrode 120, and the plurality of second portions 122a and the plurality of third portions 122b correspond to protrusions protruding from the first portion 121 in the first direction X.

[0051] The first portion 121 may extend in the second direction Y and may have a first width W1 in the first direction X. The first width W1 may be defined as a minimum distance from one end (eg, left end) to the other end (eg, right end) of the first portion 121 .

[0052] The plurality of second portions 122 a and the plurality of third portions 122 b may be respectively provided on one side and the other side of the first portion 121. For example, the plurality of second portions 122 a may protrude from one side (e.g., the left side) of the first portion 121 in the first direction X and extend in a direction toward the source electrode 181, and the plurality of third portions 122 b may protrude from the other side (e.g., the right side) of the first portion 121 in the first direction X and extend in a direction toward the drain electrode 182.

[0053] All of the plurality of second portions 122 a may be formed to have the same length in the first direction X and the second direction Y, but are not limited thereto. For example, a portion of the second portions 122 a overlapping with the active layer 140 among the plurality of second portions 122 a may be formed to have the same length in the first direction X and the second direction Y, and another portion of the second portions 122 a not overlapping with the active layer 140 among the plurality of second portions 122 a may be formed to have a different length in the first direction X and the second direction Y than the portion of the second portions 122 a.

[0054] Likewise, all of the plurality of third portions 122 b may be formed to have the same length in the first direction X and the second direction Y. However, the present invention is not limited thereto.

[0055] The plurality of second portions 122a and the plurality of third portions 122b may be symmetrically arranged with respect to the first center line L1 (a virtual line passing through the center of the first portion 121). However, the present invention is not limited thereto, and the plurality of second portions 122a and the plurality of third portions 122b may be arranged to be staggered with respect to the first center line L1.

[0056] The first gate electrode 120 may include a plurality of grooves 123a and 123b, and the plurality of grooves 123a and 123b may be disposed between the plurality of second portions 122a of the first gate electrode 120 and between the plurality of third portions 122b of the first gate electrode 120. Specifically, the plurality of grooves 123a and 123b may include a plurality of first grooves 123a adjacent to the source electrode 181 and a plurality of second grooves 123b adjacent to the drain electrode 182. The plurality of first grooves 123a may be disposed between the plurality of second portions 122a of the first gate electrode 120, and the plurality of second grooves 123b may be disposed between the plurality of third portions 122b of the first gate electrode 120.

[0057] All of the plurality of first grooves 123a may be formed to have the same length in the first direction X and the second direction Y, but are not limited thereto. For example, the plurality of first grooves 123a overlapping the active layer 140 may be formed to have the same length in the first direction X and the second direction Y, and the plurality of first grooves 123a not overlapping the active layer 140 may be formed to have different lengths in the first direction X and the second direction Y.

[0058] Likewise, all of the plurality of second grooves 123 b may be formed to have the same length in the first direction X and the second direction Y. However, the present invention is not limited thereto.

[0059] The first gate electrode 120 may have a second width W2 in the first direction X. The second width W2 may be defined as a minimum distance from one end (e.g., the left end) of the plurality of second portions 122 a to one end (e.g., the right end) of the plurality of third portions 122 b , and the second width W2 may be greater than the first width W1 of the first portion 121 .

[0060] Unlike the first gate electrode 120, the second gate electrode 160 may not include a plurality of grooves or a plurality of protrusions. In this way, the first gate electrode 120 and the second gate electrode 160 may be provided in different shapes. The second gate electrode 160 may overlap the entire first portion 121 along the first direction X and the second direction Y. The second gate electrode 160 may not overlap the plurality of second portions 122a.

[0061] The second gate electrode 160 may extend in the second direction Y and may have a third width W3 in the first direction X. The third width W3 may be defined as a minimum distance from one end (eg, left end) to the other end (eg, right end) of the second gate electrode 160 .

[0062] According to an embodiment of the present invention, the third width W3 of the second gate electrode 160 may be the same as the first width W1 of the first portion 121 of the first gate electrode 120 , and the third width W3 may be smaller than the second width W2 of the first gate electrode 120 .

[0063] According to an embodiment of the present invention, the first gate electrode 120 and the second gate electrode 160 may overlap with each other. In this case, a first center line L1 passing through the center of the first gate electrode 120 and a second center line L2 passing through the center of the second gate electrode 160 may overlap with each other and thus coincide with each other in a plan view of the thin film transistor substrate.

[0064] Since the third width W3 of the second gate electrode 160 is set to be smaller than the second width W2 of the first gate electrode 120 and equal to the first width W1 of the first portion 121, the first gate electrode 120 and the second gate electrode 160 are arranged so that the first center line L1 of the first gate electrode 120 and the second center line L2 of the second gate electrode 160 coincide with each other on the plan view of the thin film transistor substrate, so again as Figure 1A As shown in FIG, one end of the second gate electrode 160 (e.g., the left end of the second gate electrode 160) may overlap with a region disposed between one end (e.g., the left end) of the first portion 121 and one end (e.g., the left end) of the second portion 122a. Similarly, the other end (e.g., the right end) of the second gate electrode 160 may overlap with a region disposed between the other end (e.g., the right end) of the first portion 121 and one end (e.g., the right end) of the third portion 122b.

[0065] Specifically, one end of the second gate electrode 160 may coincide with one end of the first portion 121 in a plan view of the thin film transistor substrate, and the other end of the second gate electrode 160 may coincide with the other end of the first portion 121 in a plan view of the thin film transistor substrate.

[0066] According to an embodiment of the present invention, since a plurality of first grooves 123 a and a plurality of second grooves 123 b are formed on one side and the other side of the first gate electrode 120, respectively, the region where the first gate electrode 120 and the active layer 140 overlap with each other but do not overlap with the second gate electrode 160 can be reduced. By forming a dual-gate structure in this manner, the HJS region, i.e., the high junction stress region, can be minimized or at least reduced in the region where the first gate electrode 120 and the active layer 140 overlap with each other but do not overlap with the second gate electrode 160.

[0067] Conventionally, in the case of a dual-gate structure, the width of the lower gate electrode is formed to be greater than the width of the upper gate electrode. In this case, the electric field applied to the active layer from the lower gate electrode having a relatively large width and the electric field applied to the active layer from the upper gate electrode having a relatively small width are different from each other, so that the electric field applied to the channel portion of the active layer is formed asymmetrically. Note that the asymmetrical formation of the electric field means that the electric field of a relatively narrow area like the upper gate electrode is applied to the upper region of the active layer, and the electric field of a relatively large area like the lower gate electrode is applied to the lower region of the active layer. Thus, a high junction stress region (hereinafter referred to as HJS region) is generated in the region where the channel portion of the active layer is formed. In this case, when the HJS region is generated, the threshold voltage Vth of the thin film transistor changes, and the life of the device is shortened.

[0068] According to one embodiment of the present invention, since multiple first grooves 123a and multiple second grooves 123b are formed on one side and the other side of the first gate electrode 120, respectively, the area of ​​the region where the first gate electrode 120 overlaps with the active layer 140 but does not overlap with the second gate electrode 160 can be reduced. By forming a dual-gate structure in this manner, the electric field generated by the first gate electrode 120 is not applied to the active layer 140 in the region where the multiple first grooves 123a and the multiple second grooves 123b are formed, thereby reducing the phenomenon in which the electric field applied from the first gate electrode 120 to the active layer 140 and the electric field applied from the second gate electrode 160 to the active layer 140 are asymmetrically formed. As a result, the HJS region is relatively reduced, thereby minimizing, suppressing, or reducing the problem in which the characteristics of the device are degraded or the life of the thin film transistor substrate is shortened due to changes in the threshold voltage Vth of the thin film transistor.

[0069] Figure 2A is a cross-sectional view of a thin film transistor substrate according to one embodiment of the present invention. In this case, Figure 2A The cross-section in the figure corresponds to the Figure 1A A cross section taken along line II'.

[0070] like Figure 2A As shown in , a thin film transistor substrate according to an embodiment of the present invention may include a substrate 100, a buffer layer 110, a first gate electrode 120, a first gate insulating layer 130, an active layer 140, a second gate insulating layer 150, a second gate electrode 160, an interlayer insulating layer 170, a source electrode 181 and a drain electrode 182.

[0071] The substrate 100 may be made of glass or plastic. In particular, the substrate 100 may be made of a transparent plastic having flexible properties, such as polyimide. When polyimide is used as the substrate 100, a heat-resistant polyimide that can withstand high temperatures may be used, considering the high-temperature deposition process performed on the substrate 100.

[0072] A buffer layer 110 may be formed on the substrate 100. The buffer layer 110 may protect the active layer 140 by blocking air and moisture. The buffer layer 110 may be formed of an inorganic insulating material such as silicon oxide, silicon nitride, or metal oxide, but is not limited thereto and may be formed of an organic insulating material. The buffer layer 110 may be formed of a single layer or multiple layers, or the buffer layer 110 may be omitted.

[0073] The first gate electrode 120 may be formed on the buffer layer 110. In addition, although not shown, when the buffer layer 110 is omitted, the first gate electrode 120 may be formed on the substrate 100.

[0074] According to an embodiment of the present invention, the first gate electrode 120 may include a first portion 121, a second portion 122a, and a third portion 122b. In this case, the second portion 122a may protrude from one side (e.g., the left side) of the first portion 121 and extend toward the source electrode 181, and the third portion 122b may protrude from the other side (e.g., the right side) of the first portion 121 and extend toward the drain electrode 182.

[0075] The second portion 122 a and the third portion 122 b may be formed symmetrically with respect to the first portion 121 .

[0076] According to one embodiment of the present invention, Figure 2A As shown in the enlarged view in FIG, the first gate electrode 120 may be formed in a stepped shape. Specifically, the first portion 121 may have a first thickness h1 from the buffer layer 110, and the second portion 122a and the third portion 122b may have a second thickness h2 from the buffer layer 110. In this case, the first thickness h1 may be greater than the second thickness h2.

[0077] The first gate electrode 120 may include at least one of an aluminum-based metal such as aluminum (Al) or an aluminum alloy, a silver-based metal such as silver (Ag) or a silver alloy, a copper-based metal such as copper (Cu) or a copper alloy, a molybdenum-based metal such as molybdenum (Mo) or a molybdenum alloy, chromium (Cr), tantalum (Ta), neodymium (Nd), and titanium (Ti). The first gate electrode 120 may have a structure including one metal layer or a multilayer structure including at least two metal layers each having different physical properties.

[0078] The first gate insulating layer 130 may be provided on the first gate electrode 120. Specifically, the first gate insulating layer 130 may be provided on the entire surface of the substrate 100 and may be provided on the first gate electrode 120 and the buffer layer 110. As a result, the first gate electrode 120 may be surrounded by the buffer layer 110 and the first gate insulating layer 130.

[0079] The first gate insulating layer 130 may include a silicon nitride layer (SiNx) or a silicon oxide layer (SiOx), but is not limited thereto. The first gate insulating layer 130 may be formed of a single layer or multiple layers including an inorganic insulating material and / or an organic insulating material.

[0080] The active layer 140 may be disposed on the first gate insulating layer 130 .

[0081] The active layer 140 may include a semiconductor material, for example, an oxide semiconductor material. The oxide semiconductor material may include, for example, at least one of an IZO (InZnO)-based oxide semiconductor material, an IGO (InGaO)-based oxide semiconductor material, an ITO (InSnO)-based oxide semiconductor material, an IGZO (InGaZnO)-based oxide semiconductor material, an IGZTO (InGaZnSnO)-based oxide semiconductor material, a GZTO (GaZnSnO)-based oxide semiconductor material, a GZO (GaZnO)-based oxide semiconductor material, an ITZO (InSnZnO)-based oxide semiconductor material, and a FIZO (FeInZnO)-based oxide semiconductor material.

[0082] The active layer 140 may include a channel portion 141, a first connection portion 142a connected to a first side (e.g., left side) of the channel portion 141, and a second connection portion 142b connected to a second side (e.g., right side) of the channel portion 141 opposite to the first side of the channel portion 141.

[0083] The first and second connection portions 142 a and 142 b may have conductive properties by performing a conductive process of ion doping or plasma treatment on a semiconductor material using the second gate electrode 160 as a mask.

[0084] The conductive process can be defined as a process for imparting conductive properties to the oxide semiconductor material. The oxide semiconductor material subjected to the conductive process may have conductive properties. The conductive process may include, for example, a doping process using dopant ions and a plasma process applying plasma to make it conductive. Through the conductive process, a portion of the active layer 140, for example, the first connecting portion 142a and the second connecting portion 142b, may be conductive, thereby having conductive properties. Therefore, the first connecting portion 142a and the second connecting portion 142b may have better conductivity than the channel portion 141, and each of them may be used as a wiring or source / drain electrode.

[0085] The channel portion 141 may overlap the first portion 121 of the first gate electrode 120 , the first connection portion 142 a may overlap the second portion 122 a of the first gate electrode 120 , and the second connection portion 142 b may overlap the third portion 122 b of the first gate electrode 120 .

[0086] One end (e.g., the left end) of the channel portion 141 may coincide with one end (e.g., the left end) of the first portion 121 in a plan view of the thin film transistor substrate, and the other end (e.g., the right end) of the channel portion 141 may coincide with the other end (e.g., the right end) of the first portion 121 in a plan view of the thin film transistor substrate. However, the present invention is not limited thereto. As described later, Figure 5A As shown in FIG, the channel portion 141 may also overlap with the first portion 121, the second portion 122a, and the third portion 122b.

[0087] The first connection portion 142a and the second connection portion 142b may overlap with the second portion 122a and the third portion 122b, respectively.

[0088] According to an embodiment of the present invention, the active layer 140 may be provided in a stepped shape according to the steps formed in the first portion 121, the second portion 122a, and the third portion 122b of the first gate electrode 120. Each of the first connection portion 142a and the second connection portion 142b may have a stepped form.

[0089] Therefore, the distance between the active layer 140 and the first portion 121 along the third direction Z and the distance between the active layer 140 and the second portion 122 a or the third portion 122 b along the third direction Z may be the same. In this case, each distance may be defined as the shortest distance between the active layer 140 and the first gate electrode 120 .

[0090] The second gate insulating layer 150 may be formed on the active layer 140. Specifically, the second gate insulating layer 150 may be provided on the entire surface of the substrate 100 and may be provided on the active layer 140 and the first gate insulating layer 130. As a result, the active layer 140 may be surrounded by the first gate insulating layer 130 and the second gate insulating layer 150.

[0091] The second gate insulating layer 150 may include a silicon nitride layer (SiNx) or a silicon oxide layer (SiOx), but is not limited thereto. The second gate insulating layer 150 may be formed of a single layer or multiple layers including an inorganic insulating material and / or an organic insulating material. In addition, although not shown, the second gate insulating layer 150 is not limited to being provided on the entire surface of the substrate 100, but may be formed in correspondence with one end and the other end of the second gate electrode 160. In this case, the active layer 140 may not be formed to be surrounded by the first gate insulating layer 130 and the second gate insulating layer 150.

[0092] The second gate electrode 160 may be formed on the second gate insulating layer 150 .

[0093] One end (e.g., the left end) of the second gate electrode 160 may coincide with one end (e.g., the left end) of the first portion 121 of the first gate electrode 120 in a plan view of the thin film transistor substrate, and the other end (e.g., the right end) of the second gate electrode 160 may coincide with the other end (e.g., the right end) of the first portion 121 of the first gate electrode 120 in a plan view of the thin film transistor substrate.

[0094] The second gate electrode 160 may include at least one of an aluminum-based metal such as aluminum (Al) or an aluminum alloy, a silver-based metal such as silver (Ag) or a silver alloy, a copper-based metal such as copper (Cu) or a copper alloy, a molybdenum-based metal such as molybdenum (Mo) or a molybdenum alloy, chromium (Cr), tantalum (Ta), neodymium (Nd), and titanium (Ti). The second gate electrode 160 may have a structure including one metal layer or a multilayer structure including at least two metal layers each having different physical properties.

[0095] The interlayer insulating layer 170 may insulate the second gate electrode 160 from the source electrode 181 and also from the drain electrode 182. The interlayer insulating layer 170 may be formed of a single layer or multiple layers including an inorganic insulating material and / or an organic insulating material.

[0096] A first contact hole CH1 and a second contact hole CH2 may be provided in the interlayer insulating layer 170. Thus, a portion of the upper surface of the first connection portion 142a of the active layer 140 may be exposed through the first contact hole CH1, and further, a portion of the upper surface of the second connection portion 142b of the active layer 140 may be exposed through the second contact hole CH2. The first connection portion 142a of the active layer 140 may extend in the first direction X toward the source electrode 181, and the second connection portion 142b of the active layer 140 may extend in the first direction X toward the drain electrode 182.

[0097] The channel portion 141 of the active layer 140 may overlap the first portion 121. The first connection portion 142a may overlap a portion of the second portions 122a. The second connection portion 142b may overlap a portion of the third portions 122b.

[0098] The source electrode 181 and the drain electrode 182 may be disposed on the interlayer insulating layer 170 .

[0099] The source electrode 181 may be electrically connected to the first connection portion 142 a of the active layer 140 through the first contact hole CH1 , and the drain electrode 182 may be electrically connected to the second connection portion 142 b of the active layer 140 through the second contact hole CH2 .

[0100] The source electrode 181 and the drain electrode 182 may be formed of the same material as the second gate electrode 160 , but are not limited thereto and may be formed of a material based on knowledge in the art.

[0101] Figure 2B is a cross-sectional view of a thin film transistor substrate according to one embodiment of the present invention. In this case, Figure 2B The cross-section in the figure corresponds to the Figure 1A The cross section is taken along line II-II'. Figure 2B The implementation method in Figure 2A The embodiment is the same as in the embodiment, and the difference lies in the structure of the first gate electrode, so the different structures will be mainly described below.

[0102] like Figure 2B As shown in FIG, the first gate electrode 120 may include only the first portion 121 without including the second portion and the third portion (see FIG. Figure 2A 122a and 122b in FIG. 122b). Figure 1A A plurality of first grooves and a plurality of second grooves are formed on one side and the other side of the first portion 121, respectively (see Figure 1A 123a and 123b in FIG), and thus only the first portion 121 may be formed on the buffer layer 110 without separate second and third portions (see FIG. Figure 2A 122a and 122b in FIG.

[0103] According to an embodiment of the present invention, since the first gate electrode 120 includes only the first portion 121, the electric field applied from the first gate electrode 120 to the active layer 140 and the electric field applied from the second gate electrode 160 to the active layer 140 can be formed symmetrically. Therefore, the HJS region is not generated or can be minimized or at least reduced. As a result, the degree of variation in the threshold voltage Vth of the thin film transistor according to the embodiment can be reduced, and the problem of shortened device life can be solved or at least alleviated.

[0104] Figure 2C is a cross-sectional view of a thin film transistor substrate according to one embodiment of the present invention. In this case, Figure 2C The cross-section in the figure corresponds to the Figure 1A The cross section is taken along line III-III'. Figure 2C In the embodiment, the substrate, the buffer layer, the first gate insulating layer, the second gate insulating layer, the interlayer insulating layer, the source electrode and the drain electrode are connected to the Figure 2AThe embodiments are the same as those described in the embodiment, so different configurations will be mainly described below.

[0105] like Figure 2C As shown in , a plurality of second portions 122a may be spaced apart from each other by a predetermined interval and disposed on the buffer layer 110. A plurality of first grooves 123a are disposed between the plurality of second portions 122a. Every two adjacent second portions of the plurality of second portions 122a may be separated by each groove of the plurality of first grooves 123a. As described above, the active layer 140 and the first gate electrode 120 may not overlap in the region where the plurality of first grooves 123a are formed.

[0106] According to an embodiment of the present invention, since the first gate electrode 120 and the active layer 140 do not overlap in the region where the plurality of first grooves 123a are formed, the first gate electrode 120 and the active layer 140 overlap each other but do not overlap with the second gate electrode 160 (see FIG. Figure 1A ), the extent of application of the electric field from the first gate electrode 120 to the active layer 140 is minimized or at least reduced, and thus the HJS region of the thin film transistor substrate according to an embodiment of the present invention can be minimized or at least reduced. Therefore, the problem that the threshold voltage Vth of the thin film transistor according to an embodiment of the present invention fluctuates and the life of the device is shortened can be suppressed, prevented or reduced.

[0107] Figure 3A is a cross-sectional view of a thin film transistor substrate according to another embodiment of the present invention. In this case, Figure 3A The cross-section in the figure corresponds to the Figure 1A The cross section is taken along line II' in FIG. Figure 3A The implementation method in Figure 2A The embodiment is the same as in the embodiment, and the difference lies in the structure of the first gate insulating layer and the active layer, so the different structures will be mainly described below.

[0108] like Figure 3A As shown in , the first gate insulating layer 130 may not be formed to have the same thickness (or height), but may have different thicknesses. Figure 3A As shown in the enlarged view in FIG, a portion of the first gate insulating layer 130 overlapping the first portion 121 of the first gate electrode 120 may have a third thickness h3, and another portion of the first gate insulating layer 130 overlapping the second portion 122a of the first gate electrode 120 may have a fourth thickness h4. In this case, the difference between the fourth thickness h4 and the third thickness h3 may be the same as the first portion (see FIG. Figure 2AThe difference between the first thickness h1 of the first gate insulating layer 130 and the second thickness h2 of the second portion 122a is the same. Furthermore, the relationship between the first gate insulating layer 130 and the third portion 122b is the same as the relationship between the first gate insulating layer 130 and the second portion 122a, and a repeated description will be omitted. The thickness (or height) is defined along a third direction Z that is orthogonal to the longitudinal and horizontal directions.

[0109] According to another embodiment of the present invention, the upper surface of the first gate insulating layer 130 may be flat by forming a portion of the first gate insulating layer 130 overlapping the first portion 121 and another portion overlapping the second portion 122a or the third portion 122b to different thicknesses.

[0110] The active layer 140 may be disposed on the first gate insulating layer 130. In this case, since the upper surface of the first gate insulating layer 130 is flat, the active layer 140 may be disposed on the first gate insulating layer 130 without a separate step.

[0111] According to another embodiment of the present invention, since the active layer 140 is not provided with a separate step, the distance between the active layer 140 and the first portion 121 of the first gate electrode 120 along the third direction Z and the distance between the active layer 140 and the second portion 122a or the third portion 122b of the first gate electrode 120 along the third direction Z may be different from each other.

[0112] More specifically, if Figure 3A As shown in the enlarged view of FIG, the distance between the active layer 140 and the first portion 121 of the first gate electrode 120 may be a third thickness h3, and the distance between the active layer 140 and the second portion 122a or the third portion 122b of the first gate electrode 120 may be a fourth thickness h4. As a result, the distance between the second portion 122a or the third portion 122b and the active layer 140 increases, and thus the intensity of the electric field applied from the second portion 122a or the third portion 122b to the active layer 140 can be relatively reduced.

[0113] As a result, since the intensity of the electric field applied from the second portion 122a or the third portion 122b to the active layer 140 can be reduced, the problem in which the electric field applied from the first gate electrode 120 and the second gate electrode 160 to the active layer 140 is asymmetrically formed can be eliminated, minimized, or reduced. Therefore, since HJS is reduced, the degree of fluctuation of the threshold voltage Vth of the thin film transistor according to another embodiment of the present invention can be reduced, and the problem in which the life of the thin film transistor substrate according to another embodiment of the present invention is shortened can be further eliminated, minimized, or reduced.

[0114] Figure 3Bis a cross-sectional view of a thin film transistor substrate according to another embodiment of the present invention. In this case, Figure 3B The cross-section in the figure corresponds to the Figure 1A The cross section is taken along line II-II'. Figure 3B The implementation method in Figure 2B The embodiment is the same as in the embodiment, and the difference lies in the structure of the first gate insulating layer and the active layer, so the different structures will be mainly described below.

[0115] like Figure 3B As shown in , the first gate insulating layer 130 may not be formed to have the same thickness (or height), but may be formed to have different thicknesses. Therefore, the thickness of the portion of the first gate insulating layer 130 overlapping with the first portion 121 and the thickness of another portion of the first gate insulating layer 130 not overlapping with the first portion 121 may be different from each other. In this case, the thickness of the portion of the first gate insulating layer 130 overlapping with the first portion 121 may be relatively smaller than the thickness of another portion of the first gate insulating layer 130 not overlapping with the first portion 121.

[0116] According to another embodiment of the present invention, by forming a portion of the first gate insulating layer 130 overlapping the first portion 121 and another portion not overlapping the first portion 121 to have different thicknesses, the upper surface of the first gate insulating layer 130 may be flat.

[0117] The active layer 140 may be disposed on the first gate insulating layer 130. In this case, since the upper surface of the first gate insulating layer 130 is flat, the active layer 140 may be disposed on the first gate insulating layer 130 without a separate step.

[0118] Figure 4 is a plan view of a thin film transistor substrate according to another embodiment of the present invention. Figure 4 The implementation method in Figure 1A The embodiment is the same as in the embodiment, and the difference lies in the structure of the first gate electrode and the second gate electrode, so the different structure will be mainly described below.

[0119] like Figure 4 As shown in FIG, the first gate electrode 120 and the second gate electrode 160 may overlap each other. In this case, the first width of the first portion 121 of the first gate electrode 120 (see FIG. Figure 1B W1 in FIG. 1 may be smaller than the third width of the second gate electrode 160 (see FIG. Figure 1B W3 in ).

[0120] By forming a dual-gate structure in this manner, the plurality of second portions 122 a and the plurality of third portions 122 b of the first gate electrode 120 can overlap with the second gate electrode 160. Furthermore, by overlapping the plurality of second portions 122 a and the plurality of third portions 122 b with the second gate electrode 160, the plurality of first recesses 123 a and the plurality of second recesses 123 b can also overlap with the second gate electrode 160.

[0121] Specifically, one end (e.g., the left end) of the second gate electrode 160 may overlap with a region from one end (e.g., the left end) of the first portion 121 to one end (e.g., the left end) of the plurality of second portions 122a, and similarly, the other end (e.g., the right end) of the second gate electrode 160 may overlap with a region from the other end (e.g., the right end) of the first portion 121 to one end (e.g., the right end) of the plurality of third portions 122b.

[0122] According to another embodiment of the present invention, since the second gate electrode 160 overlaps with the plurality of second portions 122a, the plurality of third portions 122b, the plurality of first grooves 123a, and the plurality of second grooves 123b, the HJS region can be reduced. At the same time, even if the first center line of the first gate electrode 120 (see FIG. Figure 1B L1 in FIG) and the second center line of the second gate electrode 160 (see FIG). Figure 1B L2) in the thin film transistor substrate according to another embodiment of the present invention does not overlap in the plan view of the thin film transistor substrate due to process errors when manufacturing the thin film transistor substrate, which can also reduce the HJS area. In addition, in this regard, reference will be made to Figure 8 Describe in more detail.

[0123] Figure 5A is a cross-sectional view of a thin film transistor substrate according to another embodiment of the present invention. In this case, Figure 5A The cross-section in the figure corresponds to the Figure 4 The cross section is taken along line IV-IV'. Figure 5A The implementation method in Figure 3A The embodiment is the same as in the embodiment, and the difference lies in the structure of the first gate electrode, so the different structures will be mainly described below.

[0124] like Figure 5A As shown in , the first gate electrode 120 may include a first portion 121 , a second portion 122 a , and a third portion 122 b .

[0125] The width of the first portion 121 in the first direction X (see Figure 1B W1 in the figure may be smaller than the width of the second gate electrode 160 in the first direction X (see Figure 1BTherefore, one end (eg, the left end) of the first portion 121 may be disposed relatively closer to the center of the first gate electrode 120 than one end (eg, the left end) of the second gate electrode 160 .

[0126] The second portion 122 a may overlap the channel portion 141 and the first connection portion 142 a , and the third portion 122 b may overlap the channel portion 141 and the second connection portion 142 b .

[0127] The channel portion 141 of the active layer 140 may overlap with the first portion 121, the second portion 122a, and the third portion 122b. Specifically, one end of the channel portion 141 may be disposed in a region extending from the boundary between the first portion 121 and the second portion 122a to one end (e.g., the left end) of the second portion 122a. The other end of the channel portion 141 may be disposed in a region extending from the boundary between the first portion 121 and the third portion 122b to one end (e.g., the right end) of the third portion 122b.

[0128] By being formed in this manner, one end of the channel portion 141 may overlap with the second portion 122 a , and the other end of the channel portion 141 may overlap with the third portion 122 b .

[0129] The second gate electrode 160 may overlap the first gate electrode 120. Specifically, the second gate electrode 160 may overlap the first portion 121, the second portion 122a, and the third portion 122b.

[0130] One end (e.g., the left end) of the second gate electrode 160 may be disposed in a region extending from the boundary between the first portion 121 and the second portion 122a to one end (e.g., the left end) of the second portion 122a. The other end (e.g., the right end) of the second gate electrode 160 may be disposed in a region extending from the boundary between the first portion 121 and the third portion 122b to one end (e.g., the right end) of the third portion 122b.

[0131] By being formed in this manner, one end of the second gate electrode 160 may overlap with the second portion 122 a , and the other end of the second gate electrode 160 may overlap with the third portion 122 b .

[0132] According to another embodiment of the present invention, one end of the second gate electrode 160 overlaps the second portion 122a, and the other end of the second gate electrode 160 overlaps the third portion 122b, so that even if the first center line of the first gate electrode 120 (see FIG. Figure 1B L1 in FIG) and the second center line of the second gate electrode 160 (see FIG). Figure 1B L2) in the thin film transistor substrate is relatively non-overlapping on the plane view, and the effect of reducing the HJS area can also be maintained. Figure 8 Describe in more detail.

[0133] Figure 5B is a cross-sectional view of a thin film transistor substrate according to another embodiment of the present invention. In this case, Figure 5B The cross-section in the figure corresponds to the Figure 4 The cross section is taken along the line V-V' in FIG. Figure 5B The implementation method in Figure 3B The embodiment is the same as in the embodiment, and the difference lies in the structure of the first part of the first gate electrode, so the different structure will be mainly described below.

[0134] like Figure 5B As shown in , the first portion 121 of the first gate electrode 120 may overlap the channel portion 141 of the active layer 140 and the second gate electrode 160 , and the first portion 121 may be formed to have a width smaller than that of the channel portion 141 and the second gate electrode 160 in the first direction X.

[0135] One end and the other end of the first portion 121 do not correspond to one end and the other end of the channel portion 141 , respectively, and may not correspond to one end and the other end of the second gate electrode 160 .

[0136] In addition, refer to Figure 5B and Figure 4 , the channel portion 141 of the active layer 140 may overlap with at least a portion of the second portions among the multiple second portions 122a and at least a portion of the first grooves among the multiple first grooves 123a. Similarly, the channel portion 141 of the active layer 140 may overlap with at least a portion of the third portions among the multiple third portions 122b and at least a portion of the second grooves among the multiple second grooves 123b.

[0137] Figure 6 is a plan view of a thin film transistor substrate according to another embodiment of the present invention. Figure 6 The implementation method in Figure 4 The embodiment is the same as in the embodiment, and the difference lies in the structure of the first gate electrode, so the different structures will be mainly described below.

[0138] like Figure 6 As shown in FIG, the plurality of second portions 122a of the first gate electrode 120 may include a first region 122a1 and a second region 122a2, and the plurality of third portions 122b of the first gate electrode 120 may include a third region 122b1 and a fourth region 122b2.

[0139] The first region 122a1 may be defined as a portion protruding in the first direction X while contacting one end (e.g., the left end) of the first portion 121 , and the second region 122a2 may be defined as a portion protruding from one end of the first region 122a1 in the first direction X and extending toward the source electrode 181 .

[0140] Similarly, the third region 122b1 can be defined as a portion protruding in the first direction X while contacting the other end (e.g., the right end) of the first portion 121, and the fourth region 122b2 can be defined as a portion protruding from one end of the third region 122b1 in the first direction X and extending toward the drain electrode 182.

[0141] According to another embodiment of the present invention, the first region 122 a 1 and the third region 122 b 1 may overlap with the second gate electrode 160 , and the second region 122 a 2 and the fourth region 122 b 2 may not overlap with the second gate electrode 160 .

[0142] In addition, the thickness of the first region 122a1 and the third region 122b1 and the thickness of the second region 122a2 and the fourth region 122b2 may be different from each other, which will be referred to in detail. Figure 7A Describe in more detail.

[0143] Figure 7A is a cross-sectional view of a thin film transistor substrate according to another embodiment of the present invention. In this case, Figure 7A The cross-section in the figure corresponds to the Figure 6 The cross section is taken along line VI-VI'. Figure 7A The implementation method in Figure 5A The embodiment is the same as in the embodiment, and the difference lies in the configuration of the second portion and the third portion of the first gate electrode, so the different configurations will be mainly described below.

[0144] like Figure 7A As shown in FIG, the second portion 122 a and the third portion 122 b of the first gate electrode 120 may respectively include different regions having different thicknesses.

[0145] Specifically, the second portion 122a may include a first region 122a1 disposed on one side (eg, left side) of the first portion 121, and a second region 122a2 disposed on one side (eg, left side) of the first region 122a1. In addition, the first region 122a1 has a thickness (see FIG. 2 ) of the first portion 121. Figure 2A The second region 122a2 may have the same first thickness as h1 in the first region 122a1, and the second thickness h2 may be different from the first thickness h1 of the first region 122a1. In this case, the first thickness h1 of the first region 122a1 may be greater than the second thickness h2 of the second region 122a2.

[0146] Likewise, the third portion 122b may include a third region 122b1 disposed on the other side (e.g., right side) of the first portion 121, and a fourth region 122b2 disposed on one side (e.g., right side) of the third region 122b1. In addition, the third region 122b1 has a thickness (see FIG. 1 ) that is substantially the same as that of the first portion 121. Figure 2A The fourth region 122b2 may have the same first thickness as h1 in the third region 122b1, and the second thickness h2 may be different from the first thickness h1 of the third region 122b1. In this case, the first thickness h1 of the third region 122b1 may be greater than the second thickness h2 of the fourth region 122b2.

[0147] The first region 122a1 and the third region 122b1 may correspond to one end (eg, left end) and the other end (eg, right end) of the channel portion, respectively, and may also correspond to one end and the other end of the second gate electrode 160, respectively.

[0148] According to another embodiment of the present invention, by forming the first region 122a1 and the third region 122b1 having the same first thickness h1 as the first portion 121, a phenomenon in which an electric field formed from the first portion 121, the first region 122a1, and the third region 122b1 of the first gate electrode 120 and applied to the active layer 140 and an electric field formed from the second gate electrode 160 and applied to the active layer 140 are asymmetrically formed can be minimized, eliminated, or reduced. Thus, when the thin film transistor substrate according to another embodiment of the present invention is turned on, an HJS region can be removed, minimized, or reduced, and the problem of shortened life of the thin film transistor substrate can be eliminated, minimized, or reduced.

[0149] Figure 7B is a cross-sectional view of a thin film transistor substrate according to another embodiment of the present invention. In this case, Figure 7B The cross-section in the figure corresponds to the Figure 6 The cross section is taken along line VII-VII'. Figure 7B The implementation method in Figure 5B The embodiment is the same as in the embodiment, and the difference lies in the configuration of the second portion and the third portion of the first gate electrode, so the different configurations will be mainly described below.

[0150] like Figure 7B As shown in FIG, the first portion 121 of the first gate electrode 120 may overlap the channel portion 141 of the active layer 140 and the second gate electrode 160 and may be formed to have a width smaller than that of the channel portion 141 and the second gate electrode 160 in the first direction X.

[0151] One end and the other end of the first portion 121 may not correspond to one end and the other end of the channel portion 141 , respectively, and may not correspond to one end and the other end of the second gate electrode 160 .

[0152] Figure 8 is a plan view of a thin film transistor substrate according to another embodiment of the present invention. Figure 8 The implementation method in Figure 1A The embodiment is the same as in the embodiment, and the difference lies in the form in which the first gate electrode and the second gate electrode overlap each other, so the different configurations will be mainly described below.

[0153] like Figure 8 As shown in , the first gate electrode 120 and the second gate electrode 160 may overlap each other. In this case, the first gate electrode 120 and the second gate electrode 160 may be arranged to be partially offset from each other. Specifically, a first center line L1 passing through the center of the first gate electrode 120 and a second center line L2 passing through the center of the second gate electrode 160 may not coincide with each other in a plan view of the thin film transistor substrate and may be formed to be spaced apart from each other in the first direction X.

[0154] Specifically, the first center line L1 may be spaced apart from the second center line L2 in the first direction X and close to the drain electrode 182 . However, the present invention is not limited thereto, and the first center line L1 may be spaced apart from the second center line L2 in the first direction X and close to the source electrode 181 .

[0155] By forming a dual-gate structure in this manner, the distance between one end (e.g., the left end) of the first portion 121 of the first gate electrode 120 and one end (e.g., the left end) of the second gate electrode 160 can be greater than the distance between the other end (e.g., the right end) of the first portion 121 of the first gate electrode 120 and the other end (e.g., the right end) of the second gate electrode 160.

[0156] In addition, although not shown, the first gate electrode 120 may be further moved in the direction of the drain electrode 182 so that the first center line L1 may be moved in the direction of the drain electrode 182. In this case, the other end (e.g., the right end) of the first portion 121 may coincide with the other end of the second gate electrode 160.

[0157] Figure 9 is a plan view of a thin film transistor substrate according to another embodiment of the present invention. Figure 9 The implementation method in Figure 1A The embodiment is the same as in, except that multiple third parts and multiple second grooves are not provided, so the different configurations will be mainly described below.

[0158] like Figure 9, the first gate electrode 120 may include a first portion 121 and a plurality of second portions 122 disposed on one side of the first portion 121. In this case, one side of the first gate electrode 120 (e.g., the left side of the first gate electrode 120) and the other side of the first gate electrode 120 (e.g., the right side of the first gate electrode 120) may be asymmetrically formed about a straight line passing through the center of the first gate electrode 120 in the second direction Y.

[0159] A plurality of second portions 122 may be provided on one side of the first gate electrode 120, and a plurality of grooves 123 may be provided between the plurality of second portions 122. The second gate electrode 160 may overlap a portion of the first portion 121 and a portion of each of the plurality of second portions 122 along the first direction X. The second gate electrode 160 may overlap a portion of each of a portion of the second portions in the plurality of second portions 122.

[0160] According to another embodiment of the present invention, since a plurality of grooves 123 are formed on one side of the first gate electrode 120, the area of ​​the region where the first gate electrode 120 and the active layer 140 overlap with each other but do not overlap with the second gate electrode 160 can be reduced. By forming a dual-gate structure in this manner, the HJS region can be minimized or at least reduced in the region where the first gate electrode 120 and the active layer 140 overlap with each other but do not overlap with the second gate electrode 160.

[0161] Figure 10 FIG. 1 is a cross-sectional view of a display device including a thin film transistor substrate according to an embodiment of the present invention.

[0162] like Figure 10 As shown in , a display device according to an embodiment of the present invention may include a substrate 100, a buffer layer 110, a first gate electrode 120, a first gate insulating layer 130, an active layer 140, a second gate insulating layer 150, a second gate electrode 160, an interlayer insulating layer 170, a source electrode 181, a drain electrode 182, a planarization layer 190, a first electrode 200, a bank layer 210, a light emitting layer 220, and a second electrode 230. In one or more embodiments, the first electrode 200, the bank layer 210, the light emitting layer 220, and the second electrode 230 form a light emitting element.

[0163] The substrate 100, the buffer layer 110, the first gate electrode 120, the first gate insulating layer 130, the active layer 140, the second gate insulating layer 150, the second gate electrode 160, the interlayer insulating layer 170, the source electrode 181 and the drain electrode 182 are the same as those described above, and thus repeated description thereof will be omitted.

[0164] A planarization layer 190 may be disposed on the source electrode 181 and the drain electrode 182 .

[0165] The third contact hole CH3 may be provided in the planarization layer 190 so that the drain electrode 182 may be exposed through the third contact hole CH3. However, in some cases, the source electrode 181 may be exposed through the third contact hole CH3.

[0166] The first electrode 200 may be formed on the planarization layer 190 and may be connected to the source electrode 181 or the drain electrode 182 through the third contact hole CH3. The first electrode 200 may function as an anode.

[0167] The bank layer 210 may be provided to cover the edge of the first electrode 200 to define a light emitting region. Therefore, the upper surface region of the first electrode 200 that is not covered by the bank layer 210 and is exposed may become the light emitting region.

[0168] The light-emitting layer 220 may be disposed on the first electrode 200. The light-emitting layer 220 may include a red light-emitting layer, a green light-emitting layer, and a blue light-emitting layer patterned for each pixel, or may be formed of a white light-emitting layer connected together for all sub-pixels. When the light-emitting layer 220 is formed of a white light-emitting layer, the light-emitting layer 220 may include, for example, a first stack including a blue light-emitting layer, a second stack including a yellow-green light-emitting layer, and a charge generation layer disposed between the first and second stacks, but is not limited thereto.

[0169] The second electrode 230 may be disposed on the light emitting layer 220. The second electrode 230 may function as a cathode.

[0170] Although not shown, an encapsulation layer for preventing moisture or oxygen from penetrating may be additionally formed on the second electrode 230 .

[0171] Figure 11 is a schematic diagram of a display device according to an embodiment of the present invention.

[0172] like Figure 11 As shown in , a display device according to an embodiment of the present invention may include a display panel 410 , a gate driver 420 , a data driver 430 , and a controller 440 .

[0173] The display panel 410 includes gate lines GL and data lines DL, and pixels SP are provided at respective intersections of the gate lines GL and the data lines DL. An image is displayed by driving the pixels P. The gate lines GL, the data lines DL, and the pixels P may be provided on a substrate 100 .

[0174] The controller 440 controls the gate driver 420 and the data driver 430. The controller 440 outputs a gate control signal GCS for controlling the gate driver 420 and a data control signal DCS for controlling the data driver 430 by using a signal provided from an external system (not shown). In addition, the controller 440 samples input video data input from the external system, rearranges the sampled input video data, and provides the rearranged digital video data RGB to the data driver 430.

[0175] The gate control signal GCS includes a gate start pulse (GSP), a gate shift clock (GSC), a gate output enable signal (GOE), a start signal (Vst), and a gate clock (GCLK).

[0176] The data control signal DCS includes a source start pulse (SSP), a source shift clock signal (SSC), a source output enable signal (SOE), and a polarity control signal (POL).

[0177] The data driver 430 supplies data voltages to the data lines DL of the display panel 410. Specifically, the data driver 430 converts the video data RGB input from the controller 440 into analog data voltages and supplies the data voltages to the data lines DL.

[0178] The gate driver 420 may be mounted on the display panel 410. As described above, the structure in which the gate driver 420 is directly mounted on the display panel 410 is referred to as a gate-in-panel (GIP) structure. Specifically, in the GIP structure, the gate driver 420 may be provided on the substrate 100.

[0179] The gate driver 420 may include a shift register 450 .

[0180] The shift register 450 sequentially supplies gate pulses to the gate lines GL during one frame using a start signal and a gate clock transmitted from the controller 440. Herein, one frame refers to a period during which one image is output through the display panel 410. The gate pulses have a turn-on voltage capable of turning on a switching device (thin film transistor) provided in a pixel P.

[0181] In addition, during the remaining period of a frame when no gate pulse is supplied, the shift register 450 supplies a gate-off signal to the gate line GL to turn off the switching device. Hereinafter, the gate pulse and the gate-off signal are collectively referred to as a scan signal GS.

[0182] Figure 12 is a circuit diagram of a pixel included in a display device according to an embodiment of the present invention.

[0183] like Figure 12As shown in , a pixel P of a display device according to an embodiment of the present invention includes a first thin film transistor T1 , a second thin film transistor T2 , and a capacitor Cst.

[0184] The first thin film transistor T1 is a driving thin film transistor, and the second thin film transistor T2 is a switching thin film transistor. At least one of the first thin film transistor T1 and the second thin film transistor T2 can be formed by the various thin film transistors described above.

[0185] The first thin film transistor T1 is switched according to the data voltage Vdata supplied from the second thin film transistor T2 , generates a data current according to the driving voltage VDD supplied from the power line PL, and supplies the data current to the organic light emitting diode OLED.

[0186] The second thin film transistor T2 is switched according to the scan signal GS supplied to the gate line GL and supplies the data voltage Vdata supplied from the data line DL to the first thin film transistor T1 .

[0187] According to an embodiment of the present invention, the above Figures 1A to 9 The thin film transistor of the embodiment may be used as at least one of the first thin film transistor T1 and the second thin film transistor T2.

[0188] The capacitor Cst serves to maintain a data voltage supplied to the first thin film transistor T1 for one frame, and is provided between a gate electrode and a source electrode of the first thin film transistor T1.

[0189] The organic light emitting diode OLED emits predetermined light according to the data current supplied from the first thin film transistor T1.

[0190] Therefore, the present invention can have the following advantages.

[0191] According to embodiments of the present invention, the first gate electrode is provided with multiple recesses. This reduces the area of ​​the region where the first gate electrode overlaps the active layer but not the second gate electrode, thereby partially eliminating the HJS region. Consequently, even when the thin film transistor substrate according to embodiments of the present invention is turned on, the degree of fluctuation in the threshold voltage Vth is reduced, and the problem of shortened lifespan of the thin film transistor substrate can be resolved or at least mitigated.

[0192] According to an embodiment of the present invention, the first gate insulating layer disposed on the first gate electrode has different thicknesses, allowing the upper surface of the first gate insulating layer to be flat. Furthermore, the active layer is disposed on the flat first gate insulating layer, allowing the distance between the first portion of the first gate electrode and the active layer to be shorter than the distance between the multiple second portions of the first gate electrode and the active layer. In this case, by increasing the distance between the multiple second portions and the active layer, the intensity of the electric field applied to the active layer by the multiple second portions on the active layer is reduced, thereby reducing the phenomenon in which the electric field applied from the first gate electrode and the second gate electrode is asymmetrically formed, thereby minimizing or at least reducing the HJS region. Therefore, even when the thin film transistor substrate according to an embodiment of the present invention is turned on, the degree of fluctuation in the threshold voltage Vth can be reduced, and the problem of shortened lifespan of the thin film transistor substrate can be solved or at least alleviated.

[0193] According to an embodiment of the present invention, at least a portion of the multiple grooves provided in the first gate electrode overlap with the second gate electrode, thereby reducing the phenomenon of asymmetric formation of the electric field applied from the first gate electrode and the second gate electrode to the active layer even if the center line of the first gate electrode and the center line of the second gate electrode are partially offset due to actual process errors.

[0194] According to an embodiment of the present invention, the plurality of second portions of the first gate electrode include first and second regions having different thicknesses, and the first regions and first portions of the plurality of second portions are configured to have the same thickness. This reduces the asymmetry of the electric fields applied to the active layer from the first and second gate electrodes. Therefore, even when the thin film transistor substrate according to an embodiment of the present invention is turned on, the degree of fluctuation in the threshold voltage Vth can be reduced, and the problem of shortened lifespan of the thin film transistor substrate can be resolved or at least alleviated.

[0195] It is obvious to those skilled in the art that various substitutions, modifications and variations are possible within the scope of the present invention without departing from the spirit and scope of the present invention. Therefore, the scope of the present invention is indicated by the following claims, and all changes or modifications derived from the meaning, scope and equivalents of the claims should be interpreted as included within the scope of the present invention.

Claims

1. A thin film transistor substrate, comprising: substrate; a first gate electrode on the substrate, the first gate electrode comprising a first portion and a second portion; an active layer on the first gate electrode; a second gate electrode on the active layer, the second gate electrode at least overlapping the first portion of the first gate electrode; a source electrode connected to the first side of the active layer; and a drain electrode connected to the second side of the active layer, The second portion protrudes from one end of the first portion in a first direction toward one of the source electrode and the drain electrode, and a thickness of the second portion is smaller than a thickness of the first portion. 2 . The thin film transistor substrate of claim 1 , wherein one end of the second gate electrode overlaps with a region extending from a boundary between the first portion and the second portion to one end of the second portion. 3 . The thin film transistor substrate according to claim 1 , wherein a distance between the first portion and the active layer is smaller than a distance between the second portion and the active layer.

4. The thin film transistor substrate according to claim 3, further comprising: a first gate insulating layer between the first gate electrode and the active layer, A first thickness of a first portion of the first gate insulating layer overlapping the first portion is smaller than a second thickness of a second portion of the first gate insulating layer overlapping the second portion.

5. The thin film transistor substrate according to claim 1, wherein the first gate electrode further includes a third portion, the third portion protruding from the other end of the first portion in a second direction toward the other of the source electrode and the drain electrode, the second direction being opposite to the first direction, and The thickness of the third portion is smaller than the thickness of the first portion.

6. The thin film transistor substrate according to claim 1, wherein the active layer comprises: Channel Department; a first connection portion on a first side of the channel portion; and a second connection portion on a second side of the channel portion opposite to the first side of the channel portion, The channel portion overlaps with the first portion of the first gate electrode, and one end of the channel portion overlaps with a region extending from a boundary between the first portion and the second portion to one end of the second portion. 7 . The thin film transistor substrate of claim 1 , wherein the second portion includes a first region contacting the one end of the first portion and a second region extending from the first region, and a thickness of the first region is greater than a thickness of the second region.

8. A thin film transistor substrate, comprising: substrate; a first gate electrode on the substrate, the first gate electrode comprising a first portion and a plurality of second portions, the plurality of second portions being separated from one another with a plurality of first grooves interposed therebetween; an active layer on the first gate electrode; a second gate electrode on the active layer, the second gate electrode overlapping at least a portion of the first gate electrode; a source electrode connected to the first side of the active layer; and a drain electrode connected to the second side of the active layer, wherein the plurality of second portions protrude from a first end of the first portion in a first direction toward one of the source electrode and the drain electrode, and One end of the second gate electrode overlaps with a region extending from the first end of the first portion to one end of the second portion. 9 . The thin film transistor substrate of claim 8 , wherein the one end of the second gate electrode overlaps the plurality of first grooves.

10. A thin film transistor substrate according to claim 8, wherein the first gate electrode further comprises a plurality of third portions, the plurality of third portions protruding from the second end of the first portion in a second direction toward the other of the source electrode and the drain electrode, the second direction being opposite to the first direction, the plurality of third portions being separated from each other with a plurality of second grooves sandwiched between the plurality of third portions. 11 . The thin film transistor substrate of claim 10 , wherein the other end of the second gate electrode overlaps with a region extending from the second end of the first portion to one end of the third portion. 12 . The thin film transistor substrate of claim 10 , wherein a first center line passing through a center of the first gate electrode and a second center line passing through a center of the second gate electrode do not coincide with each other relative to each other in a plan view of the thin film transistor substrate. 13 . The thin film transistor substrate of claim 8 , wherein at least a portion of the second portions among the plurality of second portions and at least a portion of the first grooves among the plurality of first grooves overlap the active layer.

14. The thin film transistor substrate according to claim 8, The active layer comprises: a channel portion; a first connection portion on a first side of the channel portion; and a second connection portion on a second side of the channel portion, and The first side of the channel portion overlaps with a region extending from a boundary between the first portion and the second portion to the one end of the second portion.

15. A display device, comprising: Light emitting element; and A thin film transistor substrate according to claim 1 or 8 connected to the light emitting element.

16. A thin film transistor substrate, comprising: a first gate electrode extending in a first direction, the first gate electrode including a first portion and a plurality of second portions protruding from a first end of the first portion in a second direction different from the first direction, the plurality of second portions being spaced apart from each other; an active layer on the first gate electrode and extending in the second direction, the active layer partially overlapping the first portion and a portion of the second portions among the plurality of second portions along the first direction; a source electrode connected to the first side of the active layer; a drain electrode connected to a second side of the active layer, the second side of the active layer being opposite to the first side of the active layer along the second direction; and A second gate electrode is on the active layer and extends in the first direction, the second gate electrode partially overlapping the first gate electrode along the second direction without overlapping one end of the plurality of second portions. 17 . The thin film transistor substrate of claim 16 , wherein the second gate electrode overlaps the entire first portion of the first gate electrode along the first direction and the second direction. 18 . The thin film transistor substrate of claim 16 , wherein the second gate electrode overlaps a portion of the first portion of the first gate electrode and a portion of each of the plurality of second portions of the first gate electrode along the second direction. 19 . The thin film transistor substrate of claim 16 , wherein every two adjacent second portions of the plurality of second portions are separated by respective grooves of the plurality of grooves.

20. The thin film transistor substrate according to claim 16, wherein the active layer comprises: Channel Department; a first connection portion extending toward the source electrode in the second direction and connected to the source electrode; and a second connection portion extending toward the drain electrode in the second direction and connected to the drain electrode. 21 . The thin film transistor substrate of claim 20 , wherein each of the first connection portion and the second connection portion has a stepped form.

22. The thin film transistor substrate according to claim 20, wherein the channel portion overlaps the first portion of the first gate electrode, and One of the first connection portion and the second connection portion overlaps with a portion of the second portions of the first gate electrode.

23. The thin film transistor substrate according to claim 16, wherein the first gate electrode further comprises a plurality of third portions separated from each other, the plurality of third portions protruding from the second end of the first portion along the second direction, the second end of the first portion being opposite to the first end of the first portion along the second direction. 24 . The thin film transistor substrate of claim 16 , wherein a thickness of the first portion of the first gate electrode is greater than a thickness of each of the plurality of second portions of the first gate electrode.

25. The thin film transistor substrate of claim 16, wherein a distance from the active layer to the first portion of the first gate electrode along a third direction is the same as a distance from the active layer to the second portion of the first gate electrode along the third direction, and the third direction is different from the first direction and the second direction.

26. The thin film transistor substrate of claim 16, wherein a distance from the active layer to the first portion of the first gate electrode along a third direction is smaller than a distance from the active layer to the second portion of the first gate electrode along the third direction, and the third direction is different from the first direction and the second direction. 27 . The thin film transistor substrate of claim 16 , wherein the second gate electrode does not overlap with the plurality of second portions of the first gate electrode. 28 . The thin film transistor substrate of claim 16 , wherein the second gate electrode overlaps a portion of each second portion among a portion of the plurality of second portions of the first gate electrode.

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