Display panel and display device

Abstract

The invention discloses a display panel and a display device. The display panel comprises a gate driving unit with a gate transistor and a storage capacitor, an active part of the gate transistor is located on a first active layer, a first capacitor plate of the storage capacitor is located on a second active layer, and a gate of the gate transistor and a second capacitor plate of the storage capacitor are located on a first gate layer. The storage capacitor further comprises a first compensation pole plate arranged opposite to the first capacitor pole plate and the second capacitor pole plate, and the first compensation pole plate, the second active layer and the first grid layer are arranged in different layers. The first compensation polar plate is arranged in the storage capacitor in the gate driving unit, so that the first compensation polar plate, the first capacitor polar plate and the second capacitor polar plate form the capacitor, the area of the storage capacitor is reduced under the condition that the capacitance of the storage capacitor is not changed, the area occupation of the storage capacitor in the non-display area is reduced, and the display effect is improved. The frame size of the display panel is reduced, and the narrow frame design is realized.

Description

Technical Field

[0001] The present application relates to the field of display technology, and in particular to a display panel and a display device. Background Art

[0002] The existing OLED (Organic Light-Emitting Diode) display devices have increasingly higher requirements for power consumption and screen-to-body ratio. In order to reduce power consumption and increase screen-to-body ratio, low-temperature polysilicon oxide (LTPO) technology is used. LTPO technology refers to the simultaneous use of low-temperature polysilicon thin-film transistors and oxide thin-film transistors, so that the driving circuit takes into account the advantages of low-temperature polysilicon thin-film transistors and oxide thin-film transistors, thereby reducing power consumption and leakage current.

[0003] The border width of current display devices using LTPO technology is relatively large, which is contrary to the narrow border design of current products. Summary of the invention

[0004] The embodiments of the present application provide a display panel and a display device to solve the technical problem of large borders of existing display devices using LTPO technology.

[0005] To solve the above-mentioned problems, the technical solutions provided by this application are as follows:

[0006] The present application provides a display panel, which includes a plurality of gate driving units, wherein the gate driving units include gate transistors and storage capacitors connected to each other, wherein the active portion of the gate transistors is located on a first active layer, the first capacitor plate of the storage capacitor is located on a second active layer, and the gate of the gate transistor and the second capacitor plate of the storage capacitor are located on the first gate layer;

[0007] The storage capacitor further includes a first compensation plate disposed opposite to the first capacitor plate and the second capacitor plate, and the first compensation plate is disposed in a different layer from the second active layer and the first gate layer.

[0008] Other features and advantages of the present application will be described in detail in the subsequent detailed description. BRIEF DESCRIPTION OF THE DRAWINGS

[0009] In order to more clearly illustrate the technical solutions in the embodiments of the present application, the following briefly introduces the drawings required for use in the description of the embodiments. Obviously, the drawings described below are only some embodiments of the present application, and those skilled in the art can obtain other drawings based on these drawings without creative work.

[0010] In order to more completely understand the present application and its beneficial effects, the following description will be given in conjunction with the accompanying drawings, wherein the same figure numbers represent the same parts in the following description.

[0011] Figure 1 This is a simplified diagram of the first structure of the display panel of this application;

[0012] Figure 2 is an equivalent circuit diagram of a pixel driving circuit in a display panel of the present application;

[0013] Figure 3 This is a simplified diagram of the second structure of the display panel of this application;

[0014] Figure 4 A third structural diagram of the display panel of the present application;

[0015] Figure 5 is an equivalent circuit diagram of a gate driving circuit in a display panel of the present application;

[0016] Figure 6 This is a schematic diagram of the film layer in the display panel of this application;

[0017] Figure 7 A diagram of the stacked film layers of the light shielding layer and the first gate layer in the display panel of the present application;

[0018] Figure 8 A film layer diagram of the first active layer in the display panel of the present application;

[0019] Fig. 9 This is a film layer stack diagram of the first active layer and the first gate layer in the display panel of this application.

[0020] Fig.10 This is a laminated film diagram of the light shielding layer and the second active layer in the display panel of this application.

[0021] Fig.11 This is a film layer stacking diagram of the first active layer, the second active layer and the first gate layer in the display panel of the present application.

[0022] Fig.12 This is a film layer diagram of the second gate layer in the display panel of this application.

[0023] Fig.13 It is a film layer stacking diagram of the first active layer, the second active layer, the first gate layer and the second gate layer in the display panel of the present application.

[0024] Fig.14 This is a film layer diagram of the first source and drain layer in the display panel of this application.

[0025] Fig.15It is a film layer stacking diagram of the first active layer, the second active layer, the first gate layer, the second gate layer and the first source and drain layer in the display panel of the present application.

[0026] Fig.16 This is a film layer diagram of the second source and drain layer in the display panel of this application.

[0027] Fig.17 It is a film layer stacking diagram of the first active layer, the second active layer, the first gate layer, the second gate layer, the first source and drain layer, and the second source and drain layer in the display panel of the present application. DETAILED DESCRIPTION

[0028] The technical solutions in the embodiments of the present application will be described clearly and completely below in conjunction with the drawings in the embodiments of the present application. Obviously, the described embodiments are only part of the embodiments of the present application, not all of the embodiments. Based on the embodiments in the present application, all other embodiments obtained by those skilled in the art without creative work are within the scope of protection of the present application. In addition, it should be understood that the specific implementation methods described herein are only used to illustrate and explain the present application, and are not used to limit the present application. In the present application, unless otherwise stated, the directional words used, such as "upper" and "lower", generally refer to the upper and lower parts of the device in actual use or working state, specifically the drawing direction in the drawings; and "inside" and "outside" refer to the outline of the device.

[0029] See also Figures 1 to 17 The present application provides a display panel 100, which includes a display area AA and a non-display area NA arranged on one side of the display area AA.

[0030] In this embodiment, the display area AA includes a pixel driving circuit 300 having a plurality of pixel transistors, the plurality of pixel transistors including silicon semiconductor transistors and oxide transistors, the active portion of the silicon semiconductor transistors being located in the first active layer 123 , and the active portion of the oxide transistors being located in the second active layer 127 .

[0031] In this embodiment, the non-display area NA is disposed on one side of the display area AA, and the non-display area NA includes a plurality of cascaded gate driving units 200a, each of which includes a plurality of gate transistors and a storage capacitor Cst1 connected to the gate transistors;

[0032] In this embodiment, the active portion of the gate transistor is located in the first active layer 123 , the first capacitor plate Ca of the storage capacitor is located in the second active layer 127 , and the gate of the gate transistor and the second capacitor plate Cb of the storage capacitor are located in the first gate layer 125 .

[0033] In this embodiment, the storage capacitor further includes a first compensation plate CP1 disposed opposite to the first capacitor plate Ca and the second capacitor plate Cb. The first compensation plate CP1 is disposed in a different layer from the second active layer 127 and the first gate layer 125 .

[0034] In some embodiments of the present application, the storage capacitor Cst1 of the gate driving unit 200a is generally composed of two layers of metal material, so that the number of film layers of the display panel 100 is large, thereby increasing the number of mask plates, resulting in a more complicated process and higher cost; while the present application uses the material of one of the first active layer 123 and the second active layer 127 to set the active part of the gate transistor, and the material of the other to set a plate of the storage capacitor Cst1, so that the one plate of the storage capacitor Cst1 is replaced by the metal material with the active layer material, and the metal layer originally used to prepare the one plate of the storage capacitor Cst1 is removed, the number of film layers of the display panel 100 is reduced, and the preparation process of the display panel 100 is simplified.

[0035] At the same time, the present application sets a first compensation plate CP1 in the storage capacitor in the gate driving unit 200a, so that the first compensation plate CP1, the first capacitor plate Ca and the second capacitor plate Cb form a capacitor, and the area of ​​the storage capacitor is reduced while the capacitance of the storage capacitor remains unchanged, and the area occupied by the storage capacitor in the non-display area NA is reduced, thereby reducing the frame size of the display panel 100 and realizing a narrow frame design.

[0036] It should be noted that the silicon semiconductor transistor of the present application is a P-type transistor, and the oxide transistor is an N-type transistor.

[0037] It should be noted that the pixel transistor in the present application is a transistor constituting the pixel driving circuit 300 , and the gate transistor is a transistor constituting the gate driving circuit 200 .

[0038] The technical solution of the present application is now described in conjunction with specific embodiments.

[0039] See also Figure 1 The display panel 100 includes a display area AA and a non-display area NA disposed adjacent to the display area AA, and the display area AA is disposed within the display area AA. Optionally, the non-display area NA surrounds the display area AA, so that the display area AA is surrounded by the non-display area NA. The display area AA is an area within the display panel 100 for performing a display function, and a plurality of display units for realizing the display function are disposed therein. The non-display area NA may be a frame area of ​​the display panel 100, and a functional component that assists the display unit in the display area AA to perform display may be disposed therein.

[0040] See also Figure 1The lower side of the display area AA is provided with a binding terminal 400, which can be connected to an external circuit, and transmits the signal input by the external circuit to the data line, thereby driving the display panel 100 to display the picture. For example, the binding terminal 400 can be bound and connected to a chip or a flip chip film, etc., to provide power and driving signals for the display panel 100.

[0041] In this embodiment, a plurality of light-emitting devices LED and a pixel driving circuit 300 for driving the light-emitting devices LED may be arranged in an array in the display area AA. The pixel driving circuit 300 may be a 7T1C, 7T2C, 8T2C, 8T3C, 8T4C or other pixel driving circuit 300. This application does not impose any specific limitation thereto. The following description will be made using the 8T2C pixel driving circuit 300 as an example.

[0042] See also Figure 2 The pixel driving circuit 300 may include a switch transistor T2A, a driving transistor T1A, a compensation transistor T3A, a first reset transistor T4A, a second reset transistor T7A, a third reset transistor T8A, a first light emitting transistor T5A, a second light emitting transistor T6A, a boost capacitor Cboost, and a control capacitor Cst2.

[0043] See also Figure 2, a first electrode of the switch transistor T2A is connected to the data signal line Data, a second electrode of the switch transistor T2A is connected to the control node A1, and a gate of the switch transistor T2A receives a switch control signal Pscan1; a first electrode of the driving transistor T1A is connected to the control node A1, a second electrode of the driving transistor T1A is connected to the control node B1, and a gate of the driving transistor T1A is connected to the control node Q1; a first electrode of the compensation transistor T3A is connected to the control node Q1, a second electrode of the compensation transistor T3A is connected to the control node B1, and a gate of the compensation transistor T3A receives a compensation control signal Nscan1; a first electrode of the first reset transistor T4A receives a first reset signal Vi1, a second electrode of the first reset transistor T4A is connected to the control node Q1, and a gate of the first reset transistor T4A receives a first reset control signal Nscan2; a first electrode of the second reset transistor T7A is connected to a second reset signal Vi2, a second electrode of the second reset transistor T7A is connected to the anode of the light emitting device, and a The gate receives the second reset control signal Pscan2; the first electrode of the third reset transistor T8A receives the third reset signal Vi3, the second electrode of the third reset transistor T8A is connected to the control node A1, and the gate of the third reset transistor T8A receives the third reset control signal Vi3; the first electrode of the first light-emitting transistor T5A is connected to the high-level source VDD, the second electrode of the first light-emitting transistor T5A is connected to the control node A1, and the gate of the first light-emitting transistor T5A receives the light-emitting control signal EM; the first electrode of the second light-emitting transistor T6A is connected to the second node B1, the second electrode of the second light-emitting transistor T6A is connected to the anode of the light-emitting device, and the gate of the second light-emitting transistor T6A receives the light-emitting control signal EM; one end of the boost capacitor Cboost is connected to the control node Q1, and the other end of the boost capacitor Cboost is connected to the gate of the switching transistor T2A; one end of the control capacitor Cst2 is connected to the control node Q1, and the other end of the control capacitor Cst2 is connected to the high-level source VDD; the cathode of the light-emitting device is connected to the low-level source VSS.

[0044] In this embodiment, the high level source VDD is used to provide a constant high voltage level to the pixel driving circuit 300 , and the low level source VSS is used to provide a constant low voltage level to the pixel driving circuit 300 .

[0045] In this embodiment, the switch transistor T2A, the drive transistor T1A, the second reset transistor T7A, the third reset transistor T8A, the first light-emitting transistor T5A, and the second light-emitting transistor T6A can be one of P-type transistors or N-type transistors, and the compensation transistor T3A and the first reset transistor T4A can be the other of P-type transistors or N-type transistors; this application is described by taking the switch transistor T2A, the drive transistor T1A, the second reset transistor T7A, the third reset transistor T8A, the first light-emitting transistor T5A, and the second light-emitting transistor T6A as P-type transistors, and the compensation transistor T3A and the first reset transistor T4A as N-type transistors as an example.

[0046] In this embodiment, the capacitance value of the boost capacitor Cboost is less than the capacitance value of the control capacitor Cst2. In this embodiment, the control capacitor Cst2 is mainly used to maintain the stability of the potential of the third node Q1, so the capacitance of the control capacitor Cst2 is relatively large, for example, the capacitance value range of the control capacitor Cst2 can be 45fF to 55fF, and the capacitance value range of the boost capacitor Cboost can be 5fF to 15fF.

[0047] In this embodiment, the first electrode may be one of the source and the drain, and the second electrode may be the other of the source and the drain.

[0048] See also Figure 3 and Figure 4 The gate driving circuit 200 is disposed in the non-display area NA, and the gate driving circuit 200 can be disposed on both sides of the display area AA; the gate driving circuit 200 can include N cascaded gate driving units 200a, the N gate driving units 200a can be arranged along the first direction X, and the structure of the gate driving unit 200a can be various, for example, Figure 3 In the structure, the non-display area NA may include a plurality of first gate circuits 210 arranged and cascaded along the first direction X, a plurality of second gate circuits 220 arranged and cascaded along the first direction X, a plurality of third gate circuits 230 arranged and cascaded along the first direction X, a plurality of fourth gate circuits 240 arranged and cascaded along the first direction X, and a plurality of fifth gate circuits 250 arranged and cascaded along the first direction X.

[0049] In this embodiment, the second direction Y is parallel to the scan line of the display panel 100, the angle between the first direction X and the second direction Y is greater than 0° and less than or equal to 90°, and the scan line can be a gate signal transmission line, such as at least one of a compensation control line, a first reset control line, a switch control line, a second reset control line or a light emitting control line.

[0050] See also Figure 3 and Figure 4The first gate circuit 210 is arranged on both sides of the display area AA. The first gate circuit 210 is used to transmit the compensation control signal Nscan1. A first gate circuit 210 is connected to two compensation control lines, that is, a first gate circuit 210 is used to output the compensation control signal Nscan1 to two rows of pixel driving circuits 300, that is, two rows of pixel driving circuits 300 require a first gate circuit 210.

[0051] See also Figure 3 and Figure 4 The second gate circuit 220 is arranged on both sides of the display area AA, the second gate circuit 220 and the first gate circuit 210 can be arranged along the second direction Y or the first direction X, the second gate circuit 220 is used to transmit the first reset control signal Nscan2, and a second gate circuit 220 is connected to two first reset control lines; at the same time, the first-level second gate circuit 220 of the present application is used to output the first reset control signal Nscan2 to the two-row pixel driving circuit 300, that is, the two-row pixel driving circuit 300 requires a first-level second gate circuit 220.

[0052] It should be noted that the attached Figure 3 and Figure 4 The second gate circuit 220 and the first gate circuit 210 are alternately arranged along the first direction X as an example for explanation. The actual situation can be adjusted according to the wiring space of the display panel. For example, the first gate circuit 210 can be arranged in a single column along the first direction X, and the second gate circuit 220 can be arranged in a single column along the first direction X.

[0053] See also Figure 3 and Figure 4 The fifth gate circuit 250 is arranged on both sides of the display area AA, and is located between the display area AA and the first gate circuit 210, and between the display area AA and the second gate circuit 220. The fifth gate circuit 250 is used to transmit the switch control signal Pscan1, and a fifth gate circuit 250 is connected to two switch control lines; at the same time, the first-level fifth gate circuit 250 of the present application is used to output the switch control signal Pscan1 to a row of pixel driving circuits 300, that is, a row of pixel driving circuits 300 requires a first-level fifth gate circuit 250.

[0054] Please note that Figure 3 and Figure 4 , a first gate circuit 210, a second gate circuit 220 and a fifth gate circuit 250 are provided on both sides of each display area AA, that is, the first gate circuit 210, the second gate circuit 220 and the fifth gate circuit 250 of the present application are driven simultaneously on both sides.

[0055] See also Figure 3 and Figure 4The third gate circuit 230 is arranged on the first side of the display area AA, and the third gate circuit 230 is located on the side of the first gate circuit 210 away from the display area AA. The third gate circuit 230 is used to transmit the second reset control signal Pscan2, and a third gate circuit 230 is connected to two second reset control lines; at the same time, the first-level fourth gate circuit 240 of the present application is used to output the compensation control signal Nscan1 to the two-row pixel driving circuit 300, that is, the two-row pixel driving circuit 300 requires a first-level third gate circuit 230.

[0056] See also Figure 3 and Figure 4 The fourth gate circuit 240 is arranged on the second side of the display area AA, and the fourth gate circuit 240 is located on the side of the first gate circuit 210 away from the display area AA. The fourth gate circuit 240 is used to transmit the light-emitting control signal EM, and a fourth gate circuit 240 is connected to two light-emitting control lines; at the same time, the first-level fourth gate circuit 240 of the present application is used to output the compensation control signal Nscan1 to the two-row pixel driving circuit 300, that is, the two-row pixel driving circuit 300 requires a first-level fourth gate circuit 240.

[0057] It should be noted that, in the present application, only the third gate circuit 230 is provided on one side of the display area AA, and only the fourth gate circuit 240 is provided on the other side of the display area AA, that is, the third gate circuit 230 and the fourth gate circuit 240 are unilaterally driven.

[0058] It should be noted that since the first reset signal Vi1 , the second reset signal Vi2 and the third reset signal Vi3 are all constant voltages, they do not need to be controlled by the corresponding gate driving circuit 200 and can be directly connected to the corresponding constant voltage source.

[0059] In this embodiment, the first gate circuit 210, the second gate circuit 220, the third gate circuit 230, the fourth gate circuit 240, and the fifth gate circuit 250 of the present application can be gate circuits of mTnC. In the following embodiment, the structure of the gate driving unit 200a of the present application is explained by taking the first gate circuit 210 and the second gate circuit 220 as 16T4C as an example.

[0060] It should be noted that Figure 3 and Figure 4 The difference is that Figure 4 The middle display panel also has an under-screen camera area CUP. Figure 3 The under-screen camera area CUP is not set.

[0061] See also Figure 5The gate driving unit 200a may include a receiving circuit 221 and an output circuit 222, the receiving circuit 221 and the output circuit 222 are arranged along the second direction Y, the receiving circuit 221 is used to receive the level transmission signal generated by the upper gate driving circuit 200, the output circuit 222 is electrically connected to the receiving circuit 221 through the second node Q2 and the first node P2, and is used to output the control signal of the current level and the level transmission signal of the next level according to the signal of the second node Q2 and the signal of the first node P2.

[0062] See also Figure 5 The output circuit 222 includes a second output transistor T10 and a first output transistor T9, the gate of the second output transistor T10 is electrically connected to the second node Q2, the source of the second output transistor T10 is electrically connected to the high potential line VGH, and the drain of the second output transistor T10 is electrically connected to the output terminal OUT in the gate driving circuit 200; the gate of the first output transistor T9 is electrically connected to the first node P2, the source of the first output transistor T9 is electrically connected to the low potential line VGL, and the drain of the first output transistor T9 is electrically connected to the output terminal OUT.

[0063] See also Figure 5 The receiving circuit 221 includes a first node control module 221a and a second node control module 221b, the first output transistor T9 and the first node control module 221a are connected to the first node P2, and the second output transistor T10 and the second node control module 221b are connected to the second node Q2.

[0064] See also Figure 5 , the storage capacitor includes a first capacitor C1 and a second capacitor C2, and the voltage stabilizing capacitor includes a third capacitor C3 and a fourth capacitor C4. The first capacitor C1 includes a first plate C1a and a second plate C1b, and the first plate C1a and the second plate C1b are respectively connected to different internal nodes in the first node control module 221a; the second capacitor C2 includes a third plate C2a and a fourth plate C2b, and the third plate C2a and the fourth plate C2b are respectively connected to different internal nodes in the second node control module 221b; the third capacitor C3 includes a fifth plate C3a and a sixth plate C3b, and the fifth plate C3a is connected to the source of the first output transistor T9, and the sixth plate C3b is connected to the first node P2; the fourth capacitor C4 includes a seventh plate C4a and an eighth plate C4b, and the seventh plate C4a is connected to the source of the second output transistor T10, and the eighth plate C4b is connected to the second node Q2.

[0065] See also Figure 5The receiving circuit 221 includes a third transistor T3, a gate of the third transistor T3 is loaded with the first clock signal line XCK, a source of the third transistor T3 is connected to the start signal line STV, and a drain of the third transistor T3 is connected to the control node N3.

[0066] See also Figure 5 The receiving circuit 221 includes a fourth transistor T4, a fifth transistor T5, a sixth transistor T6 and a seventh transistor T7, the gate of the fifth transistor T5 is electrically connected to the control node N3, the source of the fifth transistor T5 is loaded with the first clock signal line XCK, the gate of the fourth transistor T4 is loaded with the first clock signal line XCK, the source of the fourth transistor T4 is loaded with the low potential line VGL, the drain of the fourth transistor T4 is electrically connected to the control node N2, the drain of the fifth transistor T5 is electrically connected to the control node N2, the gate of the sixth transistor T6 is electrically connected to the control node N1, the drain of the sixth transistor T6 is electrically connected to the source of the seventh transistor T7, the source of the sixth transistor T6 and the gate of the seventh transistor T7 are both loaded with the second clock signal line CK, and the drain of the seventh transistor T7 is electrically connected to the second node Q2.

[0067] See also Figure 5 The receiving circuit 221 includes a thirteenth transistor T13, a first capacitor C1, a first transistor T1 and a second transistor T2, the gate of the thirteenth transistor T13 is electrically connected to the control line Contorol to load the control signal, the source of the thirteenth transistor T13 is loaded with the high potential line VGH, the drain of the thirteenth transistor T13 is electrically connected to the control node N3, the gate of the first transistor T1 is electrically connected to the control node N2, the source of the first transistor T1 is loaded with the high potential line VGH, the drain of the first transistor T1 is electrically connected to the source of the second transistor T2, the drain of the second transistor T2 is loaded with the second clock signal line CK, the gate of the second transistor T2 is electrically connected to the control node N4, and the first capacitor C1 is electrically connected between the gate and the drain of the second transistor T2.

[0068] See also Figure 5 The receiving circuit 221 includes an eleventh transistor T11, a second capacitor C2, and a twelfth transistor T12. The output circuit 222 may further include a third capacitor C3 electrically connected between the gate and the source of the tenth transistor T10. The gate of the eleventh transistor T11 and the gate of the twelfth transistor T12 may be loaded with a low potential line VGL to maintain opening. The source and the drain of the eleventh transistor T11 are electrically connected to the control node N2 and the control node N1, respectively. The second capacitor C2 is electrically connected between the gate and the drain of the sixth transistor T6. The source and the drain of the twelfth transistor T12 are electrically connected to the control node N3 and the first node P2, respectively.

[0069] See also Figure 5 The receiving circuit 221 includes an eighth transistor T8, a gate of the eighth transistor is connected to the control node N3, a drain of the eighth transistor T8 is connected to the high potential line VGH, and a source of the eighth transistor T8 is connected to the second node Q2.

[0070] See also Figure 5 , the receiving circuit 221 includes a fourteenth transistor T14, a fifteenth transistor T15 and a sixteenth transistor T16. The source of the fourteenth transistor T14 is connected to the start signal line STV, the gate of the fourteenth transistor T14 is loaded with the first clock signal line XCK, and the drain of the fourteenth transistor T14 is electrically connected to the source of the fifteenth transistor T15; the gate of the fifteenth transistor T15 is loaded with the low potential line VGL, and the drain of the fifteenth transistor T15 is electrically connected to the control node N4; the gate and source of the sixteenth transistor T16 are both electrically connected to the control node N4, and the drain of the sixteenth transistor T16 is electrically connected to the first node P2.

[0071] See also Figure 5 The output circuit 222 further includes a fourth capacitor C4, a first plate of the fourth capacitor C4 is connected to the output terminal OUT, and a second plate of the fourth capacitor C4 is connected to the first node P2.

[0072] It should be noted that the source of the fourteenth transistor T14 and the source of the third transistor T3 are connected to the start signal line STV only in the first level, and in the gate drive circuit 200 after the second level, the source of the fourteenth transistor T14 and the source of the third transistor T3 are electrically connected to the output terminal OUT of the gate drive circuit 200 of the previous level.

[0073] It should be noted that the source and drain in the above transistor of the present application are only different in naming, as long as one of them is the input terminal and the other is the output terminal.

[0074] It should be noted that all transistors in the gate driving circuit 200 of the present application may be N-type transistors or P-type transistors, and all transistors in the gate driving circuit 200 of this embodiment are described by taking P-type transistors as an example.

[0075] It should be noted that the first node control module 221a of the present application may include a first transistor T1 and a second transistor T2, and the second node control module 221b may include a sixth transistor T6 and a seventh transistor T7.

[0076] See also Figure 6The display area AA and the non-display area NA of the display panel 100 may be provided with a base substrate 110 and an array driving layer 120 provided on the base substrate 110; in the display area AA, the display panel 100 may also be provided with a pixel definition layer (not shown) provided on the array driving layer 120, a light emitting device layer (not shown) provided on the same layer as the pixel definition layer, and an encapsulation layer (not shown) provided on the pixel definition layer. The following mainly describes the film layer structure in the non-display area NA and the display area AA.

[0077] In the present embodiment, the base substrate 110 supports various layers disposed on the base substrate 110. When the display panel 100 is a bottom-emitting light-emitting display device or a double-sided light-emitting display device, a transparent base substrate is used. When the display panel 100 is a top-emitting light-emitting display device, a semi-transparent or opaque base substrate as well as a transparent base substrate may be used.

[0078] In the present embodiment, the base substrate 110 is used to support various film layers disposed on the base substrate 110, and the base substrate 110 may be made of an insulating material such as glass, quartz, or a polymer resin. The base substrate 110 may be a rigid substrate or a flexible substrate that can be bent, folded, curled, etc. Examples of flexible materials for the flexible substrate include polyimide (PI), but are not limited to polyimide (PI).

[0079] In this embodiment, the base substrate 110 may include a first flexible substrate 111, a first barrier layer 112, a second flexible substrate 113, and a second barrier layer 114 that are stacked. The first flexible substrate 111 and the second flexible substrate 113 may be formed of the same material such as polyimide, and the first barrier layer 112 and the second barrier layer 114 may be formed of an inorganic material including, for example, at least one of SiOx and SiNx.

[0080] In the present embodiment, the first flexible substrate 111 is formed by coating a polymer material on a support substrate (not shown) and then curing the polymer material, the second flexible substrate 113 is formed by coating the same material as the first flexible substrate 111 and curing the material, and the second flexible substrate 113 is formed by the same method as the method of forming the first flexible substrate 111. Each of the first flexible substrate 111 and the second flexible substrate 113 may be formed to have a thickness of about 8 μm to about 12 μm. In addition, when the base substrate 110 is formed of the first flexible substrate 111 and the second flexible substrate 113, small holes, cracks, etc. formed during the manufacture of the first flexible substrate 111 are covered by the second flexible substrate 113, so that the above-mentioned defects can be removed.

[0081] See also Figure 6, the array driving layer 120 may include a plurality of thin film transistors, the thin film transistors may be of an etching barrier type, a back channel etching type, or may be divided into a bottom gate thin film transistor, a top gate thin film transistor and the like according to the position of the gate electrode and the active layer, or may be divided into an N-type thin film transistor and a P-type thin film transistor according to the performance of the thin film transistor, for example, the gate transistor in the non-display area AA may be a P-type thin film transistor, and the pixel transistor in the display area AA may be an N-type thin film transistor and a P-type thin film transistor; secondly, Figure 6 The thin film transistor in the Figure 2 The structural diagram of any transistor is merely a schematic diagram of each film layer of the display panel 100 of the present application.

[0082] See also Figure 6 The array driving layer 120 may include a third barrier layer 135 disposed on the base substrate 110, a light shielding layer 121 embedded in the barrier layer 135, a buffer layer 122 disposed on the barrier layer 135, a first active layer 123 disposed on the buffer layer 122, a first insulating layer 124 disposed on the first active layer 123, a first gate layer 125 disposed on the first insulating layer 124, a second insulating layer 126 disposed on the first gate layer 125, and a first gate layer 126 disposed on the second insulating layer 126. A second active layer 127, a third insulating layer 128 disposed on the second active layer 127, a second gate layer 129 disposed on the third insulating layer 128, a fourth insulating layer 130 disposed on the second gate layer 129, a first source-drain layer 131 disposed on the fourth insulating layer 130, a first planarizing layer 132 disposed on the first source-drain layer 131, a second source-drain layer 133 disposed on the first planarizing layer 132, and a second planarizing layer 134 disposed on the second source-drain layer 133.

[0083] See also Figure 6 The light-shielding layer 121 is disposed on the second blocking layer 114. The light-shielding layer 121 is used to block external light from entering the thin film transistor from the bottom. The material of the light-shielding layer 121 can be composed of a black light-shielding material, such as a black light-shielding metal or a black organic material. The light-shielding layer 121 of the present application is disposed in both the display area AA and the non-display area NA.

[0084] See also Figure 6 The buffer layer 122 is disposed on the light-shielding layer 121. The buffer layer 122 is used to isolate the light-shielding layer 121 from the upper metal material. The material of the buffer layer 122 may include a compound composed of nitrogen, silicon and oxygen, such as a single-layer silicon oxide film layer, or a silicon oxide-silicon nitride stacked structure.

[0085] See also Figure 6, a first active layer 123 is arranged on the buffer layer 122, and a second active layer 127 is arranged on the second insulating layer 126. In the present application, the material of the first active layer 123 may be low-temperature polysilicon, and the material of the second active layer 127 may be indium gallium zinc oxide semiconductor; since the transistors in the gate driving unit 200a are all P-type transistors, no metal oxide semiconductor is arranged in the non-display area AA of the present application, and the pixel driving circuit 300 has N-type transistors and P-type transistors, so the display area AA of the present application is provided with metal oxide semiconductors and low-temperature polycrystalline silicon semiconductors.

[0086] See also Figure 6 The first insulating layer 124, the second insulating layer 126, the third insulating layer 128, and the fourth insulating layer 130 are respectively arranged on the corresponding metal layers or semiconductor layers, and are separated by different layers of metal layers or semiconductor layers; the materials of the first insulating layer 124, the second insulating layer 126, the third insulating layer 128, and the fourth insulating layer 130 can be an inorganic substance composed of at least two elements in silicon oxynitride or an organic material with flatness.

[0087] See also Figure 6 The first gate layer 125 and the second gate layer 129 are respectively disposed on corresponding insulating layers. The materials of the first gate layer 125 and the second gate layer 129 may be copper, molybdenum or molybdenum-titanium alloy.

[0088] See also Figure 6 The first source-drain electrode layer 131 is disposed on the fourth insulating layer 130 , and the second source-drain electrode layer 133 is disposed on the first planar layer 132 . The materials of the first source-drain electrode layer 131 and the second source-drain electrode layer 133 may be copper or molybdenum-titanium alloy, copper or titanium, etc.

[0089] See also Figure 6 The first flat layer 132 and the second flat layer 134 are laid in a whole layer to ensure the flatness of the film layer of the array driving layer 120. The materials of the first flat layer 132 and the second flat layer 134 can be inorganic substances composed of nitride oxide silicon or organic materials with flatness.

[0090] according to Figure 6It can be seen from the structure that two of the three plates of the storage capacitor in the non-display area AA of the present application are respectively composed of the material of the first gate layer 125 and the material of the second active layer 127, for example, the first plate C1a, the third plate C2a, the fifth plate C3a and the seventh plate C4a are located in the second active layer 127, the first plate C1a and the third plate C2a are the first capacitor plate Ca of the present application, the second plate C1b, the fourth plate C2b, the sixth plate C3b and the eighth plate C4b are located in the first gate layer 125, the second plate C1b and the fourth plate C2b are the second capacitor plate Cb of the present application, the metal layer and the insulating layer between the original second active layer 127 and the first gate layer 125 are removed, the number of film layers of the display panel 100 is reduced, the preparation process of the display panel 100 is simplified, and the cost of the display panel 100 is reduced.

[0091] It should be noted that when all transistors in the gate driving circuit 200 of this embodiment are N-type transistors, the second active layer 127 can be used to set the active parts of all transistors in the gate driving circuit 200, and the material of the first active layer 123 and the material of the first gate layer 125 can form the two plates of the storage capacitor Cst1.

[0092] The structure of each film layer in the gate driving unit 200a is described below according to the stack diagram.

[0093] See also Figure 7 , Figure 7 FIG. 1 is a diagram of the stacked film layers of the light shielding layer 121 and the first gate layer 125 in the display panel 100 of the present application.

[0094] In the present embodiment, the first gate layer 125 includes a first gate T9G of the first output transistor T9 and a second gate T10G of the second output transistor T10 , and the first gate T9G and the second gate T10G are arranged in the first direction X.

[0095] In this embodiment, the first gate T9G includes a first trunk gate T9Ga and a plurality of first branch gates T9Gb connected to the first trunk gate T9Ga, the first trunk gate T9Ga extends along a first direction X, the plurality of first branch gates T9Gb extend along a second direction Y, and the plurality of first branch gates T9Gb are spaced apart in the first direction X, and the first trunk gate T9Ga and part of the first branch gates T9Gb are reused as a sixth plate C3b.

[0096] In this embodiment, the second gate T10G includes a second trunk gate T10Ga and a plurality of second branch gates T10Gb connected to the second trunk gate T10Ga, the second trunk gate T10Ga extends along the first direction X, the plurality of second branch gates T10Gb extend along the second direction Y, and the plurality of second branch gates T10Gb are spaced apart in the first direction X, and the second trunk gate T10Ga and part of the second branch gates T10Gb are reused as the eighth plate C4b.

[0097] In this embodiment, in the first direction X, the interval between two adjacent first branch gates T9Gb may be equal, and the interval between two adjacent second branch gates T10Gb may be equal.

[0098] In this embodiment, in the first direction X, a distance between two adjacent first branch gates T9Gb and a distance between two adjacent second branch gates T10Gb may be equal.

[0099] In this embodiment, in the second direction Y, the line width of the first stem gate T9Ga is smaller than the line width of the second stem gate T10Ga.

[0100] See also Figure 7 The first gate layer 125 also includes a second plate C1b of the first capacitor C1 and a fourth plate C2b of the second capacitor C2. The second plate C1b and the fourth plate C2b are arranged along the first direction X. The second plate C1b is disposed close to the sixth plate C3b, and the fourth plate C2b is disposed close to the eighth plate C4b.

[0101] In this embodiment, the area of ​​the second electrode plate C1b may be greater than the area of ​​the fourth electrode plate C2b.

[0102] See also Figure 7 The first gate layer 125 also includes a gate T1G of a first transistor T1, a gate T2G of a second transistor T2, a gate T3G of a third transistor T3, a gate T4G of a fourth transistor T4, a gate T5G of a fifth transistor T5, a gate T6G of a sixth transistor T6, a gate T7G of a seventh transistor T7, a gate T8G of an eighth transistor T8, a gate T11G of an eleventh transistor T11, a gate T12G of a twelfth transistor T12, a gate T13G of a thirteenth transistor T13, a gate T14G of a fourteenth transistor T14, a gate T15G of a fifteenth transistor T15, and a gate T16G of a sixteenth transistor T16.

[0103] See also Figure 7, the gate T2G of the second transistor T2, the gate T6G of the sixth transistor T6 and the gate T16G of the sixteenth transistor T16 all extend along the first direction X, and the gate T1G of the first transistor T1, the gate T3G of the third transistor T3, the gate T4G of the fourth transistor T4, the gate T8G of the eighth transistor T8, the gate T12G of the twelfth transistor T12, the gate T13G of the thirteenth transistor T13, the gate T14G of the fourteenth transistor T14, the gate T15G of the fifteenth transistor T15 and the gate T11G of the eleventh transistor T11 extend along the second direction Y.

[0104] See also Figure 7 The gate T2G of the second transistor T2 and the gate T16G of the sixteenth transistor T16 are both connected to the second electrode plate C1b, and the gate T2G of the second transistor T2 and the gate T6G of the sixth transistor T6 are located on a side of the fourth electrode plate C2b away from the second electrode plate C1b; the gate T6G of the sixth transistor T6 is connected to the fourth electrode plate C2b, and the gate T6G of the sixth transistor T6 is located on a side of the fourth electrode plate C2b close to the second electrode plate C1b.

[0105] See also Figure 7 , the gate T3G of the third transistor T3, the gate T4G of the fourth transistor T4 and the gate T14G of the fourteenth transistor T14 are connected, and the gate T14G of the fourteenth transistor T14 and the gate T4G of the fourth transistor T4 are connected through a longitudinal conductive structure, the gate T14G of the fourteenth transistor T14 and the gate T3G of the third transistor T3 are both located on the same side of the gate T4G of the fourth transistor T4, and the gate T3G of the third transistor T3, the gate T4G of the fourth transistor T4 and the gate T14G of the fourteenth transistor T14 are located on a side of the fourth plate C2b away from the second output transistor T10.

[0106] See also Figure 7 , the gate T15G of the fifteenth transistor T15 is connected to the gate T11G of the eleventh transistor T11, the gate T4G of the fourth transistor T4, the gate T13G of the thirteenth transistor T13, the gate T15G of the fifteenth transistor T15 and the gate T11G of the eleventh transistor T11 are arranged between the second electrode plate C1b and the fourth electrode plate C2b, and the gate T13G of the thirteenth transistor T13 is arranged close to the output circuit 222, the gate T15G of the fifteenth transistor T15 is arranged far away from the output circuit 222, and the gate T4G of the fourth transistor T4 is arranged between the thirteenth transistor T13 and the eleventh transistor T11.

[0107] See also Figure 7, the gate T7G of the seventh transistor T7 is arranged between the fourth plate C2b and the second output transistor T10, the gate T12G of the twelfth transistor T12 is arranged between the second plate C1b and the first output transistor T9, the gate T5G of the fifth transistor T5 and the gate T8G of the eighth transistor T8 are connected, and the gate T5G of the fifth transistor T5 and the gate T8G of the eighth transistor T8 are both arranged between the fourth plate C2b and the second plate C1b, and the gate T5G of the fifth transistor T5 and the gate T8G of the eighth transistor T8 are arranged close to the second plate C1b.

[0108] See also Figure 7 The light shielding layer 121 includes two first compensation plates CP1 and two second compensation plates CP2. The two first compensation plates CP1 are respectively arranged opposite to the corresponding second plate C1b and fourth plate C2b, and the two second compensation plates CP2 are respectively arranged opposite to the corresponding sixth plate C3b and eighth plate C4b.

[0109] In this embodiment, the orthographic projections of the second electrode plate C1b and the fourth electrode plate C2b on the base substrate 110 are located within the orthographic projection of the first compensation electrode plate CP1 on the base substrate 110, that is, the area of ​​the first compensation electrode plate CP1 of the first capacitor C1 is larger than the area of ​​the second electrode plate C1b, that is, the area of ​​the first compensation electrode plate CP1 of the second capacitor C2 is larger than the area of ​​the fourth electrode plate C2b.

[0110] In this embodiment, since no other structure is set in the shading layer 121 in the non-display area NA, the area of ​​the first compensation plate CP1 of the present application can be larger than the upper capacitor plate to increase the relative area of ​​the first compensation plate CP1 and the upper capacitor plate, thereby increasing the capacitance of the capacitor.

[0111] In the present embodiment, since the first capacitor C1 is used to maintain the potential of the gate of the second transistor T2 and the gate of the sixteenth transistor T16, and the second capacitor C2 is used to maintain the potential of the gate of the sixth transistor T6, the load of the first capacitor C1 is greater than the load of the second capacitor C2, that is, the capacitance of the first capacitor C1 of the present application is greater than the capacitance of the second capacitor C2; and in order to make the capacitance of the first capacitor C1 greater than the capacitance of the second capacitor C2, the present application can make the area of ​​the first compensation plate CP1 in the first capacitor C1 greater than the area of ​​the first compensation plate CP1 in the second capacitor C2, and increase the relative area between the capacitor plates to increase the capacitance of the capacitor.

[0112] It should be noted that the provision of the first compensation plate CP1 can increase the capacitance of the first capacitor C1 and the second capacitor C2, and considering the narrow frame, the present application can reduce the area of ​​the original first capacitor C1 and the second capacitor C2 by half, that is, the reduction in the area of ​​the first capacitor C1 and the second capacitor C2 reduces the relative area between the capacitor plates, and the provision of the first compensation plate CP1 compensates for the reduction in the capacitance of the first capacitor C1 and the second capacitor C2, which is equivalent to reducing the area ratio of the first capacitor C1 and the second capacitor C2 in the non-display area NA, but the capacitance of the first capacitor C1 and the second capacitor C2 does not change, thereby realizing the narrow frame design of the product.

[0113] In this embodiment, the orthographic projections of the sixth electrode plate C3b and the eighth electrode plate C4b on the base substrate 110 are located within the orthographic projection of the second compensation electrode plate CP2 on the base substrate 110, that is, the area of ​​the second compensation electrode plate CP2 of the third capacitor C3 is larger than the area of ​​the sixth electrode plate C3b, that is, the area of ​​the second compensation electrode plate CP2 of the fourth capacitor C4 is larger than the area of ​​the eighth electrode plate C4b.

[0114] In this embodiment, since no other structure is set in the shading layer 121 in the non-display area NA, the area of ​​the second compensation plate CP2 of the present application can be larger than the upper capacitor plate to increase the relative area of ​​the second compensation plate CP2 and the upper capacitor plate, thereby increasing the capacitance of the capacitor.

[0115] In the present embodiment, since the third capacitor C3 is used to maintain the potential of the gate of the first output transistor T9, and the fourth capacitor C4 is used to maintain the potential of the gate of the second output transistor T10, and since the gate driving unit of the present application is used to output a compensation control signal or a reset control signal, and the compensation control signal or the reset control signal is an effective level when the high level is high, in order to maintain the stability of the high-level signal, the load of the fourth capacitor C4 of the present application is greater than the load of the third capacitor C3, that is, the capacitance of the fourth capacitor C4 of the present application is greater than the capacitance of the third capacitor C3; and in order to make the capacitance of the fourth capacitor C4 greater than the capacitance of the third capacitor C3, the present application can make the area of ​​the second compensation plate CP2 in the third capacitor C3 greater than the area of ​​the second compensation plate CP2 in the fourth capacitor C4, and increase the relative area between the capacitor plates to increase the capacitance of the capacitor.

[0116] It should be noted that, since the patterns of the electrodes in the first output transistor T9 and the second output transistor T10 are arranged relatively closely, and the plates of the capacitors have trunk gate reuse, even if the second compensation plate CP2 is set, the width reduction of the third capacitor C3 and the fourth capacitor C4 is relatively limited; that is, when the capacitance of the original third capacitor C3 and the fourth capacitor C4 is sufficient, the present application may not need to set the second compensation plate CP2; secondly, while ensuring that the areas of the third capacitor C3 and the fourth capacitor C4 remain unchanged, the present application may increase the capacitance of the third capacitor C3 and the fourth capacitor C4 through the setting of the second compensation plate CP2 to maintain the stability of the first node and the second node in the corresponding stage.

[0117] It should be noted that, since the first capacitor C1 and the second capacitor C2 are storage capacitors, and the third capacitor C3 and the fourth capacitor C4 are voltage-stabilizing capacitors, the load of the first capacitor C1 and the second capacitor C2 of the present application is greater than the load of the third capacitor C3 and the fourth capacitor C4, and therefore the capacitance of the storage capacitor of the present application is greater than the capacitance of the voltage-stabilizing capacitor.

[0118] See also Figure 8 and Fig. 9 , Figure 8 is a film layer diagram of the first active layer 123 in the display panel 100 of the present application, Fig. 9 FIG. 1 is a film layer stacking diagram of the first active layer 123 and the first gate layer 125 in the display panel 100 of the present application.

[0119] In this embodiment, the first active layer 123 includes a first active portion T9A of the first output transistor T9 and a second active portion T10A of the second output transistor T10, the first active portion T9A and the second active portion T10A both extend along the first direction X, and the first active portion T9A and the second active portion T10A are connected; the first active portion T9A and the plurality of first branch gates T9Gb partially overlap, the second active portion T10A and the plurality of second branch gates T10Gb partially overlap, and the portion where the first active portion T9A and the plurality of first branch gates T9Gb overlap is the channel of the first output transistor T9, and the portion where the second active portion T10A and the plurality of second branch gates T10Gb overlap is the channel of the second output transistor T10.

[0120] Since the second output transistor T10 is used to control the output of a low level to quickly turn off the pixel transistors in the display area AA, the second output transistor T10 needs a stronger output capability; see Figure 8 and Fig. 9In the second direction Y, the width of the first active portion T9A is smaller than the width of the second active portion T10A. The increase in the width of the second active portion T10A increases the width of the second active portion T10A, thereby increasing the driving capability of the second output transistor T10.

[0121] In this embodiment, the first active layer 123 also includes an active portion T1A of a first transistor T1, an active portion T2A of a second transistor T2, an active portion T3A of a third transistor T3, an active portion T4A of a fourth transistor T4, an active portion T5A of a fifth transistor T5, an active portion T6A of a sixth transistor T6, an active portion T7A of a seventh transistor T7, an active portion T8A of an eighth transistor T8, an active portion T11A of an eleventh transistor T11, an active portion T12A of a twelfth transistor T12, an active portion T13A of a thirteenth transistor T13, an active portion T14A of a fourteenth transistor T14, an active portion T15A of a fifteenth transistor T15, and an active portion T16A of a sixteenth transistor T16; at the same time, the active portions of the above transistors all have overlapping portions with the gates of the corresponding transistors, and the overlapping portions are channels of the corresponding transistors.

[0122] In this embodiment, the active portion T2A of the second transistor T2 , the active portion T6A of the sixth transistor T6 , and the active portion T16A of the sixteenth transistor T16 extend along the second direction Y, and the active portions of the remaining transistors are all along the first direction X.

[0123] In this embodiment, the active portion T7A of the seventh transistor T7, the active portion T8A of the eighth transistor T8, the active portion T13A of the thirteenth transistor T13, the active portion T12A of the twelfth transistor T12 and the active portion T16A of the sixteenth transistor T16 are connected in sequence in the first direction X, the active portion T5A of the fifth transistor T5 and the active portion T11A of the eleventh transistor T11 are connected, and the active portions of the remaining transistors are arranged separately from each other.

[0124] See also Fig.10 and Fig.11 , Fig.10 1 is a film layer diagram of the light shielding layer 121 and the second active layer 127 in the display panel 100 of the present application. Fig.11 1 is a film layer stacking diagram of the first active layer 123 , the second active layer 127 and the first gate layer 125 in the display panel 100 of the present application.

[0125] In this embodiment, the second active layer 127 includes a first plate C1a of the first capacitor C1, a third plate C2a of the second capacitor C2, a fifth plate C3a of the third capacitor C3 and a seventh plate C4a of the fourth capacitor C4. The first plate C1a and the second plate C1b are at least partially overlapped, the third plate C2a and the fourth plate C2b are at least partially overlapped, the fifth plate C3a and the sixth plate C3b are at least partially overlapped, and the seventh plate C4a and the eighth plate C4b are at least partially overlapped.

[0126] See also Fig.11 In order to increase the capacitance of the storage capacitor and the voltage-stabilizing capacitor, the present application makes the area of ​​the first plate C1a larger than the area of ​​the second plate C1b, and the area of ​​the third plate C2a larger than the area of ​​the fourth plate C2b, which is equivalent to the area of ​​the first capacitor plate Ca of the present application being larger than the area of ​​the second capacitor plate Cb; at the same time, the area of ​​the fifth plate C3a is larger than the area of ​​the sixth plate C3b, and the area of ​​the seventh plate C4a is larger than the area of ​​the eighth plate C4b, that is, the orthographic projection of the second plate C1b on the second active layer 127 is located in the first plate C1a, the orthographic projection of the fourth plate C2b on the second active layer 127 is located in the third plate C2a, the orthographic projection of the sixth plate C3b on the second active layer 127 is located in the fifth plate C3a, and the orthographic projection of the eighth plate C4b on the second active layer 127 is located in the seventh plate C4a.

[0127] It should be noted that, since the first electrode plate C1a needs to be connected to the sixteenth transistor T16, a conductive structure connected to the sixteenth transistor T16 is provided in the first electrode plate C1a of the present application, and the region thereof does not overlap with the second electrode plate C1b.

[0128] See also Fig.11 The fifth electrode plate C3a includes a first trunk electrode plate C3aa and a plurality of first branch electrodes C3ab connected to the first trunk electrode plate C3aa, the first trunk electrode plate C3aa extends along the first direction X, the plurality of first branch electrodes C3ab extends along the second direction Y, and the plurality of first branch electrodes C3ab are spaced apart in the first direction X, the first trunk electrode plate C3aa at least partially overlaps with the first trunk gate T9Ga, the first branch electrode plate C3ab at least partially overlaps with the corresponding first branch gate T9Gb, and the length of the first branch electrode plate C3ab is less than the length of the first branch gate T9Gb.

[0129] See also Fig.11The seventh electrode plate C4a includes a second trunk electrode plate C4aa and a plurality of second branch electrodes C4ab connected to the second trunk electrode plate C4aa, the second trunk electrode plate C4aa extends along the first direction X, the plurality of second branch electrodes C4ab extend along the second direction Y, and the plurality of second branch electrodes C4ab are spaced apart in the first direction X, the second trunk electrode plate C4aa at least partially overlaps with the second trunk gate T10Ga, the second branch electrode plate C4ab at least partially overlaps with the corresponding second branch gate T10Gb, and the length of the second branch electrode plate C4ab is less than the length of the second branch gate T10Gb.

[0130] exist Fig.11 In the structure, in order to increase the capacitance of the third capacitor C3 and the fourth capacitor C4, the present application further increases the capacitance of the corresponding capacitor by setting multiple branch plates in the fifth plate C3a and the seventh plate C4a, and overlapping the branch plates with the corresponding branch gates.

[0131] See also Fig.11 Since the width of the first trunk gate T9Ga is smaller than the width of the second trunk gate T10Ga, the overlapping area of ​​the first trunk gate T9Ga and the first trunk plate C3aa is smaller than the overlapping area of ​​the second trunk gate T10Ga and the second trunk plate C4aa. In order to reduce the difference in capacitance between the third capacitor C3 and the fourth capacitor C4, the present application can make the length of the first branch plate C3ab greater than the length of the second branch plate C4ab in the second direction Y, that is, the area of ​​the fifth plate C3a is greater than the area of ​​the seventh plate C4a, thereby reducing the difference in capacitance between the third capacitor C3 and the fourth capacitor C4.

[0132] In this embodiment, the overlapping area between the fifth electrode plate C3a and the first grid electrode T9G may be greater than or equal to the overlapping area between the seventh electrode plate C4a and the second grid electrode T10G.

[0133] See also Figure 6 and Fig.10 In order to simplify the wiring of the storage capacitor, the first compensation plate CP1 of the present application is electrically connected to the first capacitor plate Ca through an electrical connector CTE. The electrical connector CTE can be set in the first source-drain layer 131. One end of the electrical connector CTE is electrically connected to the first capacitor plate Ca through a via hole, and the other end of the electrical connector CTE is electrically connected to the second capacitor plate Cb through a via hole, so that the first compensation plate CP1 and the upper capacitor plate are connected in series, which is equivalent to moving the plate originally set in the second active layer 127 to the light shielding layer 121, thereby reducing the area of ​​the capacitor plates in the second active layer 127 and the first gate layer 125.

[0134] It should be noted that, since no other structures are set in the light shielding layer 121 in the non-display area NA, the area of ​​the first compensation plate CP1 of the present application can be set large enough to increase the relative area of ​​the first compensation plate CP1 and the upper capacitor plate, thereby increasing the capacitance of the capacitor; for example, the difference between the area of ​​the first compensation plate CP1 and the area of ​​the first capacitor plate Ca can be greater than the difference between the area of ​​the first capacitor plate Ca and the area of ​​the second capacitor plate Cb.

[0135] See also Fig.12 and Fig.13 , Fig.12 is a film layer diagram of the second gate layer 129 in the display panel 100 of the present application, Fig.13 1 is a film layer stack diagram of the first active layer 123 , the second active layer 127 , the first gate layer 125 and the second gate layer 129 in the display panel 100 of the present application.

[0136] In this embodiment, the second gate layer 129 includes a first output segment 129a and a second output segment 129b. The first output segment 129a and the second output segment 129b extend along the second direction Y. The first output segment 129a is arranged close to the second output transistor T10 and extends toward an end away from the second output transistor T10. The second output segment 129b is arranged on a side of the first electrode plate C1a away from the third electrode plate C2a.

[0137] In this embodiment, the first output segment 129a is connected to the drain of the first output transistor T9 and the second output transistor T10 to transmit the control signal output by the gate driving unit 200a of the present application to the surface; the second output segment 129b is connected to the gate driving unit 200a that outputs the light-emitting control signal EM, which is equivalent to the gate driving unit 200a that outputs the light-emitting control signal EM transmitting the light-emitting control signal EM to the display area AA through the second output segment 129b and other output segments.

[0138] See also Fig.14 and Fig.15 , Fig.14 1 is a film layer diagram of the first source-drain electrode layer 131 in the display panel 100 of the present application. Fig.15 1 is a film layer stack diagram of the first active layer 123 , the second active layer 127 , the first gate layer 125 , the second gate layer 129 and the first source and drain layer 131 in the display panel 100 of the present application.

[0139] In this embodiment, the display panel 100 also includes a first source-drain layer 131 disposed on a side of the second active layer 127 away from the first active layer 123, and the first source-drain layer 131 includes a first source T9S and a first drain T9D of the first output transistor T9, and a second source T10S and a second drain T10D of the second output transistor T10.

[0140] In this embodiment, the first drain T9D includes a first main drain T9Da and a plurality of first branch drains T9Db connected to the first main drain T9Da, the first main drain T9Da extends along a first direction X, and the plurality of first branch drains T9Db extend along a second direction Y; for example Fig.14 In the structure, the first drain T9D includes one first main drain T9Da and three first branch drains T9Db, and the first main drain T9Da is arranged away from the display area AA.

[0141] In this embodiment, the first source T9S includes a first main source T9Sa and a plurality of first branch sources T9Sb connected to the first main source T9Sa, the first main source T9Sa extends along a first direction X, and the plurality of first branch sources T9Sb extend along a second direction Y; for example Fig.14 In the structure, the first source T9S includes one first main source T9Sa and two first branch sources T9Sb, and the first main source T9Sa is arranged on a side of the first main drain T9Da close to the display area AA.

[0142] See also Fig.14 and Fig.15 , a plurality of first branch source electrodes T9Sb are spaced apart in the first direction X, a plurality of first branch source electrodes T9Sb and a plurality of first branch drain electrodes T9Db are spaced apart in the first direction X, and a first branch gate electrode T9Gb is disposed between adjacent first branch source electrodes T9Sb and first branch drain electrodes T9Db.

[0143] In this embodiment, the second drain T10D includes a second main drain T10Da and a plurality of second branch drains T10Db connected to the second main drain T10Da, the second main drain T10Da extends along the first direction X, and the plurality of second branch drains T10Db extend along the second direction Y; for example Fig.14 In the structure, the second drain T10D includes one second main drain T10Da and three second branch drains T10Db, and the second main drain T10Da is arranged close to the display area AA.

[0144] In this embodiment, the second source T10S includes a second main source T10Sa and a plurality of second branch sources T10Sb connected to the second main source T10Sa, the second main source T10Sa extends along the first direction X, and the plurality of second branch sources T10Sb extends along the second direction Y; for example Fig.14 In the structure, the second source T10S includes one second main source T10Sa and two second branch sources T10Sb, and the second main source T10Sa is arranged on a side of the second main drain T10Da away from the display area AA.

[0145] See also Fig.14 and Fig.15 , a plurality of second branch source electrodes T10Sb are spaced apart in the first direction X, a plurality of second branch source electrodes T10Sb and a plurality of second branch drain electrodes T10Db are spaced apart in the first direction X, and a second branch gate electrode T10Gb is disposed between adjacent second branch source electrodes T10Sb and second branch drain electrodes T10Db.

[0146] See also Fig.14 and Fig.15 The first trunk drain T9Da, the first trunk gate T9Ga and the fifth electrode C3a are at least partially overlapped, and the second trunk source T10Sa, the second trunk gate T10Ga and the seventh electrode C4a are at least partially overlapped.

[0147] See also Fig.14 and Fig.15 A second branch drain T10Db close to the first output transistor T9 among the plurality of second branch drains T10Db is shared with a first branch drain T9Db close to the second output transistor T10 among the plurality of first branch drains T9Db.

[0148] See also Fig.14 and Fig.15 The display panel 100 includes a plurality of first contact holes HL1 and a plurality of second contact holes HL2 disposed in the region where the first output transistor T9 is located, the first drain electrode T9D is connected to the first active portion T9A through the plurality of first contact holes HL1, and the first source electrode T9S is connected to the first active portion T9A through the plurality of second contact holes HL2.

[0149] See also Fig.14 and Fig.15 The display panel 100 includes a plurality of third contact holes HL3 and a plurality of fourth contact holes HL4 disposed in the region where the second output transistor T10 is located, the second drain electrode T10D is connected to the first active portion T9A through the plurality of third contact holes HL3, and the second source electrode T10S is connected to the first active portion T9A through the plurality of fourth contact holes HL4.

[0150] In the present embodiment, the first contact hole HL1 , the second contact hole HL2 , the third contact hole HL3 and the fourth contact hole HL4 penetrate the second insulating layer 126 , the third insulating layer 128 , the fourth insulating layer 130 and a portion of the first insulating layer 124 .

[0151] See also Fig.14 and Fig.15 The first source-drain electrode layer 131 includes a first connection segment 401 , one end of which is connected to the second main source electrode T10Sa, and the other end of which is connected to the active portion T8A of the eighth transistor T8 through a via hole.

[0152] See also Fig.14 and Fig.15 The first source-drain electrode layer 131 includes a second connection segment 402, one end of the second connection segment 402 is connected to the second trunk gate T10Ga through a via hole, and the other end of the second connection segment 402 is connected to one end of the active portion T7A of the seventh transistor T7 through a via hole.

[0153] See also Fig.14 and Fig.15 The first source-drain electrode layer 131 includes a third connection segment 403 , one end of the third connection segment 403 is connected to the first clock signal line XCK through a via hole, and the other end of the third connection segment 403 is connected to the gate T7G of the seventh transistor T7 through a via hole.

[0154] See also Fig.14 and Fig.15 The first source-drain layer 131 includes a fourth connection segment 404, one end of the fourth connection segment 404 is connected to the other end of the active portion T7A of the seventh transistor T7 through a via hole, the other end of the fourth connection segment 404 is connected to one end of the active portion T6A of the sixth transistor T6 through a via hole, and the middle segment of the fourth connection segment 404 is connected to the third electrode plate C2a of the second capacitor C2 through a via hole.

[0155] See also Fig.14 and Fig.15 The first source-drain electrode layer 131 includes a fifth connection segment 405, one end of which is connected to the other end of the gate T7G of the seventh transistor T7 through a via hole, and the other end of the fifth connection segment 405 is connected to the other end of the active portion T6A of the sixth transistor T6 through a via hole.

[0156] See also Fig.14 and Fig.15 The first source-drain layer 131 includes a sixth connection segment 406, one end of which is connected to one end of the active portion T3A of the third transistor T3 through a via hole, and the other end of which is connected to one end of the active portion T14A of the fourteenth transistor T14 through a via hole.

[0157] See also Fig.14 and Fig.15 The first source-drain layer 131 includes a seventh connection segment 407, one end of the seventh connection segment 407 is connected to the other end of the active portion T14A of the fourteenth transistor T14 through the via hole, and the other end of the seventh connection segment 407 is connected to one end of the active portion T15A of the fifteenth transistor T15 through the via hole.

[0158] See also Fig.14 and Fig.15 The first source-drain electrode layer 131 includes an eighth connection segment 408 , one end of the eighth connection segment 408 is connected to the other end of the active portion T15A of the fifteenth transistor T15 through a via hole, and the other end of the eighth connection segment 408 is connected to the second plate C1b of the first capacitor C1 through a via hole.

[0159] See also Fig.14 and Fig.15 The first source-drain electrode layer 131 includes a ninth connection segment 409 , one end of the ninth connection segment 409 is connected to the first electrode plate C1a of the first capacitor C1 through a via hole, and the other end of the ninth connection segment 409 is connected to one end of the active portion T2A of the second transistor T2 through a via hole.

[0160] See also Fig.14 and Fig.15 The first source-drain electrode layer 131 includes a tenth connection segment 410 , one end of which is connected to the other end of the active portion T2A of the second transistor T2 through a via hole, and the other end of the tenth connection segment 410 is connected to the second clock signal line CK through a via hole.

[0161] See also Fig.14 and Fig.15 The first source-drain electrode layer 131 includes an eleventh connection segment 411, one end of the eleventh connection segment 411 is connected to the other end of the active portion T3A of the third transistor T3 through the via hole, and the other end of the eleventh connection segment 411 is connected to one end of the gate T6G of the sixth transistor T6 through the via hole.

[0162] See also Fig.14 and Fig.15 The first source-drain layer 131 includes a twelfth connection segment 412 , one end of which is connected to the other end of the gate T6G of the sixth transistor T6 through a via hole, and the other end of the twelfth connection segment 412 is connected to the active portion T11A of the eleventh transistor T11 through a via hole.

[0163] See also Fig.14 and Fig.15The first source-drain electrode layer 131 includes a thirteenth connection segment 413 , one end of the thirteenth connection segment 413 is connected to the active portion T16A of the sixteenth transistor T16 through the via hole, and the other end of the thirteenth connection segment 413 is connected to the second plate C1b of the first capacitor C1 through the via hole.

[0164] See also Fig.14 and Fig.15 The first source-drain layer 131 includes a fourteenth connection segment 414, one end of the fourteenth connection segment 414 is connected to one end of the active portion T4A of the fourth transistor T4 through a via hole, the other end of the fourteenth connection segment 414 is connected to the gate T12G of the twelfth transistor T12 through a via hole, a first connection area in the middle of the fourteenth connection segment 414 is connected to the gate T15G of the fifteenth transistor T15 through a via hole, and a second connection area in the middle of the fourteenth connection segment 414 is connected to the second low potential line VGL2 through a via hole.

[0165] See also Fig.14 and Fig.15 The first source-drain layer 131 includes a fifteenth connection segment 415, one end of the fifteenth connection segment 415 is connected to the other end of the active portion T4A of the fourth transistor T4 through the via hole, the other end of the fifteenth connection segment 415 is connected to the gate T1G of the first transistor T1 through the via hole, and the middle segment of the fifteenth connection segment 415 is connected to one end of the active portion T11A of the eleventh transistor T11 through the via hole.

[0166] See also Fig.14 and Fig.15 The first source-drain electrode layer 131 includes a sixteenth connection segment 416, one end of which is connected to the end of the gate T8G of the eighth transistor T8 through the via hole, and the other end of which is connected to the active portion T12A of the twelfth transistor T12 through the via hole.

[0167] See also Fig.14 and Fig.15 The first source-drain electrode layer 131 includes a seventeenth connection segment 417, one end of the seventeenth connection segment 417 is connected to one end of the active portion T5A of the fifth transistor T5 through the via hole, and the other end of the seventeenth connection segment 417 is connected to the first clock signal line XCK through the via hole.

[0168] See also Fig.14 and Fig.15 The first source-drain layer 131 includes an eighteenth connection segment 418, one end of the eighteenth connection segment 418 is connected to the other end of the active portion T16A of the sixteenth transistor T16 through a via hole, and the other end of the eighteenth connection segment 418 is connected to the first trunk gate T9Ga of the first output transistor T9 through a via hole.

[0169] See also Fig.14 and Fig.15 The first source-drain electrode layer 131 includes a nineteenth connection segment 419 , one end of the nineteenth connection segment 419 is connected to the first electrode plate C1a of the first capacitor C1 through the via hole, and the other end of the nineteenth connection segment 419 is connected to one end of the first transistor T1 through the via hole.

[0170] See also Fig.14 and Fig.15 The first source-drain layer 131 includes a twentieth connection segment 420 , one end of the twentieth connection segment 420 is connected to the other end of the first transistor T1 through a via hole, and the other end of the twentieth connection segment 420 is connected to the second high potential line VGH2 through a via hole.

[0171] See also Fig.14 and Fig.15 The first source-drain layer 131 includes a twenty-first connection segment 421, one end of the twenty-first connection segment 421 is connected to the gate T13G of the thirteenth transistor T13 through the via hole, and the other end of the twenty-first connection segment 421 is connected to the control line Contorol.

[0172] See also Fig.14 and Fig.15 The first source-drain electrode layer 131 includes a twenty-second connection segment 422, one end of the twenty-second connection segment 422 is connected to the second output segment 129b through the via hole, and the first output segment 129a is connected to the second main drain T10Da through the via hole.

[0173] See also Fig.14 and Fig.15 The first source-drain layer 131 includes a twenty-third connecting segment 423, one end of the twenty-second connecting segment 422 is connected to the first main drain T9Da, and the other end of the twenty-third connecting segment 423 is connected to the sixth connecting segment 406 of the next-level gate driving unit 200a to transmit the control signal of this level to the fourth transistor T4 and the fourteenth transistor T14 of the next level.

[0174] See also Fig.16 and Fig.17 , Fig.16 1 is a film layer diagram of the second source-drain electrode layer 133 in the display panel 100 of the present application. Fig.17 1 is a film layer stack diagram of the first active layer 123 , the second active layer 127 , the first gate layer 125 , the second gate layer 129 , the first source-drain electrode layer 131 , and the second source-drain electrode layer 133 in the display panel 100 of the present application.

[0175] In this embodiment, the display panel 100 also includes a second source and drain layer 133 arranged on the side of the first source and drain layer 131 away from the second active layer 127, the second source and drain layer 133 includes a first high potential line VGH1 and a first low potential line VGL1, the first high potential line VGH1 and the first low potential line VGL1 extend along the first direction X, the first high potential line VGH1 is electrically connected to at least one second branch drain T10Db, and the first low potential line VGL1 is electrically connected to at least one first branch drain T9Db.

[0176] exist Fig.16 In the structure, the second source-drain layer 133 includes two first high potential lines VGH1 and one first low potential line VGL1, the first low potential line VGL1 is connected to the first branch source T9Sb of the first transistor T1, and the two first high potential lines VGH1 are both connected to the second branch source T10Sb of the second transistor T2.

[0177] In this embodiment, the first high potential line VGH1 and the first low potential line VGL1 both extend along the first direction X and are arranged along the second direction Y. The first low potential line VGL1 is disposed close to the display area AA, and the two first high potential lines VGH1 are disposed away from the display area AA. The width of the first low potential line VGL1 is greater than the width of any first high potential line VGH1.

[0178] In this embodiment, the second source-drain layer 133 further includes a second low potential line VGL2, an initial signal line STV, a first clock signal line XCK, a second clock signal line CK, a second high potential line VGH2 and a control line Contorol extending along the first direction X and arranged in sequence along the second direction Y. The control line Contorol is arranged adjacent to the first high potential line VGH1.

[0179] It should be noted that the initial signal line STV is only connected to the sixth connection segment 406 in the first-stage gate driving unit 200a, and the sixth connection segment 406 in the second-stage and above gate driving units 200a is connected to the output end of the output circuit 222 of the previous-stage gate driving unit 200a.

[0180] It should be noted that in order to increase the wiring space of the present application, the conductor parts located in the first active layer 123 and on both sides of the channel in some transistors of the present application are reused as the source or drain of the corresponding transistor, and there is no need to separately set the source or drain of the corresponding transistor in the first source and drain layer 131.

[0181] It should be noted that the third gate circuit 230, the fourth gate circuit 240, and the fifth gate circuit 250 of the present application are also applicable to the technical solution of the present application. For example, a capacitor plate located in the light-shielding layer is provided in the storage capacitor and / or the voltage-stabilizing capacitor of the above three gate circuits to reduce the space occupied by the storage capacitor and / or the voltage-stabilizing capacitor in the corresponding gate circuit to achieve a narrow frame design; or while keeping the area unchanged, the capacitance of the storage capacitor and / or the voltage-stabilizing capacitor is increased to improve the control of the capacitor over the corresponding node potential.

[0182] The present application also provides a display device, which includes the above-mentioned display panel. The display device can be: a mobile phone, a tablet computer, a television, a monitor, a notebook computer, a digital photo frame, a navigator, or any other product or component with a display function.

[0183] In the description of this application, the terms "first" and "second" are used for descriptive purposes only and should not be understood as indicating or implying relative importance or implicitly indicating the number of technical features indicated. Thus, a feature defined as "first" or "second" may explicitly or implicitly include one or more features. In the description of this application, the meaning of "plurality" is two or more, unless otherwise clearly and specifically defined.

[0184] In the above embodiments, the description of each embodiment has its own emphasis. For parts that are not described in detail in a certain embodiment, reference can be made to the relevant descriptions of other embodiments.

[0185] In the above embodiments, the structures shown in the drawings are only schematic diagrams, and the specific structure of the display panel of the present application is mainly based on the description.

[0186] The embodiments, implementation methods and related technical features of the present application can be combined and replaced with each other without conflict.

[0187] The above are only preferred embodiments of the present application and do not constitute any form of limitation to the present application. However, any simple modifications, equivalent changes and modifications made to the above embodiments based on the technical essence of the present application without departing from the content of the technical solution of the present application are still within the scope of the technical solution of the present application.

Claims

1. A display panel, characterized in that: A plurality of gate driving units are included, wherein the gate driving units include gate transistors and storage capacitors connected to each other, wherein the active portion of the gate transistors is located on a first active layer, the first capacitor plate of the storage capacitor is located on a second active layer, and the gate of the gate transistor and the second capacitor plate of the storage capacitor are located on the first gate layer; The storage capacitor further includes a first compensation plate disposed opposite to the first capacitor plate and the second capacitor plate, and the first compensation plate is disposed in a different layer from the second active layer and the first gate layer.

2. The display panel according to claim 1, characterized in that: The display panel includes a base substrate and a light shielding layer disposed on the base substrate, the light shielding layer is disposed between the base substrate and the first active layer, and the first gate layer is disposed between the first active layer and the second active layer; Wherein, the first compensation electrode is located in the light shielding layer.

3. The display panel according to claim 2, characterized in that: The area of ​​the first compensation plate is larger than the area of ​​the first capacitor plate, and the area of ​​the first capacitor plate is larger than the area of ​​the second capacitor plate.

4. The display panel according to claim 3, characterized in that: A difference between an area of ​​the first compensation plate and an area of ​​the first capacitor plate is greater than a difference between an area of ​​the first capacitor plate and an area of ​​the second capacitor plate.

5. The display panel according to claim 2, characterized in that: The first compensation electrode plate is electrically connected to the first capacitor electrode plate through an electrical connector.

6. The display panel according to any one of claims 2 to 5, characterized in that: The display panel comprises an output circuit and a receiving circuit, the storage capacitor is located in the receiving circuit, the output circuit comprises a voltage-stabilizing capacitor, one capacitor plate of the voltage-stabilizing capacitor is located in the second active layer, and the other capacitor plate of the voltage-stabilizing capacitor is located in the first gate layer; Wherein, an orthographic projection area of ​​one of the voltage-stabilizing capacitors on the substrate is smaller than or equal to an orthographic projection area of ​​one of the storage capacitors on the substrate.

7. The display panel according to claim 6, characterized in that: The light shielding layer further includes a second compensation plate corresponding to the voltage-stabilizing capacitor, and the second compensation plate is electrically connected to a capacitor plate in the voltage-stabilizing capacitor located in the second active layer.

8. The display panel according to claim 6, characterized in that: The receiving circuit includes a first node control module and a second node control module, the first output transistor and the first node control module are connected to the first node, the second output transistor and the second node control module are connected to the second node, the first node is electrically connected to a low potential line, and the second node is electrically connected to a high potential line; The storage capacitor includes a first capacitor and a second capacitor, the first capacitor is connected to the first node, the second capacitor is connected to the second node, and the area of ​​the first compensation plate in the first capacitor is greater than the area of ​​the first compensation plate in the second capacitor.

9. The display panel according to claim 6, characterized in that: The capacitance of the storage capacitor is greater than the capacitance of the voltage-stabilizing capacitor.

10. A display device, characterized in that: The display device comprises the display panel according to any one of claims 1 to 9.

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