Electrostatic discharge (ESD) protection circuit and working method thereof

Abstract

The invention provides an electrostatic discharge (ESD) protection circuit, which comprises a first diode, a second diode and a first electrostatic discharge module, and is characterized in that the anode of the first diode is coupled to an input / output port, and the cathode of the first diode is coupled to a voltage source pin; the cathode of the second diode is coupled to the input / output port and the anode of the first diode, and the anode of the second diode is connected with the first electrostatic discharge module; the first end of the first electrostatic discharge module is connected with the anode of the second diode, and the second end of the first electrostatic discharge module is coupled with a ground pin. According to the circuit, positive and negative voltage input and output of the input and output port can be realized, the electrostatic discharge protection requirement is met, and latch-up can be prevented.

Description

Technical Field

[0001] The present invention relates to the field of circuits, and in particular to an electrostatic discharge (ESD) circuit and a working method thereof. Background Art

[0002] The recent trend of miniaturizing integrated circuits (ICs) has resulted in smaller devices that consume less power but offer higher speeds than before. The miniaturization process has also increased the device's susceptibility to electrostatic discharge (ESD) events due to various factors, such as thinner dielectric layer thickness and the associated reduced dielectric breakdown voltage. ESD is one of the causes of damage to electronic circuits and a consideration in semiconductor advanced technology.

[0003] In the traditional ESD solution, the input / output (IO) pins are composed of N-type MOS tubes and P-type MOS tubes, so that there is a parasitic diode between the IO and the ground, with the anode of the parasitic diode connected to the ground and the cathode connected to the IO. Because there is a parasitic diode between the input / output (IO) port and the ground, when the IO port outputs a negative voltage, the parasitic diode will be turned on, embedding the input / output voltage of the IO, and may even cause the risk of double locking of the chip.

[0004] In traditional solutions, when the voltage of the IO port is lower than -0.6V, the parasitic diode will turn on. The larger the voltage difference, the greater the leakage. Under extreme conditions, the latch effect will be triggered, and even chip burning will occur. Therefore, traditional IO cannot support negative voltage applications below -0.6V.

[0005] In order to meet the electrostatic discharge protection requirements of positive and negative voltage IO, a new electrostatic discharge protection circuit needs to be designed. Summary of the invention

[0006] Based on the above situation, the main purpose of the present invention is to provide an electrostatic discharge protection circuit and a working method thereof, which can meet the requirements of input and output electrostatic discharge protection with positive and negative voltage resistance and can prevent latch-up.

[0007] To achieve the above object, the present invention provides an electrostatic discharge protection circuit, comprising: a first diode, a second diode, and a first electrostatic discharge module, wherein:

[0008] The anode of the first diode is coupled to the input / output port, and the cathode of the first diode is coupled to the voltage source pin; the cathode of the second diode is coupled to the input / output port and the anode of the first diode, and the anode of the first diode is connected to the first electrostatic discharge module; the first end of the first electrostatic discharge module is connected to the anode of the second diode, and the second end is coupled to the ground pin; when the operating voltage of the input / output port is a negative voltage, and the absolute value of the operating voltage is less than or equal to V1+VD, the first electrostatic discharge module and the second diode are cut off, and when the input / output port receives a negative ESD voltage, and the absolute value of the negative ESD voltage is greater than V1+VD, the negative charge of the negative ESD voltage is released to the ground pin through the second diode and the first electrostatic discharge module; wherein VD is the absolute value of the critical voltage drop of the second diode being turned on, and V1 is the absolute value of the critical voltage drop of the first electrostatic discharge module being turned on.

[0009] Preferably, the circuit further comprises a second electrostatic discharge module, one end of which is coupled to the voltage source pin, and the other end of which is coupled to the ground pin.

[0010] Preferably, the first electrostatic discharge module includes a P-type MOS tube.

[0011] Preferably, the drain of the P-type MOS tube is connected to the anode of the second diode, the source of the P-type MOS tube is connected to the ground pin, and the gate of the P-type MOS tube is connected to the ground pin through a resistor R0.

[0012] Preferably, the gate of the P-type MOS tube is connected to the anode of the second diode through a capacitor C0.

[0013] Preferably, the first electrostatic discharge module includes an N-type MOS transistor.

[0014] Preferably, the source of the N-type MOS tube is connected to the anode of the second diode, the drain of the N-type MOS tube is connected to the ground pin, and the gate of the N-type MOS tube is connected to the anode of the second diode through a resistor R0.

[0015] Preferably, the gate of the N-type MOS tube is connected to the ground pin via a capacitor C0.

[0016] Preferably, the second electrostatic discharge module is a power clamp circuit.

[0017] The present invention also provides a layout of an electrostatic discharge protection circuit, comprising: the first diode, the second diode, the first electrostatic discharge module, a p+ isolation ring, an N-type well and a deep N-type well as claimed in claim 1, wherein the N-type well surrounds the first diode, the deep N-type well surrounds the second diode and the first electrostatic discharge module, and the p+ isolation ring surrounds the N-type well and the deep N-type well.

[0018] Preferably, the cathodes of the first diode and the second diode surround the anode, and the N-type well surrounds the cathode of the first diode.

[0019] Preferably, when the first electrostatic discharge module includes a MOS tube, the drain of the MOS tube is located between two silicided barrier layers, the outer sides of the two silicided barrier layers are gates, the outer sides of the two gates are sources, and the substrate of the MOS tube surrounds the source, the gate, the drain and the silicided barrier layers.

[0020] The present invention also provides a working method of an electrostatic discharge protection circuit, wherein the voltage source pin is connected to a positive power supply VCC, the first electrostatic discharge module is selected so that the value of V1+VD is equal to VCC, and the working method comprises:

[0021] When the voltage of the input / output port is between 0V and VCC, the first diode, the second diode and the first electrostatic discharge module are all cut off;

[0022] When the voltage of the input / output port is between 0V and -VCC, the first diode is turned off, and the second diode and the first electrostatic discharge module are also turned off, so that the input / output port can work normally within the range of -VCC to VCC.

[0023] Preferably, the working method further comprises:

[0024] When the input / output port receives a positive ESD voltage, the first diode is turned on, and positive charges of the positive ESD voltage flow into the voltage source pin through the first diode, wherein the positive ESD voltage is higher than a voltage VCC of the voltage source pin.

[0025] Preferably, the working method further comprises:

[0026] When the input / output port receives a negative ESD voltage, the second diode is turned on by the first electrostatic discharge module, and the negative charge of the negative ESD voltage is released to the ground pin through the second diode and the first electrostatic discharge module, wherein the absolute value of the negative ESD voltage is greater than V1+VD.

[0027] The present invention also provides a chip, comprising the electrostatic discharge protection circuit as described above.

[0028] The present invention also provides an LED lamp, comprising the chip as described above.

[0029] The electrostatic discharge (ESD) protection circuit provided by the present invention connects a voltage source pin, a first diode, a second diode, a first electrostatic discharge module and a ground pin in series in sequence, and the input and output ports are located between the first diode and the second diode. There is no parasitic diode between the input and output ports and the ground. When the operating voltage of the input and output ports is a negative voltage and the value is less than or equal to V1+VD, the input and output ports can normally output negative voltages. Compared with the solution in the prior art in which the input and output ports are only grounded through the second diode, the input and output ports can normally output a larger negative voltage range and can support more negative voltage application scenarios. Within the negative voltage range, there will be no risk of large current being injected into the substrate to trigger latching or chip burning.

[0030] When the first electrostatic discharge module is selected so that the value of V1+VD is equal to VCC, when the input and output ports operate at a voltage range of -VCC to VCC (output or input voltage in this range), the first diode and the second diode are both cut off, and the first electrostatic discharge module is also cut off. Therefore, the normal operation of the input and output ports within the voltage range of -VCC to VCC is achieved, and there is no risk of large current being injected into the substrate to trigger latching or burning, and when the input and output ports receive an ESD voltage exceeding the voltage range of -VCC to VCC, the ESD current can be discharged in time.

[0031] The working method of the electrostatic discharge (ESD) protection circuit in the present invention can flexibly realize electrostatic discharge in different electrostatic occasions. BRIEF DESCRIPTION OF THE DRAWINGS

[0032] The preferred embodiments of the electrostatic discharge (ESD) protection circuit and its working method of the present invention will be described below with reference to the accompanying drawings.

[0033] Figure 1 FIG. 4 is a schematic diagram of an electrostatic discharge (ESD) protection circuit according to a preferred embodiment of the present invention.

[0034] Figure 2 FIG. 4 is another schematic diagram of an electrostatic discharge (ESD) protection circuit according to a preferred embodiment of the present invention.

[0035] Figure 3 for Figure 1 and Figure 2 A schematic diagram of a first electrostatic discharge module in FIG. 1 , wherein:

[0036] Figure 3-1It is a Gate-to-Drain PMOS (Gdpmos, gate to drain PMOS) tube;

[0037] Figure 3-2 It is a Gate Couple PMOS (Gcpmos, gate coupled PMOS) tube;

[0038] Figure 3-3 It is a Grounded-gate NMOS (Ggnmos, gate grounded NMOS) tube;

[0039] Figure 3-4 It is a Gate Couple NMOS (Gcnmos, gate coupled NMOS) tube.

[0040] Figure 4 for Figure 2 Schematic diagram of the second electrostatic discharge module in.

[0041] Figure 5 for Figure 1 The specific implementation layout.

[0042] Figure 6 The working method of the electrostatic discharge (ESD) protection circuit.

[0043] Figure 7 Another working method of the electrostatic discharge (ESD) protection circuit. DETAILED DESCRIPTION

[0044] The present invention is described below based on embodiments, but the present invention is not limited to these embodiments. In the following detailed description of the present invention, some specific details are described in detail. In order to avoid confusing the essence of the present invention, known methods, processes, procedures, and components are not described in detail.

[0045] In addition, persons of ordinary skill in the art will appreciate that the drawings provided herein are for illustration purposes and are not necessarily drawn to scale.

[0046] Unless the context clearly requires otherwise, throughout the specification and claims, the words "include", "comprising" and similar words should be interpreted in an inclusive sense rather than an exclusive or exhaustive sense; that is, in the sense of "including but not limited to".

[0047] In the description of the present invention, it should be understood that the terms "first", "second", etc. are only used for descriptive purposes and cannot be understood as indicating or implying relative importance. In addition, in the description of the present invention, unless otherwise specified, "plurality" means two or more.

[0048] Please refer to Figure 1 , Figure 1 Shown is a schematic diagram of an electrostatic discharge (ESD) protection circuit of a preferred embodiment of the present invention. The electrostatic discharge (ESD) protection circuit is included in a chip, which can be an LED chip. One or more of the LED chips can form an LED lamp.

[0049] In this embodiment, the electrostatic discharge (ESD) protection circuit includes: a first diode 110, a second diode 130 and a first electrostatic discharge module 140, wherein the anode of the first diode 110 is coupled to the input / output port 120, and the cathode thereof is coupled to the voltage source pin; the cathode of the second diode 130 is coupled to the input / output port 120 and the anode of the first diode 110, and the anode thereof is connected to the first electrostatic discharge module 140; the first end of the first electrostatic discharge module 140 is connected to the anode of the second diode 130, and the second end is coupled to the ground pin.

[0050] In this embodiment, when the operating voltage (for example, output or output) of the input-output port 120 is a negative voltage and the absolute value of the operating voltage is less than or equal to V1+VD, the first electrostatic discharge module 140 and the second diode 130 are cut off, and when the input-output port 120 receives a negative ESD voltage and the absolute value of the negative ESD voltage is greater than V1+VD, the negative charge of the negative ESD voltage is released to the ground pin through the second diode 130 and the first electrostatic discharge module 140.

[0051] In this embodiment, VD is the absolute value of the critical voltage drop when the second diode 130 is turned on, and V1 is the absolute value of the critical voltage drop when the first electrostatic discharge module 140 is turned on.

[0052] The electrostatic discharge protection circuit in this embodiment connects the voltage source pin, the first diode, the second diode, the first electrostatic discharge module and the ground pin in series in sequence. The input and output ports are located between the first diode and the second diode. There is no parasitic diode between the input and output ports and the ground. When the operating voltage of the input and output ports is a negative voltage and the value is less than or equal to V1+VD, the input and output ports can normally output negative voltages. Compared with the solution in the prior art where the input and output ports are only grounded through the second diode, the input and output ports can normally output a larger negative voltage range and can support more negative voltage application scenarios.

[0053] In this embodiment, the voltage threshold absolute value V1 of the first electrostatic discharge module 140 at which the first electrostatic discharge module 140 is turned on may be 5V to 8V.

[0054] When the above chip is installed in the circuit and works normally: the voltage source pin is connected to the positive voltage source VCC, the ground pin is grounded, and when the voltage (output or input voltage) of the input / output port 120 is 0V to VCC, the first diode 110 and the second diode 130 will not be turned on, so there will be no leakage to the voltage source pin and the ground pin; when the voltage of the input / output port 120 is 0V to -(V1+VD), the first diode 110 is turned off, the input / output port 120 will not leak to the voltage source pin, the first electrostatic discharge module 140 and the second diode 130 are also turned off, so the input / output port 120 will not leak to the ground pin, and will not trigger the latch effect or burn the chip.

[0055] In addition, due to the existence of the first electrostatic discharge module 140 , there is no direct parasitic body diode between the second diode and the ground pin.

[0056] Therefore, when the above chip is installed in the circuit, the electrostatic discharge is as follows: when the input-output port 120 receives a positive ESD voltage, the first diode 110 is turned on, and the positive charge of the positive ESD voltage is conducted to the voltage source pin for discharge through the first diode 110. When the input-output port 120 receives a negative ESD voltage, the first diode 110 is turned off, the second diode 130 and the first electrostatic discharge module 140 are turned on, and the negative charge of the negative ESD voltage is conducted to the ground pin for discharge through the second diode 130 and the first electrostatic discharge module 140.

[0057] In this embodiment, VCC may be 1.8V, 5.5V or 5V.

[0058] In other embodiments of the present invention, VCC may also be 10V, 16V, 20V, 25V or 30V.

[0059] In this embodiment, the positive ESD voltage is generally a very high voltage, such as HBM 2KV.

[0060] It can be understood that, no matter it is a positive ESD voltage or a negative ESD voltage, the absolute value of the voltage is much higher than the voltage of the voltage source pin.

[0061] Please refer to Figure 2 , Figure 2 Another schematic diagram of an electrostatic discharge protection circuit according to a preferred embodiment of the present invention.

[0062] In this embodiment, Figure 1 The electrostatic discharge protection circuit 10 and other common IO circuits (such as Figure 2 20) common voltage source pin and ground pin as shown in FIG.

[0063] In this embodiment, in addition to including Figure 1The electrostatic discharge (ESD) protection circuit 10 in this embodiment further includes a second electrostatic discharge module 30, one end of which is coupled to the voltage source pin, and the other end of which is coupled to the ground pin.

[0064] In this embodiment, the electrostatic discharge (ESD) protection circuit includes at least two normal IO circuits 20 , and the at least two normal IO circuits 20 share the voltage of the voltage source pin and the voltage of the ground pin.

[0065] Please refer to Figure 3 , Figure 3 for Figure 1 and Figure 2 Schematic diagram of the first electrostatic discharge module 140.

[0066] In this embodiment, the first electrostatic discharge module includes a P-type metal oxide semiconductor field effect transistor (MOS). Figure 3-1 The Gate-to-Drain PMOS (Gdpmos) tube in the Figure 3-2 The Gate Couple PMOS (Gcpmos, gate coupled PMOS) tube in.

[0067] Please refer to Figure 3-1 The drain of the P-type MOS tube is connected to the anode of the second diode 130 , the source of the P-type MOS tube is connected to the ground pin, and the gate of the P-type MOS tube is connected to the ground pin through a resistor R0 .

[0068] Please refer to Figure 3-2 Furthermore, the gate of the P-type MOS tube is connected to the anode of the second diode 130 through the capacitor C0. In this embodiment, the P-type MOS tube introduces an RC trigger circuit, which can further reduce the trigger voltage of the P-type MOS tube and improve the turn-on uniformity.

[0069] In another embodiment of the present invention, the first electrostatic discharge module includes an N-type MOS transistor.

[0070] For example, Figure 3-3 The Grounded-gate NMOS (Ggnmos, gate grounded NMOS) tube in the figure, or Figure 3-4 The Gate Couple NMOS (Gcnmos, gate coupled NMOS) tube in.

[0071] Please refer to Figure 3-3The source of the N-type MOS tube is connected to the anode of the second diode 130, the drain of the N-type MOS tube is connected to the ground pin, and the gate of the N-type MOS tube is connected to the anode of the second diode 130 through the resistor R0.

[0072] Please refer to Figure 3-4 The gate of the N-type MOS tube is connected to the ground pin via capacitor C0. In this embodiment, the N-type MOS tube further introduces an RC trigger circuit, which can further reduce the trigger voltage of the N-type MOS tube and improve the turn-on uniformity.

[0073] Please refer to Figure 4 , Figure 4 for Figure 2 Schematic diagram of the second electrostatic discharge module 30.

[0074] The electrostatic discharge protection circuit 10 in this embodiment shares the voltage source pin and the ground pin with other common IO circuits 20 , and can achieve electrostatic discharge in a wider range and prevent latch-up by cooperating with the second electrostatic discharge module 30 .

[0075] In this embodiment, the second electrostatic discharge module 30 is a power clamp circuit.

[0076] In this embodiment, when the input / output port 120 encounters a positive ESD voltage, the positive charge of the positive ESD voltage can be conducted to the common voltage source pin through the first diode 110. When the input / output ports IO2 to IOn encounter a positive ESD voltage, the positive charge of the positive ESD voltage can be conducted to the common voltage source pin through MPESD. At this time, due to the RC delay composed of R1 and C1 in the second electrostatic discharge module 30, the voltage vtg at the RC end is at a low level. After the transistor MP0 (P-type MOS tube) and the transistor MN0 (N-type MOS tube) form an inverter, the output end vg voltage is pulled to a high level, so that the high potential at the vg end triggers the transistor MN1 (N-type MOS tube) to turn on, so that the positive charge of the positive ESD voltage is discharged to the ground pin through MN1.

[0077] Therefore, the electrostatic discharge (ESD) protection circuit in this embodiment shares the voltage source pin and the ground pin with other circuits, and can flexibly realize electrostatic discharge and prevent latch-up by cooperating with the second electrostatic discharge module.

[0078] Please refer to Figure 5 , Figure 5 for Figure 1 The specific implementation layout.

[0079] In this embodiment, the layout of the electrostatic discharge protection circuit includes: a first diode (region 100), a second diode (region 101), a first electrostatic discharge module (region 102), a p+ isolation ring (region 103), an N-type well (region 104) and a deep N-type well (region 108), wherein the N-type well encloses the first diode, the deep N-type well encloses the second diode and the first electrostatic discharge module, and the p+ isolation ring surrounds the N-type well and the deep N-type well.

[0080] In this embodiment, the area 100 corresponds to Figure 1 In the first diode 110. In this embodiment, the first diode 110 is a p-type diode (p+ / NW).

[0081] In this embodiment, the region 101 corresponds to the second diode 130. In this embodiment, the second diode is an n-type diode (n+ / PW).

[0082] In this embodiment, the cathodes of the first diode and the second diode surround the anode, and the N-type well (region 104) surrounds the cathode (region 106) of the first diode.

[0083] In this embodiment, the region 102 corresponds to the first electrostatic discharge module 140. In this embodiment, the first electrostatic discharge module 140 is implemented by NMOS. Figure 3 Figure c or figure d in the figure.

[0084] In this embodiment, the region 101 and the region 102 are separated from the P-type substrate (PSUB) by a deep N-type well (Deep N Well, DNW, region 108), and the potential of the deep N-type well is connected to VCC or left floating.

[0085] In this embodiment, the region 103 is a p+ isolation ring surrounding the region 100 .

[0086] In this embodiment, the region 100 where the first diode 110 is located includes: region 104, region 105 and region 106, wherein region 104 is an N-type well (NW), region 105 is a p+ active region (i.e., the anode of the first diode 110), and region 106 is an n+ active region (i.e., the cathode of the first diode 110). Region 105 is located in the center, region 106 surrounds region 105, and region 104 encloses region 106.

[0087] In this embodiment, region 107 is an n+ isolation ring, and region 108 is a deep N-type well (DNW), wherein region 107 surrounds region 108 , and region 108 encloses region 101 and region 102 .

[0088] In this embodiment, the region 101 where the second diode 120 is located includes region 109 and region 110, wherein region 109 is a p+ active region (i.e., the anode of the first diode 110), region 110 is an n+ active region (i.e., the cathode of the second diode 110), and region 109 surrounds region 110.

[0089] In this embodiment, the region 102 where the first electrostatic discharge module 140 is located includes regions 111, 112, 113, 114, and 115. Region 111 is a p+ substrate contact (i.e., the substrate end of NMOS), region 112 is an n+ active region (i.e., the source end of NMOS), region 114 is an n+ active region (i.e., the drain end of NMOS), region 113 is the gate end of NMOS, and region 115 is a silicide barrier layer. Region 114 is located in the middle of region 102, two regions 115 are respectively located outside region 114, two regions 113 are respectively located outside two regions 115, two regions 112 are respectively located outside two regions 113, and region 111 surrounds region 112, region 113, region 114, and region 115.

[0090] from Figure 5 It can be seen that the electrostatic discharge protection circuit in the present invention is simple to implement.

[0091] The present invention further provides a chip, comprising the electrostatic discharge protection circuit 10 described above.

[0092] The present invention also provides an LED lamp, comprising the above-mentioned chip.

[0093] Please refer to Figure 6 , Figure 6 The present invention shows a working method of an electrostatic discharge protection circuit, which is used for Figure 1 middle.

[0094] In this embodiment, the voltage source pin is connected to a positive power source VCC, the first electrostatic discharge module is selected so that the value of V1+VD is equal to VCC, and the ground pin is grounded.

[0095] The method comprises the following steps:

[0096] In step S300 , when the voltage of the input / output port 120 is between 0V and VCC, the first diode 110 , the second diode 120 and the first electrostatic discharge module are all turned off.

[0097] In step S302, when the voltage of the input / output port 120 is between 0V and -VCC, the first diode 110 and the first electrostatic discharge module 140 are also turned off, so that the input / output port can work normally within the range of -VCC to VCC.

[0098] In step S304, when the input / output port 120 receives a positive ESD voltage, the first diode 110 is turned on, and the positive charge of the positive ESD voltage flows into the voltage source pin through the first diode 110, wherein the positive ESD voltage value is higher than the voltage VCC of the voltage source pin. In other embodiments of the present invention, the positive charge of the positive ESD voltage flows into the ground pin through the first diode 110 and the second electrostatic discharge module 30.

[0099] In step S306, when the input / output port receives a negative ESD voltage, the second diode 130 and the first electrostatic discharge module 140 are turned on, and the negative charge of the negative ESD voltage is released to the ground pin through the second diode 130 and the first electrostatic discharge module 140, wherein the absolute value of the negative ESD voltage is greater than V1+VD.

[0100] The electrostatic discharge (ESD) protection circuit provided in this embodiment sequentially connects the voltage source pin, the first diode, the second diode, the first electrostatic discharge module and the ground pin in series, the input and output ports are located between the first diode and the second diode, and there is no parasitic diode between the input and output ports and the ground. When the input and output ports operate in the voltage range (input or output) -VCC to VCC, the first diode and the second diode are both cut off, and the first electrostatic discharge module is also cut off. Therefore, the normal operation of the input and output ports within the voltage range of -VCC to VCC is achieved, and there is no risk of large current injection into the substrate to trigger latching or burning. When the input and output ports receive an ESD voltage exceeding the voltage range of -VCC to VCC, the ESD charge can be discharged in time.

[0101] Please refer to Figure 7 , Figure 7 Another method of operating an electrostatic discharge (ESD) protection circuit is shown.

[0102] In this embodiment, before the chip including the electrostatic discharge protection circuit 10 is mounted on a circuit, when an ESD test is performed, the voltage source pin is grounded and the ground pin is left floating.

[0103] The method comprises the following steps:

[0104] In step S400 , when the input / output port 120 receives a positive ESD voltage, the first diode 110 is turned on, the second diode 130 and the first electrostatic discharge module 140 are turned off, and the positive charge of the positive ESD voltage flows into the voltage source pin through the first diode 120 .

[0105] In step S402, when the input-output port 120 receives a negative ESD voltage, the second diode 130 and the first electrostatic discharge module 140 are turned on, and the first diode 110 is turned off, and the negative charge of the negative ESD voltage is released to the voltage source pin through the second diode 130 and the second electrostatic discharge module 30, wherein the absolute value of the negative ESD voltage is greater than V1+VD.

[0106] Therefore, the working method of the electrostatic discharge (ESD) protection circuit in the present invention can flexibly realize electrostatic discharge in different situations.

[0107] It should be noted that the use of step numbers (letters or numbers) to refer to certain specific method steps in the present invention is only for the purpose of convenience and brevity of description, and is by no means intended to limit the order of these method steps by letters or numbers. Those skilled in the art will understand that the order of the relevant method steps should be determined by the technology itself and should not be inappropriately limited by the existence of step numbers. Those skilled in the art can determine various permissible and reasonable step orders based on the technology itself.

[0108] Those skilled in the art will appreciate that, without conflict, the above-mentioned preferred solutions can be freely combined and superimposed.

[0109] It should be understood that the above-mentioned embodiments are merely illustrative and not restrictive. Without departing from the basic principles of the present invention, various obvious or equivalent modifications or substitutions that can be made by those skilled in the art to the above-mentioned details will be included in the scope of the claims of the present invention.

Claims

1. An electrostatic discharge protection circuit, comprising: The first diode and the second diode are characterized in that they also include a first electrostatic discharge module, wherein: The anode of the first diode is coupled to the input-output port, and the cathode of the first diode is coupled to the voltage source pin; The cathode of the second diode is coupled to the input / output port and the anode of the first diode, and the anode of the second diode is connected to the first electrostatic discharge module; A first end of the first electrostatic discharge module is connected to the anode of the second diode, and a second end is coupled to a ground pin; When the operating voltage of the input / output port is a negative voltage and the absolute value of the operating voltage is less than or equal to V1+VD, the first electrostatic discharge module and the second diode are cut off; when the input / output port receives a negative ESD voltage and the absolute value of the negative ESD voltage is greater than V1+VD, the negative charge of the negative ESD voltage is released to the ground pin through the second diode and the first electrostatic discharge module; Wherein, VD is the absolute value of the critical voltage drop when the second diode is turned on, and V1 is the absolute value of the critical voltage drop when the first electrostatic discharge module is turned on.

2. The electrostatic discharge protection circuit according to claim 1, characterized in that: A second electrostatic discharge module is also included, one end of which is coupled to the voltage source pin, and the other end of which is coupled to the ground pin.

3. The electrostatic discharge protection circuit according to claim 1, characterized in that: The first electrostatic discharge module includes a P-type MOS tube.

4. The electrostatic discharge protection circuit according to claim 3, characterized in that: The drain of the P-type MOS tube is connected to the anode of the second diode, the source of the P-type MOS tube is connected to the ground pin, and the gate of the P-type MOS tube is connected to the ground pin through a resistor R0.

5. The electrostatic discharge protection circuit according to claim 4, characterized in that: The gate of the P-type MOS tube is connected to the anode of the second diode through a capacitor C0.

6. The electrostatic discharge protection circuit according to claim 1, characterized in that: The first electrostatic discharge module includes an N-type MOS tube.

7. The electrostatic discharge protection circuit according to claim 6, characterized in that: The source of the N-type MOS tube is connected to the anode of the second diode, the drain of the N-type MOS tube is connected to the ground pin, and the gate of the N-type MOS tube is connected to the anode of the second diode through the resistor R0.

8. The electrostatic discharge protection circuit according to claim 7, characterized in that: The gate of the N-type MOS tube is connected to the ground pin via a capacitor C0.

9. The electrostatic discharge protection circuit according to claim 2, characterized in that: The second electrostatic discharge module is a power clamp circuit.

10. A layout of an electrostatic discharge protection circuit, characterized in that: include: The first diode, the second diode, the first electrostatic discharge module, the p+ isolation ring, the N-type well and the deep N-type well as claimed in claim 1, wherein the N-type well surrounds the first diode, the deep N-type well surrounds the second diode and the first electrostatic discharge module, and the p+ isolation ring surrounds the N-type well and the deep N-type well.

11. The layout of the electrostatic discharge protection circuit according to claim 10, characterized in that: The cathodes of the first diode and the second diode surround the anode, and the N-type well surrounds the cathode of the first diode.

12. The layout of the electrostatic discharge protection circuit according to claim 10, characterized in that: When the first electrostatic discharge module includes a MOS tube, the drain of the MOS tube is located between two silicided barrier layers, the outer sides of the two silicided barrier layers are gates, the outer sides of the two gates are sources, and the substrate of the MOS tube surrounds the source, the gate, the drain and the silicided barrier layers.

13. A method for operating an electrostatic discharge protection circuit as claimed in claims 1 to 9, characterized in that: The voltage source pin is connected to a positive power supply VCC, the first electrostatic discharge module is selected so that the value of V1+VD is equal to VCC, and the working method includes: When the voltage of the input / output port is between 0V and VCC, the first diode, the second diode and the first electrostatic discharge module are all cut off; When the voltage of the input / output port is between 0V and -VCC, the first diode is turned off, and the second diode and the first electrostatic discharge module are also turned off, so that the input / output port can work normally within the range of -VCC to VCC.

14. The working method according to claim 13, further comprising: When the input / output port receives a positive ESD voltage, the first diode is turned on, and positive charges of the positive ESD voltage flow into the voltage source pin through the first diode, wherein the positive ESD voltage value is higher than the voltage VCC of the voltage source pin.

15. The working method according to claim 14, further comprising: When the input / output port receives a negative ESD voltage, the second diode is turned on by the first electrostatic discharge module, and the negative charge of the negative ESD voltage is released to the ground pin through the second diode and the first electrostatic discharge module, wherein the absolute value of the negative ESD voltage is greater than V1+VD.

16. A chip, characterized in that: The invention comprises the electrostatic discharge protection circuit as claimed in claims 1 to 9.

17. An LED lamp, characterized in that: Comprising the chip as claimed in claim 16.

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