Transistor, preparation method thereof and electronic equipment

Abstract

The invention provides a transistor, a preparation method thereof and electronic equipment, relates to the technical field of semiconductor chips, and aims to solve the problem that a protection device is low in self-destruction speed. The transistor comprises a semiconductor layer, a source electrode, a drain electrode, a first well region, a second well region, a gate structure and a first doping part. The source electrode and the drain electrode are located on the two sides of the semiconductor layer in the first direction respectively. The first well region and the second well region are arranged at an interval and extend into the semiconductor layer from the surface, away from the drain electrode, of the semiconductor layer, and first doping ions are arranged in the first well region and the second well region. The gate structure is located at one side of the semiconductor layer away from the drain. The first doping part is provided with second doping ions and comprises a first sub-part and a second sub-part which are connected with each other; in the first direction, the gate structure shields the first sub-portion and the first well region, at least part of the second sub-portion is exposed by the gate structure, and the second sub-portion is connected with the source electrode. Through the arrangement, the transistor is locally overheated so as to be quickly self-destroyed.

Description

Technical Field

[0001] The present disclosure relates to the field of semiconductor chip technology, and in particular to a transistor and a method for preparing the same, and an electronic device. Background Art

[0002] In the design of a protection circuit that requires the protection device to burn out to play a protective role, the burnout time of the protection device determines the effectiveness of the protection circuit.

[0003] In a circuit where MOSFET is used as a protection device, a short circuit is required to increase the current rapidly and burn out the device. However, as a circuit overload protection device, existing MOSFETs still need some time to reach a high current, and during this time, there is still a risk of damaging other devices in the circuit. Summary of the invention

[0004] The embodiments of the present disclosure provide a transistor and a method for manufacturing the same, and an electronic device, aiming to solve the problem of slow self-destruction speed of a protection device.

[0005] To achieve the above objectives, the embodiments of the present disclosure adopt the following technical solutions:

[0006] On the one hand, a transistor is provided, comprising: a semiconductor layer, a source, a drain, a first well region, a second well region, a gate structure and a first doped portion. The source and the drain are respectively located on both sides of the semiconductor layer along the first direction. The first well region and the second well region are arranged at intervals, and both extend from the surface of the semiconductor layer away from the drain to the inside of the semiconductor layer, and the first well region and the second well region have first doped ions. The gate structure is located on the side of the semiconductor layer away from the drain. The first doped portion has second doped ions, including a first sub-portion and a second sub-portion connected, the first sub-portion is located in the first well region, and the second sub-portion is located in the second well region; the projection of the first sub-portion in the first direction is located within the projection of the gate structure in the first direction; the projection of the second sub-portion in the first direction partially overlaps with the projection of the gate structure in the first direction. Wherein, the first direction is parallel to the thickness direction of the semiconductor layer.

[0007] In some embodiments, the first well region, the second well region, the first sub-portion and the second sub-portion all extend along the second direction, the first sub-portion has a first end and a second end along the second direction, the second sub-portion has a third end and a fourth end along the second direction, the first end and the third end are arranged along a third direction; the second direction and the third direction are both parallel to the semiconductor layer, and the third direction intersects with the second direction. The first doped portion further includes: a third sub-portion, the third sub-portion extends along the third direction, and the third sub-portion is connected to the first end and the third end.

[0008] In some embodiments, the second end and the fourth end are arranged along the third direction; the first doped portion further includes a fourth sub-portion, and the fourth sub-portion is connected to the second end and the fourth end.

[0009] In some embodiments, a size of the first subsection in the second direction is greater than a size of the second subsection in the second direction.

[0010] In some embodiments, the first well region includes a plurality of sub-well regions spaced apart along the second direction, the first sub-portion includes a plurality of first connecting portions and a plurality of second connecting portions alternately connected in sequence along the second direction, and the first connecting portion is located in the sub-well region.

[0011] In some embodiments, the first connecting portion has the same shape as the sub-well region.

[0012] In some embodiments, the shape of the first connection portion includes at least one of a bar, a polygon, a circle, and an ellipse; and / or the shape of the second connection portion includes at least one of a bar, a polygon, a circle, and an ellipse.

[0013] In some embodiments, the first doping ions include B and Al, and the second doping ions include N, P, As, and Sb; and / or, the first doping ions include N, P, As, and Sb, and the second doping ions include B and Al.

[0014] In some embodiments, the doping depth of the first doping ion in the first well region is 0.5 μm-15 μm; and / or the doping concentration of the first doping ion is 1E16 atom / cm 3 -1 E18atom / cm 3 .

[0015] In some embodiments, the doping depth of the second doping ion in the first doping portion is 0.2 μm-0.5 μm; and / or the doping concentration of the second doping ion is 1E18 atom / cm 3 -1 E20atom / cm 3 .

[0016] In some embodiments, the transistor further includes: a third well region extending from the surface of the semiconductor layer away from the drain to the interior of the semiconductor layer, the third well region being spaced apart from the first well region, and the third well region being located on a side of the first well region away from the second well region. The first doped portion further includes: a fifth sub-portion located in the third well region, the projection of the fifth sub-portion in the first direction partially overlapping with the projection of the gate structure in the first direction.

[0017] In some embodiments, the transistor further includes: a second doping portion, the second doping portion is located in the second well region, and the second doping portion penetrates the second sub-portion along the first direction, and the second doping portion has first doping ions.

[0018] In some embodiments, the transistor further includes: a connection structure and an isolation layer, the connection structure being located between the source and the first doped portion, and the connection structure connecting the source and the first doped portion; the isolation layer being located between the gate structure and the connection structure, and between the gate structure and the source.

[0019] On the other hand, a method for preparing a transistor is provided, comprising: performing a doping treatment on a semiconductor layer to form a first well region and a second well region, the first well region and the second well region being arranged at intervals and both extending from the surface of the semiconductor layer to the interior of the semiconductor layer, the first well region and the second well region having first doping ions; performing a doping treatment on the semiconductor layer to form a first doped portion, the first doped portion having second doping ions, the first doped portion comprising a first sub-portion and a second sub-portion connected, the first sub-portion being located in the first well region, and the second sub-portion being located in the second well region; forming a gate structure, the gate structure being located on one side of the semiconductor layer, and in a first direction, the gate structure shields the first sub-portion and the first well region, the gate structure exposing at least a portion of the second sub-portion, wherein the first direction is parallel to the thickness direction of the semiconductor layer; forming a source electrode, the source electrode being located on a side of the semiconductor layer close to the gate structure; forming a drain electrode, the drain electrode being located on a side of the semiconductor layer away from the gate structure.

[0020] In some embodiments, the forming of the gate structure includes: forming a gate dielectric layer located on one side of the semiconductor layer; forming a gate layer located on a side of the gate dielectric layer away from the semiconductor layer; forming an isolation layer covering the gate layer and the gate dielectric layer; the forming of the source includes: removing a portion of the isolation layer to expose at least a portion of the second sub-portion; forming a connecting structure located on a side of the first doped portion away from the semiconductor layer; and depositing a conductive material to form a source, wherein the source is in contact with the connecting structure.

[0021] On the other hand, an electronic device is provided, comprising the transistor as described above. BRIEF DESCRIPTION OF THE DRAWINGS

[0022] In order to more clearly illustrate the technical solutions in the present disclosure, the drawings required for use in some embodiments of the present disclosure are briefly introduced below.

[0023] Figure 1 Schematic diagram of a transistor structure according to some embodiments Figure 1 ;

[0024] Figure 2 Schematic diagram of a current path when a transistor is in a forward conduction state according to some embodiments Figure 1 ;

[0025] Figure 3 Schematic diagram of a current path when a transistor is in a forward conduction state according to some embodiments Figure 2 ;

[0026] Figure 4 Schematic diagram of a local current overshoot point of a transistor according to some embodiments Figure 1 ;

[0027] Figure 5 Schematic diagram of a local current overshoot point of a transistor according to some embodiments Figure 2 ;

[0028] Figure 6 Schematic diagram of a transistor structure according to some embodiments Figure 2 ;

[0029] Figure 7 Schematic diagram of a transistor structure according to some embodiments Figure 3 ;

[0030] Figure 8 Schematic diagram of a transistor structure according to some embodiments Figure 4 ;

[0031] Fig. 9 is a schematic flow chart of a method for manufacturing a transistor according to some embodiments;

[0032] Fig.10 is a schematic diagram of a structure after a first well region and a second well region are formed according to some embodiments;

[0033] Fig.11 is a schematic diagram of a structure after forming a first doping region according to some embodiments;

[0034] Fig.12 is a schematic diagram of a structure after forming a second doping region according to some embodiments;

[0035] Fig.13 is a schematic diagram of a structure after a gate structure is formed according to some embodiments;

[0036] Fig.14 is a schematic diagram of a structure after an isolation layer is formed according to some embodiments;

[0037] Fig.15is a schematic diagram of a structure after a connection structure is formed according to some embodiments;

[0038] Fig.16 is a schematic diagram of a structure after a source electrode is formed according to some embodiments;

[0039] Fig.17 is a schematic diagram of a structure after a drain electrode is formed according to some embodiments;

[0040] Fig.18 is a block diagram of an electronic device according to some embodiments.

[0041] Figure numerals: 1000, electronic device; 100, transistor; X, first direction; Y, second direction; Z, third direction; 1, semiconductor layer; 2, source; 3, drain; 4, first well region; 5, second well region; 41, sub-well region; 6, gate structure; 61, gate dielectric layer; 62, gate layer; 7, first doped portion; 71, first sub-portion; 711, first end; 712, second end; 713, first connecting portion; 714, second connecting portion; 72, second sub-portion; 721, third end; 722, fourth end; 73, third sub-portion; 74, fourth sub-portion; 75, fifth sub-portion; 8, third well region; 9, second doped portion; 10, connecting structure; 11, isolation layer. DETAILED DESCRIPTION

[0042] The following will be combined with the accompanying drawings to clearly and completely describe the technical solutions in some embodiments of the present disclosure. Obviously, the described embodiments are only part of the embodiments of the present disclosure, rather than all the embodiments. Based on the embodiments provided by the present disclosure, all other embodiments obtained by ordinary technicians in this field belong to the scope of protection of the present disclosure.

[0043] In the description of the present disclosure, it should be understood that the terms "center", "up", "down", "front", "back", "left", "right", "vertical", "horizontal", "top", "bottom", "inside", "outside", etc., indicating orientations or positional relationships, are based on the orientations or positional relationships shown in the accompanying drawings, and are only for the convenience of describing the present disclosure and simplifying the description, and do not indicate or imply that the device or element referred to must have a specific orientation, be constructed and operated in a specific orientation, and therefore should not be understood as a limitation on the present disclosure.

[0044] Unless the context requires otherwise, throughout the specification and claims, the term "including" is to be interpreted as an open, inclusive meaning, that is, "including, but not limited to". In the description of the specification, the terms "one embodiment", "some embodiments", "exemplary embodiments", "exemplarily" or "some examples" and the like are intended to indicate that specific features, structures, materials or characteristics associated with the embodiment or example are included in at least one embodiment or example of the present disclosure. The schematic representation of the above terms does not necessarily refer to the same embodiment or example. In addition, the specific features, structures, materials or characteristics may be included in any one or more embodiments or examples in any appropriate manner.

[0045] In the following, the terms "first" and "second" are used for descriptive purposes only and are not to be understood as indicating or implying relative importance or implicitly indicating the number of the indicated technical features. Thus, a feature defined as "first" or "second" may explicitly or implicitly include one or more of the features. In the description of the embodiments of the present disclosure, unless otherwise specified, "plurality" means two or more.

[0046] When describing some embodiments, the expression "connected" and its derivatives may be used. For example, when describing some embodiments, the term "connected" may be used to indicate that two or more components have direct physical or electrical contact with each other.

[0047] “At least one of A, B, and C” has the same meaning as “at least one of A, B, or C” and both include the following combinations of A, B, and C: A only, B only, C only, the combination of A and B, the combination of A and C, the combination of B and C, and the combination of A, B, and C.

[0048] “A and / or B” includes the following three combinations: A only, B only, and a combination of A and B.

[0049] The use of "adapted to" or "configured to" herein is meant to be open and inclusive language that does not exclude devices adapted or configured to perform additional tasks or steps.

[0050] As used herein, "approximately" includes the stated value and an average that is within an acceptable range of deviation from the particular value, where the acceptable range of deviation is determined by one of ordinary skill in the art taking into account the measurements in question and the errors associated with the measurement of the particular quantity (i.e., the limitations of the measurement system).

[0051] Exemplary embodiments are described herein with reference to cross-sectional views and / or plan views that are idealized exemplary drawings. In the drawings, the thickness of layers and regions are exaggerated for clarity. Therefore, variations in shape relative to the drawings due to, for example, manufacturing techniques and / or tolerances are conceivable. Therefore, the exemplary embodiments should not be interpreted as being limited to the shapes of the regions shown herein, but include shape deviations due to, for example, manufacturing. For example, an etched region shown as a rectangle will typically have curved features. Therefore, the regions shown in the drawings are schematic in nature, and their shapes are not intended to illustrate the actual shape of regions of the device, and are not intended to limit the scope of the exemplary embodiments.

[0052] It should be noted that, in this application, words such as "exemplarily" or "for example" are used to indicate examples, illustrations or explanations. Any embodiment or design described as "exemplarily" or "for example" in this application should not be interpreted as being more preferred or more advantageous than other embodiments or designs. Specifically, the use of words such as "exemplarily" or "for example" is intended to present related concepts in a specific way.

[0053] In the control module or test module, a protection circuit is usually provided to prevent abnormal conditions (such as overvoltage, overcurrent, short circuit, etc.) in the circuit from causing damage to the device. A protection device is provided in the protection circuit. When an abnormal condition occurs in the circuit, the protection device can burn itself out to cut off the circuit. The protection device may include: fuses, protectors, and semiconductor devices such as MOSFET. Among them, the fuse is the most common circuit protection device. Its working principle is to cut off the circuit by melting itself. The time dimension is in seconds, which takes a long time. Before the fuse cuts off the circuit, other devices in the test module will also be burned due to excessive current, and it cannot provide effective failure analysis value.

[0054] In a circuit where MOSFET is used as a protection device, a short circuit is required to increase the current rapidly and burn out the device. However, as a circuit overload protection device, existing MOSFETs still need some time to reach a high current, and during this time, there is still a risk of damaging other devices in the circuit.

[0055] On the other hand. In the circuit of the debugging test conditions, a short-term large current overload will cause the device to gradually damage, but the temperature will not rise significantly before the device is damaged. Therefore, when the current in the test module is too large, the MOSFET device cannot burn out quickly, and the information of the current overload in the test module cannot be quickly transmitted, resulting in abnormal test current, but it is difficult to detect. Since the MOSFET device failed to burn out in time, the overloaded current was mistaken for the normal test current. Without further changing the test conditions, testing under the abnormal current condition is not conducive to obtaining valuable test results.

[0056] In summary, in the design of a protection circuit that requires the protection device to burn out to play a protective role, the burnout time of the protection device determines the effectiveness of the protection circuit. Therefore, it is necessary to develop a new protection device that can react quickly to current overload and burn out.

[0057] Based on this, some embodiments of the present disclosure provide a transistor. Figure 1 As shown, the transistor 100 includes: a semiconductor layer 1 , a source 2 , a drain 3 , a first well region 4 , a second well region 5 , a gate structure 6 and a first doped portion 7 .

[0058] Semiconductor is a material with electrical conductivity between conductors and insulators at room temperature. Semiconductors include intrinsic semiconductors and impurity semiconductors. A pure semiconductor without impurities and defects, whose internal electron and hole concentrations are equal, is called an intrinsic semiconductor. A semiconductor doped with a certain amount of impurities is called an impurity semiconductor or a non-intrinsic semiconductor. Among them, the impurities doped into the impurity semiconductor can provide a certain concentration of carriers (such as holes or electrons, among which the impurity semiconductor doped with impurities that provide electrons (such as pentavalent phosphorus) is also called an electron-type semiconductor or an N (negative) type semiconductor, and the impurity semiconductor doped with impurities that provide holes (such as trivalent boron) is also called a hole-type semiconductor or a P (positive) type semiconductor), which can improve the conductivity of the intrinsic semiconductor. Generally, the greater the carrier concentration, the lower the resistivity of the semiconductor and the better the conductivity.

[0059] In this embodiment, the material of the semiconductor layer 1 may be silicon carbide (SiC) material, and in this case, the transistor 100 may be referred to as a SiC MOSFET. SiC is a semiconductor material with a large bandgap, which can make the transistor 100 have a higher withstand voltage. In addition, the material of the semiconductor layer 1 may also include, for example, single crystal silicon, single crystal germanium, II IV group compound semiconductor materials, III IV group compounds, and other suitable semiconductor materials.

[0060] It is understandable that the material of the semiconductor layer 1 is not limited to SiC. For example, semiconductor materials such as gallium nitride (GaN) materials and diamond also have a large bandgap, so that semiconductor materials such as gallium nitride (GaN) materials and diamond can also be applied to the above transistor 100.

[0061] The source electrode 2 and the drain electrode 3 are respectively located on two sides of the semiconductor layer 1 along a first direction X. The first direction X is parallel to the thickness direction of the semiconductor layer 1 .

[0062] The first well region 4 and the second well region 5 have first doping ions, and the first well region 4 and the second well region 5 have the same doping type. The first doping portion 7 has second doping ions, and the doping type of the first doping portion 7 is different from the doping type of the first well region 4 and the second well region 5. In some embodiments, the first well region 4 and the second well region 5 are both P-wells (P-well), and the first doping portion 7 is an N-type semiconductor. In other embodiments, the first well region 4 and the second well region 5 are both N-wells (N-well), and the first doping portion 7 is a P-type semiconductor. The embodiments of the present application are explained by taking the first well region 4 and the second well region 5 as P-wells and the first doping portion 7 as an N-type semiconductor as an example.

[0063] In this embodiment, the first well region 4 and the second well region 5 are formed by performing P-type doping on the semiconductor layer 1, and both the first well region 4 and the second well region 5 extend from the surface of the semiconductor layer 1 away from the drain 3 to the inside of the semiconductor layer 1. The first well region 4 and the second well region 5 are spaced apart.

[0064] The first doped portion 7 may be an N+ region, and the first doped portion 7 may be formed by performing N-type high doping on the semiconductor layer 1. The first doped portion 7 includes a first sub-portion 71 and a second sub-portion 72 connected to each other, wherein the first sub-portion 71 may be formed by performing N-type high doping on the first well region 4, and the second sub-portion 72 may be formed by performing N-type high doping on the second well region 5. The first sub-portion 71 extends from the surface of the first well region 4 away from the drain 3 to the inside of the first well region 4, and the depth of the first sub-portion 71 is less than the depth of the first well region 4. The second sub-portion 72 extends from the surface of the second well region 5 away from the drain 3 to the inside of the second well region 5, and the depth of the second sub-portion 72 is less than the depth of the second well region 5.

[0065] The gate structure 6 is located on a side of the semiconductor layer 1 away from the drain 3. The projection of the first sub-portion 71 in the first direction X is located within the projection of the gate structure 6 in the first direction X. Then, the orthographic projections of the first sub-portion 71 and the first well region 4 on the semiconductor layer 1 are located within the edge of the orthographic projection of the gate structure 6 on the semiconductor layer 1. Then, in the first direction X, the gate structure 6 can completely cover the first sub-portion and the first well region 4, thereby shielding the first sub-portion 71 and the first well region 4.

[0066] In this embodiment, the projection of the second sub-portion 72 in the first direction X partially overlaps with the projection of the gate structure 6 in the first direction X. Then the orthographic projection of the second sub-portion 72 on the semiconductor layer 1 partially overlaps with the orthographic projection of the gate structure 6 on the semiconductor layer 1, and partially does not overlap. In the first direction X, the gate structure 6 can expose at least a portion of the second sub-portion 72. In the first direction X, the gate structure 6 can cover a portion of the second sub-portion 72, exposing at least a portion of the second sub-portion 72, so as to facilitate the connection between the source 2 and the second sub-portion 72, for example, the source 2 can be in contact with the second sub-portion 72. When the second sub-portion 72 is an N-type semiconductor, the second sub-portion 72 has a very small resistivity, and the second sub-portion 72 can form a good ohmic contact with the source 2.

[0067] In some examples, the gate structure 6 may include a gate dielectric layer 61 and a gate layer 62. The gate dielectric layer 61 is located between the gate layer 62 and the semiconductor layer 1. The orthographic projection of the gate dielectric layer 61 on the semiconductor layer 1 may overlap with the orthographic projection of the gate layer 62 on the semiconductor layer 1. Since the gate dielectric layer 61 and the gate layer 62 are laid flat on the semiconductor layer 1, the transistor 100 may become a planar gate device.

[0068] Exemplarily, the material of the gate dielectric layer 61 includes but is not limited to silicon dioxide (SiO2). The material of the gate layer 62 includes but is not limited to polysilicon. The material of the source electrode 2 may include but is not limited to metal materials such as nickel and titanium. The material of the drain electrode 3 may include but is not limited to metal materials such as nickel and titanium.

[0069] like Figure 2 and Figure 3 As shown, when the transistor 100 is in the forward conduction state, the current path includes a current path A and a current path B. Current path A: The current will flow out from the source 2, pass through the second sub-portion 72, the second well region 5 and the semiconductor layer 1 in sequence to reach the drain 3. Current path B: The current will flow out from the source 2, pass through the second sub-portion 72, the first sub-portion 71, the first well region 4 and the semiconductor layer 1 in sequence to reach the drain 3. It can be understood that the arrows shown in the figure are only exemplary to illustrate the approximate flow direction of the current when the transistor 100 is in the forward conduction state, and do not limit the actual current flow direction.

[0070] Since the drain electrode 3 can be in contact with the second sub-section 72 and can include a metal material, which has not only good electrical conductivity but also good thermal conductivity, the drain electrode 3 can help the second sub-section 72 to dissipate heat and help the second sub-section 72 to alleviate local overheating during operation.

[0071] The source electrode 2 is not directly connected to the first sub-section 71 . The source electrode 2 is connected to the second sub-section 72 , and the second sub-section 72 is connected to the first sub-section 71 . Therefore, the current flowing out of the source electrode 2 needs to be conducted to the first sub-section 71 through the second sub-section 72 .

[0072] On the one hand, if the resistance of the first subsection 71 is the same or approximately the same as the resistance of the second subsection 72, the current can be quickly and evenly distributed in the current path A and the current path B. Then, the current of the transistor 100 increases during normal operation, which is beneficial to improving the electrical performance of the transistor 100. Among them, the resistance of the first subsection 71 and the resistance of the second subsection 72 are approximately the same, which can be understood as the difference between the resistance of the first subsection 71 and the resistance of the second subsection 72 is within the acceptable deviation range, for example, the difference between the resistance of the first subsection 71 and the resistance of the second subsection 72 can be less than or equal to 5% of either one.

[0073] On the other hand, if the resistance of the first sub-section 71 is greater than the resistance of the second sub-section 72, the current tends to take the path with smaller resistance, and the current will be more inclined to take the current path A. The current will also take the current path B, but the current at the current path B is smaller. The greater the resistance of the first sub-section 71, the more uneven the currents in the current path A and the current path B are, and there is uneven heat distribution. Figure 4 Schematic diagram of a local current overshoot point of a transistor according to some embodiments Figure 1 , Figure 5 Schematic diagram of a local current overshoot point of a transistor according to some embodiments Figure 2 . refer to Figure 4 and Figure 5 Since the resistance of the first sub-section 71 is greater than the resistance of the second sub-section 72 , an excessive current may easily flow at the connection between the first sub-section 71 and the second sub-section 72 , resulting in uneven current distribution of the transistor 100 when it is working.

[0074] According to Joule's law, in the same time period, the greater the current and resistance, the higher the heat generated. In addition, in the first direction X, the gate structure 6 covers and shields the first sub-portion 71, and the first sub-portion 71 is in contact with the gate dielectric layer 61. The gate dielectric layer 61 has poor thermal conductivity, so the heat dissipation at the first sub-portion 71 is poor.

[0075] When the voltage is the normal working voltage, the current can flow in the current path A and the current path B within a certain period of time. Although the current distribution is uneven, the magnitude of the current and the heat dissipation of the transistor 100 are within a controllable range, and the device can operate normally with a higher power loss. When the voltage is overloaded, a large instantaneous current flows through the current path A and the current path B, and the first sub-section 71 generates a large amount of heat, but the heat dissipation at the first sub-section 71 is poor, so the first sub-section 71 will accumulate heat rapidly. Under the impact of heat and large current, the device will be broken down, resulting in a short circuit in the circuit, and the triggering time is short.

[0076] When the above-mentioned transistor 100 is used as a protection device in a protection circuit, due to the poor heat dissipation of the first sub-section 71 and the uneven current distribution of the transistor 100, the local current of the transistor 100 is too large. The transistor 100 will be quickly broken down under the impact of the overload current, thereby disconnecting the protection circuit, which is beneficial to increasing the self-destruction speed of the protection device and accelerating the reaction time of the transistor 100 as a protection device, thereby protecting other devices from being damaged by the overload current, which is beneficial to improving the effectiveness of the protection circuit.

[0077] When the transistor 100 is applied to a circuit for debugging test conditions, when the voltage is the normal operating voltage, the transistor 100 is already operating at a higher power loss, and heat is already accumulated in the first subsection 71. When the voltage is overloaded and the first subsection 71 is impacted by the overload current, the transistor 100 can heat up quickly and self-destruct quickly, thereby reflecting that there is a problem with the test conditions and guiding the change of the test conditions, which is conducive to obtaining valuable test results.

[0078] In addition, since the first sub-portion 71 is shielded by the gate structure 6 in the first direction X, the transistor 100 provided by the present application cannot be distinguished from the conventional transistor 100 in appearance. In a circuit for the purpose of information protection, a protection circuit having the above-mentioned transistor 100 can be arranged near the device to be protected. When information protection is started, the transistor 100 provided by the present application has local current accumulation, causing the overall circuit to be destroyed due to a short circuit, thereby playing a role in information confidentiality.

[0079] The resistance of the first sub-section 71 and the resistance of the second sub-section 72 can be controlled by means of a doping process and an annealing process. The resistance of the first sub-section 71 needs to be controlled within an appropriate range to avoid excessive resistance of the first sub-section 71, which may cause local overheating and damage to the device during normal operation.

[0080] In some embodiments, reference Figure 6, the first well region 4, the second well region 5, the first sub-portion 71 and the second sub-portion 72 all extend along the second direction Y, the first sub-portion 71 has a first end 711 and a second end 712 along the second direction Y, the second sub-portion 72 has a third end 721 and a fourth end 722 along the second direction Y, and the first end 711 and the third end 721 are arranged along the third direction Z. The second direction Y and the third direction Z are both parallel to the semiconductor layer 1, and the third direction Z intersects with the second direction Y. In the embodiment of the present application, the second direction Y and the third direction Z are perpendicular to each other as an example for explanation.

[0081] In this embodiment, the two ends of the first sub-portion 71 and the second sub-portion 72 close to each other can be connected together. For example, the first doped portion 7 further includes a third sub-portion 73, the third sub-portion 73 extends along the third direction Z, and the third sub-portion 73 is connected to the first end 711 and the third end 721. The first sub-portion 71, the second sub-portion 72 and the third sub-portion 73 can be connected areas formed in the same doping process.

[0082] Through the above arrangement, the first sub-section 71 and the second sub-section 72 can be connected through the third sub-section 73, so that the current flowing out of the source 2 is conducted to the first sub-section 71 through the second sub-section 72 and the third sub-section 73. If the normal use of the transistor 100 is considered, the electrical connection performance between the second sub-section 72, the third sub-section 73 and the first sub-section 71 can be improved by optimizing the doping process, increasing the doping concentration, etc., so that the current is quickly distributed in the first sub-section 71, the second sub-section 72 and the third sub-section 73. If the transistor 100 is considered to self-destruct quickly, the electrical connection performance between the second sub-section 72, the third sub-section 73 and the first sub-section 71 can be poor by adjusting the doping process, etc., so that the current is unevenly distributed in the transistor 100, resulting in local overheating of the transistor 100 and rapid self-destruction. In addition, the above-mentioned arrangement is helpful to improve the electrical connection performance between the second sub-section 72, the third sub-section 73 and the first sub-section 71, reduce the resistance of the first sub-section 71, and thus control the resistance of the first sub-section 71 within an appropriate range, thereby avoiding the resistance of the first sub-section 71 being too large, which may cause local overheating and damage to the device during normal operation.

[0083] In some embodiments, reference Figure 6, the first end 711 and the third end 721 are arranged along the third direction Z, and the second end 712 and the fourth end 722 are arranged along the third direction Z. Then the length of the first subsection 71 in the second direction Y is the same as the length of the second subsection 72 in the second direction Y, and the first subsection 71 and the second subsection 72 are aligned in the third direction Z. The third subsection 73 is connected to the first end 711 and the third end 721. The first doped portion 7 also includes a fourth subsection 74, which is connected to the second end 712 and the fourth end 722. From the perspective of the first direction X, the first subsection 71, the second subsection 72, the third subsection 73 and the fourth subsection 74 can be connected to form a rectangle. The first subsection 71, the second subsection 72, the third subsection 73 and the fourth subsection 74 can be connected areas formed in the same doping process.

[0084] In this embodiment, the second end 712 and the fourth end 722 are further connected by the fourth sub-section 74, which is beneficial to improve the electrical connection performance between the first sub-section 71 and the second sub-section 72. It is beneficial to further improve the ability of the second sub-section 72 to transmit current to the first sub-section 71.

[0085] In some embodiments, Figure 6 As shown, the size of the first sub-section 71 in the second direction Y is greater than the size of the second sub-section 72 in the second direction Y. Here, the size of the first sub-section 71 in the second direction Y can be understood as the extension length of the first sub-section 71 in the second direction Y. The size of the second sub-section 72 in the second direction Y can be understood as the extension length of the second sub-section 72 in the second direction Y.

[0086] In this embodiment, only one end of the first sub-section 71 and the second sub-section 72 can be aligned in the third direction Z, for example, the first end 711 and the second end 712 are aligned in the third direction Z, or the second end 712 and the fourth end 722 are aligned in the third direction Z.

[0087] Through the above configuration, the size of the second sub-section 72 in the second direction Y is smaller than the size of the first sub-section 71 in the second direction Y, so space can be reserved at the location of the second sub-section 72 to facilitate the subsequent setting of the lead-out structure, etc.

[0088] In some embodiments, Figure 6 and Figure 7As shown, the first well region 4 may include a plurality of sub-well regions 41 arranged at intervals along the second direction Y. The first sub-portion 71 may include a plurality of first connecting portions 713 and a plurality of second connecting portions 714 alternately connected in sequence along the second direction Y. Here, the plurality of first connecting portions 713 and second connecting portions 714 alternately connected in sequence may be understood as the first connecting portions 713 and the second connecting portions 714 being alternately arranged to form a plurality of first connecting portions 713 and a plurality of second connecting portions 714 spaced apart from each other.

[0089] One first connection portion 713 is located in one sub-well region 41. The number of the first connection portions 713 is the same as the number of the sub-well regions 41, and the plurality of first connection portions 713 is disposed in a one-to-one correspondence with the plurality of sub-well regions 41.

[0090] Through the above arrangement, the number and position of the sub-well regions 41 can be flexibly arranged according to the space of different semiconductor layers 1, so that the size of the first sub-portion 71 in the second direction Y can be adjusted, which is beneficial to avoid other lead-out structures and leave space for arrangement of other lead-out structures.

[0091] In addition, by reducing the number of sub-well regions 41, the size of the first sub-portion 71 in the second direction Y can be reduced accordingly, thereby facilitating the reduction of the resistance of the first sub-portion 71. Exemplarily, the above method can be used as one of the methods for controlling the resistance of the first sub-portion 71, so that the resistance value of the first sub-portion 71 is within a suitable range, and the resistance of the first sub-portion 71 is prevented from being too large, which may cause local overheating and damage to the device during normal operation.

[0092] In some embodiments, Figure 7 As shown, the first connection portion 713 has the same shape as the sub-well region 41. The "same shape" here can be understood as, from the perspective of the first direction X, that is, on the YZ plane, the shape of the first connection portion 713 is the same as or approximately the same as the shape of the sub-well region 41. Or, it can be understood that the shape of the orthographic projection of the first connection portion 713 on the semiconductor layer 1 is the same as or approximately the same as the shape of the orthographic projection of the sub-well region 41 on the semiconductor layer 1. The shape of the first connection portion 713 is approximately the same as the shape of the sub-well region 41, which can be understood as the shape of the first connection portion 713 and the shape of the sub-well region 41 are both close to the same shape, for example, both are close to the positive direction, but due to process errors, the shape of the first connection portion 713 or the shape of the sub-well region 41 may not be a regular square, as long as the shape of the first connection portion 713 and the shape of the sub-well region 41 are both close to the same shape.

[0093] It should be noted that the shape of the first connection portion 713 may be the same as or approximately the same as the shape of the sub-well region 41, and the shape and size of the first connection portion 713 may be different from the shape and size of the sub-well region 41, that is, the shape of the first connection portion 713 is similar to the shape of the sub-well region 41. For example, on the YZ plane, the shape of the first connection portion 713 is a square with a side length a, and the shape of the sub-well region 41 is also a square with a side length b, a<b. Then, on the YZ plane, the shape of the first connection portion 713 is the same as the shape of the sub-well region 41, but the shape and size of the first connection portion 713 are different from the shape and size of the sub-well region 41.

[0094] In this embodiment, the sub-well region 41 may be doped to form the first connection portion 713. The above configuration is conducive to designing the shape of the sub-well region 41 and then designing the shape of the first connection portion 713. The first connection portion 713 has the same shape as the sub-well region 41, which is conducive to improving the structural regularity of the transistor 100.

[0095] In some embodiments, Figure 7 As shown, the shape of the first connection portion 713 may include at least one of a bar, a polygon, a circle, and an ellipse. Correspondingly, the shape of the sub-well region 41 may also include at least one of a bar, a polygon, a circle, and an ellipse. The shape of the sub-well region 41 is the same as the shape of the first connection portion 713.

[0096] In some embodiments, the shape of the second connection portion 714 may include at least one of a bar, a polygon, a circle, and an ellipse.

[0097] In some embodiments, the shape of the first well region 4 may include at least one of a stripe, a polygon, a circle, and an ellipse. Accordingly, the shape of the first sub-portion 71 may also include at least one of a stripe, a polygon, a circle, and an ellipse.

[0098] Through the above arrangement, the shapes of the first well region 4, the second well region 5, the first connecting portion 713, the second connecting portion 714 and the first sub-portion 71 can be freely combined. Different shape combinations can be selected according to process requirements or layout design, which is conducive to adapting to different preparation scenarios.

[0099] In some embodiments, the first doping ions include B and Al, and the second doping ions include N, P, As and Sb. At this time, the doping type of the first well region 4 and the second well region 5 is P-type doping, and the first well region 4 and the second well region 5 are both P-wells. The doping type of the first doping portion 7 is N-type doping, and the first doping portion 7 is an N-type semiconductor.

[0100] In other embodiments, the first doping ions include N, P, As and Sb, and the second doping ions include B and Al. In this case, the doping type of the first well region 4 and the second well region 5 is N-type doping, and the first well region 4 and the second well region 5 are both N-wells. The doping type of the first doping portion 7 is P-type doping, and the first doping portion 7 is a P-type semiconductor.

[0101] In some examples, the doping depth of the first doping ion in the first well region 4 is 0.5 μm-15 μm. In some examples, the doping concentration of the first doping ion is 1E16 atom / cm 3 -1 E18atom / cm 3 Through the above arrangement, the first well region 4 and the second well region 5 are formed.

[0102] In some examples, the doping depth of the second doping ion in the first doping portion 7 is 0.2 μm-0.5 μm. In some examples, the doping concentration of the second doping ion is 1E18 atom / cm 3 -1 E20atom / cm 3 Through the above arrangement, the first doping region is formed.

[0103] In some embodiments, Figure 8 As shown, the transistor 100 further includes a third well region 8. The third well region 8 is formed by doping the semiconductor layer 1, and the third well region 8 has the same doping type as the first well region 4. The doping depths of the first well region 4, the second well region 5, and the third well region 8 may be the same. The third well region 8 extends from the surface of the semiconductor layer 1 away from the drain 3 to the inside of the semiconductor layer 1, and the third well region 8 is spaced apart from the first well region 4, and the third well region 8 is located on the side of the first well region 4 away from the second well region 5.

[0104] The first doping section 7 also includes a fifth subsection 75. The fifth subsection 75 may be formed by doping the third well region 8. The doping type of the fifth subsection 75 may be the same as the doping type of the first subsection 71. The first subsection 71, the second subsection 72 and the fifth subsection 75 may be formed in the same doping process. And the doping depths of the first subsection 71, the second subsection 72 and the fifth subsection 75 may be the same. The fifth subsection 75 is located in the third well region 8, and the fifth subsection 75 extends from the surface of the third well region 8 away from the drain 3 to the inside of the third well region 8. The projection of the fifth subsection 75 in the first direction X partially overlaps with the projection of the gate structure 6 in the first direction X. Then the orthographic projection of the fifth subsection 75 on the semiconductor layer 1 partially overlaps with the orthographic projection of the gate structure 6 on the semiconductor layer 1, and partially does not overlap. In the first direction X, the gate layer 62 exposes at least part of the fifth subsection 75. The fifth subsection 75 may be connected to the source 2, for example, the fifth subsection 75 may be in contact with the source 2. When the fifth sub-portion 75 is an N-type semiconductor, the fifth sub-portion 75 has a very small resistivity, and the fifth sub-portion 75 can form a good ohmic contact with the source electrode 2 .

[0105] In some examples, the transistor 100 may have a central plane that passes through the center of the first well region 4 and is perpendicular to the surface of the semiconductor layer 1 away from the drain 3. The second well region 5 and the third well region 8 are located on both sides of the central plane and are symmetrically arranged with respect to the central plane. The second sub-portion 72 and the fifth sub-portion 75 are located on both sides of the central plane and are symmetrically arranged with respect to the central plane.

[0106] The above arrangement is helpful to improve the design regularity of the transistor 100 and facilitate the preparation and formation of the transistor 100 .

[0107] In some embodiments, reference Figure 8 , the transistor 100 also includes a second doping portion 9. The doping type of the second doping portion 9 may be the same as the doping type of the first well region 4. The second doping portion 9 has a first doping ion. The second doping portion 9 is located in the second well region 5, and the second doping portion 9 penetrates the second sub-portion 72 along the first direction X. Exemplarily, the second doping portion 9 may be formed by performing P-type high doping on the second well region 5. The second doping portion 9 extends from the surface of the second well region 5 away from the drain 3 to the inside of the second well region 5. The depth of the second doping portion 9 is less than the depth of the second well region 5, or the depth of the second doping portion 9 may also be greater than or equal to the depth of the second well region 5. Then the current flowing out from the source 2 can be conducted to the second sub-portion 72 via the second doping portion 9. The second doping portion 9 is conducive to improving the reverse withstand voltage capability of the transistor 100.

[0108] In some embodiments, reference Figure 8The transistor 100 further includes a connection structure 10. The connection structure 10 is located between the source 2 and the first doped portion 7, and the connection structure 10 connects the source 2 and the first doped portion 7. The connection structure 10 may cover a portion of the surface of the second sub-portion 72, thereby achieving contact connection with the first doped portion 7. The material of the connection structure 10 may include a metal material, such as nickel. In this way, the connection structure 10 can not only play a conductive role but also a thermal conductive role, helping the second sub-portion 72 to dissipate heat. The connection structure 10 can form an ohmic contact with the source 2.

[0109] The transistor 100 may further include an isolation layer 11. The isolation layer 11 is located between the gate structure 6 and the connection structure 10, and between the gate structure 6 and the source 2. The isolation layer 11 may cover the gate structure 6, wrap the gate dielectric layer 61 and the gate layer 62, and isolate the gate layer 62 from the source 2 and the connection structure 10.

[0110] Some embodiments of the present application also provide a method for preparing a transistor. The method is used, for example, to prepare the transistor 100 in some of the above embodiments. Fig. 9 As shown, the preparation method includes: S100-S500.

[0111] S100, performing doping treatment on the semiconductor layer to form a first well region and a second well region, wherein the first well region and the second well region are spaced apart and both extend from the surface of the semiconductor layer to the inside of the semiconductor layer, and the first well region and the second well region have first doping ions.

[0112] For example, Fig.10 As shown, the material of the semiconductor layer 1 includes but is not limited to SiC. For example, the material of the semiconductor layer 1 may also include GaN-based materials, diamond, and the like.

[0113] For example, Fig.10 As shown, the first doping ions may include B and Al, and the second doping ions may include N, P, As, and Sb. Alternatively, the first doping ions may include N, P, As, and Sb, and the second doping ions may include B and Al. This embodiment is explained by taking the first doping ions as P-type ions and the second doping ions as N-type ions as an example.

[0114] In this step, refer to Fig.10 The semiconductor layer 1 is doped with P-type ions such as B and Al by ion implantation. The implantation depth of P-type ions can be between 0.5 μm and 1 μm, and the implantation concentration of P-type ions can be between 1E16 atom / cm 3 -1 E18atom / cm 3The doping depth and doping concentration of the second well region 5 may be the same as those of the first well region 4. In this step, the third well region 8 may be formed while the first well region 4 and the second well region 5 are formed.

[0115] S200, performing doping treatment on the semiconductor layer to form a first doped portion, wherein the first doped portion has second doping ions, the first doped portion includes a first sub-portion and a second sub-portion connected to each other, the first sub-portion is located in the first well region, and the second sub-portion is located in the second well region.

[0116] In this step, refer to Fig.10 and Fig.11 , an ion implantation process can be used to implant N-type ions, such as N, P, As, Sb, etc., into the semiconductor layer 1 to form a first doping portion 7, and the first doping portion 7 is an N-type semiconductor. The doping depth of the first doping portion 7 can be between 0.2 μm and 0.5 μm. The doping concentration of the first doping portion 7 can be between 1E18 atom / cm 3 -1E20atom / cm 3 In this step, while the first sub-portion 71 and the second sub-portion 72 are formed, a fifth sub-portion 75 can be formed, and the fifth sub-portion 75 is located in the third well region 8 .

[0117] After forming the first doping portion 7, refer to Fig.11 and Fig.12 , an ion implantation process may be used to implant P-type ions, such as B, Al, etc., into the first sub-section 71 and the fifth sub-section 75, thereby forming the second doping section 9. The doping depth of the second doping section 9 may be between 0.5 μm and 1 μm. The doping concentration of the second doping section 9 may be between 1E18 atom / cm 3 -1 E20atom / cm 3 between.

[0118] S300, forming a gate structure, wherein the gate structure is located on one side of the semiconductor layer, and in a first direction, the gate structure shields the first sub-portion and the first well region, and the gate structure exposes at least a portion of the second sub-portion, wherein the first direction is parallel to a thickness direction of the semiconductor layer.

[0119] In this step, refer to Fig.13For example, a gate dielectric layer 61 and a gate layer 62 may be sequentially formed on one side of the semiconductor layer 1 by a deposition process. The gate layer 62 is located on the side of the gate dielectric layer 61 away from the semiconductor layer 1. The material of the gate dielectric layer 61 may include but is not limited to silicon oxide, and the material of the gate layer 62 may include but is not limited to polysilicon. Exemplarily, the thickness of the gate dielectric layer 61 may range from 30nm to 200nm, and the thickness of the polysilicon may range from 300nm to 1000nm. Exemplarily, the polysilicon may be doped with P element to form the gate layer 62, and the doping concentration may be 1E20atom / cm 3 -8E20atom / cm 3 The width of the gate layer 62 is less than or equal to the width of the gate dielectric layer 61. For example, the orthographic projections of the gate dielectric layer 61 and the gate layer 62 on the semiconductor layer 1 overlap.

[0120] refer to Fig.13 and Fig.14 , after forming the gate structure 6, an isolation layer 11 can be formed on the side of the gate structure 6 away from the semiconductor layer 1 by a deposition process. The width of the isolation layer 11 is greater than the width of either the gate dielectric layer 61 or the gate layer 62. The isolation layer 11 covers the upper surface and side surfaces of the gate structure 6, and it can be understood that the isolation layer 11 wraps the gate layer 62 and the gate dielectric layer 61. The isolation layer 11 can contact the gate dielectric layer 61, the second sub-section 72 and the fifth sub-section 75, and the isolation layer 11 can cooperate with the gate dielectric layer 61 to achieve wrapping and covering of the gate layer 62. Exemplarily, the material of the isolation layer 11 includes but is not limited to a single layer or any multi-layer combination of silicon dioxide, borophosphorus glass and silicon nitride. Exemplarily, the thickness of the isolation layer 11 ranges from 0.6μm to 2μm.

[0121] S400 , forming a source electrode, wherein the source electrode is located on a side of the semiconductor layer close to the gate structure.

[0122] In this step, refer to Fig.14 and Fig.15 , an etching process may be used to remove part of the isolation layer 11 to expose at least part of the second sub-portion 72. A deposition process may be used to form a connection structure 10 on the side of the first doped portion 7 away from the semiconductor layer 1. For example, Ni may be deposited and then treated by a high temperature annealing process to form an ohmic contact between the connection structure 10 and the first doped portion 7.

[0123] refer to Fig.15 and Fig.16 After forming the connection structure 10, a deposition process may be used to deposit a conductive material to form a source electrode 2, and the source electrode 2 is in contact with the connection structure 10. The conductive material includes but is not limited to metal materials such as nickel.

[0124] S500 , forming a drain electrode, wherein the drain electrode is located at a side of the semiconductor layer away from the gate structure.

[0125] For example, reference Fig.16 and Fig.17 In the embodiment of the present application, a sputtering process can be used to form a drain electrode 3 on the side of the semiconductor layer 1 away from the source electrode 2. The drain electrode 3 can be in a flat plate shape, and then a high temperature annealing process is used to process the drain electrode 3 so that the drain electrode 3 forms an ohmic contact with the semiconductor layer 1. Optionally, the material of the drain electrode 3 includes but is not limited to nickel.

[0126] In some embodiments of the present application, the "width" of each structure refers to the lateral dimension in the cross-sectional diagram shown in the drawings. The "depth" of each structure refers to the vertical dimension in the cross-sectional diagram shown in the drawings.

[0127] like Fig.18 As shown, some embodiments of the present disclosure also provide an electronic device 1000. The electronic device 1000 may be a power electronic device 1000, that is, a device with a power electronic device (also referred to as a semiconductor device or a power semiconductor device) as a main functional element. For example, the electronic device 1000 may be a converter, an electronic switch, an electronic AC power controller, etc. Among them, the converter includes but is not limited to a DC chopper (DC / DC, or DC to DC power supply), a rectifier (AC / DC, or AC-DC converter), an inverter (DC / AC, or DC-AC converter), etc., and the electronic switch includes but is not limited to a power switch power supply circuit, etc. The electronic device 1000 may also be a user device or terminal device of different types such as a computer, a mobile phone, a tablet computer, a wearable device, and a vehicle-mounted device; the electronic device 1000 may also be a network device such as a base station. The electronic device 1000 may also be a device such as a power amplifier used in the above-mentioned electronic device 1000. The embodiment of the present application does not impose any special restrictions on the specific form of the above-mentioned electronic device 1000. The embodiment of the present application does not impose any special restrictions on the specific type of the electronic device 1000.

[0128] Fig.18 1 is a block diagram of an electronic device according to some embodiments. The electronic device 1000 includes a circuit board and a transistor 100 provided by some embodiments above, the circuit board and the transistor 100 are electrically connected, and the circuit board is used to provide the transistor 100 with a required electrical signal.

[0129] It is to be understood that the structure illustrated in the embodiment of the present application does not constitute a specific limitation on the electronic device 1000. In other embodiments of the present application, the electronic device 1000 may include more components than those shown in the figure, or combine certain components, or separate certain components, or arrange the components differently. The components shown in the figure may be implemented in hardware, software, or a combination of software and hardware.

[0130] Some embodiments of the present application provide that the transistor 100 can be applied to the above-mentioned electronic device 1000. Of course, the specific application scenario of the above-mentioned transistor 100 is not limited thereto. It can be understood that any electronic device 1000 that needs to use the transistor 100 belongs to the application scenario of the embodiments of the present application.

[0131] The above are only specific embodiments of the present invention, but the protection scope of the present invention is not limited thereto. Any changes or substitutions that can be easily thought of by a person skilled in the art within the technical scope disclosed by the present invention should be included in the protection scope of the present invention. Therefore, the protection scope of the present invention should be based on the protection scope of the claims.

Claims

1. A transistor, characterized in that: include: Semiconductor layer; A source electrode and a drain electrode, respectively located on two sides of the semiconductor layer along a first direction; A first well region and a second well region, wherein the first well region and the second well region are spaced apart and both extend from a surface of the semiconductor layer away from the drain electrode to the inside of the semiconductor layer, and the first well region and the second well region have first doping ions; A gate structure, located on a side of the semiconductor layer away from the drain; a first doped portion having a second doping ion, comprising a first sub-portion and a second sub-portion connected to each other, wherein the first sub-portion is located in a first well region, and the second sub-portion is located in a second well region; a projection of the first sub-portion in the first direction is located within a projection of the gate structure in the first direction; and a projection of the second sub-portion in the first direction partially overlaps with a projection of the gate structure in the first direction; The first direction is parallel to the thickness direction of the semiconductor layer.

2. The transistor according to claim 1, characterized in that: The first well region, the second well region, the first sub-portion and the second sub-portion all extend along a second direction, the first sub-portion has a first end and a second end along the second direction, the second sub-portion has a third end and a fourth end along the second direction, and the first end and the third end are arranged along a third direction; the second direction and the third direction are both parallel to the semiconductor layer, and the third direction intersects with the second direction; The first doped portion further includes: a third sub-portion, the third sub-portion extending along the third direction, the third sub-portion connected to the first end and the third end.

3. The transistor according to claim 2, characterized in that The second end and the fourth end are arranged along the third direction; The first doped portion further includes a fourth sub-portion connected to the second end and the fourth end.

4. The transistor according to claim 2, characterized in that A size of the first sub-portion in the second direction is greater than a size of the second sub-portion in the second direction.

5. The transistor according to claim 2, characterized in that: The first well region includes a plurality of sub-well regions arranged at intervals along the second direction, the first sub-portion includes a plurality of first connecting portions and a plurality of second connecting portions alternately connected in sequence along the second direction, and the first connecting portion is located in the sub-well region.

6. The transistor according to claim 5, characterized in that The first connection portion has the same shape as the sub-well region.

7. The transistor according to claim 6, characterized in that The shape of the first connecting portion includes at least one of a bar, a polygon, a circle, and an ellipse; and / or, The shape of the second connection portion includes at least one of a bar, a polygon, a circle, and an ellipse.

8. The transistor according to claim 1, characterized in that The first doping ions include B and Al, and the second doping ions include N, P, As and Sb; and / or, The first doping ions include N, P, As, and Sb, and the second doping ions include B and Al.

9. The transistor according to claim 8, characterized in that The doping depth of the first doping ions in the first well region is 0.5 μm-15 μm; and / or, The doping concentration of the first doping ion is 1E16atom / cm 3 -1 E18atom / cm 3 .

10. The transistor according to claim 8, characterized in that The doping depth of the second doping ions in the first doping portion is 0.2 μm-0.5 μm; and / or, The doping concentration of the second doping ion is 1E18atom / cm 3 -1 E20atom / cm 3 .

11. The transistor according to claim 1, characterized in that: The transistor further comprises: a third well region extending from a surface of the semiconductor layer away from the drain electrode to an interior of the semiconductor layer, the third well region being spaced apart from the first well region and being located on a side of the first well region away from the second well region; The first doping portion further includes: A fifth sub-portion is located in the third well region, and a projection of the fifth sub-portion in the first direction partially overlaps with a projection of the gate structure in the first direction.

12. The transistor according to claim 1, characterized in that It also includes: a second doping portion, the second doping portion is located in the second well region, and the second doping portion penetrates the second sub-portion along the first direction, and the second doping portion has first doping ions.

13. The transistor according to claim 1, characterized in that Also includes: A connection structure, located between the source electrode and the first doped portion, and the connection structure connects the source electrode and the first doped portion; An isolation layer is located between the gate structure and the connection structure, and between the gate structure and the source.

14. A method for preparing a transistor, characterized in that: Performing doping on the semiconductor layer to form a first well region and a second well region, wherein the first well region and the second well region are spaced apart and both extend from the surface of the semiconductor layer to the inside of the semiconductor layer, and the first well region and the second well region have first doping ions; Performing a doping process on the semiconductor layer to form a first doped portion, wherein the first doped portion has second doping ions, the first doped portion includes a first sub-portion and a second sub-portion connected to each other, the first sub-portion is located in the first well region, and the second sub-portion is located in the second well region; forming a gate structure, wherein the gate structure is located at one side of the semiconductor layer, and in a first direction, the gate structure shields the first sub-portion and the first well region, and the gate structure exposes at least a portion of the second sub-portion, wherein the first direction is parallel to a thickness direction of the semiconductor layer; forming a source electrode, wherein the source electrode is located on a side of the semiconductor layer close to the gate structure; A drain is formed, wherein the drain is located at a side of the semiconductor layer away from the gate structure.

15. The method for preparing a transistor according to claim 14, characterized in that: The forming of the gate structure comprises: forming a gate dielectric layer located on one side of the semiconductor layer; forming a gate layer located on a side of the gate dielectric layer away from the semiconductor layer; forming an isolation layer covering the gate layer and the gate dielectric layer; The forming of the source includes: removing a portion of the isolation layer to expose at least a portion of the second sub-portion; forming a connection structure located on a side of the first doped portion away from the semiconductor layer; A conductive material is deposited to form a source electrode, wherein the source electrode contacts the connection structure.

16. An electronic device, characterized in that: The electronic device comprises the transistor according to any one of claims 1-13.

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