Manufacturing method of high-brightness thin film flip chip

Abstract

The invention discloses a manufacturing method of a high-brightness thin film flip chip, and relates to the technical field of semiconductors, and the method comprises the following steps: S1, depositing an AgNi alloy thin film on the light emitting surface of the thin film flip chip; s2, performing patterning treatment on the AgNi alloy film to obtain a plurality of blocky units arranged in an array, and forming a top-layer metasurface layer; and S3, depositing and forming a top layer protection layer on the top layer metasurface layer. According to the invention, a roughening treatment mode of chemical corrosion is avoided, the metasurface structure is formed on the light emitting surface of the thin film flip chip through patterning treatment, and the light precipitation rate of the thin film flip chip can be effectively improved, so that the brightness of the thin film flip chip is remarkably enhanced.

Description

Technical Field

[0001] The invention relates to the technical field of semiconductors, and in particular to a method for manufacturing a high-brightness thin-film flip chip. Background Art

[0002] At present, a thin film flip-chip LED (TFFC-LEDs) is available on the market. TFFC-LEDs introduce an electrode through-hole structure similar to flip-chip LEDs, design a through-hole for the n-electrode, lead the electrode from the bottom through GaN epitaxy, and add a special total reflection structure to the through-hole and the bottom, which can effectively solve the light absorption problem of the electrode. In addition, TFFC-LEDs use a sapphire substrate removal process to avoid the total reflection phenomenon caused by the sapphire substrate, thereby achieving a higher light extraction rate and a better light output angle.

[0003] However, due to the gap between the refractive index of the GaN epitaxial layer of TFFC-LEDs and the refractive index of air, photons are prone to total reflection at the GaN-air interface, which seriously affects the light extraction rate and weakens the brightness of TFFC-LEDs. Usually, technicians use chemical etching to roughen the light-emitting surface of the GaN epitaxial layer to reduce the total reflection of photons and achieve the purpose of improving the light extraction rate.

[0004] However, the chemical corrosion roughening treatment method has a limited effect on improving the light extraction efficiency of TFFC-LEDs. In addition, the chemical corrosion roughening process has poor stability, is easily interfered by external factors, and has poor repeatability. This will cause the light extraction efficiency of mass-produced TFFC-LEDs to fluctuate, and even excessive roughening may occur, resulting in damage to the photoelectric performance of TFFC-LEDs. Summary of the invention

[0005] The purpose of the present invention is to overcome the shortcomings of the prior art. The present invention provides a method for manufacturing a high-brightness thin-film flip chip, which avoids the use of a roughening treatment method using chemical corrosion. A super surface structure is formed on the light-emitting surface of the thin-film flip chip through patterning treatment, which can effectively improve the light extraction rate of the thin-film flip chip, thereby significantly enhancing the brightness of the thin-film flip chip.

[0006] The present invention provides a method for manufacturing a high-brightness thin-film flip chip, comprising the following steps:

[0007] S1, depositing a AgNi alloy thin film on the light-emitting surface of the thin film flip chip;

[0008] S2, patterning the AgNi alloy film to obtain a plurality of block units arranged in an array to form a top super surface layer;

[0009] S3. Depositing a top protective layer on the top super surface layer.

[0010] Specifically, the thickness of the AgNi alloy film is in the range of 1 to 50 nm; the distance between two adjacent block units is in the range of 10 to 200 μm.

[0011] Specifically, the material of the top protective layer is SiO2 or Al2O3, and the thickness of the top protective layer is in the range of 10 to 100 nm.

[0012] Specifically, before step S1, the method further includes:

[0013] S101, sequentially growing a U-GaN layer, an N-GaN layer, an MQW light-emitting layer and a P-GaN layer on a sapphire substrate to form an epitaxial layer;

[0014] S102, etching to form a first through hole at a preset position of the epitaxial layer, wherein the first through hole extends from the P-GaN layer to the N-GaN layer;

[0015] S103, cleaning the first through hole with a tetramethylamino hydroxide solution;

[0016] S104, depositing an ITO transparent conductive layer on the P-GaN layer, wherein the ITO transparent conductive layer avoids the first through hole;

[0017] S105, forming a first passivation layer by deposition along the surface of the ITO transparent conductive layer and the first through hole;

[0018] S106, etching to form a second through hole in the first passivation layer above the ITO transparent conductive layer, wherein the second through hole exposes the ITO transparent conductive layer;

[0019] S107, depositing a first Ag layer on the first passivation layer above the ITO transparent conductive layer, wherein the first Ag layer covers the second through hole;

[0020] S108, performing in-situ heat treatment on the first Ag layer to form a bottom super surface layer;

[0021] S109, depositing a second Ag layer and a TiW layer on the bottom super surface layer in sequence, wherein the bottom super surface layer, the second Ag layer and the TiW layer constitute a reflective layer;

[0022] S110, depositing a metal barrier layer on the reflective layer, wherein the metal barrier layer wraps a side wall of the reflective layer;

[0023] S111, depositing a second passivation layer along the surfaces of the first passivation layer and the metal barrier layer;

[0024] S112, etching and removing the first passivation layer and the second passivation layer above the bottom of the first through hole to form an N-type conductive through hole, wherein the N-GaN layer is exposed through the N-type conductive through hole;

[0025] S113, depositing a first bonding layer on the second passivation layer, wherein the first bonding layer fills the first through hole, and the first bonding layer is in contact with the N-GaN layer;

[0026] S114, bonding a conductive substrate on the first bonding layer through a second bonding layer;

[0027] S115, peeling off the sapphire substrate to expose the U-GaN layer; the light emitted by the MQW light-emitting layer is emitted from the U-GaN layer.

[0028] Specifically, after step S3, the method further includes:

[0029] S301, etching a predetermined area of ​​the top protective layer to form a conductive window, wherein the conductive window extends to the metal barrier layer;

[0030] S302, depositing a P-type electrode in the conductive window; a first gap exists between the P-type electrode and the sidewall of the conductive window;

[0031] S303, depositing an electrode protection layer in the conductive window, wherein the electrode protection layer fills the first gap;

[0032] S304, etching to form a conductive channel in a preset area of ​​the electrode protection layer, wherein the conductive channel exposes the top of the P-type electrode;

[0033] S305 , depositing an N-type electrode on a side of the conductive substrate away from the P-type electrode.

[0034] Specifically, the depth of the first through hole is in the range of 0.8 to 2 μm, the opening diameter of the first through hole is in the range of 20 to 200 μm, and the distance between two adjacent first through holes is in the range of 100 to 500 μm.

[0035] Specifically, in step S103, the concentration of the tetramethylamino hydroxide solution is in the range of 2-30 wt %, the cleaning time is in the range of 5-60 min, and the cleaning temperature is in the range of 25-90° C.

[0036] Specifically, in step S107, the thickness of the first Ag layer is in the range of 0.5 to 2 nm;

[0037] In step S108, the temperature range of the in-situ heat treatment is 100-180°C, the duration range of the in-situ heat treatment is 5-15 minutes, and the cooling rate after the in-situ heat treatment is 1-5°C / s;

[0038] In step S109 , the thickness of the second Ag layer is in the range of 50 to 250 nm, and the thickness of the TiW layer is in the range of 100 to 400 nm.

[0039] Specifically, in step S115, the sapphire substrate is peeled off by laser, the power range of the laser is 0.4-1.2W, and the sapphire substrate is heated to 60-120°C.

[0040] Specifically, the thickness of the electrode protection layer is in the range of 10 to 100 nm, and the material of the electrode protection layer is SiO2.

[0041] Compared with the prior art, the present invention has the following beneficial effects:

[0042] The manufacturing method of the high brightness thin film flip chip of the present invention first deposits an AgNi alloy thin film on the light-emitting surface of the thin film flip chip, then patterns the AgNi alloy thin film to obtain a plurality of block units arranged in an array to form a top super surface layer; finally, deposits a top protective layer on the top super surface layer. This avoids the use of chemical corrosion to roughen the light-emitting surface of the thin film flip chip, the process has high stability, and the super surface structure of the top super surface layer can effectively improve the light extraction rate of the thin film flip chip, thereby significantly enhancing the brightness of the thin film flip chip. BRIEF DESCRIPTION OF THE DRAWINGS

[0043] In order to more clearly illustrate the embodiments of the present invention or the technical solutions in the prior art, the drawings required for use in the embodiments or the description of the prior art will be briefly introduced below. Obviously, the drawings described below are only some embodiments of the present invention. For ordinary technicians in this field, other drawings can be obtained based on these drawings without paying creative work.

[0044] Figure 1 1 is a schematic diagram of a first process of a method for manufacturing a high-brightness thin-film flip chip according to an embodiment of the present invention;

[0045] Figure 2 Schematic diagram of the structure of the AgNi alloy film in an embodiment of the present invention;

[0046] Figure 3 is a schematic diagram of the structure of the top super surface layer in an embodiment of the present invention;

[0047] Figure 4 is a schematic diagram of the structure of the top protective layer in an embodiment of the present invention;

[0048] Figure 5 1 is a second process diagram of the method for manufacturing a high-brightness thin-film flip chip according to an embodiment of the present invention;

[0049] Figure 6 is a schematic structural diagram of a sapphire substrate and an epitaxial layer in an embodiment of the present invention;

[0050] Figure 7 is a schematic structural diagram of a first through hole in an embodiment of the present invention;

[0051] Figure 8 is a schematic structural diagram of an ITO transparent conductive layer in an embodiment of the present invention;

[0052] Fig. 9 is a schematic structural diagram of a first passivation layer in an embodiment of the present invention;

[0053] Fig.10 is a schematic structural diagram of a second through hole in an embodiment of the present invention;

[0054] Fig.11 is a schematic structural diagram of the first Ag layer in an embodiment of the present invention;

[0055] Fig.12 is a schematic diagram of the structure of the bottom super surface layer in an embodiment of the present invention;

[0056] Fig.13 is a schematic structural diagram of a second Ag layer and a TiW layer in an embodiment of the present invention;

[0057] Fig.14 is a schematic structural diagram of a metal barrier layer in an embodiment of the present invention;

[0058] Fig.15 is a schematic structural diagram of a second passivation layer in an embodiment of the present invention;

[0059] Fig.16 is a schematic structural diagram of an N-type conductive through hole in an embodiment of the present invention;

[0060] Fig.17 is a schematic structural diagram of the first bonding layer in an embodiment of the present invention;

[0061] Fig.18 is a schematic structural diagram of a second bonding layer and a conductive substrate in an embodiment of the present invention;

[0062] Fig.19 is a schematic structural diagram of peeling off a sapphire substrate in an embodiment of the present invention;

[0063] Fig. 20 1 is a third flow chart of the method for manufacturing a high-brightness thin-film flip chip in an embodiment of the present invention;

[0064] Fig.21 is a schematic structural diagram of a conductive window in an embodiment of the present invention;

[0065] Fig. 22 is a schematic structural diagram of a P-type electrode in an embodiment of the present invention;

[0066] Fig.23 is a schematic structural diagram of an electrode protection layer in an embodiment of the present invention;

[0067] Fig.24 is a schematic structural diagram of a conductive channel in an embodiment of the present invention;

[0068] Fig.25 Schematic diagram of the structure of an N-type electrode in an embodiment of the present invention.

[0069] In the accompanying drawings, 1, AgNi alloy film; 2, top super surface layer; 3, top protective layer; 4, sapphire substrate; 5, U-GaN layer; 6, N-GaN layer; 7, MQW light-emitting layer; 8, P-GaN layer; 101, epitaxial layer; 102, first through hole; 104, ITO transparent conductive layer; 105, first passivation layer; 106, second through hole; 107, first Ag layer; 108, bottom super surface layer; 109, second Ag layer; 109ˊ, TiW layer; 110, metal barrier layer; 111, second passivation layer; 112, N-type conductive through hole; 113, first bonding layer; 114, second bonding layer; 114ˊ, conductive substrate; 1134, eutectic bonding layer; 301, conductive window; 302, P-type electrode; 303, electrode protection layer; 304, conductive channel; 305, N-type electrode. DETAILED DESCRIPTION

[0070] The following will be combined with the drawings in the embodiments of the present invention to clearly and completely describe the technical solutions in the embodiments of the present invention. Obviously, the described embodiments are only part of the embodiments of the present invention, not all of the embodiments. Based on the embodiments of the present invention, all other embodiments obtained by ordinary technicians in this field without creative work are within the scope of protection of the present invention.

[0071] The present invention provides a method for manufacturing a high-brightness thin-film flip chip. Figure 1 The first process diagram of the method for manufacturing a high-brightness thin-film flip chip in an embodiment of the present invention is shown, and the method comprises the following steps:

[0072] S1, depositing a AgNi alloy thin film on the light-emitting surface of the thin film flip chip;

[0073] Figure 2The schematic diagram of the structure of the AgNi alloy film in the embodiment of the present invention is shown. The AgNi alloy film 1 can be deposited on the light-emitting surface of the thin film flip chip by magnetron sputtering technology without damaging the original film layer of the thin film flip chip.

[0074] AgNi alloy has high reflectivity, oxidation resistance, corrosion resistance, and high temperature resistance. Using AgNi alloy as a material for thin film deposition can prevent Ag from oxidizing and turning black during the deposition process, which affects the light extraction effect. In addition, AgNi alloy can effectively prevent Ag migration, thereby preventing Ag from diffusing and migrating into the GaN layer of the chip during long-term use of the thin film flip chip, reducing the risk of leakage of the thin film flip chip.

[0075] Specifically, the thickness of the AgNi alloy film 1 is in the range of 1 to 50 nm, which can be selected according to specific needs, such as 1 nm, 5 nm, 10 nm, 20 nm, 30 nm, 40 nm, 50 nm, etc.

[0076] S2, patterning the AgNi alloy film to obtain a plurality of block units arranged in an array to form a top super surface layer;

[0077] Figure 3 A schematic structural diagram of the top super surface layer in an embodiment of the present invention is shown. The AgNi alloy film 1 can be patterned by photolithography technology and dry etching, and the AgNi alloy film 1 is divided into a plurality of array-arranged block units. The plurality of array-arranged block units constitute the top super surface layer 2. The process has good stability and is not easily disturbed by external factors.

[0078] Specifically, the shape of any of the block units can be a triangle, trapezoid, circle, rhombus, rectangle, square or irregular shape, etc.; preferably, the shape of the block unit is circular, which can be adapted to thin film flip chips of different wavelengths and has wide applicability; among them, when the block unit is a circular structure with a diameter of 100nm, the top super surface layer 2 has excellent light extraction efficiency.

[0079] Furthermore, the spacing between two adjacent block units ranges from 10 to 200 μm, which can be adjusted according to the thin film flip chip of different wavelengths, such as 10 μm, 20 μm, 30 μm, 40 μm, 50 μm, 100 μm, 150 μm, 200 μm, etc.

[0080] S3, depositing a top protective layer on the top super surface layer;

[0081] Figure 4The schematic diagram of the structure of the top protective layer in the embodiment of the present invention is shown, and the top protective layer 3 can be deposited by atomic layer deposition technology or plasma enhanced chemical vapor deposition technology. The top protective layer 3 can further prevent the migration of Ag in the block unit, and can also effectively protect the top super surface layer 2 to prevent the top super surface layer 2 from being oxidized.

[0082] Specifically, the material of the top protective layer 3 is SiO2 or Al2O3, and the thickness of the top protective layer 3 is in the range of 10 to 100 nm, which can effectively isolate the top super surface layer 2 from contact with the external environment. Preferably, the atomic layer deposition technology is used to deposit 50 nm thick Al2O3 as the top protective layer 3. Al2O3 has good optical properties, a relatively low refractive index, and a wide light transmission range, and will not affect the top super surface layer 2's regulation of light.

[0083] The manufacturing method of the high brightness thin film flip chip of the present invention first deposits an AgNi alloy thin film 1 on the light-emitting surface of the thin film flip chip, then patterns the AgNi alloy thin film 1 to obtain a plurality of block units arranged in an array to form a top super surface layer 2; finally, deposits a top protective layer 3 on the top super surface layer 2. In this way, the light-emitting surface of the thin film flip chip is roughened by chemical corrosion, the process is highly stable, and the super surface structure of the top super surface layer 2 can effectively improve the light extraction rate of the thin film flip chip, thereby significantly enhancing the brightness of the thin film flip chip.

[0084] Figure 5 The second process diagram of the method for manufacturing a high-brightness thin-film flip chip in an embodiment of the present invention is shown. In the method for manufacturing a high-brightness thin-film flip chip of the present invention, before step S1, the method further includes:

[0085] S101, sequentially growing a U-GaN layer, an N-GaN layer, an MQW light-emitting layer and a P-GaN layer on a sapphire substrate to form an epitaxial layer;

[0086] Figure 6 A schematic structural diagram of a sapphire substrate and an epitaxial layer in an embodiment of the present invention is shown.

[0087] The sapphire substrate 4 can be a patterned sapphire substrate, a patterned sapphire substrate with a silicon dioxide array, or a flat sapphire substrate without a pattern; preferably, the sapphire substrate 4 is a patterned sapphire substrate, so that the U-GaN layer 5 directly deposited on the patterned sapphire substrate imprints its pattern, so that after the sapphire substrate 4 is peeled off, the exposed U-GaN layer 5 can have a patterned surface.

[0088] The U-GaN layer 5 is an undoped gallium nitride layer, the N-GaN layer 6 is an N-type doped gallium nitride layer, the MQW light-emitting layer 7 is a light-emitting system composed of multiple quantum wells, and the P-GaN layer 8 is a P-type doped gallium nitride layer; the U-GaN layer 5, the N-GaN layer 6, the MQW light-emitting layer 7 and the P-GaN layer 8 together constitute the epitaxial layer 101.

[0089] S102, etching to form a first through hole at a preset position of the epitaxial layer, wherein the first through hole extends from the P-GaN layer to the N-GaN layer;

[0090] Figure 7 The schematic diagram of the structure of the first through hole in the embodiment of the present invention is shown. The first through hole 102 can be etched on the epitaxial layer 101 by using photolithography technology and inductively coupled plasma etching technology as the first electrical connection channel. Specifically, the depth of the first through hole 102 ranges from 0.8 to 2 μm, the aperture diameter of the first through hole 102 ranges from 20 to 200 μm, and the spacing between two adjacent first through holes 102 ranges from 100 to 500 μm, so that a first electrical connection channel with a good arrangement density can be formed to prepare for the conduction of subsequent current.

[0091] Preferably, the depth of the first through hole 102 is 1.2 μm, the aperture diameter of the first through hole 102 is 50 μm, the spacing between two adjacent first through holes 102 is 150 μm, and the size and arrangement density of the first through holes 102 are reasonable, taking into account both the light-emitting area and the current extraction efficiency, which is beneficial to improving the brightness of the thin film flip chip.

[0092] In some specific embodiments, the diameter of the first through hole 102 gradually decreases from the P-GaN layer 8 to the N-GaN layer 6 , and its longitudinal cross-section forms an inverted trapezoidal structure, which is conducive to reducing the difficulty of growing subsequent film layers on the hole wall of the first through hole 102 .

[0093] S103, cleaning the first through hole with a tetramethylamino hydroxide solution;

[0094] Under the protection of the photoresist, the entire epitaxial wafer is immersed in a tetramethylammonium hydroxide solution. The tetramethylammonium hydroxide solution can improve the flatness of the first through hole 102 after etching, and can eliminate the dangling bonds on the surface of the gallium nitride after etching, thereby reducing the carrier capture phenomenon caused by the edge effect, which is beneficial to improving the radiation recombination efficiency of the thin film flip chip and further improving the luminescence performance of the thin film flip chip.

[0095] In addition, the hole wall of the first through hole 102 treated with the tetramethylammonium hydroxide solution has good adhesion with the first passivation layer 105 deposited subsequently, which can reduce the occurrence of micro leakage of the thin film flip chip under high voltage use.

[0096] Specifically, the concentration of the tetramethylamino hydroxide solution is in the range of 2 to 30 wt %, the cleaning time is in the range of 5 to 60 min, and the cleaning temperature is in the range of 25 to 90° C., which can be adjusted according to the size and arrangement density of the first through holes 102 .

[0097] Preferably, the concentration of the tetramethylamino hydroxide solution is 10 wt %, the cleaning time is 5 min, and the cleaning temperature is 75° C., taking both cleaning efficiency and cleaning effect into consideration.

[0098] S104, depositing an ITO transparent conductive layer on the P-GaN layer, wherein the ITO transparent conductive layer avoids the first through hole;

[0099] Figure 8 The schematic diagram of the structure of the ITO transparent conductive layer in the embodiment of the present invention is shown. The ITO transparent conductive layer 104 can be deposited by using photolithography technology and magnetron sputtering technology; specifically, the thickness of the ITO transparent conductive layer 104 is in the range of 10 to 20 nm, and can be used as an ohmic contact layer. Preferably, the thickness of the ITO transparent conductive layer 104 is 10 nm, and the light transmission performance is good.

[0100] Further, the ITO transparent conductive layer 104 is rapidly heat treated for 3 to 6 minutes in an oxygen atmosphere at 400 to 500° C., which can effectively improve the crystal structure of the ITO transparent conductive layer 104, improve the conductivity of the ITO transparent conductive layer 104, and enhance the light transmission performance of the ITO transparent conductive layer 104. Preferably, the ITO transparent conductive layer 104 is rapidly heat treated for 3 minutes in an oxygen atmosphere at 450° C., with high treatment efficiency.

[0101] S105, forming a first passivation layer by deposition along the surface of the ITO transparent conductive layer and the first through hole;

[0102] Fig. 9 The schematic diagram of the structure of the first passivation layer in the embodiment of the present invention is shown. The first passivation layer 105 can be deposited by chemical vapor deposition technology. Specifically, the material of the first passivation layer 105 can be SiO2, SiN x , Al2O3, the thickness of the first passivation layer 105 is in the range of 50 to 500 nm, and has a good passivation protection effect.

[0103] Preferably, the material of the first passivation layer 105 is SiO 2 , the thickness of the first passivation layer 105 is 400 nm, and the structural strength is good.

[0104] S106, etching to form a second through hole in the first passivation layer above the ITO transparent conductive layer, wherein the second through hole exposes the ITO transparent conductive layer;

[0105] Fig.10 A schematic diagram of the structure of the second through hole in an embodiment of the present invention is shown. The second through hole 106 can be etched in the first passivation layer 105 by using photolithography technology and wet etching process to serve as a second electrical connection channel; specifically, the diameter of the second through hole 106 ranges from 1 to 50 μm, and the spacing between two adjacent second through holes 106 ranges from 10 to 100 μm, which can form a second electrical connection channel with a good arrangement density to prepare for the subsequent current conduction.

[0106] Preferably, the diameter of the second through hole 106 is 10 μm, and the distance between two adjacent second through holes 106 is 25 μm, so that a higher density of second through holes 106 can be formed, which is conducive to uniform injection of current into the ITO transparent conductive layer 104 .

[0107] S107, depositing a first Ag layer on the first passivation layer above the ITO transparent conductive layer, wherein the first Ag layer covers the second through hole;

[0108] Fig.11 The schematic diagram of the structure of the first Ag layer in the embodiment of the present invention is shown. The first Ag layer 107 can be deposited by photolithography technology and magnetron sputtering technology. Specifically, the thickness of the first Ag layer 107 is in the range of 0.5 to 2 nm, which is very thin, and is prepared for the subsequent in-situ heat treatment to form the bottom super surface layer 108. Preferably, the thickness of the first Ag layer 107 is 1 nm, and the heat treatment has an excellent effect on it.

[0109] S108, performing in-situ heat treatment on the first Ag layer to form a bottom super surface layer;

[0110] Fig.12 The schematic diagram of the structure of the bottom super surface layer in the embodiment of the present invention is shown. After the first Ag layer 107 is deposited and formed, the first Ag layer 107 is directly heated in situ in the device cavity to form a bottom super surface layer 108; specifically, the temperature range of the in-situ heat treatment is 100-180°C, so that the first Ag layer 107 is agglomerated under the action of heat and surface to form a dispersed island structure. These dispersed island structures constitute the bottom super surface layer 108, which can change the propagation path of light and can effectively improve the light extraction rate of the thin film flip chip, thereby significantly enhancing the brightness of the thin film flip chip. Moreover, the bottom super surface layer 108 can produce a synergistic effect with the top super surface layer 2, significantly weakening the total reflection phenomenon at the gallium nitride-air interface, thereby effectively improving the light extraction rate of the thin film flip chip.

[0111] Preferably, the temperature of the in-situ heat treatment is 130° C., which can promote rapid molding of the island structure and is not likely to damage other film layer structures.

[0112] Furthermore, the duration of the in-situ heat treatment is in the range of 5 to 15 minutes, so as to ensure that the first Ag layer 107 can be fully aggregated to form a dispersed island structure; preferably, the duration of the in-situ heat treatment is 5 minutes, which has high production efficiency.

[0113] In some specific embodiments, after the in-situ heat treatment is completed, the bottom super surface layer 108 is cooled by blowing nitrogen or cooling the carrier cooling water to improve the structural stability of the bottom super surface layer 108. Specifically, the cooling rate is controlled to be in the range of 1 to 5°C / s, which is conducive to improving the performance of the bottom super surface layer 108 and improving its structural strength; preferably, the cooling rate is controlled to be 5°C / s, the cooling rate is fast, and the morphology of the formed island structure is good.

[0114] Generally, the size of the island structure increases with the increase of the thickness of the first Ag layer 107. For thin film flip chips of different wavelengths, the effect of the underlying super surface layer 108 can be enhanced by adjusting the size of the island structure.

[0115] S109, depositing a second Ag layer and a TiW layer on the bottom super surface layer in sequence, wherein the bottom super surface layer, the second Ag layer and the TiW layer constitute a reflective layer;

[0116] Fig.13 The schematic diagram of the structure of the second Ag layer and the TiW layer in the embodiment of the present invention is shown. The second Ag layer 109 and the TiW layer 109' can be deposited in sequence by magnetron sputtering technology. Specifically, the thickness of the second Ag layer 109 is in the range of 50 to 250 nm. Together with the underlying super surface layer 108, a good diffuse reflection effect can be formed, which is beneficial to improving the brightness of the thin film flip chip. The thickness of the TiW layer 109' is in the range of 100 to 400 nm, which can effectively protect the second Ag layer 109 and prevent the second Ag layer 109 from being damaged when depositing subsequent film layers.

[0117] Preferably, the thickness of the second Ag layer 109 is 180 nm, and the thickness of the TiW layer 109' is 250 nm. Together with the underlying super surface layer 108, the reflective layer has excellent reflective effect.

[0118] S110, depositing a metal barrier layer on the reflective layer, wherein the metal barrier layer wraps a side wall of the reflective layer;

[0119] Fig.14The schematic diagram of the structure of the metal barrier layer in the embodiment of the present invention is shown. The metal barrier layer 110 can be deposited by using photolithography technology and electron beam evaporation technology. The metal barrier layer 110 wraps the side wall of the reflective layer to prevent Ag migration and diffusion. In addition, the metal barrier layer 110 is also the main structure of the subsequent fan-out P-type electrode 302.

[0120] In some specific embodiments, the metal barrier layer 110 adopts a stacked metal structure, and the metal barrier layer 110 includes but is not limited to a stack of one or more of Ni, Ti, Au, Pt, Ru, La, Cr, and Al, has good density and high strength, and can effectively block the migration and diffusion of Ag.

[0121] S111, depositing a second passivation layer along the surfaces of the first passivation layer and the metal barrier layer;

[0122] Fig.15 The schematic diagram of the structure of the second passivation layer in the embodiment of the present invention is shown. The second passivation layer 111 can be formed by deposition using chemical vapor deposition technology. The material of the second passivation layer 111 can be SiO2, SiN x , Al2O3, and a combination of one or more thereof, the thickness of the second passivation layer 111 is in the range of 300 to 1500 nm, which can provide excellent passivation protection effect.

[0123] Preferably, the material of the second passivation layer 111 is SiO 2 , and the thickness of the second passivation layer 111 is 600 nm, which can form a good match with the first passivation layer 105 and further improve the passivation protection effect.

[0124] S112, etching and removing the first passivation layer and the second passivation layer above the bottom of the first through hole to form an N-type conductive through hole, wherein the N-GaN layer is exposed through the N-type conductive through hole;

[0125] Fig.16 The schematic diagram of the structure of the N-type conductive via in the embodiment of the present invention is shown. The N-type conductive via 112 can be opened in the first passivation layer 105 and the second passivation layer 111 above the bottom of the first via 102 by using photolithography technology and inductively coupled plasma etching technology, so as to prepare for the subsequent connection of the first bonding layer 113 to the N-GaN layer 6. Specifically, the diameter of the N-type conductive via 112 ranges from 10 to 100 μm, which is slightly smaller than the bottom diameter of the first via 102, and has a large current conduction efficiency; preferably, the diameter of the N-type conductive via 112 is 70 μm, which basically meets the use requirements of large current.

[0126] S113, depositing a first bonding layer on the second passivation layer, wherein the first bonding layer fills the first through hole, and the first bonding layer is in contact with the N-GaN layer;

[0127] Fig.17 A schematic structural diagram of the first bonding layer in an embodiment of the present invention is shown. The first bonding layer 113 can be deposited by electron beam evaporation technology. The first bonding layer 113 adopts a laminated metal structure. The first bonding layer 113 includes but is not limited to one or more stacks of Ni, Ti, Au, Pt, Ru, La, Cr, Al, Sn, and In, which can exert a good bonding effect and reduce the internal stress during the bonding process.

[0128] Specifically, the first bonding layer 113 is a Cr / Ti / Au / Sn / Au laminated metal structure, and the thickness of the Cr / Ti / Au / Sn / Au laminated metal structure ranges from 1 to 3 μm, which can not only exert a good bonding effect, but also effectively reduce the internal stress during the bonding process. Preferably, the thickness of the Cr / Ti / Au / Sn / Au laminated metal structure is 2.5 μm, and the bonding effect is stable and reliable.

[0129] S114, bonding a conductive substrate on the first bonding layer through a second bonding layer;

[0130] Fig.18 A schematic structural diagram of a second bonding layer and a conductive substrate in an embodiment of the present invention is shown.

[0131] Specifically, the second bonding layer 114 is a Ti / Au laminated metal structure, and the thickness of the Ti / Au laminated metal structure ranges from 0.5 to 1.5 μm, which can effectively cooperate with the first bonding layer 113 to form a good bonding effect and reduce the internal stress during the bonding process. Preferably, the thickness of the Ti / Au laminated metal structure is 1 μm, and the bonding effect is stable and reliable.

[0132] Specifically, the conductive substrate 114 ′ may be a conductive silicon substrate or a metal substrate; preferably, the conductive substrate 114 ′ is a metal substrate, which has high conductivity, good heat dissipation performance, and high mechanical strength.

[0133] Specifically, the first bonding layer 113 and the second bonding layer 114 are bonded by hot pressing eutectic bonding, including: first, applying a certain pressure to the conductive substrate 114' and the sapphire substrate 4 at room temperature, so that the surface of the first bonding layer 113 and the surface of the second bonding layer 114 diffuse into each other to form an interconnected structure; then, applying 3000kg / cm2 of heat to the conductive substrate 114' and the sapphire substrate 4 at 260°C. 2 The pressure is applied and maintained for 15 minutes, so that the first bonding layer 113 and the second bonding layer 114 are completely diffused and fused to form a eutectic bonding layer 1134.

[0134] In this way, the bonding quality between the first bonding layer 113 and the second bonding layer 114 can be effectively improved, the voids in the eutectic bonding layer 1134 can be reduced, and the bonding is firm and reliable.

[0135] S115, peeling off the sapphire substrate to expose the U-GaN layer; the light emitted by the MQW light-emitting layer is emitted from the U-GaN layer;

[0136] Fig.19 The schematic diagram of the structure of stripping the sapphire substrate in the embodiment of the present invention is shown. The sapphire substrate 4 can be stripped by laser stripping technology. The laser power is selected to be 0.4-1.2W, and the sapphire substrate 4 is heated to 60-120°C, which has a good stripping effect on the sapphire substrate 4. Preferably, the laser power is selected to be 0.45W, and the sapphire substrate 4 is heated to 100°C, which has little damage to the U-GaN layer 5.

[0137] Furthermore, the chip structure body after stripping the sapphire substrate 4 is immersed in a 10% dilute hydrochloric acid solution for 3 to 6 minutes to remove the gallium nitride remaining on the surface of the U-GaN layer 5; preferably, the immersion time is 4 minutes, which causes little damage to the chip structure body. It is subsequently washed with ultrapure water to remove the residual HCl.

[0138] The manufacturing method of the high-brightness thin-film flip chip of the present invention can significantly weaken the total reflection phenomenon at the gallium nitride-air interface through the joint synergistic effect of the bottom super-surface layer 108 and the top super-surface layer 2, thereby further improving the light extraction rate of the thin-film flip chip, so that the brightness of the thin-film flip chip is effectively improved.

[0139] Fig. 20 The third process diagram of the method for manufacturing a high-brightness thin-film flip chip in an embodiment of the present invention is shown. In the method for manufacturing a high-brightness thin-film flip chip of the present invention, after step S3, the method further includes:

[0140] S301, etching a predetermined area of ​​the top protective layer to form a conductive window, wherein the conductive window extends to the metal barrier layer;

[0141] Fig.21 A schematic diagram of the structure of the conductive window in an embodiment of the present invention is shown. The conductive window 301 can be formed by etching the chip edge area preset in the top protective layer 3 using photolithography technology and inductively coupled plasma etching technology. Specifically, the conductive window 301 is a rectangular structure with a large area, which is convenient for the subsequent formation of a large electrode.

[0142] In some specific embodiments, the etching gas used to etch and form the conductive window 301 includes, but is not limited to, one or more of Ar, O 2 , Cl 2 , BCl 3 , and CF 4 .

[0143] S302, depositing a P-type electrode in the conductive window; a first gap exists between the P-type electrode and the sidewall of the conductive window;

[0144] Fig. 22 A schematic diagram of the structure of the P-type electrode in an embodiment of the present invention is shown. The P-type electrode 302 can be deposited by electron beam evaporation technology. The P-type electrode 302 adopts a laminated metal structure. The P-type electrode 302 includes but is not limited to one or more stacks of Ni, Ti, Au, Pt, Ru, La, Cr, Al, Sn, and In, which is beneficial to improving the structural stability of the P-type electrode 302 so that it can withstand large currents.

[0145] Specifically, the P-type electrode 302 is a first Cr / Ti / Ni / Au laminated metal structure, the thickness of the first Cr / Ti / Ni / Au laminated metal structure is in the range of 0.5 to 1.5 μm, the structure has good stability, and is convenient for subsequent lead welding. Preferably, the thickness of the first Cr / Ti / Ni / Au laminated metal structure is 1 μm.

[0146] S303, depositing an electrode protection layer in the conductive window, wherein the electrode protection layer fills the first gap;

[0147] Fig.23 A schematic diagram of the structure of the electrode protection layer in an embodiment of the present invention is shown. The electrode protection layer 303 can be deposited by plasma enhanced chemical vapor deposition technology. Specifically, the thickness of the electrode protection layer 303 is in the range of 10 to 100 nm. The material of the electrode protection layer 303 is SiO2, which can prevent a short circuit between the side wall of the conductive window 301 and the P-type electrode 302.

[0148] Preferably, the thickness of the electrode protection layer 303 is 60 nm, so as to facilitate subsequent etching in the electrode protection layer 303 to form a conductive channel 304 of sufficient depth.

[0149] S304, etching to form a conductive channel in a preset area of ​​the electrode protection layer, wherein the conductive channel exposes the top of the P-type electrode;

[0150] Fig.24 A schematic diagram of the structure of the conductive channel in an embodiment of the present invention is shown. Photolithography technology and inductively coupled plasma etching technology can be used to etch a conductive channel 304 in a preset lead welding area of ​​the electrode protection layer 303. The conductive channel 304 covers the side wall of the conductive window 301, which can prevent the P-type electrode 302 from touching the side wall of the conductive window 301 during lead welding and causing a short circuit.

[0151] In some specific embodiments, the etching gas used to etch and form the conductive channel 304 includes, but is not limited to, one or more of Ar, O 2 , Cl 2 , BCl 3 , and CF 4 .

[0152] S305, depositing an N-type electrode on a side of the conductive substrate away from the P-type electrode;

[0153] Fig.25 The schematic diagram of the structure of the N-type electrode in the embodiment of the present invention is shown. The N-type electrode 305 can be deposited by electron beam evaporation technology. The N-type electrode 305 covers an entire surface of the conductive substrate 114', has a large area, good conductivity, and high heat dissipation performance. The N-type electrode 305 adopts a laminated metal structure. The N-type electrode 305 includes but is not limited to one or more stacks of Ni, Ti, Au, Pt, Ru, La, Cr, Al, Sn, and In, which is beneficial to improving the structural stability of the N-type electrode 305 so that it can withstand large currents.

[0154] Specifically, the N-type electrode 305 is a second Cr / Ti / Ni / Au laminated metal structure, the thickness of the second Cr / Ti / Ni / Au laminated metal structure is in the range of 0.5 to 1.0 μm, the structural stability is good, and it is convenient for subsequent chip mounting. Preferably, the thickness of the second Cr / Ti / Ni / Au laminated metal structure is 0.8 μm.

[0155] The manufacturing method of the high-brightness thin-film flip chip of the present invention arranges the N-type electrode 305 and the P-type electrode 302 outside the main body of the chip structure, which will neither absorb nor weaken the light inside the chip, nor block the light emitting from the U-GaN layer 5, which is beneficial to improving the light extraction rate of the thin-film flip chip, thereby helping to improve the brightness of the thin-film flip chip; moreover, both the N-type electrode 305 and the P-type electrode 302 adopt a laminated metal structure, which can effectively improve the structural stability of the electrode, enable it to withstand large currents, and play a positive role in improving the brightness of the thin-film flip chip.

[0156] Radiant flux test

[0157] While keeping the other film layer structures the same, thin film flip chips without super surface layer, with only top super surface layer, and with top super surface layer and bottom super surface layer were made respectively, and the radiation flux test was carried out under the same conditions. The results are shown in Table 1:

[0158] Table 1 Comparison of radiation flux of thin film flip chips with different structures

[0159]

[0160]

[0161] It can be seen from Table 1 that compared with the thin film flip chip without a super surface layer, the single top super surface layer can effectively improve the radiation flux of the thin film flip chip, which means that the single top super surface layer can effectively improve the light extraction rate of the thin film flip chip; the combined structure of the top super surface layer and the bottom super surface layer can extremely significantly improve the radiation flux of the thin film flip chip, which means that the combined structure of the top super surface layer and the bottom super surface layer can extremely significantly improve the light extraction rate of the thin film flip chip.

[0162] The above is a detailed introduction to the manufacturing method of a high-brightness thin-film flip chip provided by an embodiment of the present invention. Specific examples are used herein to illustrate the principles and implementation methods of the present invention. The description of the above embodiments is only used to help understand the method of the present invention and its core idea; at the same time, for general technical personnel in the field, according to the idea of ​​the present invention, there will be changes in the specific implementation method and application scope. In summary, the content of this specification should not be understood as a limitation on the present invention.

Claims

1. A method for manufacturing a high brightness thin film flip chip, characterized in that: The following steps are involved: S1, depositing a AgNi alloy thin film on the light-emitting surface of the thin film flip chip; S2, patterning the AgNi alloy film to obtain a plurality of block units arranged in an array to form a top super surface layer; S3. Depositing a top protective layer on the top super surface layer.

2. The method for manufacturing a high brightness thin film flip chip according to claim 1, characterized in that: The thickness of the AgNi alloy film ranges from 1 to 50 nm; the distance between two adjacent block units ranges from 10 to 200 μm.

3. The method for manufacturing a high brightness thin film flip chip according to claim 1, characterized in that: The material of the top protective layer is SiO2 or Al2O3, and the thickness of the top protective layer is in the range of 10 to 100 nm.

4. The method for manufacturing a high brightness thin film flip chip according to claim 1, characterized in that: Before step S1, the method further includes: 101 S101, sequentially growing a U-GaN layer, an N-GaN layer, an MQW light-emitting layer and a P-GaN layer on a sapphire substrate to form an epitaxial layer; S102, etching to form a first through hole at a preset position of the epitaxial layer, wherein the first through hole extends from the P-GaN layer to the N-GaN layer; S103, cleaning the first through hole with a tetramethylamino hydroxide solution; S104, depositing an ITO transparent conductive layer on the P-GaN layer, wherein the ITO transparent conductive layer avoids the first through hole; S105, forming a first passivation layer by deposition along the surface of the ITO transparent conductive layer and the first through hole; S106, etching to form a second through hole in the first passivation layer above the ITO transparent conductive layer, wherein the second through hole exposes the ITO transparent conductive layer; S107, depositing a first Ag layer on the first passivation layer above the ITO transparent conductive layer, wherein the first Ag layer covers the second through hole; S108, performing in-situ heat treatment on the first Ag layer to form a bottom super surface layer; S109, depositing a second Ag layer and a TiW layer on the bottom super surface layer in sequence, wherein the bottom super surface layer, the second Ag layer and the TiW layer constitute a reflective layer; S110, depositing a metal barrier layer on the reflective layer, wherein the metal barrier layer wraps a side wall of the reflective layer; S111, depositing a second passivation layer along the surfaces of the first passivation layer and the metal barrier layer; S112, etching and removing the first passivation layer and the second passivation layer above the bottom of the first through hole to form an N-type conductive through hole, wherein the N-GaN layer is exposed through the N-type conductive through hole; S113, depositing a first bonding layer on the second passivation layer, wherein the first bonding layer fills the first through hole, and the first bonding layer is in contact with the N-GaN layer; S114, bonding a conductive substrate on the first bonding layer through a second bonding layer; S115, peeling off the sapphire substrate to expose the U-GaN layer; the light emitted by the MQW light-emitting layer is emitted from the U-GaN layer.

5. The method for manufacturing a high brightness thin film flip chip according to claim 4, characterized in that: After step S3, the method further includes: S301, etching a predetermined area of ​​the top protective layer to form a conductive window, wherein the conductive window extends to the metal barrier layer; S302, depositing a P-type electrode in the conductive window; a first gap exists between the P-type electrode and the sidewall of the conductive window; S303, depositing an electrode protection layer in the conductive window, wherein the electrode protection layer fills the first gap; S304, etching to form a conductive channel in a preset area of ​​the electrode protection layer, wherein the conductive channel exposes the top of the P-type electrode; S305 , depositing an N-type electrode on a side of the conductive substrate away from the P-type electrode.

6. The method for manufacturing a high brightness thin film flip chip according to claim 4, characterized in that: The depth of the first through hole is in the range of 0.8 to 2 μm, the opening diameter of the first through hole is in the range of 20 to 200 μm, and the spacing between two adjacent first through holes is in the range of 100 to 500 μm.

7. The method for manufacturing a high brightness thin film flip chip according to claim 4, characterized in that: In step S103, the concentration of the tetramethylamino hydroxide solution is in the range of 2-30 wt%, the cleaning time is in the range of 5-60 min, and the cleaning temperature is in the range of 25-90°C.

8. The method for manufacturing a high brightness thin film flip chip according to claim 4, characterized in that: In step S107, the thickness of the first Ag layer ranges from 0.5 to 2 nm; In step S108, the temperature range of the in-situ heat treatment is 100-180°C, the duration range of the in-situ heat treatment is 5-15 minutes, and the cooling rate after the in-situ heat treatment is 1-5°C / s; In step S109 , the thickness of the second Ag layer is in the range of 50 to 250 nm, and the thickness of the TiW layer is in the range of 100 to 400 nm.

9. The method for manufacturing a high brightness thin film flip chip according to claim 4, characterized in that: In step S115, the sapphire substrate is peeled off by laser, the power of the laser is in the range of 0.4 to 1.2 W, and the sapphire substrate is heated to 60 to 120°C.

10. The method for manufacturing a high brightness thin film flip chip according to claim 5, characterized in that: The thickness of the electrode protection layer is in the range of 10 to 100 nm, and the material of the electrode protection layer is SiO2.

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