Light emitting diode chip and preparation method thereof

Abstract

The invention discloses a light-emitting diode chip and a preparation method thereof, and relates to the field of semiconductor photoelectric devices. The light-emitting diode chip comprises a substrate, an N-type semiconductor layer, an active layer and a P-type semiconductor layer, the N-type semiconductor layer, the active layer and the P-type semiconductor layer are sequentially stacked on the substrate, and a transparent conductive layer and a P-type electrode are sequentially stacked on the P-type semiconductor layer; a step part is arranged on the N-type semiconductor layer, and an N-type electrode is arranged on the step part; the light-emitting diode chip further comprises a passivation layer which covers the exposed P-type semiconductor layer, the transparent conducting layer, the P-type electrode, the step part and the N-type electrode, and open holes used for electric connection are formed in the P-type electrode and the N-type electrode. The top layer of the P-type electrode and the top layer of the N-type electrode are each provided with an adhesion layer, the adhesion layers are Ti layers, and the thickness of the adhesion layers is # imgabs0 #. By means of the light-emitting diode chip and the manufacturing method thereof, the reliability of the light-emitting diode chip can be improved.

Description

Technical Field

[0001] The invention relates to the field of semiconductor optoelectronic devices, and in particular to a light emitting diode chip and a preparation method thereof. Background Art

[0002] LED chips are widely used in lighting, indoor and outdoor display screens, backlight sources, display lamps and other fields due to their advantages of high brightness, low voltage, low energy consumption and long life. The conditions and environments faced by them are various, especially the use environment of indoor and outdoor display screens is more stringent. During the terminal application of the display screen, the chip electrodes are corroded and fall off due to environmental influences such as high temperature, water vapor and chemical corrosion, forming an open circuit phenomenon, such as Figure 1 As shown, it will also cause electrochemical migration of metal Au in the electrode, causing short circuit failure, such as Figure 2 shown. Summary of the invention

[0003] The technical problem to be solved by the present invention is to provide a light emitting diode epitaxial wafer and a preparation method thereof, which can improve the light emitting efficiency of the light emitting diode.

[0004] In order to solve the above problems, the present invention discloses a light-emitting diode chip, which includes a substrate, an N-type semiconductor layer, an active layer and a P-type semiconductor layer sequentially stacked on the substrate, a transparent conductive layer and a P-type electrode sequentially stacked on the P-type semiconductor layer; a step portion is provided on the N-type semiconductor layer, and an N-type electrode is provided on the step portion; the light-emitting diode chip also includes a passivation layer, which covers the exposed P-type semiconductor layer, the transparent conductive layer, the P-type electrode, the step portion and the N-type electrode, and an opening for electrical connection is provided above the P-type electrode and the N-type electrode;

[0005] The top layers of the P-type electrode and the N-type electrode are both provided with an adhesion layer, and the adhesion layer is a Ti layer.

[0006] As an improvement of the above technical solution, the P-type electrode includes a first contact layer, a first reflective layer, an anode protection layer, a second reflective layer and an adhesion layer stacked in sequence;

[0007] The transparent conductive layer is an ITO layer, the first contact layer is a Ni layer, and when the first contact layer is formed, the surface roughness of the transparent conductive layer is ≥1nm, and the first contact layer

[0008] The first reflective layer is an Al layer or an Ag layer, the standard electrode potential of the anode protection layer is lower than that of the second reflective layer, and the second reflective layer is a stacked structure consisting of any one of a Pt layer and an Au layer or both.

[0009] As an improvement of the above technical solution, the N-type electrode includes a second contact layer, a first reflective layer, an anode protection layer, a second reflective layer and an adhesion layer stacked in sequence;

[0010] The second contact layer is a stacked structure formed by any one of a Ti layer and a Ni layer or both;

[0011] The first reflective layer is an Al layer or an Ag layer, the standard electrode potential of the anode protection layer is lower than that of the second reflective layer, and the second reflective layer is a stacked structure consisting of any one of a Pt layer and an Au layer or both.

[0012] As an improvement of the above technical solution, the thickness of the first reflective layer is

[0013] The second reflective layer is an Au layer with a thickness of

[0014] The thickness of the adhesive layer is

[0015] As an improvement of the above technical solution, the anode protection layer includes a first sublayer and a second sublayer alternately stacked, and the number of stacking cycles is 2 to 5;

[0016] The first sublayer is one of a Ti layer, a Ni layer, and a Pt layer, and the second sublayer is one of a Ti layer, a Ni layer, and a Pt layer; the thickness of the first sublayer is The thickness of the second sublayer is

[0017] As an improvement of the above technical solution, the first sub-layer is a Ti layer, and the second sub-layer is a Ni layer.

[0018] As an improvement of the above technical solution, the thickness of the first contact layer is

[0019] As an improvement of the above technical solution, the second contact layer includes a third sublayer and a fourth sublayer alternately stacked, the stacking period number is 3 to 5, the third sublayer is a Ti layer, and the thickness is The fourth sublayer is a Ni layer, and its thickness is

[0020] Correspondingly, the present invention also discloses a method for preparing a light emitting diode chip, which is used to prepare the above-mentioned light emitting diode chip, and comprises:

[0021] providing a substrate;

[0022] An N-type semiconductor layer, an active layer and a P-type semiconductor layer are sequentially formed on a substrate;

[0023] Etching to form a step portion;

[0024] forming a transparent conductive layer on the P-type semiconductor layer;

[0025] forming a P-type electrode on the transparent conductive layer and forming an N-type electrode on the step portion;

[0026] forming a passivation layer, and forming openings for electrical connection above the P-type electrode and the N-type electrode;

[0027] The top layers of the P-type electrode and the N-type electrode are both provided with an adhesion layer, and the adhesion layer is a Ti layer.

[0028] As an improvement of the above technical solution, the P-type electrode includes a first contact layer, a first reflective layer, an anode protection layer, a second reflective layer and an adhesion layer stacked in sequence; the first contact layer is a Ni layer, and when the first contact layer is formed, the surface roughness of the ITO layer is ≥1nm, and the first contact layer

[0029] In the step of forming a transparent conductive layer on the P-type semiconductor layer, the transparent conductive layer is not annealed;

[0030] In the step of forming a P-type electrode on the transparent conductive layer and forming an N-type electrode on the step portion, after forming the first contact layer and the first reflective layer in the P-type electrode, annealing is performed, the annealing temperature is 550° C. to 620° C., and the annealing time is 5 min to 15 min.

[0031] The implementation of the present invention has the following beneficial effects:

[0032] In the light emitting diode chip of an embodiment of the present invention, an adhesive layer is provided on the top layer of the P-type electrode and the N-type electrode, and the adhesive layer is a Ti layer. Ti is easy to oxidize and can combine with the passivation layer. Moreover, since the Ti layer covers (wrapped) the entire electrode, the adhesion of the electrode to the passivation layer is greatly improved, so that the passivation layer can effectively protect the electrode, reduce the corrosion of high temperature, water vapor, and chemical media, thereby reducing the electrode from falling off, reducing the migration of active metals such as Au, and avoiding short circuit failure. BRIEF DESCRIPTION OF THE DRAWINGS

[0033] Figure 1 It is a physical picture of the electrode shedding defect in the prior art;

[0034] Figure 2 It is a physical picture of electrode metal migration in the prior art;

[0035] Figure 3is a schematic structural diagram of a light emitting diode chip in one embodiment of the present invention;

[0036] Figure 4 It is a schematic diagram of the structure of a P-type electrode in an embodiment of the present invention;

[0037] Figure 5 It is a schematic diagram of the structure of an N-type electrode in an embodiment of the present invention;

[0038] Figure 6 is a schematic structural diagram of a second contact layer in one embodiment of the present invention;

[0039] Figure 7 is a schematic structural diagram of an anode protection layer in one embodiment of the present invention;

[0040] In the figure, 1 is a substrate, 2 is an N-type semiconductor layer, 21 is a step portion, 3 is an active layer, 4 is a P-type semiconductor layer, 5 is a transparent conductive layer, 6 is a P-type electrode, 61 is a first contact layer, 62 is a first reflective layer, 63 is an anode protection layer, 64 is a second reflective layer, 65 is an adhesion layer, 7 is an N-type electrode, 71 is a second contact layer, 8 is a passivation layer, and 81 is an opening. DETAILED DESCRIPTION

[0041] In order to make the purpose, technical solutions and advantages of the present invention more clear, the present invention is described in further detail below.

[0042] In order to make the purpose, technical solutions and advantages of the present application clearer, the present application is further described in detail below in conjunction with the accompanying drawings and embodiments. Examples of the embodiments are shown in the accompanying drawings, wherein the same or similar reference numerals throughout represent the same or similar elements or elements with the same or similar functions. The embodiments described below with reference to the accompanying drawings are exemplary and are only used to explain the present application, and should not be construed as limiting the present application. In addition, it should be understood that the specific embodiments described herein are only used to explain the present application and are not intended to limit the present application.

[0043] In the description of the present application, it should be understood that the terms "length", "width", "up", "down", "left", "right", "horizontal", "top", "bottom", etc., indicating the orientation or position relationship are based on the orientation or position relationship shown in the accompanying drawings, and are only for the convenience of describing the present application and simplifying the description, rather than indicating or implying that the device or element referred to must have a specific orientation, be constructed and operated in a specific orientation, and therefore should not be understood as a limitation on the present application.

[0044] In addition, the terms "first" and "second" are used for descriptive purposes only and should not be understood as indicating or implying relative importance or implicitly indicating the number of the indicated technical features. Thus, the features defined as "first" and "second" may explicitly or implicitly include one or more of the features. In the description of this application, the meaning of "plurality" is two or more, unless otherwise clearly and specifically defined.

[0045] In the description of this application, it should be noted that, unless otherwise clearly specified and limited, the terms "installed", "connected", and "connected" should be understood in a broad sense, for example, it can be a fixed connection, a detachable connection, or an integral connection; it can be a mechanical connection, an electrical connection, or mutual communication; it can be a direct connection, or an indirect connection through an intermediate medium, it can be the internal connection of two elements or the interaction relationship between two elements. For ordinary technicians in this field, the specific meanings of the above terms in this application can be understood according to specific circumstances.

[0046] In the present application, unless otherwise clearly specified and limited, a first feature being "above" or "below" a second feature may include that the first and second features are in direct contact, or may include that the first and second features are not in direct contact but are in contact through another feature between them. Moreover, a first feature being "above", "above" and "above" a second feature includes that the first feature is directly above and obliquely above the second feature, or simply indicates that the first feature is higher in level than the second feature. A first feature being "below", "below" and "below" a second feature includes that the first feature is directly below and obliquely below the second feature, or simply indicates that the first feature is lower in level than the second feature.

[0047] The disclosure below provides many different embodiments or examples to realize the different structures of the present application. In order to simplify the disclosure of the present application, the parts and settings of specific examples are described below. Of course, they are only examples, and the purpose is not to limit the present application. In addition, the present application can repeat reference numbers and / or reference letters in different examples, and this repetition is for the purpose of simplification and clarity, and does not indicate the relationship between the various embodiments and / or settings discussed in itself. In addition, the various specific processes and examples of materials provided in the present application, but those of ordinary skill in the art can be aware of the application of other processes and / or the use scenarios of other materials.

[0048] See also Figure 3 to Figure 6, this embodiment provides a light-emitting diode chip, which includes a substrate 1, an N-type semiconductor layer 2, an active layer 3, a P-type semiconductor layer 4, a transparent conductive layer 5, an N-type electrode 7, a P-type electrode 6 and a passivation layer 8. Among them, the N-type semiconductor layer 2, the active layer 3, and the P-type semiconductor layer 4 are sequentially stacked on the substrate 1, and a step portion 21 is formed on the N-type semiconductor layer 2, and the step portion 21 exposes a portion of the N-type semiconductor layer 2, and the N-type electrode 7 is arranged on the step portion 21. The transparent conductive layer 5 is arranged on the P-type semiconductor layer 4, and the P-type electrode 6 is arranged thereon. The passivation layer 8 covers the exposed P-type semiconductor layer 4, the transparent conductive layer 5, the P-type electrode 6, the step portion 21 and the N-type electrode 7, and an opening 81 for electrical connection is arranged above the P-type electrode 6 and the N-type electrode 7.

[0049] Specifically, the P-type electrode 6 and the N-type electrode 7 are a stacked structure, and the top layer is provided with an adhesion layer 65, and the adhesion layer 65 is a Ti layer. Ti is easy to oxidize and can be combined with the passivation layer 8. Moreover, since the Ti layer covers (wrapped) the entire electrode, the adhesion of the electrode to the passivation layer 8 is greatly improved, so that the passivation layer 8 can effectively protect the electrode, reduce the corrosion of the electrode by high temperature, water vapor, and chemical media, thereby reducing the electrode from falling off, reducing the migration of active metals such as Au, avoiding short circuit failure, and greatly improving the reliability of the light-emitting diode chip.

[0050] Specifically, the substrate 1 may be a sapphire substrate, a silicon substrate or a SiC substrate, but is not limited thereto. Preferably, the substrate 1 is a sapphire substrate. The first semiconductor layer may be an N-type GaN layer, an N-type AlGaN layer, or an N-type GaAs layer, but is not limited thereto. The active layer 3 may be an InGaN-GaN type multi-quantum well layer, an InGaN-AlGaN type multi-quantum well layer, or an AlGaN-AlGaN type multi-quantum well layer, but is not limited thereto. The second semiconductor layer may be a P-type GaN layer, a P-type AlGaN layer, or a P-type GaAs layer, but is not limited thereto.

[0051] Preferably, in an embodiment of the present invention, the light emitting diode chip may further include one or more of a buffer layer, an intrinsic semiconductor layer, a stress buffer layer, an electron blocking layer, and an ohmic contact layer commonly used in the art, but is not limited thereto.

[0052] Specifically, the transparent conductive layer 5 can be an ITO layer, an IZO layer, an AZO layer, an ATO layer or an FTO layer commonly used in the art, but is not limited thereto. Preferably, in one embodiment, the transparent conductive layer 5 is an ITO layer, which has strong conductivity and can optimize current expansion, and has high light transmittance, which can improve light extraction efficiency, thereby improving the luminous efficiency of the light-emitting diode chip. Specifically, the thickness of the transparent conductive layer 5 is Preferably

[0053] Specifically, in one embodiment, except for the bottom adhesion layer 65, the P-type electrode 6 and the N-type electrode 7 may be a metal stacking structure commonly used in the art, such as a stacking structure composed of one or more of Al, Ti, Pt, Au, Ag, Cr, etc., but not limited thereto.

[0054] Specifically, the cross-section of the N-type electrode 7 and the P-type electrode 6 is a trapezoid, so that the adhesion layer 65 located on the top layer forms a wrap around the entire electrode structure, improves the adhesion with the passivation layer 8, and improves the reliability of the light-emitting diode chip, but is not limited thereto. More specifically, in one embodiment, the cross-section of the N-type electrode 7 and the P-type electrode 6 is an isosceles trapezoid, and its base angle is 40° to 60°.

[0055] Specifically, the passivation layer 8 is a SiO2 layer, an Al2O3 layer, a SiN x Preferably, in one embodiment, the passivation layer 8 is a SiO2 layer, which has a stronger adhesion to the adhesion layer 65, and can further improve the reliability of the light-emitting diode chip. Specifically, the thickness of the passivation layer 8 is Preferably

[0056] Preferably, in one embodiment of the present invention, see Figure 4 The P-type electrode 6 includes a first contact layer 61, a first reflective layer 62, an anode protection layer 63, a second reflective layer 64 and an adhesion layer 65 which are stacked in sequence.

[0057] Specifically, the first contact layer 61 is a Ni layer, which can form an ohmic contact with the transparent conductive layer 5, thereby forming an electrical connection between the electrode and the P-type semiconductor layer 4. Moreover, Ni is chemically stable, and has a higher standard electrode potential than the commonly used Cr, making it more resistant to electrochemical corrosion, greatly reducing the risk of electrode drop, and improving the reliability of the light-emitting diode chip.

[0058] Specifically, the first reflective layer 62 and the second reflective layer 64 are both metals with high reflectivity, which can reflect light directed to the electrode to prevent the light from being absorbed by the electrode, thereby improving the luminous efficiency. In addition, the second reflective layer 64 has good ductility and conductivity, and can be well coated on the entire electrode surface, forming good conditions for the subsequent adhesion layer 65 to wrap the electrode as a whole. However, since the metal used in the second reflective layer 64 usually includes Pt, Au, etc., its standard electrode potential is relatively high and chemical migration is prone to occur, an anode protection layer 63 is introduced, and a metal with a standard electrode potential lower than that of the second reflective layer 64 is used to form a good protection for the second reflective layer 64 to prevent its chemical migration. Therefore, based on the above-mentioned P-type electrode 6, not only the luminous efficiency of the light-emitting diode chip can be improved, but also the reliability can be further improved.

[0059] More preferably, in one embodiment, the transparent conductive layer 5 is an ITO layer, the first contact layer 61 is a Ni layer, and the surface roughness of the transparent conductive layer 5 is ≥1nm when the first contact layer 61 is formed. It should be noted that in conventional electrode structures, especially in the structure of the reflective electrode (generally the second layer is an Al layer), a Cr layer is generally used as the contact layer, which has good adhesion to the N-type semiconductor layer 2 / transparent conductive layer 5, but is not resistant to chemical corrosion. For this reason, in the present application, the first contact layer 61 is replaced with a Ni layer that is more resistant to chemical corrosion, but its adhesion to the transparent conductive layer 5 (ITO layer) is poor. For this reason, in the present embodiment, the surface roughness (RMS) of the transparent conductive layer 5 (ITO layer) is controlled to be ≥1nm when the first contact layer 61 is formed, thereby improving the adhesion performance of the first contact layer 61 (Ni layer) to the transparent conductive layer 5. It should be further noted that the surface roughness of the traditional ITO layer is generally large after the deposition is completed, which is above 1nm. However, the surface roughness of the ITO layer is reduced to less than 0.7 nm after annealing, which is not conducive to the formation of the Ni layer. Therefore, the surface roughness of the ITO layer is controlled to be ≥ 1 nm in this application.

[0060] Specifically, the first contact layer 61 To improve the adhesion with the transparent conductive layer 5, it is more preferably More preferably

[0061] Preferably, in one embodiment, see Figure 5 The N-type electrode 7 includes a second contact layer 71, a first reflective layer 62, an anode protection layer 63, a second reflective layer 64 and an adhesion layer 65 which are stacked in sequence.

[0062] Specifically, the second contact layer 71 is a stacked structure formed by any one of a Ti layer and a Ni layer or both; these metals can form an ohmic contact with the N-type semiconductor layer 2. Moreover, the chemical properties of Ni and Ti are relatively stable, and they have a higher standard electrode potential than the commonly used Cr, making them more resistant to electrochemical corrosion, greatly reducing the risk of electrode drop, and improving the reliability of the light-emitting diode chip.

[0063] Specifically, the first reflective layer 62 and the second reflective layer 64 are both metals with high reflectivity, which can reflect light directed to the electrode to prevent the light from being absorbed by the electrode, thereby improving the luminous efficiency. In addition, the second reflective layer 64 has good ductility and conductivity, and can be well coated on the entire electrode surface, forming good conditions for the subsequent adhesion layer 65 to wrap the electrode as a whole. However, since the metal used in the second reflective layer 64 usually includes Pt, Au, etc., its standard electrode potential is relatively high and chemical migration is prone to occur, an anode protection layer 63 is introduced, and a metal with a standard electrode potential lower than that of the second reflective layer 64 is used to form a good protection for the second reflective layer 64 to prevent its chemical migration. Therefore, based on the above-mentioned P-type electrode 6, not only the luminous efficiency of the light-emitting diode chip can be improved, but also the reliability can be further improved.

[0064] More preferably, in one embodiment, see Figure 6 The second contact layer 71 includes a third sublayer and a fourth sublayer alternately stacked, and the stacking period number is 3 to 5. The third sublayer is a Ti layer, and its thickness is The fourth sublayer is a Ni layer, and its thickness is Based on the above-mentioned second contact layer 71, it can not only form a good ohmic contact with the N-type semiconductor layer 2, but also improve the chemical corrosion resistance and reliability. It should be noted that since the N-type semiconductor layer 2 is an N-type semiconductor, a metal material with a smaller work function (such as commonly used Al, etc.) should be selected when forming an ohmic contact. Although Ni is used in this embodiment to improve corrosion resistance, its work function is as high as 4.5eV, and the ohmic contact with the N-type semiconductor layer 2 is poor. Therefore, this embodiment uses Ti with a lower work function and Ni to form the second contact layer 71 together, which optimizes the ohmic contact performance and chemical corrosion resistance.

[0065] Specifically, in some embodiments, the first reflective layer 62 is an Al layer or an Ag layer, but is not limited thereto. Preferably, the first reflective layer 62 is an Al layer. The thickness of the first reflective layer 62 is Preferably

[0066] Specifically, in some embodiments, the second reflective layer 64 is a laminated structure composed of any one of a Pt layer and an Au layer, or both, but is not limited thereto. Preferably, the second reflective layer 64 is an Au layer. The thickness of the second reflective layer 64 is Preferably

[0067] Specifically, in some embodiments, the anode protection layer 63 is a stacked structure formed by one or at least two of a Ti layer, a Ni layer, and a Pt layer, but is not limited thereto. The thickness of the anode protection layer 63 is Preferably But it is not limited to this.

[0068] Preferably, in one embodiment, see Figure 7 The anode protection layer 63 includes a first sublayer and a second sublayer alternately stacked, and the number of stacking periods is 2 to 5; the first sublayer is one of a Ti layer, a Ni layer, and a Pt layer, and the second sublayer is one of a Ti layer, a Ni layer, and a Pt layer; the thickness of the first sublayer is The thickness of the second sublayer is Further preferably, the first sublayer is a Ti layer, and the second sublayer is a Ni layer.

[0069] Accordingly, in another embodiment of the present invention, a method for preparing a light emitting diode chip is provided, which is used to prepare the above-mentioned light emitting diode chip, and comprises:

[0070] S1, providing a substrate 1;

[0071] S2, sequentially forming an N-type semiconductor layer 2, an active layer 3 and a P-type semiconductor layer 4 on a substrate 1;

[0072] Specifically, the N-type semiconductor layer 2 , the active layer 3 , and the P-type semiconductor layer 4 may be formed by MOCVD, MBE, or the like, but the present invention is not limited thereto.

[0073] S3, etching to form a step portion 21;

[0074] Specifically, the step portion 21 may be formed by photolithography and etching, and the etching process may be dry etching or wet etching, but is not limited thereto.

[0075] S4, forming a transparent conductive layer 5 on the P-type semiconductor layer 4;

[0076] Specifically, the transparent conductive layer 5 can be formed by PVD, electron beam evaporation, etc., but is not limited thereto. Preferably, in one embodiment, an ITO layer is formed by electron beam evaporation as the transparent conductive layer 5, and after evaporation contact, no annealing is performed to keep the ITO layer relatively rough, thereby optimizing adhesion with the subsequent first contact layer 61.

[0077] S5, forming a P-type electrode 6 on the transparent conductive layer 5, and forming an N-type electrode 7 on the step portion 21;

[0078] Specifically, the P-type electrode 6 and the N-type electrode 7 can be formed by PVD, electron beam evaporation or other processes, but are not limited thereto. The N-type electrode 7 can be formed first, and then the P-type electrode 6 can be formed, or the P-type electrode 6 can be formed first, and then the N-type electrode 7 can be formed.

[0079] Preferably, in one embodiment, when forming the P-type electrode 6, after evaporating the first contact layer 61 and the first reflective layer 62, annealing is performed, and the annealing temperature is 550°C to 620°C, and the annealing time is 5min to 15min. Through annealing, firstly, the crystal defects of the transparent conductive layer 5 (ITO layer) can be reduced, and its ohmic contact with the P-type semiconductor layer 4 can be improved, thereby improving the light transmittance; secondly, annealing makes the adhesion between the ITO layer and the Ni layer stronger. Thirdly, the Ni layer can be clustered, and then part of the Al can be directly in contact with the ITO layer, reducing the absorption of light by the Ni layer and improving the light extraction efficiency. Fourthly, since the annealed Al still contacts the ITO layer in clusters, the P-type electrode 6 still ensures good ohmic contact with the ITO layer.

[0080] Based on the structure of the LED chip and the traditional electrode structure (Cr+Al+Au) in this embodiment, a salt spray test was performed to verify the results, and the results are as follows:

[0081]

[0082]

[0083] It can be seen from the table that the electrode structure of the present invention can significantly reduce the number of electrode drops and metal migration, thereby effectively improving the reliability of the light emitting diode chip.

[0084] In the description of this specification, the description with reference to the terms "one embodiment", "some embodiments", "example", "specific example", or "some examples" means that the specific features, structures, materials or characteristics described in conjunction with the embodiment or example are included in at least one embodiment or example of the present application. In this specification, the schematic representation of the above terms does not necessarily refer to the same embodiment or example. Moreover, the specific features, structures, materials or characteristics described may be combined in any one or more embodiments or examples in a suitable manner.

[0085] Although the embodiments of the present application have been shown and described, those skilled in the art will appreciate that various changes, modifications, substitutions and variations may be made to the embodiments without departing from the principles and spirit of the present application, and that the scope of the present application is defined by the claims and their equivalents.

Claims

1. A light emitting diode chip, characterized in that: The light emitting diode chip comprises a substrate, an N-type semiconductor layer, an active layer and a P-type semiconductor layer sequentially stacked on the substrate, a transparent conductive layer and a P-type electrode sequentially stacked on the P-type semiconductor layer; a step portion is provided on the N-type semiconductor layer, and an N-type electrode is provided on the step portion; the light emitting diode chip further comprises a passivation layer, which covers the exposed P-type semiconductor layer, the transparent conductive layer, the P-type electrode, the step portion and the N-type electrode, and an opening for electrical connection is provided above the P-type electrode and the N-type electrode; The top layers of the P-type electrode and the N-type electrode are both provided with an adhesion layer, and the adhesion layer is a Ti layer with a thickness of 2. The light emitting diode chip according to claim 1, characterized in that: The P-type electrode comprises a first contact layer, a first reflective layer, an anode protection layer, a second reflective layer and an adhesion layer stacked in sequence; The transparent conductive layer is an ITO layer, the first contact layer is a Ni layer, and when the first contact layer is formed, the surface roughness of the transparent conductive layer is ≥1nm, and the thickness of the first contact layer is The first reflective layer is an Al layer or an Ag layer, the standard electrode potential of the anode protection layer is lower than that of the second reflective layer, and the second reflective layer is a stacked structure consisting of any one of a Pt layer and an Au layer or both.

3. The light emitting diode chip according to claim 1, characterized in that: The N-type electrode comprises a second contact layer, a first reflective layer, an anode protection layer, a second reflective layer and an adhesion layer stacked in sequence; The second contact layer is a stacked structure formed by any one of a Ti layer and a Ni layer or both; The first reflective layer is an Al layer or an Ag layer, the standard electrode potential of the anode protection layer is lower than that of the second reflective layer, and the second reflective layer is a stacked structure consisting of any one of a Pt layer and an Au layer or both.

4. The light emitting diode chip according to claim 2 or 3, characterized in that: The thickness of the first reflective layer is The second reflective layer is an Au layer with a thickness of The thickness of the adhesive layer is 5. The light emitting diode chip according to claim 2 or 3, characterized in that: The anode protection layer comprises a first sublayer and a second sublayer alternately stacked, and the number of stacking cycles is 2 to 5; The first sublayer is one of a Ti layer, a Ni layer, and a Pt layer, and the second sublayer is one of a Ti layer, a Ni layer, and a Pt layer; the thickness of the first sublayer is The thickness of the second sublayer is 6. The light emitting diode chip according to claim 5, characterized in that: The first sub-layer is a Ti layer, and the second sub-layer is a Ni layer.

7. The light emitting diode chip according to claim 2, characterized in that: The thickness of the first contact layer is 8. The light emitting diode chip according to claim 3, characterized in that: The second contact layer includes a third sublayer and a fourth sublayer alternately stacked, and the stacking period number is 3 to 5. The third sublayer is a Ti layer, and the thickness is The fourth sublayer is a Ni layer, and its thickness is 9. A method for preparing a light emitting diode chip, for preparing the light emitting diode chip according to any one of claims 1 to 8, characterized in that: include: providing a substrate; An N-type semiconductor layer, an active layer and a P-type semiconductor layer are sequentially formed on a substrate; Etching to form a step portion; forming a transparent conductive layer on the P-type semiconductor layer; forming a P-type electrode on the transparent conductive layer and forming an N-type electrode on the step portion; forming a passivation layer, and forming openings for electrical connection above the P-type electrode and the N-type electrode; The top layers of the P-type electrode and the N-type electrode are both provided with an adhesion layer, and the adhesion layer is a Ti layer with a thickness of 10. The method for preparing a light emitting diode chip according to claim 9, characterized in that: The P-type electrode comprises a first contact layer, a first reflective layer, an anode protection layer, a second reflective layer and an adhesion layer stacked in sequence; the first contact layer is a Ni layer, and when the first contact layer is formed, the surface roughness of the ITO layer is ≥1nm, and the thickness of the first contact layer is In the step of forming a transparent conductive layer on the P-type semiconductor layer, the transparent conductive layer is not annealed; In the step of forming a P-type electrode on the transparent conductive layer and forming an N-type electrode on the step portion, after forming the first contact layer and the first reflective layer in the P-type electrode, annealing is performed, the annealing temperature is 550° C. to 620° C., and the annealing time is 5 min to 15 min.

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