Display device

Abstract

A display device is disclosed. The display device may include: a substrate including a plurality of sub-pixels; a driving transistor in each of the plurality of sub-pixels; a passivation layer on the driving transistor; a planarization layer on the passivation layer; a contact hole formed in the passivation layer and the planarization layer to expose a source electrode of the driving transistor; a first anode on the top surface of the planarization layer and the contact hole; a first bank configured to cover an edge of the first anode; and a second bank disposed on the first anode in the contact hole, in which a height of the second bank is equal to or less than a height of the planarization layer. Therefore, the design freedom degree and the aperture opening ratio can be improved.

Description

[0001] CROSS-REFERENCE TO RELATED APPLICATIONS

[0002] This application claims the priority of Korean Patent Application No. 10-2023-0128871 filed in the Korean Intellectual Property Office on September 26, 2023, the disclosure of which is incorporated herein by reference. Technical Field

[0003] The present disclosure relates to a display device, and more particularly to a display device having an improved aperture ratio and improved design freedom. Background Art

[0004] The application range of liquid crystal display (LCD) devices and organic light emitting display (OLED) devices, which have been widely used so far, is gradually expanding.

[0005] Unlike a liquid crystal display (LCD) device having a backlight, an organic light emitting display (OLED) device does not require a separate light source. The advantages of an organic light emitting display device are that the organic light emitting display device can be made light and thin, the process can be simplified, and since the organic light emitting display device can be operated by a low voltage, the power consumption is low. Among them, the organic light emitting display device can have an autonomous light emitting element, and the layer of the organic light emitting display device can be composed of a thin organic film. The advantage of an organic light emitting display device is that the organic light emitting display device can have excellent flexibility and elasticity compared to other display devices. Summary of the invention

[0006] An object to be achieved by the present disclosure is to provide a high-resolution display device.

[0007] Another object to be achieved by the present disclosure is to provide a display device with improved design freedom.

[0008] Still another object to be achieved by the present disclosure is to provide a display device having an improved aperture ratio.

[0009] The objects of the present disclosure are not limited to the above-mentioned objects, and other objects not mentioned above can be clearly understood by those skilled in the art from the following description.

[0010] A display device according to an embodiment of the present disclosure may include: a substrate including a plurality of sub-pixels; a driving transistor in each of the plurality of sub-pixels; a passivation layer on the driving transistor; a planarization layer on the passivation layer; a contact hole formed in the passivation layer and the planarization layer to expose a source electrode of the driving transistor; a first anode on a top surface of the planarization layer and the contact hole; a first bank configured to cover an edge of the first anode; and a second bank disposed on the first anode in the contact hole, wherein a height of the second bank is equal to or less than a height of the planarization layer. Therefore, the degree of freedom of design and the aperture ratio can be improved.

[0011] Additional details of exemplary embodiments are included in the detailed description and the accompanying drawings.

[0012] According to an embodiment of the present disclosure, the second bank is disposed in the contact hole so that an abnormal light emitting region caused by a step difference of the planarization layer is not visually recognized, which can improve display quality.

[0013] According to an embodiment of the present disclosure, by providing the second bank in the contact hole using a residue, it is not necessary to ensure a process margin between the planarization layer and the second bank, which can improve the degree of freedom in design.

[0014] According to an embodiment of the present disclosure, the second bank is provided only in the contact hole, so that the non-light emitting area of ​​the contact area can be minimized and the aperture ratio can be improved.

[0015] According to an embodiment of the present disclosure, a second anode having a flat surface may be further disposed on the second bank in the contact region, so that light may be emitted even in the contact region, which may improve an aperture ratio.

[0016] The effects according to the present disclosure are not limited to those exemplified above, and more various effects are included in the present disclosure.

[0017] According to an embodiment of the present disclosure, a method for manufacturing a display device may include: etching a portion of a passivation layer and a portion of a planarization layer to form a contact hole; depositing a first anode on the planarization layer and the contact hole; coating the planarization layer and the contact hole to form a dam coating layer, wherein a height of the dam coating layer in the contact hole is greater than a height of the dam coating layer on the planarization layer; etching the dam coating layer to form a first dam and a second dam. BRIEF DESCRIPTION OF THE DRAWINGS

[0018] The above and other aspects, features and other advantages of the present disclosure will be more clearly understood from the following detailed description taken in conjunction with the accompanying drawings, in which:

[0019] Figure 1 is a schematic configuration diagram of a display device according to an embodiment of the present disclosure;

[0020] Figure 2 is along Figure 1 A cross-sectional view taken along line II-II';

[0021] Figure 3 is a cross-sectional view of a display device according to another embodiment of the present disclosure;

[0022] Figure 4 is a cross-sectional view of a display device according to yet another embodiment of the present disclosure;

[0023] Figure 5 is a cross-sectional view of a display device according to yet another embodiment of the present disclosure;

[0024] Figure 6 is a cross-sectional view of a display device according to a comparative example; and

[0025] 7A to 7E is a process diagram for explaining a method of manufacturing a display device according to an embodiment of the present disclosure. DETAILED DESCRIPTION

[0026] By referring to the exemplary embodiments described in detail below in conjunction with the accompanying drawings, the advantages and features of the present disclosure and the methods for achieving these advantages and features will be clear. However, the present disclosure is not limited to the exemplary embodiments disclosed herein, but will be implemented in various forms. The exemplary embodiments are provided only by way of example so that those skilled in the art can fully understand the disclosure of the present disclosure and the scope of the present disclosure.

[0027] The shapes, sizes, ratios, angles, numbers, etc. shown in the accompanying drawings for describing the exemplary embodiments of the present disclosure are merely examples, and the present disclosure is not limited thereto. Throughout the disclosure, similar reference numerals generally represent similar elements. In addition, in the following description of the present disclosure, the detailed description of known related technologies may be omitted to avoid unnecessarily obscuring the subject matter of the present disclosure. Terms such as "including", "having" and "consisting of..." used herein are generally intended to allow the addition of other components, unless these terms are used together with the term "only". Unless otherwise expressly stated, any reference to the singular may include the plural.

[0028] Even if not explicitly stated, the components are interpreted as including the ordinary error range.

[0029] When terms such as "on", "over", "below" and "beside" are used to describe the positional relationship between two parts, one or more parts may be located between the two parts unless these terms are used together with the terms "immediately" or "directly".

[0030] When an element or a layer is disposed “on” another element or layer, the other layer or element may be directly on the other element or interposed therebetween.

[0031] Although the terms "first", "second", etc. are used to describe various components, these components are not limited by these terms. These terms are only used to distinguish one component from other components. Therefore, the first component to be mentioned below can be the second component in the technical concept of the present disclosure.

[0032] Like reference numbers generally refer to like elements throughout the disclosure.

[0033] The size and thickness of each component shown in the drawings are illustrated for convenience of description, and the present disclosure is not limited to the size and thickness of the components shown.

[0034] The features of the various embodiments of the present disclosure may be partially or completely adhered to or combined with each other and may interlock and operate in technically different ways, and the embodiments may be performed independently of each other or in association with each other.

[0035] Hereinafter, a display device according to an exemplary embodiment of the present disclosure will be described in detail with reference to the accompanying drawings.

[0036] Figure 1 is a schematic configuration diagram of a display device according to an embodiment of the present disclosure. Figure 2 is along Figure 1 For ease of description, Figure 1 Only the display panel PN among various constituent elements of the display device 100 is shown.

[0037] Reference Figure 1 , the display device 100 may include a display panel PN, and the display panel PN includes a plurality of sub-pixels SP.

[0038] The display panel PN is configured to display an image to a user, and includes a plurality of sub-pixels SP. In the display panel PN, a plurality of scan lines and a plurality of data lines may intersect with each other, and each of the plurality of sub-pixels may be connected to the scan line and the data line. In addition, although not shown in the drawings, the plurality of sub-pixels SP may be respectively connected to a high potential power line, a low potential power line, a reference line, etc.

[0039] The display panel PN may have a display area AA and a non-display area NA configured to surround the display area AA.

[0040] The display panel PN refers to an organic display panel using an organic light emitting element, which injects electrons and holes from a cathode for injecting electrons and an anode for injecting holes into a light emitting layer, and emits light when excitons formed by coupling the injected electrons and holes drop from an excited state to a ground state.

[0041] The display area AA is an area of ​​the display device 100 that displays an image. The display area AA may include a plurality of sub-pixels SP constituting a plurality of pixels and a circuit configured to operate the plurality of sub-pixels SP. The plurality of sub-pixels SP are the smallest units constituting the display area AA. n sub-pixels SP may constitute a single pixel. Specifically, each of the sub-pixels SP is an element for displaying one color. The sub-pixel SP may be defined as an area where a plurality of scan lines arranged along a first direction and a plurality of data lines arranged along a second direction different from the first direction intersect with each other. In this case, the first direction may be Figure 1 The horizontal direction (X-axis direction) in the embodiment, and the second direction can be Figure 1 The vertical direction (Y-axis direction) in FIG. 2 is a vertical direction (Y-axis direction). However, the present disclosure is not limited thereto. The sub-pixels SP may each include a light emitting area EA from which light is emitted and a non-light emitting area NEA from which no light is emitted.

[0042] A light emitting element, a thin film transistor for operating the light emitting element, etc. may be provided in each of the plurality of sub-pixels SP. The light emitting element may be defined differently depending on the type of the display panel. For example, in the case where the display panel is an organic light emitting display panel, the light emitting element may be an organic light emitting element (OLED).

[0043] A plurality of lines for transmitting various types of signals to a plurality of sub-pixels SP may be provided in the display area AA. Although not shown in the drawings, for example, the plurality of lines may include a plurality of data lines for supplying data voltages to the plurality of sub-pixels SP and a plurality of scan lines for supplying scan signals to the plurality of sub-pixels SP. The plurality of scan lines may extend in one direction in the display area AA and may be connected to the plurality of sub-pixels SP. The plurality of data lines may extend in a direction different from one direction in the display area AA and may be connected to the plurality of sub-pixels SP. In addition, a low potential power line, a high potential power line, etc. may also be provided in the display area AA. However, the present disclosure is not limited thereto.

[0044] The non-display area NA may be defined as an area where an image is not displayed, that is, an area extending from the display area AA. The non-display area NA may include link lines and pad electrodes for transmitting signals to the sub-pixels SP in the display area AA. Alternatively, the non-display area NA may include driver ICs such as a gate driver IC and a data driver IC.

[0045] However, the non-display area NA may be located on the rear surface of the display panel PN (ie, a surface on which the sub-pixels SP do not exist). Alternatively, the non-display area NA may not be included. However, the present disclosure is not limited to the configuration shown in the drawings.

[0046] Reference Figure 1 and Figure 2 The display panel PN may include a substrate 110, a buffer layer 111, a gate insulating layer 112, an interlayer insulating layer 113, a passivation layer 114, a planarization layer 115, a first bank 116a, a second bank 116b, a light emitting element 120, and a contact hole CH.

[0047] The substrate 110 is a supporting member for supporting other components of the display device 100 and may be made of an insulating material. For example, the substrate 110 may be made of glass, resin, etc. In addition, the substrate 110 may include plastic such as a polymer or polyimide (PI) and may be made of a material having flexibility.

[0048] A buffer layer 111 may be provided on the substrate 110. The buffer layer 111 may reduce the penetration of moisture or impurities through the substrate 110. For example, the buffer layer 111 may be configured as a single layer or a multilayer made of silicon oxide (SiOx) or silicon nitride (SiNx). However, the present disclosure is not limited thereto. However, depending on the type of the substrate 110 or the type of the driving transistor, the buffer layer 111 may not be included. However, the present disclosure is not limited thereto.

[0049] A driving transistor DT including an active layer ACT, a gate electrode GE, a source electrode SE, and a drain electrode DE may be disposed on the buffer layer 111 .

[0050] First, the active layer ACT of the driving transistor DT can be arranged on the buffer layer 111. The active layer ACT can be made of a semiconductor material such as an oxide semiconductor, amorphous silicon or polycrystalline silicon. However, the present disclosure is not limited to this. In addition, although not shown in the drawings, in addition to the driving transistor DT, other transistors such as a switching transistor, a sensing transistor and a light-emitting control transistor can be additionally provided. The active layers of these transistors can be made of a semiconductor material such as an oxide semiconductor, amorphous silicon or polycrystalline silicon. However, the present disclosure is not limited to this. In addition, the active layers of transistors such as the driving transistor DT, the switching transistor, the sensing transistor and the light-emitting control transistor included in the pixel circuit can be made of the same material or different materials.

[0051] A gate insulating layer 112 may be disposed on the active layer ACT. The gate insulating layer 112 may be an insulating layer for electrically insulating the active layer ACT and the gate electrode GE. The gate insulating layer 112 may be configured as a single layer or multiple layers made of silicon oxide (SiOx) or silicon nitride (SiNx). However, the present disclosure is not limited thereto.

[0052] A gate electrode GE may be disposed on the gate insulating layer 112. The gate electrode GE may be made of a conductive material such as copper (Cu), aluminum (Al), molybdenum (Mo), nickel (Ni), titanium (Ti), chromium (Cr), or an alloy thereof. However, the present disclosure is not limited thereto.

[0053] An interlayer insulating layer 113 may be disposed on the gate electrode GE. A contact hole CH may be formed in the interlayer insulating layer 113, and the source electrode SE and the drain electrode DE are connected to the active layer ACT through the contact hole CH. The interlayer insulating layer 113 may be an insulating layer for protecting components disposed under the interlayer insulating layer 113. The interlayer insulating layer 113 may be configured as a single layer or a multilayer made of silicon oxide (SiOx) or silicon nitride (SiNx). However, the present disclosure is not limited thereto.

[0054] A source electrode SE and a drain electrode DE electrically connected to the active layer ACT may be disposed on the interlayer insulating layer 113. The source electrode SE and the drain electrode DE may each be made of a conductive material such as copper (Cu), aluminum (Al), molybdenum (Mo), nickel (Ni), titanium (Ti), chromium (Cr), or an alloy thereof. However, the present disclosure is not limited thereto.

[0055] A passivation layer 114 may be disposed on the source electrode SE and the drain electrode DE. The passivation layer 114 is an insulating layer for protecting components disposed below the passivation layer 114. For example, the passivation layer 114 may be made of an insulating inorganic material such as silicon oxide (SiOx) and silicon nitride (SiNx). In addition, the passivation layer 114 may be made of an insulating organic material, etc. However, the present disclosure is not limited thereto.

[0056] A planarization layer 115 may be disposed on the passivation layer 114. The planarization layer 115 may planarize the upper portion of the pixel circuit including the driving transistor DT. The planarization layer 115 may be configured as a single layer or multiple layers and may be made of, for example, benzocyclobutene or an acrylic-based organic material. However, the present disclosure is not limited thereto.

[0057] A plurality of light emitting elements 120 are disposed on the planarization layer 115 and are respectively disposed in a plurality of sub-pixels SP. The light emitting element 120 may be an element configured to emit light by current, and include a red light emitting element configured to emit red light, a green light emitting element configured to emit green light, and a blue light emitting element configured to emit blue light. The combination of the light emitting elements 120 may realize various colors including white. For example, the light emitting element 120 may be an organic light emitting diode. However, the present disclosure is not limited thereto.

[0058] A contact hole CH having an inverted tapered shape is formed in the passivation layer 114 and the planarization layer 115. For example, the contact hole CH may be disposed in the light emitting area EA. However, the present disclosure is not limited thereto. The source electrode SE of the driving transistor DT and the first anode 121a may be electrically connected through the contact hole CH. That is, the contact hole CH may be disposed so that the source electrode SE is exposed. In this case, the contact hole CH may be disposed so that a portion of the top surface of the passivation layer 114 is exposed. Therefore, a step difference may be formed between the passivation layer 114 and the planarization layer 115.

[0059] The first anode 121a may be disposed on the planarization layer 115 and the contact hole CH. The first anode 121a may be a layer for supplying positive holes to the light emitting layer 122. In the case where the display device 100 is a top emission type display device, the first anode 121a may include a reflective layer made of an opaque conductive material having a high reflectivity, such as silver (Ag), aluminum (Al), gold (Au), molybdenum (Mo), tungsten (W), chromium (Cr) or an alloy thereof, so that the light emitted from the light emitting layer 122 is reflected by the first anode 121a and propagates in an upward direction, that is, propagates in a direction toward the cathode 123 on the upper side. In addition, the first anode 121a may also include a transparent conductive layer disposed on the reflective layer and configured to supply positive holes to the light emitting layer 122. Therefore, for example, the first anode 121a may have a structure in which a layer made of indium tin oxide (ITO), a layer made of molybdenum titanium (MoTi) and a layer made of indium tin oxide (ITO) are stacked. However, the present disclosure is not limited thereto.

[0060] A first bank 116a may be provided on the planarization layer 115 and the first anode 121a. The first bank 116a may define the light emitting area EA of each of the sub-pixels SP by covering the edge of the first anode 121a of the light emitting element 120. The first bank 116a may be made of an insulating material for insulating the first anode 121a of adjacent sub-pixels SP. In addition, the first bank 116a may be configured as a black bank with a high light absorption rate for suppressing color mixing between adjacent sub-pixels SP. For example, the first bank 116a may be made of a polyimide resin, an acrylic resin, or a benzocyclobutene (BCB) resin. However, the present disclosure is not limited thereto.

[0061] At the same time, a second bank 116b is provided on the first anode 121a in the contact hole CH. In the contact area CA, since the contact hole CH is formed, a step difference may be formed by the height h2 of the planarization layer. In this case, since the light-emitting layer 122 is unevenly deposited due to the step difference, an abnormal light-emitting region may appear. Therefore, the second bank 116b may cover the step difference so that the abnormal light-emitting region is not visually recognized. In this case, since the contact hole CH exposes a portion of the top surface of the passivation layer 114, the second bank 116b may be provided to cover the step difference between the passivation layer 114 and the planarization layer 115. Therefore, the height h1 of the second bank may be greater than the height of the passivation layer 114. In addition, the second bank 116b may have a shape with a step difference. Specifically, the width W2 of the portion of the second bank 116b adjacent to the planarization layer 115 may be greater than the width W1 of the portion adjacent to the passivation layer 114. Meanwhile, since the contact hole CH exposes the side surface SS of the planarization layer 115 , the second bank 116 b in the contact hole CH may be disposed adjacent to the first anode 121 a disposed on the side surface SS of the planarization layer 115 .

[0062] The second bank 116b may be formed as a residue remaining after etching during an open mask process or a half-tone mask process for forming the first bank 116a. Therefore, the height h1 of the second bank 116b may be equal to or less than the height h2 of the planarization layer. For example, when the height h2 of the planarization layer 115 is about 2 μm and the size of the contact hole CH is 10×12 μm, the height h1 of the second bank may be about 0.2 μm. When the size of the contact hole CH is 5×7 μm, the height h1 of the second bank may be about 0.8 μm. However, the present disclosure is not limited thereto. That is, the second bank 116b may be disposed only in the contact hole CH, and not disposed beyond the planarization layer 115 in the contact area CA, which may minimize the increase in the non-light emitting area NEA. At the same time, the second bank 116b may be formed by the same process as the first bank 116a and made of the same material as the first bank 116a.

[0063] A light emitting layer 122 may be disposed on the first anode 121a, the first bank 116a, and the second bank 116b. The light emitting layer 122 is a layer that emits light by combining electrons and positive holes. In the case where the display device 100 according to an embodiment of the present disclosure is an organic light emitting display device, the light emitting layer 122 may be an organic light emitting layer including an organic material that spontaneously emits light. However, the present disclosure is not limited thereto.

[0064] A cathode 123 may be disposed on the light emitting layer 122. The cathode 123 is a layer for supplying electrons to the light emitting layer 122. For example, the cathode 123 may be made of a permeable or semi-permeable conductive material. For example, the cathode 123 may be made of a transparent conductive material such as indium tin oxide (ITO) or indium zinc oxide (IZO). However, the present disclosure is not limited thereto.

[0065] In the display device, the contact hole is formed to electrically connect the electrode disposed on the planarization layer and the pixel circuit disposed below the planarization layer. In this case, in the case where the display device is an organic light-emitting display device, due to the step difference between the contact hole and the planarization layer, the light-emitting layer may not be uniformly deposited near the contact hole. That is, due to the thickness deviation of the light-emitting layer, an area with uneven brightness may be formed. A levee may be provided on the contact hole to suppress the visual recognition of the area with uneven brightness. In this case, since the levee is deposited by using a separate mask, it is necessary to consider the process margin between the planarization layer and the levee to maintain the minimum spacing distance. Therefore, it is necessary to ensure sufficient space for the process margin, and the space corresponds to the non-light-emitting area. Therefore, the space used for the process margin may reduce the aperture ratio.

[0066] In particular, this may be particularly problematic for high PPI (pixel per inch) display devices for achieving high resolution. That is, since the size of one pixel of a high resolution display device with high PPI is small, the increase in the area occupied by the bank near the contact hole may greatly affect the aperture ratio.

[0067] Therefore, in the display device 100 according to the embodiment of the present disclosure, the second bank 116 b is disposed in the contact hole CH in the contact area CA so that an abnormal light emitting area caused by a step difference of the planarization layer 115 is not visually recognized, which can improve display quality.

[0068] Furthermore, in the display device 100 according to the embodiment of the present disclosure, by providing the second bank 116 b in the contact hole CH using a residue, it is not necessary to ensure a process margin between the planarization layer 115 and the second bank 116 b , which can improve the degree of freedom in design.

[0069] Furthermore, in the display device 100 according to the embodiment of the present disclosure, the second bank 116 b is provided only in the contact hole CH, so that the non-light emitting area of ​​the contact area CA can be minimized and the aperture ratio can be improved.

[0070] Figure 3 is a cross-sectional view of a display device according to another embodiment of the present disclosure. In addition to the shape of the contact hole CH, the height h1 of the second bank 116b, and whether there is a second anode 221b of the light emitting element 220, Figure 3 The display device 200 in the embodiment is configured similarly to Figure 1 and Figure 2 Therefore, repeated description of the same components will be omitted.

[0071] Reference Figure 3 , in the contact area CA, the contact hole CH may be formed in the passivation layer 114 and the planarization layer 115. In this case, referring to the area A, one end of the passivation layer 114 and one end of the planarization layer 115 may overlap in the contact hole CH. That is, unlike the display device 100 according to the embodiment of the present disclosure, in the display device 200 according to another embodiment of the present disclosure, a portion of the passivation layer 114 exposed by the contact hole CH may be removed by dry etching. That is, in the contact hole CH, the step difference between the passivation layer 114 and the planarization layer 115 may be reduced.

[0072] Therefore, the thickness of the residue of the second bank 116b required to mitigate the step difference between the passivation layer 114 and the planarization layer 115 can be reduced. That is, in the display device 200 according to another embodiment of the present disclosure, the height h1 of the second bank 116b can be smaller than that of the display device 100 according to the embodiment of the present disclosure. However, the present disclosure is not limited thereto.

[0073] In addition, since the second bank 116b is disposed in the contact hole CH formed in the passivation layer 114 and the planarization layer 115, the step difference between the passivation layer 114 and the planarization layer 115 can be reduced, so that the second bank 116b can also be disposed more gently. Therefore, other constituent elements disposed on the second bank 116b can be uniformly disposed.

[0074] For example, the second anode 221b may be additionally disposed on the gently disposed second bank 116b to use the contact area CA as a light emitting area. The details will be further described below.

[0075] Therefore, the height h1 of the second bank may be equal to or less than the height of the planarization layer 115. That is, the top surface TS1 of the second bank 116b may be located on the same plane as the top surface of the planarization layer 115 or disposed slightly below the top surface TS2 of the planarization layer 115.

[0076] Meanwhile, the second anode 221b may be disposed on the first anode 221a. Like the first anode 221a, the second anode 221b is a layer for supplying positive holes to the light emitting layer 222. In this case, the second anode 221b is disposed on the second bank 116b in the contact hole CH. Figure 2Compared with the display device 100 shown in FIG. 1 , the second anode 221 b is disposed on the second bank 116 b in the contact hole CH, and the light emitting layer 222 and the cathode 223 are sequentially disposed on the second bank 116 b, so that the light emitting layer 222 can emit light even in the contact hole CH. That is, the area of ​​the portion having a flat surface of the light emitting element 220 can be increased by using the second bank 116 b filling the contact hole CH. Therefore, the contact area CA can be used as a light emitting area, and the problem of a reduction in the light emitting area caused by the contact area CA can be solved.

[0077] That is, in the display device 200 according to another embodiment of the present disclosure, the second embankment 116b is set only in the contact hole CH by using residues, so that there is no need to ensure a process margin between the planarization layer 115 and the second embankment 116b, which can improve the design freedom, minimize the non-luminous area, and improve the aperture ratio.

[0078] In particular, in the display device 200 according to another embodiment of the present disclosure, the passivation layer 114 exposed by the contact hole CH in the contact area CA is dry-etched, so that the step difference between the passivation layer 114 and the planarization layer 115 can be reduced. Therefore, the step difference between the passivation layer 114 and the planarization layer 115 can be reduced by providing the second bank 116a with a small amount of residue, so that the degree of freedom in design can be improved.

[0079] In particular, in the display device 200 according to another embodiment of the present disclosure, the second anode 221b is additionally provided on the second bank 116b in the contact hole CH, so that the portion having a flat surface of the light emitting element 220 can be increased. That is, since light can be emitted even in the contact area CA, the light emitting area can be increased, and the aperture ratio can be improved.

[0080] Figure 4 is a cross-sectional view of a display device according to another embodiment of the present disclosure. In addition to the configuration of the planarization layer 315, the height h2 of the planarization layer, and the height h1 of the second bank, Figure 4 The display device 300 in the embodiment is configured similar to Figure 3 The display device 200 in FIG. 1 is substantially the same as that in FIG. 1 . Therefore, repeated description of the same components will be omitted.

[0081] Reference Figure 4 , the planarization layer 315 may include a first planarization layer 315 a and a second planarization layer 315 b .

[0082] Specifically, the first planarization layer 315a may be disposed on the passivation layer 114. The first planarization layer 315a may planarize the upper portion of the pixel circuit including the driving transistor DT. The first planarization layer 315a may be configured as a single layer or multiple layers and may be made of, for example, a benzocyclobutene or acrylic-based organic material. However, the present disclosure is not limited thereto.

[0083] The second planarization layer 315b may be disposed on the first planarization layer 315a. Referring to region A, the second planarization layer 315b may be disposed to cover the side surface of the first planarization layer 315a in the contact hole CH to suppress the situation where the light emitting layer 122 is unevenly deposited and the light emitting efficiency is deteriorated due to the step difference of the first planarization layer 315a. In this case, in the contact hole CH, one end of the second planarization layer 315b may overlap with one end of the passivation layer 114. At the same time, the second planarization layer 315b may be made of the same material as the first planarization layer 315a. However, the present disclosure is not limited thereto.

[0084] In this case, since the height of the planarization layer 315 increases with the provision of the second planarization layer 315b, the amount of the bank residue in the contact hole CH may increase. Therefore, a wide range of the height h1 of the second bank can be selected by adjusting the exposure dose. For example, the height h1 of the second bank can be equal to or less than the height h2 of the planarization layer, and equal to or less than the height h3 of the first planarization layer.

[0085] In the display device 300 according to another embodiment of the present disclosure, the second embankment 116b is set only in the contact hole CH by using a residue, so that there is no need to ensure a process margin between the planarization layer 315 and the second embankment 116b, which can improve the design freedom, minimize the non-luminous area, and improve the aperture ratio.

[0086] In particular, in a display device 300 according to another embodiment of the present disclosure, the second planarization layer 315b can be configured to cover the side surface of the first planarization layer 315a, so that the planarization layer 315 can be gently inclined and the light emitting layer 122 can be uniformly deposited, which can improve display quality.

[0087] Figure 5 4 is a cross-sectional view of a display device according to another embodiment of the present disclosure. In addition to the positions of the contact hole CH, the first bank 416a and the second bank 416b, Figure 5 The display device 400 in the embodiment is configured similar to Figure 3 The display device 200 in FIG. 1 is substantially the same as that in FIG. 1 . Therefore, repeated description of the same components will be omitted.

[0088] Reference Figure 5, the contact hole CH may be disposed adjacent to the non-emission area NEA to minimize the non-emission area. That is, the contact hole CH may be disposed adjacent to the first bank 416a. Therefore, one end of the first bank 416a and one end of the second bank 416b may be connected in the contact hole CH. That is, the first bank 416a and the second bank 416b may partially overlap each other, so that the non-emission area can be minimized.

[0089] In the display device 400 according to still another embodiment of the present disclosure, the second bank 416 b is provided only in the contact hole CH by using a residue, so that there is no need to ensure a process margin between the planarization layer 115 and the second bank 416 b , which can improve the degree of freedom in design.

[0090] In particular, in the display device 400 according to still another embodiment of the present disclosure, the first bank 416 a and the second bank 416 b are disposed to overlap each other in the contact hole CH, so that the non-light emitting area can be minimized and the aperture ratio can be improved.

[0091] Figure 6 is a cross-sectional view of a display device according to a comparative example. Unlike the display device according to the embodiment of the present disclosure, Figure 6 The display device 500 in FIG. 1 is a display device in which the bank 516 disposed in the contact area CA is not exposed by the open mask process or the half-tone mask process.

[0092] Reference Figure 6 In the contact area CA, the bank 516 may be provided not only in the contact hole CH but also to extend beyond the contact hole CH to the top surface of the planarization layer 115. Therefore, since light cannot be emitted in the contact area CA, a non-light emitting area may increase and an aperture ratio may be deteriorated.

[0093] 7A to 7E is a process diagram for explaining a method of manufacturing a display device according to an embodiment of the present disclosure.

[0094] First, refer to Fig. 7A , a process of etching a portion of the passivation layer 114 and a portion of the planarization layer 115 may be performed to form the contact hole CH. Specifically, the process of forming the contact hole CH may be performed by sequentially performing a process of applying a photoresist onto the passivation layer 114, a process of selectively exposing the photoresist, a process of coating the passivation layer 114 with the planarization layer 115, a process of applying a photoresist onto the planarization layer 115, and a process of selectively exposing the photoresist.

[0095] Next, refer to Figure 7B , a first anode 121 a may be deposited on the planarization layer 115 and the contact hole CH.

[0096] Next, a bank patterning process may be performed. Figure 7C , a bank coating layer 116' is formed by coating the planarization layer 115 and the contact hole CH with a bank forming composition. The bank forming composition may be a material for forming the first bank 116a and the second bank 116b, and includes a polyimide resin, an acrylic resin, or a benzocyclobutene (BCB) resin and a curing composition. After coating, the bank forming composition may flow into the contact hole CH due to the height difference between the contact hole CH and the top surface of the planarization layer 115. Therefore, immediately after applying the bank forming composition, the height h5 of the bank coating layer 116' in the contact hole CH may be greater than the height h4 of the bank coating layer 116' on the planarization layer 115. For example, in the case where the height h2 of the planarization layer 115 is about 2 μm and the size of the contact hole CH is 10×12 μm, the height h5 of the bank coating layer 116' in the contact hole may be 2.03 μm, and the height h4 of the bank coating layer 116' on the planarization layer 115 may be 1.13 μm. Meanwhile, in the case where the size of the contact hole CH is 5×7 μm, the height h5 of the bank coating layer 116′ in the contact hole may be 2.42 μm, and the height h4 of the bank coating layer 116′ on the planarization layer 115 may be 1.06 μm. In this case, a mask MS may be provided to etch the bank 116 by means of an open mask process. For example, a mask region of the mask MS is a region corresponding to the first bank 116a formed by a subsequent etching process, and corresponds to the non-light emitting area NEA, and an opening region of the mask MS may correspond to the light emitting area EA. In this case, the bank coating layer 116′ provided in the contact hole CH may be exposed without being covered by the mask MS. Meanwhile, a half-tone mask process may be performed instead of the open mask process.

[0097] Continue to refer to Fig.7D , a process of etching the bank coating layer 116' may be performed. Therefore, the first bank 116a may be provided on the top surface of the planarization layer 115, and the second bank 116b, which is a residue of the bank coating layer 116' remaining by being exposed without a mask, may be provided in the region where the contact hole CH is provided. Figure 7C As shown in , since the height of the bank coating layer 116' in the contact hole CH is greater than the height of the top surface of the planarization layer 115, even if the same exposure dose is applied, the bank coating layer 116' remains in the contact hole CH in the form of a residue, so that the second bank 116b is formed. In this case, in order to cover the step difference between the passivation layer 114 and the planarization layer 115 in the contact hole CH, the exposure dose can be adjusted so that the thickness of the residue of the bank coating layer 116' is equal to or greater than the passivation layer 114.

[0098] Finally, refer to Fig. 7E , the light emitting layer 122 and the cathode 123 are sequentially deposited on the first anode 121 a , the first bank 116 a , and the second bank 116 b , so that the process of manufacturing the display device 100 may be completed.

[0099] Exemplary embodiments of the present disclosure may also be described as follows:

[0100] According to one aspect of the present disclosure, a display device is provided. The display device includes: a substrate including a plurality of sub-pixels; a driving transistor in each of the plurality of sub-pixels; a passivation layer on the driving transistor; a planarization layer on the passivation layer; a contact hole formed in the passivation layer and the planarization layer to expose a source electrode of the driving transistor; a first anode on the top surface of the planarization layer and the contact hole; a first bank configured to cover an edge of the first anode; and a second bank disposed on the first anode in the contact hole. The height of the second bank is equal to or less than the height of the planarization layer.

[0101] A height of the second bank may be greater than a height of the passivation layer.

[0102] The second bank may be adjacent to the first anode disposed on the side surface of the planarization layer in the contact hole.

[0103] The contact hole may expose a portion of a top surface of the passivation layer, and the second bank may cover a step difference between the passivation layer and the planarization layer.

[0104] The second bank may have a shape having a step difference, and a portion of the second bank adjacent to the planarization layer may have a width greater than a width of a portion of the second bank adjacent to the passivation layer.

[0105] One end of the passivation layer may overlap one end of the planarization layer in the contact hole.

[0106] The display device may further include a second anode on the first anode, and the second anode is disposed on the second bank in the contact hole.

[0107] The planarization layer may include: a first planarization layer on the passivation layer; and a second planarization layer on the first planarization layer. The second planarization layer may cover a side surface of the first planarization layer in the contact hole.

[0108] One end of the second planarization layer may overlap one end of the passivation layer in the contact hole.

[0109] The plurality of sub-pixels may include a light emitting region and a non-light emitting region, and the contact hole may be provided in the light emitting region.

[0110] The plurality of sub-pixels may include a light emitting region and a non-light emitting region, the contact hole is disposed adjacent to the non-light emitting region, and one end of the first bank may be connected to the second bank in the contact hole.

[0111] Although the embodiments of the present disclosure have been described in detail with reference to the accompanying drawings, the present disclosure is not limited thereto and can be implemented in a variety of different forms without departing from the technical concept of the present disclosure. Therefore, the exemplary embodiments of the present disclosure are provided for illustrative purposes only and are not intended to limit the technical concept of the present disclosure. The scope of the technical concept of the present disclosure is not limited thereto. Therefore, it should be understood that the above exemplary embodiments are illustrative in all aspects and do not limit the present disclosure. The scope of protection of the present disclosure should be interpreted based on the following claims, and all technical concepts within their equivalent scope should be interpreted as falling within the scope of the present disclosure.

Claims

1. A display device, comprising: a substrate comprising a plurality of sub-pixels; a drive transistor in each of the plurality of sub-pixels; a passivation layer on the drive transistor; a planarization layer on the passivation layer; forming a contact hole in the passivation layer and the planarization layer to expose a source electrode of the driving transistor; a first anode on the top surface of the planarization layer and the contact hole; a first bank configured to cover an edge of the first anode; as well as a second bank disposed on the first anode in the contact hole, Wherein, the height of the second bank is equal to or less than the height of the planarization layer.

2. The display device according to claim 1, wherein: A height of the second bank is greater than a height of the passivation layer.

3. The display device according to claim 1, wherein: The second bank is adjacent to the first anode disposed on a side surface of the planarization layer in the contact hole.

4. The display device according to claim 1, wherein: The contact hole exposes a portion of a top surface of the passivation layer, and the second bank covers a step difference between the passivation layer and the planarization layer.

5. The display device according to claim 4, wherein: The second bank has a shape having the step difference, and a width of a portion of the second bank adjacent to the planarization layer is greater than a width of a portion of the second bank adjacent to the passivation layer.

6. The display device according to claim 1, wherein: One end of the passivation layer overlaps one end of the planarization layer in the contact hole.

7. The display device according to claim 6, further comprising: a second anode on the first anode, Wherein, the second anode is arranged on the second bank in the contact hole.

8. The display device according to claim 1, wherein: The planarization layer comprises: a first planarization layer on the passivation layer; and a second planarization layer on the first planarization layer, and Wherein, in the contact hole, the second planarization layer covers the side surface of the first planarization layer.

9. The display device according to claim 8, wherein: One end of the second planarization layer overlaps one end of the passivation layer in the contact hole.

10. The display device according to claim 1, wherein: The plurality of sub-pixels include a light emitting region and a non-light emitting region, and the contact hole is disposed in the light emitting region.

11. The display device according to claim 1, wherein: The plurality of sub-pixels include a light-emitting region and a non-light-emitting region, the contact hole is disposed adjacent to the non-light-emitting region, and one end of the first bank is connected to the second bank in the contact hole.

12. The display device according to claim 1, wherein: The contact hole is in an inverted cone shape. 13 . The display device according to claim 8 , wherein a height of the second bank is equal to or smaller than a height of the first planarization layer.

14. A method for manufacturing a display device according to claims 1 to 13, etching a portion of the passivation layer and a portion of the planarization layer to form the contact hole; depositing the first anode on the planarization layer and the contact hole; coating the planarization layer and the contact hole to form a bank coating layer, wherein a height of the bank coating layer in the contact hole is greater than a height of the bank coating layer on the planarization layer; The bank coating layer is etched to form the first bank and the second bank.

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