Display device and method of manufacturing same

Abstract

The invention relates to a display device and a method of manufacturing the same. The display device includes: a first barrier insulating layer on a first substrate and including a first contact hole; a pad having a portion on the first barrier insulating layer and another portion inserted into the first contact hole; a second barrier insulating layer including a first portion on an upper surface of the portion of the pad and a second portion on an upper surface of another portion of the pad; a third barrier insulating layer on a second portion of the second barrier insulating layer; a coating layer on the third barrier insulating layer; a second substrate on the coating layer and the first portion of the second barrier insulating layer; a first connection line on the second substrate and electrically connected to the pad; and a flexible film including a lead electrode inserted into the opening portion of the first substrate.

Description

Technical Field

[0001] The present disclosure relates to a display device and a method of manufacturing the display device. Background Art

[0002] With the development of information-oriented society, various demands for display devices are increasing. For example, various electronic devices such as smart phones, digital cameras, laptop computers, navigation devices, and smart TVs are using display devices. The display device may be a flat panel display device, such as a liquid crystal display device, a field emission display device, and an organic light emitting display device. In such a flat panel display device, the light emitting display device may include a light emitting element that can emit light by itself, so that each of the pixels of the display panel can emit light by itself. Therefore, the light emitting display device can display an image without a backlight unit that provides light to the display panel.

[0003] It will be understood that this "background technology section" is intended, in part, to provide a useful background for understanding the technology. However, this "background technology section" may also include ideas, concepts, or cognitions that were not known or understood by a person skilled in the relevant art before the corresponding effective filing date of the subject matter disclosed herein. Summary of the invention

[0004] Aspects of the present disclosure provide a display device that can improve reliability in such a manner that an optical process can be accurately performed by easily recognizing an alignment key, and a method of manufacturing the display device.

[0005] Aspects of the present disclosure also provide a display device and a method of manufacturing the display device that can save manufacturing time and cost by reducing a non-display area and simplifying a manufacturing process.

[0006] It should be noted that the objects of the present disclosure are not limited to the above objects, and other objects will be apparent to those skilled in the art from the following description.

[0007] According to an embodiment, a display device may include: a first substrate having an opening portion; a first blocking insulating layer disposed on the first substrate, the first blocking insulating layer including a first contact hole; a pad having a portion disposed on the first blocking insulating layer and another portion inserted into the first contact hole; a second blocking insulating layer including a first portion disposed on an upper surface of the portion of the pad and a second portion disposed on an upper surface of another portion of the pad; a third blocking insulating layer disposed on the second portion of the second blocking insulating layer; a coating disposed on the third blocking insulating layer; a second substrate disposed on the coating and the first portion of the second blocking insulating layer; a first connecting line disposed on the second substrate and electrically connected to the pad; and a flexible film including a lead electrode inserted into the opening portion of the first substrate.

[0008] The third blocking insulating layer may absorb light, and the coating layer may include an organic material.

[0009] A height of the first portion of the second blocking insulating layer from the upper surface of the first substrate may be greater than a height of the second portion of the second blocking insulating layer from the upper surface of the first substrate.

[0010] The second barrier insulating layer may further include a third portion that does not overlap the pad. The third barrier insulating layer and the coating layer may be disposed on the third portion of the second barrier insulating layer.

[0011] A height of the first portion of the second blocking insulating layer from the upper surface of the first substrate may be greater than a height of the third portion of the second blocking insulating layer from the upper surface of the first substrate.

[0012] The first connection line may be inserted into a second contact hole formed in the second substrate and the first portion of the second blocking insulating layer.

[0013] The display device may further include: a gate insulator disposed on the second substrate; a second connection line disposed on the gate insulator and electrically connected to the first connection line; and an interlayer dielectric layer disposed in a layer between the second connection line and the first connection line.

[0014] The display device may further include a contact portion covering a lower surface of the lead electrode and a lower surface of the pad to electrically connect the lead electrode to the pad.

[0015] The contact portion may be a sintered metal organic decomposition ink, conductive ink, or metal paste containing silver (Ag), copper (Cu), aluminum (Al), or chromium (Cr).

[0016] The lead electrode may be disposed on a lower surface of the pad through an adhesive portion.

[0017] According to an embodiment, a method for manufacturing a display device may include: preparing a first substrate; forming a first blocking insulating layer including a first contact hole on the first substrate; forming a pad in a pad area of ​​the first substrate, a portion of the pad being disposed on the first blocking insulating layer, and another portion of the pad being inserted into the first contact hole; forming an alignment key on the first blocking insulating layer in a key area of ​​the first substrate; forming a second blocking insulating layer, the second blocking insulating layer including a first portion disposed on an upper surface of the portion of the pad and the alignment key, and a second portion disposed on an upper surface of another portion of the pad; forming a third blocking insulating layer on the first portion and the second portion of the second blocking insulating layer; forming a coating on the third blocking insulating layer; etching the coating disposed on the first portion of the second blocking insulating layer; and etching the third blocking insulating layer disposed on the first portion of the second blocking insulating layer.

[0018] Forming the coating layer may include providing a fluid organic solution on the third barrier insulating layer such that a thickness of the coating layer disposed on a first portion of the second barrier insulating layer is less than a thickness of the coating layer disposed on a second portion of the second barrier insulating layer.

[0019] Etching the coating layer may include etching the coating layer disposed on the first portion of the second blocking insulating layer to expose the third blocking insulating layer while leaving the coating layer disposed on the second portion of the second blocking insulating layer.

[0020] Etching the third blocking insulating layer may include etching the exposed third blocking insulating layer on the first portion of the second blocking insulating layer, and the remaining coating layer protects the third blocking insulating layer on the second portion of the second blocking insulating layer.

[0021] Etching the third blocking insulating layer may further include: exposing a first portion of the second blocking insulating layer.

[0022] The method may also include forming a second substrate on the coating layer and a first portion of the second blocking insulating layer; forming a second contact hole penetrating the second substrate and the first portion of the second blocking insulating layer to expose the pad; and forming a first connecting line, which is disposed on the second substrate and inserted into the second contact hole, and the first connecting line is electrically connected to the pad.

[0023] The method may further include separating the alignment key by cutting along a cutting line between the pad region and the key region.

[0024] The method may further include forming an opening portion of the first substrate by etching a lower portion of the first substrate to expose the pad.

[0025] The method may further include inserting a flexible film into the opening portion to dispose a lead electrode of the flexible film on a lower surface of the pad.

[0026] The method may further include electrically connecting the lead electrode to the pad through the contact portion.

[0027] According to an embodiment, the light-absorbing blocking insulating layer is not aligned with the alignment key in the display device, so that the alignment key can be easily identified. Therefore, the optical process can be accurately performed and the reliability can be improved. By reducing the area of ​​the non-display area and simplifying the manufacturing process, the manufacturing time and cost can be reduced.

[0028] It should be noted that the effects of the present disclosure are not limited to the above-mentioned effects, and other effects of the present disclosure will be apparent to those skilled in the art from the following description. BRIEF DESCRIPTION OF THE DRAWINGS

[0029] The above and other aspects and features of the present disclosure will become more apparent by describing in detail embodiments of the present disclosure with reference to the attached drawings.

[0030] Figure 1 is a schematic plan view showing a display device according to an embodiment.

[0031] Figure 2 is a schematic cross-sectional view showing a display device according to an embodiment.

[0032] Figure 3 It is shown along Figure 1 A schematic cross-sectional view of the example taken along line II'.

[0033] Figure 4 is a bottom view showing a display device according to an embodiment.

[0034] Figure 5 is a schematic plan view showing a part of a non-display area of ​​a display device according to an embodiment.

[0035] Figure 6 is a schematic cross-sectional view showing a portion of a display device according to an embodiment.

[0036] Figure 7 is a schematic cross-sectional view showing a connection relationship of pads in a display device according to an embodiment.

[0037] Figures 8 to 16 2 is a schematic cross-sectional view showing a process step of manufacturing a display device according to an embodiment. DETAILED DESCRIPTION

[0038] In the following description, for the purpose of explanation, many details are set forth to provide a thorough understanding of various embodiments or embodiments of the present disclosure. As used herein, "embodiment" and "embodiment" are interchangeable words, which are non-limiting examples of the devices or methods disclosed herein. However, it is apparent that various embodiments can be practiced without these specific details or with one or more equivalent arrangements. In other cases, structures and devices are shown in block diagram form to avoid unnecessary ambiguity of various embodiments. In addition, various embodiments may be different, but do not have to be exclusive, nor do they limit the present disclosure. For example, the shape, configuration, and characteristics of the embodiments may be used or implemented in other embodiments without departing from the present disclosure.

[0039] Unless otherwise specified, the embodiments shown will be understood as features of varying details that can implement some of the methods of the present disclosure in practice. Therefore, unless otherwise specified, the features, components, modules, layers, films, panels, regions and / or aspects, etc. (hereinafter individually or collectively referred to as "elements") of various embodiments can be combined, separated, interchanged and / or rearranged in other ways without departing from the present disclosure.

[0040] The use of cross-hatching and / or shading is often provided in the drawings to clarify the boundaries between adjacent elements. Therefore, the presence or absence of cross-hatching or shading does not convey or indicate any preference or requirement for specific materials, material properties, dimensions, proportions, commonalities between the elements shown, and / or any other characteristics, attributes, properties, etc. of the elements, unless otherwise stated.

[0041] In addition, in the accompanying drawings, the size and relative size of the elements may be exaggerated for the purpose of clarity and / or description. When the embodiments may be implemented differently, a specific process sequence may be performed differently from the described sequence. For example, two processes described in succession may be performed substantially simultaneously, or in an order opposite to the described sequence. In addition, the same reference numerals represent the same elements.

[0042] When an element or layer is referred to as being "on," "connected to," or "coupled to" another element or layer, it may be directly on, directly connected to, or directly coupled to the other element or layer, or there may be intervening elements or layers. However, when an element or layer is referred to as being "directly on," "directly connected to," or "directly coupled to" another element or layer, there are no intervening elements or layers. For this purpose, the term "connected" may refer to a physical connection, an electrical connection, and / or a fluid connection with or without intervening elements.

[0043] In addition, the X-axis, Y-axis and Z-axis are not limited to the three axes of the rectangular coordinate system, and therefore the X-axis, Y-axis and Z-axis can be interpreted in a broader sense. For example, the X-axis, Y-axis and Z-axis can be perpendicular to each other, or can represent different directions that are not perpendicular to each other.

[0044] For the purpose of the present disclosure, "at least one of X, Y, and Z" and "at least one selected from the group consisting of X, Y, and Z" may be interpreted as only X, only Y, only Z, or any combination of two or more of X, Y, and Z, such as, for example, XYZ, XY, YZ, XZ, etc. within the spirit and scope of the present disclosure. As used herein, the term "and / or" includes any and all combinations of one or more of the associated listed items.

[0045] Although the terms "first", "second", etc. may be used herein to describe various types of elements, these elements should not be limited by these terms. These terms are used to distinguish one element from another element. Therefore, the first element discussed below may be referred to as the second element without departing from the teachings of the present disclosure.

[0046] For the purpose of description, spatial relative terms such as "below", "below", "below", "lower", "above", "upper", "above", "higher", "side", (e.g., as in "sidewall"), etc. may be used herein, and thereby describe the relationship between an element and another (multiple) element as shown in the drawings. In addition to the orientation depicted in the drawings, spatial relative terms are intended to also include different orientations of the device in use, operation and / or manufacture. For example, if the device in the drawings is flipped, the element described as being "below" or "below" other elements or features will then be oriented "above" other elements or features. Therefore, the term "below" can include both the orientation above and below. In addition, the device can be oriented in addition (e.g., rotated 90 degrees or in other orientations), and therefore the spatial relative descriptors used herein should be interpreted accordingly. The term "overlap" or "overlapping" means that the first object can be above or below or on one side of the second object, and vice versa. Additionally, the term "overlapping" may include layer, stack, face or facing, extending over, covering or partially covering or any other suitable term as would be appreciated and understood by one of ordinary skill in the art.

[0047] The terms "face" and "facing" mean that the first element can be directly or indirectly opposite to the second element. In the case where a third element is interposed between the first and second elements, the first and second elements can be understood to be indirectly opposite to each other, although still facing each other.

[0048] When an element is described as “not overlapping” or “will not overlap” another element, this may include the elements being spaced apart, offset from each other, or positioned alongside each other, or any other suitable terminology as would be appreciated and understood by one of ordinary skill in the art.

[0049] The terminology used herein is for the purpose of describing particular embodiments and is not intended to be limiting.

[0050] In the specification and claims, the term "and / or" is intended to include any combination of the terms "and" and "or" for the purpose of its meaning and interpretation. For example, "A and / or B" may be understood to mean "A, B, or A and B". The terms "and" and "or" may be used in conjunction or in a separate sense and may be understood to be equivalent to "and / or".

[0051] As used herein, the singular forms “a”, “an” and “the” are intended to include the plural forms as well, unless the context clearly indicates otherwise.

[0052] In addition, when used in this specification, the terms "comprises", "including", "includes" and / or "comprising" and their variations specify the presence of stated features, integers, steps, operations, elements, components and / or groups thereof, but do not exclude the presence or addition of one or more other features, integers, steps, operations, elements, components and / or groups thereof.

[0053] It is also noted that as used herein, the terms "substantially," "about," and other similar terms are used as terms of approximation and not as terms of degree, and, thus, are used to account for the inherent deviations in measured, calculated, and / or provided values ​​that those of ordinary skill in the art would recognize.

[0054] Various embodiments are described herein with reference to cross-sectional views and / or exploded views as schematic diagrams of embodiments and / or intermediate structures. Therefore, variations in the shapes of the illustrations due to, for example, manufacturing techniques and / or tolerances are expected. Therefore, the embodiments disclosed herein need not be interpreted as limited to the shapes of the specifically illustrated regions, but will include deviations in shapes due to, for example, manufacturing. In this way, the regions shown in the accompanying drawings may be schematic in nature, and the shapes of these regions may not reflect the actual shapes of the regions of the device, and therefore, are not necessarily intended to be limiting.

[0055] As understood in the art, some embodiments are described and illustrated in the accompanying drawings according to functional blocks, units, parts and / or modules. It will be understood by those skilled in the art that these functional blocks, units, parts and / or modules are physically implemented by electronic (or optical) circuits such as logic circuits, discrete components, microprocessors, hard-wired circuits, memory elements, wiring connections, etc., which can be formed using semiconductor-based manufacturing techniques or other manufacturing techniques. In the case where the functional blocks, units, parts and / or modules are implemented by microprocessors or other similar hardware, they can be programmed and controlled using software (e.g., microcode) to perform the various functions discussed herein, and can be optionally driven by firmware and / or software. It is also conceivable that each functional block, unit, part and / or module can be implemented by dedicated hardware, or implemented as a combination of dedicated hardware that performs some functions and processors (e.g., one or more programmed microprocessors and associated circuits) that perform other functions. In addition, each functional block, unit, part and / or module of some embodiments can be physically divided into two or more interactive and discrete functional blocks, units, parts and / or modules without departing from the scope of this disclosure. Furthermore, the functional blocks, units, parts and / or modules of some embodiments may be physically combined into more complex functional blocks, units, parts and / or modules without departing from the scope of the present disclosure.

[0056] Unless otherwise defined or implied herein, all terms (including technical and scientific terms) used herein have the same meaning as commonly understood by those skilled in the art to which the present disclosure belongs. It will also be understood that terms (such as those defined in general dictionaries) should be interpreted as having a meaning consistent with their meaning in the context of the relevant art and the present disclosure, and should not be interpreted in an idealized or overly formal sense, unless clearly so defined herein.

[0057] Hereinafter, detailed embodiments of the present disclosure are described with reference to the accompanying drawings.

[0058] Figure 1 is a schematic plan view showing a display device according to an embodiment.

[0059] refer to Figure 1 , the display device 10 can be used by portable electronic devices such as mobile phones, smart phones, tablet PCs, mobile communication terminals, electronic notebooks, electronic books, portable multimedia players (PMPs), navigation devices, and ultra-mobile PCs (UMPCs). As another example, the display device 10 can be used as a display unit of a television, a laptop computer, a monitor, an electronic billboard, or an Internet of Things (IOT) device. As another example, the display device 10 can be applied to wearable devices such as smart watches, watch phones, glasses-type displays, and head-mounted display (HMD) devices.

[0060] When viewed from the top, the display device 10 may have a shape similar to a quadrilateral shape. For example, the corners where the sides in the X-axis direction and the sides in the Y-axis direction intersect each other may be rounded to have a selectable curvature, or may be formed at a right angle. When viewed from the top, the shape of the display device 10 is not limited to a quadrilateral shape, but may be formed in a shape similar to other polygonal shapes, a circular shape, or an elliptical shape.

[0061] The display device 10 may include a display area DA and a non-display area NDA. The display area DA may include pixels for displaying an image. Each of the pixels may include an organic light emitting diode including an organic light emitting layer, a quantum dot LED including a quantum dot light emitting layer, an inorganic light emitting diode (LED) including an inorganic semiconductor, or a micro LED. In the following description, each of the pixels may include an organic light emitting diode. However, it will be understood that the present disclosure is not limited thereto.

[0062] The pixels may be arranged or disposed in rows and columns in the display area DA. Each of the pixels may include an emission area EA defined by a pixel defining layer or a bank, and may emit light having a selectable peak wavelength through the emission area EA. In the emission area EA, light generated by the light emitting element of the display device 10 is emitted outside the display device 10.

[0063] The display area DA of the display device 10 may include a light blocking area BA surrounding the emission area EA. The light blocking area BA may prevent color mixing of light output from the emission area EA.

[0064] The non-display area NDA may be arranged around the display area DA to surround the display area DA, and may not display an image. The non-display area NDA may include a scan driver SIC that provides a scan signal to the display area DA. The scan driver SIC may be arranged on the left and right sides of the non-display area NDA. The scan driver SIC may generate a scan signal based on a scan control signal. The scan control signal may include, but is not limited to, a start signal, a clock signal, and a power voltage. The scan driver SIC may provide a scan signal to a scan line of the display area DA in a selectable order.

[0065] Figure 2 is a schematic cross-sectional view showing a display device according to an embodiment.

[0066] refer to Figure 2 The display panel 100 may include a display unit DU, a touch sensing unit TSU, and an optical member POL. The display unit DU may include a first substrate SUB1, a blocking insulating layer BIL, a second substrate SUB2, a transistor layer TRL, an emission material layer EML, and an encapsulation layer TFEL.

[0067] The first substrate SUB1 may support the display device 10. The first substrate SUB1 may be a base substrate or a base member. The first substrate SUB1 may be a flexible substrate that may be bent, folded, or curled. For example, the first substrate SUB1 may include, but is not limited to, an insulating material such as a polymer resin (e.g., polyimide (PI)). For another example, the first substrate SUB1 may be a rigid substrate including a glass material.

[0068] The blocking insulating layer BIL may be disposed on the first substrate SUB1. The blocking insulating layer BIL may include an inorganic film capable of preventing air or moisture from penetrating. For example, the blocking insulating layer BIL may include but is not limited to at least one of a silicon nitride layer, a silicon oxynitride layer, a silicon oxide layer, a titanium oxide layer, an aluminum oxide layer, and an amorphous silicon layer.

[0069] The second substrate SUB2 may be disposed on the blocking insulating layer BIL. The second substrate SUB2 may be a base substrate or a base member. The second substrate SUB2 may be a flexible substrate that may be bent, folded, or curled. For example, the second substrate SUB2 may include, but is not limited to, an insulating material such as a polymer resin (eg, polyimide (PI)).

[0070] The transistor layer TRL may be disposed on the second substrate SUB2. The transistor layer TRL may include transistors forming pixel circuits of pixels. The transistor layer TRL may include scan lines, data lines, and power lines connected to the pixels. Each of the transistors may include a semiconductor region, a source electrode, a drain electrode, and a gate electrode. For example, in the case where the scan driver is formed on one side or one side of the non-display area NDA of the display panel 100, the scan driver may include a transistor.

[0071] The transistor layer TRL may be disposed in the display area DA and the non-display area NDA. Transistors in the transistor layer TRL for pixels, scan lines, data lines, and power lines may be disposed in the display area DA. Transistors of the scan driver SIC may be disposed in the non-display area NDA.

[0072] The emission material layer EML may be disposed on the transistor layer TRL. The emission material layer EML may include a light emitting element and a pixel defining layer for defining a pixel, in each of which a pixel electrode, an emission layer, and a common electrode are sequentially stacked with each other to emit light. The light emitting element in the emission material layer EML may be disposed in the display area DA.

[0073] For example, the emission layer may be an organic light-emitting layer including an organic material. The emission layer may include a hole transport layer, an organic light-emitting layer, and an electron transport layer. In the case where the pixel electrode receives a voltage through a transistor in the transistor layer TRL and the common electrode receives a cathode voltage, holes may move to the organic light-emitting layer through the hole transport layer, and electrons may move to the organic light-emitting layer through the electron transport layer, so that they combine in the organic light-emitting layer to emit light. For example, the pixel electrode may be an anode electrode, and the common electrode may be a cathode electrode. However, it will be understood that the present disclosure is not limited thereto.

[0074] As another example, the light emitting elements may include quantum dot light emitting diodes each including a quantum dot emission layer, inorganic light emitting diodes each including an inorganic semiconductor, or micro light emitting diodes.

[0075] The encapsulation layer TFEL may cover the upper surface and the side surface of the emission material layer EML and may protect the emission material layer EML. The encapsulation layer TFEL may include at least one inorganic layer and at least one organic layer for encapsulating the emission material layer EML.

[0076] The touch sensing unit TSU may be disposed on the encapsulation layer TFEL. The touch sensing unit TSU may include a touch electrode for sensing a user's touch through capacitive sensing, and a touch line for providing a touch drive signal to the touch electrode. For example, the touch sensing unit TSU may sense a user's touch through mutual capacitance sensing or self capacitance sensing.

[0077] The touch electrodes of the touch sensing unit TSU may be disposed in a touch sensor area overlapping the display area DA. The touch lines of the touch sensing unit TSU may be disposed in a touch peripheral area overlapping the non-display area NDA.

[0078] The optical member POL may be disposed on the touch sensing unit TSU. The optical member POL may be attached to the touch sensing unit TSU by using an optically clear adhesive (OCA) film or an optically clear resin (OCR). For example, the optical member POL may include a linear polarizer and a retardation film. The retardation film may be a λ / 4 plate (quarter wave plate). The retardation film and the linear polarizer may be sequentially stacked on the touch sensing unit TSU. The optical member POL may reduce the reflection of external light to prevent color distortion caused by the reflection of external light.

[0079] The first substrate SUB1 may include an opening portion SOP. The opening portion SOP of the first substrate SUB1 may be etched so that it penetrates from the lower surface of the first substrate SUB1 to the upper surface of the first substrate SUB1. For example, the width of the bottom of the opening portion SOP may be greater than the width of the top of the opening portion SOP. During the process of manufacturing the display device 10, the pad provided in the blocking insulating layer BIL may be exposed by the opening portion SOP of the first substrate SUB1. The pad may be electrically connected to the display driver DIC through the flexible film FPCB inserted into the opening portion SOP.

[0080] The flexible film FPCB may be disposed under (or below) the first substrate SUB1. A portion of the flexible film FPCB may be inserted into the opening portion SOP of the first substrate SUB1 and electrically connected to the pad. The flexible film FPCB may support the display driver DIC. The flexible film FPCB may transmit signals and voltages from the display driver DIC to the transistor layer TRL. The flexible film FPCB may provide a scan control signal to the scan driver SIC.

[0081] The display driver DIC may be mounted on the flexible film FPCB. The display driver DIC may be an integrated circuit (IC). The display driver DIC may convert digital video data into an analog data voltage based on a data control signal from a timing controller (not shown), and may provide it to the data lines in the display area DA through the flexible film FPCB. The display driver DIC may provide a power voltage received from a power supply unit (not shown) to the power lines in the display area DA through the flexible film FPCB. Since the display device 10 may include a flexible film FPCB electrically connected to a pad at the opening portion SOP of the first substrate SUB1, the non-display area NDA may be reduced.

[0082] Figure 3 It is shown along Figure 1 A schematic cross-sectional view of the example taken along line II'.

[0083] refer to Figure 3 The display area DA of the display device 10 may include emission areas EA. In each of the emission areas EA, light generated by the light emitting element ED is emitted to the outside of the display device 10.

[0084] The display panel 100 may include a first substrate SUB1, a first blocking insulating layer BIL1, a second blocking insulating layer BIL2, a third blocking insulating layer BIL3, a second substrate SUB2, a transistor layer TRL, an emission material layer EML, an encapsulation layer TFEL, a touch sensing unit TSU, an overcoat layer OC, and an optical member POL.

[0085] The first substrate SUB1 may support the display panel 100. The first substrate SUB1 may be a base substrate or a base member. The first substrate SUB1 may be a flexible substrate that may be bent, folded, or curled. For example, the first substrate SUB1 may include, but is not limited to, an insulating material such as a polymer resin (e.g., polyimide (PI)). For another example, the first substrate SUB1 may be a rigid substrate including a glass material.

[0086] The first blocking insulating layer BIL1 may be disposed on the first substrate SUB1. The first blocking insulating layer BIL1 may include an inorganic film capable of preventing air or moisture from penetrating. For example, the first blocking insulating layer BIL1 may include but is not limited to at least one of a silicon nitride layer, a silicon oxynitride layer, a silicon oxide layer, a titanium oxide layer, an aluminum oxide layer, and an amorphous silicon layer.

[0087] The second blocking insulating layer BIL2 may be disposed on the first blocking insulating layer BIL1. The second blocking insulating layer BIL2 may include an inorganic film capable of preventing air or moisture from penetrating. For example, the second blocking insulating layer BIL2 may include but is not limited to at least one of a silicon nitride layer, a silicon oxynitride layer, and a silicon oxide layer.

[0088] The third barrier insulating layer BIL3 may be disposed on the second barrier insulating layer BIL2. The third barrier insulating layer BIL3 may include an inorganic film capable of preventing air or moisture from penetrating. The third barrier insulating layer BIL3 may improve delamination defects by increasing adhesion between the upper layer and the lower layer. For example, the third barrier insulating layer BIL3 may include, but is not limited to, amorphous silicon (a-Si).

[0089] The second substrate SUB2 may be disposed on the third blocking insulating layer BIL3. The second substrate SUB2 may be a base substrate or a base member. The second substrate SUB2 may be a flexible substrate that may be bent, folded, or curled. For example, the second substrate SUB2 may include, but is not limited to, an insulating material such as a polymer resin (eg, polyimide (PI)).

[0090] The transistor layer TRL may be disposed on the second substrate SUB2. The transistor layer TRL may include an active layer ACTL, a gate insulator GI, a gate layer GTL, an interlayer dielectric layer ILD, a first source metal layer SDL1, a first via layer VIA1, a second source metal layer SDL2, and a second via layer VIA2.

[0091] The active layer ACTL may be disposed on the second substrate SUB2. The active layer ACTL may include a semiconductor region ACT, a drain electrode DE, and a source electrode SE of the transistor TR. The semiconductor region ACT may overlap with the gate electrode GE and may be insulated from the gate electrode GE by a gate insulator GI. The drain electrode DE and the source electrode SE may be formed by making the material of the semiconductor region ACT conductive. The transistor TR may form a pixel circuit of each of the pixels.

[0092] The gate insulator GI may be disposed on the active layer ACTL. The gate insulator GI may insulate between the semiconductor region ACT of the transistor TR and the gate electrode GE. The gate insulator GI may include a contact hole through which the connection electrode CNE passes.

[0093] The gate layer GTL may be disposed on the gate insulator GI. The gate layer GTL may include a gate electrode GE of the transistor TR. The gate electrode GE may overlap the semiconductor region ACT, wherein the gate insulator GI is disposed between the gate electrode GE and the semiconductor region ACT. The gate electrode GE may receive a scan signal from a scan line. For example, the gate layer GTL may be composed of a single layer or multiple layers including at least one of molybdenum (Mo), aluminum (Al), chromium (Cr), gold (Au), silver (Ag), titanium (Ti), nickel (Ni), palladium (Pd), indium (In), neodymium (Nd), and copper (Cu).

[0094] The interlayer dielectric layer ILD may be disposed on the gate layer GTL. The interlayer dielectric layer ILD may insulate the gate layer GTL and the first source metal layer SDL1. The interlayer dielectric layer ILD may include a contact hole through which the connection electrode CNE passes.

[0095] The first source metal layer SDL1 may be disposed on the interlayer dielectric layer ILD. The first source metal layer SDL1 may include a connection electrode CNE. The connection electrode CNE may be inserted into a contact hole penetrating the interlayer dielectric layer ILD and the gate insulator GI to be connected to the source electrode SE of the transistor TR. The connection electrode CNE may electrically connect the transistor TR to the anode connection electrode ANE. The connection electrode CNE may provide the light emitting element ED with a driving current received from the pixel circuit through the anode connection electrode ANE. For example, the first source metal layer SDL1 may be composed of a single layer or multiple layers including at least one of molybdenum (Mo), aluminum (Al), chromium (Cr), gold (Au), silver (Ag), titanium (Ti), nickel (Ni), palladium (Pd), indium (In), neodymium (Nd) and copper (Cu).

[0096] The first via layer VIA1 may be disposed on the first source metal layer SDL1. The first via layer VIA1 may provide a flat surface throughout the pixel circuit and may protect the pixel circuit. The first via layer VIA1 may include an organic insulating material such as polyimide (PI). The first via layer VIA1 may include a contact hole through which the anode connection electrode ANE passes.

[0097] The second source metal layer SDL2 may be disposed on the first via layer VIA1. The second source metal layer SDL2 may include an anode connection electrode ANE, a data line DL, and a voltage line VL. The second source metal layer SDL2 may include the materials of the first source metal layer SDL1 listed above.

[0098] The anode connection electrode ANE may be inserted into a contact hole penetrating the first via layer VIA1 and connected to the connection electrode CNE. The anode connection electrode ANE may electrically connect the connection electrode CNE to the pixel electrode (anode electrode) AE of the light emitting element ED. The anode connection electrode ANE may provide the light emitting element ED with a driving current received from the connection electrode CNE.

[0099] The data line DL may extend in the Y-axis direction in the display area DA. The data line DL may be electrically connected to the transistor TR. The data line DL may provide a data voltage to the pixel circuit.

[0100] The voltage line VL may extend in the Y-axis direction in the display area DA. The voltage line VL may be electrically connected to the transistor TR or the light emitting element ED. For example, the voltage line VL may be, but is not limited to, a high level line, a low level line, an initialization voltage line, a reference voltage line, or a bias voltage line.

[0101] The second via layer VIA2 may be disposed on the second source metal layer SDL2. The second via layer VIA2 may provide a flat top surface of the transistor layer TRL. The second via layer VIA2 may include an organic insulating material such as polyimide (PI). The second via layer VIA2 may include a contact hole through which the pixel electrode AE ​​passes.

[0102] The emission material layer EML may be disposed on the transistor layer TRL. The emission material layer EML may include a light emitting element ED and a pixel defining layer PDL.

[0103] The light emitting element ED may be disposed in the emission area EA on the second via layer VIA2. The light emitting element ED of each pixel may include an anode electrode AE, an emission layer EL, and a common electrode CE. The pixel electrode AE ​​may be disposed on the second via layer VIA2. The pixel electrode AE ​​may overlap one of the emission areas EA defined by the pixel defining layer PDL. For example, the pixel electrode AE ​​may receive a driving current from the pixel circuit through the anode connection electrode ANE and the connection electrode CNE.

[0104] The emission layer EL may be disposed on the pixel electrode AE. For example, the emission layer EL may be, but is not limited to, an organic emission layer made of an organic material. If the emission layer EL is an organic light-emitting layer, when a pixel circuit of a pixel applies a selectable voltage to the pixel electrode AE ​​and the common electrode CE receives a common voltage or a cathode voltage, holes may move to the emission layer EL through the hole transport layer, and electrons may move to the emission layer EL through the hole transport layer, and they are combined in the emission layer EL to emit light.

[0105] The common electrode CE may be disposed on the emission layer EL. For example, the common electrode CE may be implemented as an electrode common to all pixels, rather than being provided as a separate electrode for each of the pixels. The common electrode CE may be disposed on the emission layer EL in the emission area EA, and may be disposed on the pixel defining layer PDL in other areas except the emission area EA.

[0106] The pixel defining layer PDL may be disposed on the second via layer VIA2 in the light blocking area BA. The pixel defining layer PDL may define the emission area EA or the opening. The pixel defining layer PDL may separate and insulate the pixel electrodes AE of the pixels from each other.

[0107] The encapsulation layer TFEL may be disposed on the common electrode CE to cover the light emitting element ED. The encapsulation layer TFEL may include at least one inorganic film to prevent oxygen or moisture from penetrating into the light emitting element ED. The encapsulation layer TFEL may include at least one organic film to protect the light emitting element ED from particles such as dust.

[0108] The touch sensing unit TSU may be disposed on the encapsulation layer TFEL. The touch sensing unit TSU may include a bridge electrode BRG, a first insulating layer IL1, a touch electrode TE, and a second insulating layer IL2.

[0109] The bridge electrode BRG may be disposed on the encapsulation layer TFEL. The bridge electrode BRG may be disposed on a different layer from the touch electrodes TE to electrically connect between adjacent touch electrodes TE.

[0110] The first insulating layer IL1 may be disposed throughout the bridge electrode BRG. The first insulating layer IL1 may have insulating and optical characteristics. For example, the first insulating layer IL1 may be an inorganic layer including at least one selected from the group consisting of a silicon nitride layer, a silicon oxynitride layer, a silicon oxide layer, a titanium oxide layer, and an aluminum oxide layer. For another example, the first insulating layer IL1 may include an organic film.

[0111] The touch electrode TE may be disposed on the first insulating layer IL1 in the light blocking area BA. The touch electrode TE may detect the touch of the user by capacitive sensing. For example, the touch sensing unit TSU may sense the touch of the user by mutual capacitance sensing at points between the touch electrodes TE or by self capacitance sensing performed on each of the touch electrodes TE. The touch electrode TE may be composed of a single layer of molybdenum (Mo), titanium (Ti), copper (Cu), aluminum (Al), or indium tin oxide (ITO), or may be composed of a stacked structure of aluminum and titanium (Ti / Al / Ti), a stacked structure of aluminum and ITO (ITO / Al / ITO), an APC alloy, and a stacked structure of an APC alloy and ITO (ITO / APC / ITO). The APC alloy may be an alloy of silver (Ag), palladium (Pd), and copper (Cu).

[0112] The second insulating layer IL2 may be disposed on the touch electrode TE. The second insulating layer IL2 may have insulating and optical functions. The second insulating layer IL2 may be made of one of the materials listed above as the material of the first insulating layer IL1.

[0113] The overcoat layer OC may be disposed on the touch sensing unit TSU to provide a flat top surface of the touch sensing unit TSU. For example, the overcoat layer OC may include an organic insulating material.

[0114] The optical member POL may be disposed on the outer coating layer OC. The optical member POL may be attached to the touch sensing unit TSU by using an optically clear adhesive (OCA) film or an optically clear resin (OCR). For example, the optical member POL may include a linear polarizer and a retardation film. The retardation film may be a λ / 4 plate (quarter wave plate). The retardation film and the linear polarizer may be sequentially stacked on the touch sensing unit TSU. The optical member POL may reduce the reflection of external light to prevent color distortion caused by the reflection of external light.

[0115] Figure 4 is a bottom view showing a display device according to an embodiment.

[0116] refer to Figure 4 , the flexible film FPCB may be disposed under (or below) the first substrate SUB1. The flexible film FPCB may be disposed at the lower edge of the display device 10. The flexible film FPCB may be attached to the lower surface of the pad PAD through an adhesive portion. The lead of the flexible film FPCB may be electrically connected to the pad PAD through a contact portion. The pad PAD may be disposed in the non-display area NDA, but the present disclosure is not limited thereto.

[0117] The display driver DIC may be mounted on the flexible film FPCB. The display driver DIC may be an integrated circuit (IC). The display driver DIC may convert digital video data into an analog data voltage based on a data control signal from a timing controller (not shown), and may provide it to the data line DL in the display area DA through the flexible film FPCB. The display driver DIC may provide a power voltage received from a power supply unit (not shown) to a voltage line VL in the display area DA through the flexible film FPCB. The display driver DIC may provide a scan control signal to the scan driver SIC through the flexible film FPCB. Since the display device 10 may include a pad PAD disposed on the first substrate SUB1 and a flexible film FPCB and a display driver DIC disposed under (or below) the first substrate SUB1, the non-display area NDA may be reduced.

[0118] Figure 5 is a schematic plan view showing a part of a non-display area of ​​a display device according to an embodiment.

[0119] refer to Figure 5, the non-display area NDA may include a signal line SL, a high-level voltage line VDL, a low-level voltage line VSL, and a touch line TL. The signal line SL, the high-level voltage line VDL, the low-level voltage line VSL, and the touch line TL may extend from the pad area PDA to the display area DA. The signal line SL may be electrically connected to the data line DL to apply a data voltage, and may be electrically connected to the scan driver SIC to provide a scan control signal. The high-level voltage line VDL may be electrically connected to the voltage line VL of the display area DA to apply a high-level voltage to the pixel circuit. The low-level voltage line VSL may be electrically connected to the common electrode CE of the light-emitting element ED to provide a low-level voltage. The touch line TL may be electrically connected to the touch electrode TE of the touch sensing unit TSU to provide a touch drive signal. The signal line SL, the high-level voltage line VDL, the low-level voltage line VSL, and the touch line TL may receive a signal or voltage from the flexible film FPCB disposed under (or below) the display panel 100 through the pad PAD.

[0120] The non-display area NDA may further include an antistatic circuit ESD. The antistatic circuit ESD may overlap the signal line SL and may be electrically connected to the signal line SL. Therefore, the antistatic circuit ESD may prevent external static electricity from flowing into the display area DA through the signal line SL.

[0121] exist Figure 5 In FIG. 1 , a solid line 101 indicates a boundary at a corner of the display panel 100. Figure 5 In FIG. 1 , a solid line 102 is an imaginary line indicating a boundary between the non-display area NDA and the display area DA of the display panel 100 . Figure 5 The solid line 103 in FIG. 1 represents the boundary of the encapsulation layer TFEL of the display panel 100. Therefore, the signal line SL, the high-level voltage line VDL, and the low-level voltage line VSL may extend to the pad PAD along the non-display area NDA on the inner side of the boundary of the encapsulation layer TFEL. The signal line SL, the high-level voltage line VDL, and the low-level voltage line VSL may not be disposed on the outer side of the encapsulation layer TFEL.

[0122] Figure 6 is a schematic cross-sectional view showing a portion of a display device according to an embodiment. Figure 7 2 is a schematic cross-sectional view showing a connection relationship of pads in a display device according to an embodiment. The same elements as those described above will be briefly described or omitted.

[0123] refer to Figure 6 and Figure 7The display device 10 may include a first substrate SUB1, a first blocking insulating layer BIL1, a pad PAD, a second blocking insulating layer BIL2, a third blocking insulating layer BIL3, a coating SLP, a second substrate SUB2, a transistor layer TRL, an emission material layer EML, an encapsulation layer TFEL, a dam DAM, an anti-static circuit ESD, an anti-crack member CDM, a touch sensing unit TSU, an outer coating OC, an optical member POL, a flexible film FPCB and a display driver DIC.

[0124] The pad PAD may be disposed on the first blocking insulating layer BIL1 and inserted into the first contact hole CNT1 formed in the first blocking insulating layer BIL1. During the process of manufacturing the display device 10, the lower surface of the pad PAD may be exposed through the opening portion SOP of the first substrate SUB1. The pad PAD may electrically connect the flexible film FPCB to the first connection line CWL1. The pad PAD may be electrically connected to the lead electrode LDE of the flexible film FPCB through the contact portion CTP. The pad PAD may be composed of a single layer or a multilayer including at least one of molybdenum (Mo), aluminum (Al), chromium (Cr), gold (Au), silver (Ag), titanium (Ti), nickel (Ni), palladium (Pd), indium (In), neodymium (Nd), and copper (Cu).

[0125] The second blocking insulating layer BIL2 may be disposed on the pad PAD. The second blocking insulating layer BIL2 may include a second contact hole CNT2 into which the first connection line CWL1 is inserted. During the process of manufacturing the display device 10, the upper surface of the pad PAD may be exposed through the second contact hole CNT2. The second blocking insulating layer BIL2 may include a first portion BIL2a, a second portion BIL2b, and a third portion BIL2c.

[0126] For example, the first portion BIL2a of the second barrier insulating layer BIL2 may be directly disposed on the upper surface of the pad PAD disposed on the first barrier insulating layer BIL1. The first portion BIL2a of the second barrier insulating layer BIL2 may include a second contact hole CNT2. The second portion BIL2b of the second barrier insulating layer BIL2 may be directly disposed on the upper surface of the pad PAD inserted into the first contact hole CNT1. The second portion BIL2b of the second barrier insulating layer BIL2 may overlap with the first contact hole CNT1. The third portion BIL2c of the second barrier insulating layer BIL2 may not overlap with the pad PAD. There may be a level difference between the first portion BIL2a and the second portion BIL2b of the second barrier insulating layer BIL2. There may be a level difference between the first portion BIL2a and the third portion BIL2c of the second barrier insulating layer BIL2. The level difference of the second barrier insulating layer BIL2 may be determined by the structure of the pad PAD and the first contact hole CNT1. The height of the first portion BIL2a of the second blocking insulating layer BIL2 may be greater than the height of each of the second portion BIL2b and the third portion BIL2c. The height of the second blocking insulating layer BIL2 may be measured from the first substrate SUB1 (eg, an upper surface).

[0127] The third blocking insulating layer BIL3 may be disposed on the second blocking insulating layer BIL2. A portion of the third blocking insulating layer BIL3 may overlap with the first contact hole CNT1, and another portion of the third blocking insulating layer BIL3 may not overlap with the pad PAD. The third blocking insulating layer BIL3 may be disposed on the second portion BIL2b and the third portion BIL2c of the second blocking insulating layer BIL2, and may not be disposed on the first portion BIL2a of the second blocking insulating layer BIL2. For example, the third blocking insulating layer BIL3 may include, but is not limited to, amorphous silicon (a-Si). The third blocking insulating layer BIL3 may absorb light during an alignment process for an optical process. For example, the third blocking insulating layer BIL3 may absorb light having a wavelength of about 600 nm or greater, but the wavelength range is not limited thereto. Therefore, during the alignment process, the portion of the pad PAD that does not overlap with the third blocking insulating layer BIL3 may be easily identified.

[0128] The coating layer SLP may coat the upper surface of the third barrier insulating layer BIL3. During the process of manufacturing the display device 10, the coating layer SLP may protect the third barrier insulating layer BIL3 disposed on the second portion BIL2b and the third portion BIL2c of the second barrier insulating layer BIL2. Therefore, the third barrier insulating layer BIL3 may not be disposed on the first portion BIL2a of the second barrier insulating layer BIL2, but may be disposed on the second portion BIL2b and the third portion BIL2c. For example, the coating layer SLP may include an organic material such as a polyimide resin, an acrylic resin, and a cardo resin. The solid content in the organic solution forming the coating layer SLP may be equal to or less than about 5wt%.

[0129] The second substrate SUB2 may be disposed on the coating layer SLP and the second barrier insulating layer BIL2. A portion of the second substrate SUB2 may be directly disposed on the first portion BIL2a of the second barrier insulating layer BIL2, and another portion of the second substrate SUB2 may be directly disposed on the coating layer SLP. The second substrate SUB2 may be a base substrate or a base member. The second substrate SUB2 may be a flexible substrate that can be bent, folded, or curled. For example, the second substrate SUB2 may include, but is not limited to, an insulating material such as a polymer resin (e.g., polyimide (PI)).

[0130] The gate insulator GI may be disposed on the second substrate SUB2, and the interlayer dielectric layer ILD may be disposed on the gate insulator GI. The interlayer dielectric layer ILD, the gate insulator GI, the second substrate SUB2, and the first portion BIL2a of the second blocking insulating layer BIL2 may include a second contact hole CNT2. The second contact hole CNT2 may be etched from the upper surface of the interlayer dielectric layer ILD and penetrate to the lower surface of the first portion BIL2a of the second blocking insulating layer BIL2. Therefore, the second contact hole CNT2 may not overlap with the third blocking insulating layer BIL3 and the coating layer SLP. During the process of forming the second contact hole CNT2, the upper surface of the pad PAD may be exposed.

[0131] The first connection line CWL1 may be disposed on the interlayer dielectric layer ILD. The first connection line CWL1 may include the same material as the first source metal layer SDL1 of the display area DA and may be formed in the same process. A portion of the first connection line CWL1 may be inserted into the second contact hole CNT2 and may contact the upper surface of the pad PAD. Another portion of the first connection line CWL1 may penetrate the interlayer dielectric layer ILD and may contact the second connection line CWL2. The first connection line CWL1 may electrically connect the pad PAD with the second connection line CWL2. The first connection line CWL1 may provide a data voltage or a power voltage received from the pad PAD to the second connection line CWL2.

[0132] The second connection line CWL2 may be disposed on the gate insulator GI. The second connection line CWL2 may include the same material as the gate layer GTL of the display area DA and may be formed in the same process. The second connection line CWL2 may provide a data voltage received from the first connection line CWL1 to the data line DL and may provide a power voltage received from the first connection line CWL1 to the voltage line VL. For example, the second connection line CWL2 may correspond to Figure 5 The signal line SL in the circuit may be electrically connected to the signal line SL.

[0133] The encapsulation layer TFEL may include a first encapsulation layer TFE1 , a second encapsulation layer TFE2 , and a third encapsulation layer TFE3 .

[0134] The first encapsulation layer TFE1 may be disposed on the emission material layer EML. The first encapsulation layer TFE1 may include an inorganic material to prevent oxygen or moisture from penetrating into the emission material layer EML. The first encapsulation layer TFE1 may extend beyond the display area DA and the dam DAM to the crack prevention member CDM. For example, the first encapsulation layer TFE1 may include but is not limited to at least one of a silicon nitride layer, a silicon oxynitride layer, a silicon oxide layer, a titanium oxide layer, an aluminum oxide layer, and an amorphous silicon layer.

[0135] The second encapsulation layer TFE2 may be disposed on the first encapsulation layer TFE1. The second encapsulation layer TFE2 may include an organic material to protect the emission material layer EML from impurities such as dust. The second encapsulation layer TFE2 may extend beyond the display area DA to the dam DAM. The second encapsulation layer TFE2 may be formed by filling an area surrounded by the dam DAM. For example, the second encapsulation layer TFE2 may include an organic film such as an acrylic resin, an epoxy resin, a phenolic resin, a polyamide resin, and a polyimide resin. The second encapsulation layer TFE2 may be formed by curing a monomer or applying a polymer.

[0136] The third encapsulation layer TFE3 may be disposed on the second encapsulation layer TFE2. The third encapsulation layer TFE3 may include an inorganic material to prevent oxygen or moisture from penetrating into the emission material layer EML. The third encapsulation layer TFE3 may extend beyond the display area DA and the dam DAM to the crack prevention member CDM. The third encapsulation layer TFE3 may be disposed on the second encapsulation layer TFE2 on the inner side of the dam DAM, and may be disposed on the first encapsulation layer TFE1 on the inner side of the crack prevention member CDM. For example, the third encapsulation layer TFE3 may be made of the materials listed above as the materials of the first encapsulation layer TFE1.

[0137] The dam DAM may surround the display area DA. The dam DAM may include the same material as the pixel defining layer PDL and may be formed in the same process. The dam DAM may have a selectable height so that the second encapsulation layer TFE2 including an organic material does not overflow the dam DAM.

[0138] The antistatic circuit ESD may be provided between the display area DA and the crack prevention member CDM. The antistatic circuit ESD may include at least one transistor. The antistatic circuit ESD may be electrically connected to the second connection line CWL2. Therefore, the antistatic circuit ESD may prevent external static electricity from flowing into the display area DA through the second connection line CWL2.

[0139] The crack preventing member CDM may surround the dam DAM. The crack preventing member CDM may be disposed at the outermost position of the display panel 100 to prevent cracks in the display panel 100. The first and third encapsulation layers TFE1 and TFE3 and the overcoat layer OC may be formed in a region surrounded by the crack preventing member CDM.

[0140] The crack prevention member CDM may include a first layer LAY1, a second layer LAY2, and a third layer LAY3. The first layer LAY1 of the crack prevention member CDM may cover the upper surface of the first connection wire CWL1 inserted into the second contact hole CNT2. The second contact hole CNT2 may be filled with the first layer LAY1, so that the level difference may be reduced. The first layer LAY1 may include the same material as the first via layer VIA1 and may be formed in the same process.

[0141] The second layer LAY2 of the crack prevention member CDM may be disposed on the first layer LAY1. The second layer LAY2 may include the same material as the second via layer VIA2, and may be formed in the same process.

[0142] The third layer LAY3 of the crack preventing member CDM may be disposed on the second layer LAY2. The third layer LAY3 may include the same material as the pixel defining layer PDL, and may be formed in the same process.

[0143] The flexible film FPCB may be disposed under (or below) the first substrate SUB1. One side or one side of the flexible film FPCB may be inserted into the opening portion SOP of the first substrate SUB1 and electrically connected to the pad PAD. The flexible film FPCB may include a lead electrode LDE disposed on one side or one side of the upper surface and inserted into the opening portion SOP. The lead electrode LDE may protrude from one side or one side of the flexible film FPCB, and the protruding portion of the lead electrode LDE may not overlap with the flexible film FPCB. The lead electrode LDE may be attached to the pad PAD and the lower surface of the first barrier insulating layer BIL1 through an adhesive portion ADM. The lead electrode LDE may be electrically connected to the pad PAD through a contact portion CTP.

[0144] The flexible film FPCB may support a display driver DIC disposed on a lower surface on the opposite side. The lead electrode LDE may be electrically connected to the display driver DIC through a lead (not shown) disposed on the lower surface of the flexible film FPCB. The other side of the flexible film FPCB may be connected to a source circuit board (not shown) under (or below) the first substrate SUB1. The flexible film FPCB may transmit signals and voltages from the display driver DIC to the display device 10. The flexible film FPCB may provide a scan control signal to the scan driver SIC.

[0145] The display driver DIC may be mounted on the flexible film FPCB. The display driver DIC may be an integrated circuit (IC). The display driver DIC may convert digital video data into an analog data voltage based on a data control signal from a timing controller (not shown), and may provide it to the data line DL in the display area DA through the flexible film FPCB. The display driver DIC may provide a power voltage received from a power supply unit (not shown) to a voltage line VL in the display area DA through the flexible film FPCB. Since the display device 10 may include a pad PAD disposed on the first substrate SUB1 and a flexible film FPCB and a display driver DIC disposed under (or below) the first substrate SUB1, the non-display area NDA may be reduced.

[0146] The contact portion CTP may cover the lower surface of the lead electrode LDE protruding from the flexible film FPCB and the lower surface of the pad PAD exposed through the opening portion SOP. The contact portion CTP may electrically connect the lead electrode LDE with the pad PAD and may stably fix the lead electrode LDE to the lower surface of the pad PAD.

[0147] For example, the contact portion CTP can be formed by low temperature sintering of a conductive ink containing nanoparticles and a polymer. The nanoparticles may include nanoscale metal particles such as silver (Ag), copper (Cu), aluminum (Al) and chromium (Cr), and the polymer may include an acrylic resin or an epoxy resin. However, it should be understood that the present disclosure is not limited thereto. The conductive ink may include a polymer as an adhesive for connecting metal particles. The nanoparticles may be brought closer to each other and aggregated via a sintering process. The contact portion CTP comprising sintered nanoparticles may have conductivity.

[0148] For another example, the contact portion CTP may be formed by low temperature sintering of metal organic decomposition ink (MOD Ink). The metal organic decomposition ink may contain liquid metal organic decomposition substances smaller than nanoparticles. The liquid metal organic decomposition substances may be converted into metal substances via a sintering process. Therefore, the contact portion CTP may have conductivity.

[0149] The contact portion CTP can be formed by printing conductive ink or metal paste on the opening portion SOP of the first substrate SUB1 using a silicone pad and sintering it using an intense pulsed light (IPL) or laser. During the sintering process, metal particles are brought close to each other and aggregated by the heat from the light pulse or laser, thereby reducing the resistance of the contact portion CTP.

[0150] The manufacturing process of the display device 10 may be simplified by electrically connecting the lead electrode LDE with the pad PAD using a contact portion of a metal paste without using ultrasonic bonding or thermocompression bonding, thereby saving manufacturing time and cost.

[0151] Figures 8 to 16 2 is a schematic cross-sectional view showing a process step of manufacturing a display device according to an embodiment.

[0152] exist Figure 8 In the embodiment, the first substrate SUB1 may support the display device 10. The first substrate SUB1 may be a base substrate or a base member.

[0153] A first blocking insulating layer BIL1 may be disposed on the first substrate SUB1. The first blocking insulating layer BIL1 may include an inorganic film capable of preventing air or moisture from penetrating. The first blocking insulating layer BIL1 may include a first contact hole CNT1.

[0154] A pad PAD may be provided on the first blocking insulating layer BIL1 in the pad area PDA. The pad PAD may be inserted into the first contact hole CNT1 formed in the first blocking insulating layer BIL1.

[0155] An alignment key KEY may be provided on the first blocking insulating layer BIL1 in the key area KA. The alignment key KEY may be used in an alignment process for an optical process. The easier the alignment key KEY is identified, the more accurately the alignment process may be performed, and the more accurately the optical process may be performed. The alignment key KEY may include the same material as the pad PAD, and may be formed in the same process.

[0156] A second blocking insulating layer BIL2 may be disposed on the pad PAD and the align key KEY. The second blocking insulating layer BIL2 may include an inorganic film capable of preventing air or moisture from penetrating. The second blocking insulating layer BIL2 may include a first portion BIL2a, a second portion BIL2b, and a third portion BIL2c.

[0157] For example, the first portion BIL2a of the second barrier insulating layer BIL2 may be directly disposed on the upper surface of the pad PAD and the alignment key KEY disposed on the first barrier insulating layer BIL1. The second portion BIL2b of the second barrier insulating layer BIL2 may be directly disposed on the upper surface of the pad PAD inserted into the first contact hole CNT1. The second portion BIL2b of the second barrier insulating layer BIL2 may overlap with the first contact hole CNT1. The third portion BIL2c of the second barrier insulating layer BIL2 may not overlap with the pad PAD or the alignment key KEY. There may be a level difference between the first portion BIL2a and the second portion BIL2b of the second barrier insulating layer BIL2. There may be a level difference between the first portion BIL2a and the third portion BIL2c of the second barrier insulating layer BIL2. The level difference of the second barrier insulating layer BIL2 may be determined by the structure of the pad PAD, the alignment key KEY and the first contact hole CNT1. The height of the first portion BIL2a of the second blocking insulating layer BIL2 may be greater than the height of each of the second portion BIL2b and the third portion BIL2c. The height of the second blocking insulating layer BIL2 may be measured from the first substrate SUB1.

[0158] exist Fig. 9 In the embodiment, a third blocking insulating layer BIL3 may be disposed on the second blocking insulating layer BIL2. The third blocking insulating layer BIL3 may be disposed on the entire surface of the second blocking insulating layer BIL2.

[0159] exist Fig.10In the embodiment of the present invention, the coating layer SLP may coat the upper surface of the third barrier insulating layer BIL3. For example, the coating layer SLP may include an organic material such as a polyimide resin, an acrylic resin, and a cardo resin. The solid content in the organic solution forming the coating layer SLP may be equal to or less than about 5wt%. The coating layer SLP may have fluidity and thus may flow downward due to the level difference of the second barrier insulating layer BIL2. Therefore, the coating layer SLP may be relatively thinly coated at a position where the coating layer SLP overlaps with the first portion BIL2a of the second barrier insulating layer BIL2, and may be relatively thickly coated at a position where the coating layer SLP overlaps with the second portion BIL2b and the third portion BIL2c of the second barrier insulating layer BIL2.

[0160] exist Fig.11 In the embodiment, since the coating layer SLP overlapping the first portion BIL2a of the second barrier insulating layer BIL2 is relatively thinly coated, it can be etched via the first etching process. Since the coating layer SLP overlapping the second portion BIL2b and the third portion BIL2c of the second barrier insulating layer BIL2 is relatively thickly coated, it can be left even after the first etching process (first etching process). For example, the first etching process may be, but is not limited to, a dry etching process for etching an organic film. The third barrier insulating layer BIL3 may be exposed at a position where the coating layer SLP has been removed.

[0161] exist Fig.12 In the embodiment of the present invention, the third blocking insulating layer BIL3 exposed by the first etching (first etching) process may be etched by the second etching (second etching) process. The third blocking insulating layer BIL3 disposed on the first portion BIL2a of the second blocking insulating layer BIL2 may be etched, while the third blocking insulating layer BIL3 disposed on the second portion BIL2b and the third portion BIL2c may be protected by the coating layer SLP and may not be etched. Therefore, the first portion BIL2a of the second blocking insulating layer BIL2 may be exposed. For example, the second etching process may be, but is not limited to, a dry etching process for etching an inorganic film.

[0162] When the first portion BIL2a of the second blocking insulating layer BIL2 is exposed, the alignment key KEY may not overlap with the third blocking insulating layer BIL3. The third blocking insulating layer BIL3 may absorb light during an alignment process for an optical process. For example, the third blocking insulating layer BIL3 may absorb light having a wavelength of 600nm or more, but the wavelength range is not limited thereto. Therefore, during the alignment process, the alignment key KEY that does not overlap with the third blocking insulating layer BIL3 may be easily identified. Since the optical process may be accurately performed, the reliability of the display device 10 may be improved.

[0163] exist Fig.13In the present invention, a second substrate SUB2 may be disposed on the coating layer SLP and the second barrier insulating layer BIL2. A portion of the second substrate SUB2 may be directly disposed on the first portion BIL2a of the second barrier insulating layer BIL2, and another portion of the second substrate SUB2 may be directly disposed on the coating layer SLP. The second substrate SUB2 may be a base substrate or a base member. The second substrate SUB2 may be a flexible substrate that can be bent, folded, or curled. For example, the second substrate SUB2 may include, but is not limited to, an insulating material such as a polymer resin (e.g., polyimide (PI)).

[0164] A gate insulator GI may be disposed on the second substrate SUB2 , and an interlayer dielectric layer ILD may be disposed on the gate insulator GI.

[0165] exist Fig.14 In the embodiment of the present invention, one surface or one surface of the first substrate SUB1 may be etched to form an opening portion SOP. At least one of a wet etching process, a dry etching process, a plasma etching process, and a laser etching process may be performed on the surface of the first substrate SUB1. Since the opening portion SOP is formed in the first substrate SUB1, the pad PAD may be exposed. One opening portion SOP may expose the pad PAD, but the present disclosure is not limited thereto.

[0166] The pad area PDA and the key area KA may be cut along a cutting line and separated from each other. During a process of manufacturing the display device 10, after an optical process is completed, the key area KA may be removed.

[0167] exist Fig.15 In the embodiment, the lead electrode LDE may be inserted into the opening portion SOP of the first substrate SUB1. The lead electrode LDE may be attached to the lower surface of the pad PAD through the adhesive portion ADM.

[0168] exist Fig.16 In the embodiment, the contact portion CTP may cover the lower surface of the lead electrode LDE and the lower surface of the pad PAD. The lead electrode LDE may be electrically connected to the pad PAD through the contact portion CTP. Fig.16 In the embodiment of the present invention, the contact portion CTP and the pad PAD are not in direct contact with each other, but in other schematic cross-sectional views, the contact portion CTP and the pad PAD may be in direct contact with each other, such as Figure 6 and Figure 7 as shown in .

[0169] Conductive ink may be applied on the lead electrode LDE and the pad PAD. The conductive ink may contain nanoparticles and polymers. The contact portion CTP may be formed by low temperature sintering of the conductive ink.

[0170] The sintered conductive ink, metal paste or metal organic decomposition ink can cover the pad PAD and the lead electrode LDE inserted into the single opening portion SOP at one time. The contact portions CTP can be separated from each other via a laser patterning process. Adjacent contact portions CTP can be spaced apart from each other. One contact portion CTP can electrically connect one pad PAD to the lead electrode LDE.

[0171] Therefore, in the display device 10, the lead electrode LDE and the pad PAD are electrically connected through the contact portion CTP, so that the lead electrode LDE of the flexible film FPCB can be electrically connected to the pad PAD without using ultrasonic bonding or thermocompression bonding. By simplifying the manufacturing process of the display device 10, manufacturing time and cost can be saved.

[0172] A cover layer CRD may be disposed on the contact portion CTP to protect the contact portion CTP. The cover layer CRD may include an organic film such as acrylic resin, epoxy resin, phenolic resin, polyamide resin, and polyimide resin. The cover layer CRD may be formed by curing a monomer or applying a polymer.

[0173] Embodiments have been disclosed herein, and although terms are used, they are used and are to be interpreted in a general and descriptive sense only and not for purposes of limitation. In some cases, as will be apparent to one of ordinary skill in the art, features, characteristics, and / or elements described in conjunction with embodiments may be used alone or in combination with features, characteristics, and / or elements described in conjunction with other embodiments, unless otherwise specifically indicated. Therefore, one of ordinary skill in the art will understand that various changes in form and detail may be made without departing from the spirit and scope of the present disclosure and as set forth in the appended claims.

Claims

1. A display device, comprising: A first substrate including an opening portion; A first blocking insulating layer, disposed on the first substrate, wherein the first blocking insulating layer comprises a first contact hole; a pad having a portion disposed on the first blocking insulating layer and another portion inserted into the first contact hole; a second blocking insulating layer including a first portion disposed on an upper surface of the portion of the pad and a second portion disposed on an upper surface of the other portion of the pad; a third blocking insulating layer, disposed on the second portion of the second blocking insulating layer; A coating layer, disposed on the third barrier insulating layer; a second substrate disposed on the coating layer and the first portion of the second blocking insulating layer; a first connection line, disposed on the second substrate and electrically connected to the pad; as well as A flexible film includes a lead electrode inserted into the opening portion of the first substrate.

2. The display device according to claim 1, wherein: The third blocking insulating layer absorbs light, and The coating comprises an organic material.

3. The display device according to claim 1, wherein: A height of the first portion of the second blocking insulating layer from an upper surface of the first substrate is greater than a height of the second portion of the second blocking insulating layer from the upper surface of the first substrate.

4. The display device according to claim 1, wherein: The second blocking insulating layer further includes a third portion that does not overlap with the pad, and The third blocking insulating layer and the coating layer are disposed on the third portion of the second blocking insulating layer.

5. The display device according to claim 4, wherein: A height of the first portion of the second blocking insulating layer from an upper surface of the first substrate is greater than a height of the third portion of the second blocking insulating layer from the upper surface of the first substrate.

6. The display device according to claim 1, wherein: The first connection line is inserted into a second contact hole formed in the second substrate and the first portion of the second blocking insulating layer.

7. The display device according to claim 1, further comprising: a gate insulator, disposed on the second substrate; a second connection line, disposed on the gate insulator and electrically connected to the first connection line; as well as An interlayer dielectric layer is provided in a layer between the second connection line and the first connection line.

8. The display device according to claim 1, further comprising: A contact portion covers a lower surface of the lead electrode and a lower surface of the pad to electrically connect the lead electrode to the pad.

9. The display device according to claim 8, wherein: The contact portion is sintered from a metal organic decomposition ink, a conductive ink or a metal paste containing silver, copper, aluminum or chromium.

10. The display device according to claim 1, wherein: The lead electrode is disposed on a lower surface of the pad through an adhesive portion.

11. A method for manufacturing a display device, the method comprising: preparing a first substrate; forming a first blocking insulating layer including a first contact hole on the first substrate; forming a pad in a pad region of the first substrate, a portion of the pad being disposed on the first blocking insulating layer, and another portion of the pad being inserted into the first contact hole; forming an alignment key on the first blocking insulating layer in a key region of the first substrate; forming a second blocking insulating layer, the second blocking insulating layer including a first portion disposed on an upper surface of the portion of the pad and an upper surface of the alignment key, and a second portion disposed on an upper surface of the other portion of the pad; forming a third blocking insulating layer on the first portion and the second portion of the second blocking insulating layer; forming a coating layer on the third barrier insulating layer; etching the coating disposed on the first portion of the second blocking insulating layer; as well as The third blocking insulating layer disposed on the first portion of the second blocking insulating layer is etched.

12. The method according to claim 11, wherein: Forming the coating comprises: A fluid organic solution is provided on the third barrier insulating layer such that a thickness of the coating disposed on the first portion of the second barrier insulating layer is less than a thickness of the coating disposed on the second portion of the second barrier insulating layer.

13. The method according to claim 12, wherein: Etching the coating comprises: The coating layer disposed on the first portion of the second blocking insulating layer is etched to expose the third blocking insulating layer while leaving the coating layer disposed on the second portion of the second blocking insulating layer.

14. The method according to claim 13, wherein: Etching the third blocking insulating layer includes: The exposed third blocking insulating layer on the first portion of the second blocking insulating layer is etched, and the remaining coating layer protects the third blocking insulating layer on the second portion of the second blocking insulating layer.

15. The method according to claim 14, wherein: Etching the third blocking insulating layer further includes: exposing the first portion of the second blocking insulating layer.

16. The method according to claim 15, further comprising: forming a second substrate on the coating layer and the first portion of the second blocking insulating layer; forming a second contact hole penetrating the second substrate and the first portion of the second blocking insulating layer to expose the pad; as well as A first connection line is formed, the first connection line being disposed on the second substrate and inserted into the second contact hole, the first connection line being electrically connected to the pad.

17. The method according to claim 16, further comprising: The alignment key is separated by cutting along a cutting line between the pad area and the key area.

18. The method according to claim 16, further comprising: An opening portion of the first substrate is formed by etching a lower portion of the first substrate to expose the pad.

19. The method according to claim 18, further comprising: A flexible film is inserted into the opening portion to place a lead electrode of the flexible film on a lower surface of the pad.

20. The method according to claim 19, further comprising: The lead electrode is electrically connected to the pad through a contact portion.

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