Display panel, manufacturing method thereof and display device

Abstract

The invention provides a display panel, a manufacturing method thereof and a display device, and relates to the technical field of display, the display panel comprises a substrate and an array layer, the array layer is located on one side of the substrate, the array layer comprises a first semiconductor layer, a first metal layer and a second metal layer, the first metal layer is located on the side, away from the substrate, of the first semiconductor layer, and the second metal layer is located on the side, away from the substrate, of the second semiconductor layer; the second metal layer is located on the side, away from the substrate, of the first metal layer; the array layer comprises a first transistor, a first active layer of the first transistor is located on the first semiconductor layer, and a first pole and a second pole of the first transistor are located on the second metal layer; the first active layer comprises a main body part, a first lug boss and a second lug boss, the first lug boss and the second lug boss are positioned on one side, facing the second metal layer, of the main body part and are in contact with the main body part, the first pole is electrically connected with the first lug boss through the first connecting hole, and the second pole is electrically connected with the second lug boss through the second connecting hole. Therefore, the manufacturing process is simplified, and the production cost is reduced.

Description

Technical Field

[0001] The present disclosure relates to the field of display technology, and in particular to a display panel and a manufacturing method thereof, and a display device. Background Art

[0002] With the continuous development of science and technology, more and more display products, such as mobile phones, tablets, laptops and smart wearable devices, are widely used in people's daily life and work, bringing great convenience to people's daily life and work, and becoming an indispensable tool for people today.

[0003] At this stage, how to simplify the manufacturing process of display products and reduce production costs has become one of the technical problems that need to be solved urgently. Summary of the invention

[0004] In order to solve the above technical problems, the present disclosure provides a display panel and a manufacturing method thereof, and a display device, aiming to simplify the manufacturing process and reduce production costs.

[0005] In a first aspect, the present disclosure provides a display panel, comprising a substrate and an array layer, wherein the array layer is located on one side of the substrate, the array layer comprises a first semiconductor layer, a first metal layer, and a second metal layer, wherein the first metal layer is located on a side of the first semiconductor layer away from the substrate, and the second metal layer is located on a side of the first metal layer away from the substrate;

[0006] The array layer includes a first transistor, a first active layer of the first transistor is located in the first semiconductor layer, and a first pole and a second pole of the first transistor are located in the second metal layer; the first active layer includes a main body, a first protruding portion and a second protruding portion, the first protruding portion and the second protruding portion are located on a side of the main body facing the second metal layer and in contact with the main body, the first pole is electrically connected to the first protruding portion through a first connecting hole, and the second pole is electrically connected to the second protruding portion through a second connecting hole.

[0007] In a second aspect, the present disclosure provides a method for manufacturing a display panel, comprising:

[0008] providing a substrate;

[0009] Forming a first sublayer in the first semiconductor layer on one side of the substrate, and forming a second sublayer in the first semiconductor layer on a side of the first sublayer facing away from the substrate;

[0010] Removing at least a portion of the first sublayer and the second sublayer to form a first active layer of the first transistor, wherein the first active layer includes a main body portion located in the first sublayer and a first convex portion and a second convex portion located in the second sublayer;

[0011] forming a gate insulating layer on a side of the second sub-layer facing away from the substrate;

[0012] Fabricating a first metal layer on a side of the gate insulating layer facing away from the substrate, and forming a gate of a first transistor on the first metal layer;

[0013] forming an interlayer insulating layer on a side of the first metal layer facing away from the substrate;

[0014] Using the first protrusion and the second protrusion as alignment structures, forming a first connection hole and a second connection hole on the interlayer insulating layer and the gate insulating layer, so that the first connection hole exposes the first protrusion, and the second connection hole exposes the second protrusion;

[0015] A second metal layer is fabricated on a side of the interlayer insulating layer away from the substrate to form a first electrode and a second electrode of the first transistor, so that the first electrode is electrically connected to the first protrusion through the connection hole, and the second electrode is electrically connected to the second protrusion through the connection hole.

[0016] In a third aspect, the present disclosure provides a display device, comprising the display panel provided in the first aspect of the present disclosure.

[0017] Compared with the prior art, the technical solution provided by the embodiments of the present disclosure has the following advantages:

[0018] In the display panel and its manufacturing method and display device provided by the present disclosure, the first active layer of the first transistor in the array layer includes a main body and a first protrusion and a second protrusion located on the same side of the main body and in contact with the main body, and the first electrode and the second electrode of the first transistor are electrically connected to the first protrusion and the second protrusion through the first connection hole and the second connection hole, respectively. When the main body, the first protrusion and the second protrusion are introduced into the first active layer, the carrier concentration of the first protrusion and the second protrusion and the main body can be designed differently, so that the carrier concentration of the first protrusion and the second protrusion is higher than the carrier concentration of the main body. In this way, there is no need to introduce an ion implantation process to change the resistivity of the source region and the drain region in the first active layer, thereby eliminating the ion implantation process in the production process and avoiding increasing the investment in equipment required for the ion implantation process, which is conducive to simplifying the process of display products and reducing production costs. BRIEF DESCRIPTION OF THE DRAWINGS

[0019] The accompanying drawings, which are incorporated in and constitute a part of this specification, illustrate embodiments consistent with the present disclosure and, together with the description, serve to explain the principles of the present disclosure.

[0020] In order to more clearly illustrate the embodiments of the present invention or the technical solutions in the prior art, the drawings required for use in the embodiments or the description of the prior art will be briefly introduced below. Obviously, for ordinary technicians in this field, other drawings can be obtained based on these drawings without paying any creative labor.

[0021] Figure 1 Shown is a schematic plan view of a display panel provided by an embodiment of the present disclosure;

[0022] Figure 2 Shown Figure 1 An AA cross-sectional view of the display panel;

[0023] Figure 3 Shown is a schematic diagram of a connection between an array layer and a light-emitting element provided in an embodiment of the present disclosure;

[0024] Figure 4 Shown Figure 1 Another AA cross-sectional view of the display panel shown;

[0025] Figure 5 Shown is a top view of a first transistor in an embodiment of the present disclosure;

[0026] Figure 6 Shown Figure 1 Another AA cross-sectional view of the display panel;

[0027] Figure 7 FIG. 1 is a schematic diagram showing a structure of a pixel driving circuit in a display panel provided by an embodiment of the present disclosure;

[0028] Figure 8 Shown Figure 7 A working timing diagram of a pixel driving circuit;

[0029] Fig. 9 FIG. 1 is a schematic diagram of a structure of a driving transistor in an embodiment of the present disclosure;

[0030] Fig.10 A schematic diagram of the structure of a threshold compensation transistor or a first reset transistor in an embodiment of the present disclosure is shown;

[0031] Fig.11 Shown with Fig.10 The first transistor in the figure corresponds to a top view;

[0032] Fig.12 FIG. 2 is another schematic diagram of the structure of a pixel driving circuit provided in an embodiment of the present disclosure;

[0033] Fig.13 Shown Figure 1Another AA cross-sectional view of the display panel;

[0034] Fig.14 Shown is a schematic diagram of a film layer forming a capacitor in a display panel in the related art;

[0035] Fig.15 Shown Figure 1 Another AA cross-sectional view of the display panel;

[0036] Fig.16 Shown Fig.15 A connection diagram of a capacitor in FIG.

[0037] Fig.17 Shown is a flow chart of a method for manufacturing a display panel provided by an embodiment of the present disclosure;

[0038] Fig.18 FIG. 1 is a schematic structural diagram of manufacturing a first semiconductor layer in a method for manufacturing a display panel provided in an embodiment of the present disclosure;

[0039] Fig.19 FIG. 1 is a schematic diagram showing a structure of forming a first protruding portion and a second protruding portion in a method for manufacturing a display panel provided in an embodiment of the present disclosure;

[0040] Fig. 20 The figure shows a structural schematic diagram of making a deleted insulating layer;

[0041] Fig.21 Shown is a schematic diagram of a structure for making a first metal layer;

[0042] Fig. 22 The figure shows a structural schematic diagram of manufacturing an interlayer insulating layer;

[0043] Fig.23 Shown is a schematic diagram of a structure for making a first connecting hole and a second connecting hole;

[0044] Fig.24 Shown is a schematic diagram of a structure for making a first pole and a second pole;

[0045] Fig.25 FIG. 1 is a schematic diagram of manufacturing a first protruding portion and a second protruding portion in a method for manufacturing a display panel provided in an embodiment of the present disclosure;

[0046] Fig.26 Another schematic diagram of manufacturing the first protruding portion and the second protruding portion in the manufacturing method of the display panel provided by the embodiment of the present disclosure is shown;

[0047] Fig. 27 Shown is a schematic structural diagram of a display device provided in an embodiment of the present disclosure. DETAILED DESCRIPTION

[0048] In order to more clearly understand the above-mentioned objectives, features and advantages of the present disclosure, the scheme of the present disclosure will be further described below. It should be noted that the embodiments of the present disclosure and the features in the embodiments can be combined with each other without conflict.

[0049] In the following description, many specific details are set forth to facilitate a full understanding of the present disclosure, but the present disclosure may also be implemented in other ways different from those described herein; it is obvious that the embodiments in the specification are only part of the embodiments of the present disclosure, rather than all of the embodiments.

[0050] Figure 1 FIG. 1 is a schematic plan view of a display panel 100 provided in an embodiment of the present disclosure. Figure 2 Shown Figure 1 An AA cross-sectional view of the display panel 100 is shown in FIG. Figure 1 and Figure 2 , the embodiment of the present disclosure provides a display panel 100, including:

[0051] A substrate 00 and an array layer 10, wherein the array layer 10 is located on one side of the substrate 00, and the array layer 10 includes a first semiconductor layer 20, a first metal layer m1, and a second metal layer m2, wherein the first metal layer m1 is located on a side of the first semiconductor layer 20 facing away from the substrate 00, and the second metal layer m2 is located on a side of the first metal layer m1 facing away from the substrate 00;

[0052] The array layer 10 includes a first transistor T0, a first active layer P1 of the first transistor T0 is located in the first semiconductor layer 20, and a first pole J1 and a second pole J2 of the first transistor T0 are located in the second metal layer m2; the first active layer P1 includes a main body B0, a first protruding portion B1 and a second protruding portion B2, the first protruding portion B1 and the second protruding portion B2 are located on a side of the main body B0 facing the second metal layer m2 and are in contact with the main body B0, the first pole J1 is electrically connected to the first protruding portion B1 through a first connecting hole K1, and the second pole J2 is electrically connected to the second protruding portion B2 through a second connecting hole K2.

[0053] It should be noted that Figure 1 The display panel with a rectangular structure is only taken as an example for description, and the actual shape of the display panel is not limited. In some other embodiments of the present disclosure, the display panel may also be embodied in any other feasible shape such as a circle, a rounded rectangle, etc. Figure 1The embodiment illustrates the connection between the pixel driving circuit 00 and the light emitting element 30 in the display panel, but does not limit the number and arrangement of the pixel driving circuit 00 and the light emitting element 30 actually included in the display panel. Optionally, the display panel provided in this embodiment can be a display panel using organic light emitting diode display technology, that is, an OLED (Organic Light-Emitting Diode) display panel, for example, please refer to Figure 3 , Figure 3 FIG. 1 is a schematic diagram showing a connection between the array layer 10 and the light emitting element provided in an embodiment of the present disclosure. Figure 2 The difference is Figure 3 The connection between the array layer 10 and the light-emitting element is illustrated. The display panel includes a light-emitting element 30 and an array layer 10 connected to the light-emitting element 30. This embodiment is described by taking the light-emitting element 30 and part of the first transistor T0 in the array layer 10 as an example. The basic structure of the light-emitting element 30 of the OLED display panel includes an anode 301, a light-emitting material layer 302 and a cathode 303. When the power supply supplies an appropriate voltage, the holes generated by the anode 301 and the electrons generated by the cathode 303 will combine in the light-emitting material layer 302 to generate bright light. Compared with liquid crystal displays, OLED display panels have the characteristics of high visibility and high brightness, and are more power-saving, light in weight and thin in thickness. Optionally, an encapsulation layer 50 may also be included on the side of the light-emitting element 30 away from the substrate 00 to achieve encapsulation of the light-emitting element. The encapsulation layer 50 may be a combination structure of an organic layer and an inorganic layer, which is not limited in this disclosure. Of course, in some other embodiments of the present invention, the display panel may also be a display panel using inorganic light-emitting diode display technology, such as a Micro LED display panel, or a Mini LED display panel, etc., which is not limited in this disclosure.

[0054] It should also be noted that this embodiment is described by taking the structure of the first transistor T0 included in the display panel as an example, and does not limit the structures of all transistors included in the display panel. In some other embodiments of the present disclosure, all transistors in the array layer 10 can be embodied as the structure shown by the first transistor T0. Of course, in some other embodiments of the present disclosure, some transistors in the array layer 10 can be embodied as the structure shown by the first transistor T0, and some transistors can be embodied as other structures. The present disclosure does not specifically limit this.

[0055] Please continue to refer to Figure 2 and Figure 3In the display panel provided by the embodiment of the present disclosure, the array layer 10 includes a first semiconductor layer 20 and a first metal layer m1 and a second metal layer m2 located on the same side of the first semiconductor layer 20. The first active layer P1 of the first transistor T0 may be located in the aforementioned first semiconductor layer 20, the gate of the first transistor T0 may be located in the aforementioned first metal layer m1, and the first electrode J1 and the second electrode J2 of the first transistor T0 may be located in the aforementioned second metal layer m2.

[0056] In the related art, when manufacturing transistors in the array layer, after the active layer is manufactured, it is usually necessary to introduce ion implantation equipment to implant ions into the source region and the drain region of the active layer, and change the contact resistance of the source region and the drain region in the active layer by ion implantation, so as to realize the electrical connection between the source of the transistor and the source region in the active layer, and realize the electrical connection between the drain of the transistor and the drain region in the active layer. Considering the high cost of ion implantation equipment, the introduction of ion implantation equipment in the manufacturing process of display products greatly increases the manufacturing cost of display products.

[0057] In order to solve the above technical problems, the embodiment of the present disclosure improves the structure of the first active layer P1 of the first transistor T0. For details, please refer to Figure 2 and Figure 3 The first active layer P1 includes a main body B0 and a first protruding portion B1 and a second protruding portion B2 located on the side of the main body B0 away from the substrate 00. The first protruding portion B1 and the second protruding portion B2 are in direct contact with the main body B0. The area where the first protruding portion B1 is located can be regarded as a source area of ​​the first active layer P1, and the area where the second protruding portion B2 is located can be regarded as a drain area of ​​the first active layer P1. Of course, in some other embodiments of the present disclosure, the area where the first protruding portion B1 is located can also be regarded as the drain area of ​​the first active layer P1, and the area where the second protruding portion B2 is located can be regarded as the source area of ​​the first active layer P1. When the first convex part B1 and the second convex part B2 are introduced into the source region and the drain region of the first active layer P1, the carrier concentration of the first convex part B1 and the second convex part B2 can be designed differently from the carrier concentration of the main part B0, for example, the carrier concentration of the first convex part B1 and the second convex part B2 is made higher, so that the first convex part B1 and the second convex part B2 have a better conductive effect, thereby respectively realizing electrical connection with the first electrode J1 and the second electrode J2 in the first transistor T0. In this way, the ion implantation process can be omitted, and there is no need to introduce ion implantation equipment in the process of display panel, thereby avoiding the problems of increased production cost and complicated production process caused by introducing ion implantation equipment for ion implantation process, so it is beneficial to simplify the manufacturing process of display panel and reduce production cost.

[0058] Optionally, the first transistor T0 in the embodiment of the present disclosure is an oxide transistor, and the corresponding first semiconductor layer 20 is an oxide semiconductor layer. When the oxide transistor is introduced into the array layer 10, the leakage current of the oxide transistor is small, which is conducive to improving the output accuracy of the circuit in which the oxide transistor is located. In the first active layer P1, the main body B0, the first protruding portion B1 and the second protruding portion B2 all include oxide materials.

[0059] Please continue to refer to Figure 2 In an optional embodiment of the present disclosure, in the first active layer P1 corresponding to the first transistor T0, the resistivity of the first protrusion B1 and the second protrusion B2 is less than the resistivity of the main body B0. In the actual process, the main body B0 can be made of a conventional active layer material, and the first protrusion B1 and the second protrusion B2 can be made of a material with a lower resistivity. In this way, the first protrusion B1 and the second protrusion B2 will have better conductivity, and the connection between the first protrusion B1 and the first pole J1 and the connection between the second protrusion B2 and the second pole J2 can be achieved without introducing an ion implantation process to change the conductivity of the source region and the drain region of the first active layer P1, thereby simplifying the manufacturing process of the display panel and reducing the production cost.

[0060] In the embodiment of the present disclosure, when the first protrusion B1 and the second protrusion B2 are introduced into the first active layer P1 to achieve electrical connection with the first pole J1 and the second pole J2, the carrier concentration in the first protrusion B1 and the second protrusion B2 is higher than the carrier concentration in the main body B0. At this time, the main body B0 can select at least one of the semiconductor materials such as IGZO, IGZTO, IGO and IZTO, and the first protrusion B1 and the second protrusion B2 can adopt ITO, IZO or IGZO series materials with relatively high In content, thereby reducing the contact resistance between the first protrusion B1 and the first pole J1, and reducing the contact resistance between the second protrusion B2 and the second pole J2, thereby achieving reliable electrical connection between the first pole J1 and the first protrusion B1, and reliable electrical connection between the second pole J2 and the second protrusion B2.

[0061] Figure 4 Shown Figure 1 Another AA cross-sectional view of the display panel shown, please refer to Figure 2 and Figure 4 In an optional embodiment of the present disclosure, the thickness of the first protruding portion B1 is greater than or equal to the thickness of the main body portion B0, and the thickness of the second protruding portion B2 is greater than or equal to the thickness of the main body portion B0.

[0062] Optionally, the first protrusion B1 and the second protrusion B2 have the same thickness, so the first protrusion B1 and the second protrusion B2 can be manufactured with the same process dimensions, which is beneficial to simplifying the overall manufacturing process of the display panel. Figure 2 The illustrated embodiment shows a solution in which the thickness of the first protruding portion B1 and the second protruding portion B2 is equal to the thickness of the main body portion B0. Figure 4 The illustrated embodiment shows a solution in which the thickness of the first protrusion B1 and the second protrusion B2 is greater than the thickness of the main body B0. Within a certain thickness range, the greater the thickness of the first protrusion B1 and the second protrusion B2, the smaller the impedance of the first protrusion B1 and the second protrusion B2 will be. In this embodiment, when the thickness of the first protrusion B1 and the second protrusion B2 is set to be greater than or equal to the thickness of the main body B0, it is beneficial to reduce the impedance of the first protrusion B1 and the second protrusion B2, and improve the electrical connection reliability between the first electrode J1 and the first protrusion B1 and the electrical connection reliability between the second electrode J2 and the second protrusion B2 in the first transistor T0.

[0063] Please continue to refer to Figure 2 and Figure 4 In an optional embodiment of the present disclosure, the thickness of the first protruding portion B1 and the second protruding portion B2 is H1, the thickness of the main body portion B0 is H2, H1 = (1 + k) × H2, wherein 0 ≤ k ≤ 20%.

[0064] Considering that when the main body B0, the first protruding portion B1 and the second protruding portion B2 are introduced into the first active layer P1, the thickness of the first protruding portion B1 and the second protruding portion B2 may affect the thickness of the display panel. If the above k value is set to be greater than 20%, the thickness of the first protruding portion B1 and the second protruding portion B2 is large, which may cause the first protruding portion B1 and the second protruding portion B2 to have a greater impact on the overall thickness of the display panel, which is not conducive to the thin design of the display panel. When the above k value is set to 20% or less, after the first protruding portion B1 and the second protruding portion B2 are introduced, the overall thickness of the display panel can be controlled within a certain range, thereby avoiding the introduction of the first protruding portion B1 and the second protruding portion B2 to have a greater impact on the overall thickness of the display panel, and meeting the thin design requirements of the display panel.

[0065] In an optional embodiment of the present disclosure, the thickness of the main body B0 is 25nm≤H2≤30nm. Considering that the operation of the transistor is based on the carrier behavior of the semiconductor, the pn structure formed between the n-type and p-type semiconductors can control the flow of current. By changing the gate voltage to control the number of carriers, the current from the source to the drain can be controlled. Therefore, the main body B0 in the first transistor T0 needs to meet a certain thickness to achieve the above control process. If the thickness of the main body B0 is set to less than 25nm, it may affect the characteristics of the semiconductor in the first transistor T0, and if the thickness of the main body B0 is set to greater than 30nm, it will have a certain impact on the overall thickness of the display panel. Therefore, in this embodiment, the thickness of the main body B0 is set to 25nm≤H2≤30nm, which can not only ensure the characteristics of the semiconductor in the first transistor T0, but also help meet the thinning requirements of the display panel. Optionally, 26nm≤H2≤29nm, or 25nm≤H2≤28nm, the present disclosure does not specifically limit this.

[0066] Please continue to refer to Figures 2 to 4 In an optional embodiment of the present disclosure, along the direction perpendicular to the substrate 00, the orthographic projection of the first connection hole K1 on the plane where the substrate 00 is located is located within the orthographic projection range of the first convex portion B1 on the plane where the substrate 00 is located, and the orthographic projection of the second connection hole K2 on the plane where the substrate 00 is located is located within the orthographic projection range of the second convex portion B2 on the plane where the substrate 00 is located. In this way, when forming the first connection hole K1 and the second connection hole K2, the first convex portion B1 and the second convex portion B2 can be used as references, and the first connection hole K1 is formed directly above the first convex portion B1 to expose the first convex portion B1, and the second connection hole K2 is formed directly above the second convex portion B2 to expose the second convex portion B2, without the need to introduce other reference objects, which is conducive to simplifying the manufacturing process of the first connection hole K1 and the second connection hole K2. When forming the first pole J1 and the second pole J2, the metal material is filled in the first connection hole K1 to realize the electrical connection between the first pole J1 and the first protrusion B1, and the metal material is filled in the second connection hole K2 to realize the electrical connection between the second pole J2 and the second protrusion B2.

[0067] Figure 5 FIG. 1 is a top view of the first transistor T0 in the embodiment of the present disclosure. Figure 5 In an optional embodiment of the present disclosure, the first active layer P1 includes a channel region Q0 and a first region Q1 and a second region Q2 located on both sides of the channel region Q0, the first protrusion B1 is located in the first region Q1, the second protrusion B2 is located in the second region Q2, and along a direction perpendicular to the plane where the substrate 00 is located, the first protrusion B1 and the second protrusion B2 do not overlap with the channel region Q0.

[0068] For transistors in related technologies, their active layers include a channel region and doped regions located on both sides of the channel region. The ion doping concentration in the doped region is different from that in the channel region. Ion doping in the doped region is usually achieved by ion implantation. Figure 4 and Figure 5 In the embodiment of the present disclosure, the process of forming the doping region by ion implantation is omitted, that is, ion doping is not performed on the main body B0, but the first convex part B1 and the second convex part B2 with higher resistivity are introduced on the side of the main body B0 away from the substrate 00. The first area Q1 where the first convex part B1 is located and the second area Q2 where the second convex part B2 is located can be regarded as the conductive area of ​​the first active layer P1 to achieve electrical connection with the first pole J1 and the second pole J2. Therefore, by introducing the first convex part B1 and the second convex part B2, the process of doping the first active layer P1 by ion implantation is omitted, which is conducive to simplifying the overall manufacturing process of the display panel and improving production efficiency.

[0069] Figure 6 Shown Figure 1 Another AA-direction cross-sectional view of the display panel is different from the above-mentioned embodiment in that Figure 6 The first transistor T0 in the embodiment includes two gates, and the first transistor T0 is a transistor with a dual-gate structure.

[0070] Please refer to Figure 6 In an optional embodiment of the present disclosure, the array layer 10 includes an auxiliary metal layer m0, which is located on the side of the first active layer P1 facing the substrate 00, and overlaps with the first active layer P1 along a direction perpendicular to the substrate 00; the gate of the first transistor T0 includes a first gate G1 and a second gate G2, the first gate G1 is located on the first metal layer m1, and the second gate G2 is located on the auxiliary metal layer m0. In the embodiment of the present disclosure, the auxiliary metal layer m0 is introduced on the side of the first active layer P1 facing the substrate 00 to form the second gate G2 of the first transistor T0. Along the direction perpendicular to the plane where the substrate 00 is located, the first gate G1 and the second gate G2 overlap with the first active layer P1 to form channel regions respectively, forming a transistor with a double-gate double-channel structure. The transistor with this structure increases the channel area of ​​the first transistor T0, which is beneficial to improving the current transmission efficiency.

[0071] Figure 7 FIG. 1 is a schematic diagram showing a structure of a pixel driving circuit in a display panel provided by an embodiment of the present disclosure. Figure 8 Shown Figure 7 A working timing diagram of the pixel driving circuit in FIG. 1, please refer to FIG. Figure 7 and Figure 8In an optional embodiment of the present disclosure, the display panel includes a plurality of pixel driving circuits 00, the pixel driving circuit 00 includes a driving transistor DT, a data writing transistor T1, a threshold compensation transistor T2 and a first reset transistor T3, wherein the gate of the driving transistor DT is connected to the first node N1, the first electrode is connected to the second node N2, and the second electrode is connected to the third node N3; the first electrode of the data writing transistor T1 is connected to the data line DA, and the second electrode is connected to the second node N2; the first electrode of the threshold compensation transistor T3 is connected to the third node N3, and the second electrode is connected to the second node N2; the first electrode of the first reset transistor T3 is connected to the first reset signal line Vref1, and the second electrode is connected to the first node N1; the first transistor T0 mentioned in the embodiment of the present disclosure includes at least one of the driving transistor DT, the threshold compensation transistor T2 and the first reset transistor T3. It should be noted that, Figure 7 The example in which the first transistor T0 includes a driving transistor DT, a first reset transistor T3, a threshold compensation transistor T2 and a data writing transistor T1 is used for illustration, but the invention is not limited thereto. In some other embodiments of the present disclosure, the first transistor T0 may include only one or any two of the driving transistor DT, the first reset transistor T3 and the threshold compensation transistor T2.

[0072] It should also be noted that Figure 7The illustrated embodiment is only described by taking the pixel driving circuit including 7 transistors as an example, but does not limit the actual structure of the pixel driving circuit. Optionally, the pixel driving circuit 00 also includes two light-emitting control transistors T4 and T5 and a second reset transistor T6, one of the two light-emitting control transistors T4 / T5 is connected between the power signal terminal PVDD and the second node N2, the other is connected between the third node N3 and the anode of the light-emitting element 30, the cathode of the light-emitting element 30 is connected to the power signal terminal PVEE, and the second reset transistor T6 is connected between the second reset signal line Vref2 and the anode of the light-emitting element 30. Among them, the control terminals of the first reset transistor T3 and the second reset transistor T6 are connected to the first control signal terminal Scan1, the control terminals of the data writing transistor T1 and the threshold compensation transistor T2 are connected to the second control signal terminal Scan2, and the control terminals of the light-emitting control transistors T4 / T5 are connected to the light-emitting control signal terminal Emit. Optionally, the working sequence of the pixel driving circuit 00 includes a reset phase t1, a data writing phase t2 and a light emitting phase t3, wherein the first reset transistor T3 and the second reset transistor T6 are turned on in the reset phase, the first reset transistor T3 is used to reset the gate of the driving transistor, and the second reset transistor T6 is used to reset the anode of the light emitting element 30. The data writing transistor T1 and the threshold compensation transistor T2 are turned on in the data writing phase, and are used to write the data signal to the second node N2 and perform threshold compensation on the gate of the driving transistor DT. The light emitting control transistors T4 and T5 are used to be turned on in the light emitting phase, and in the light emitting phase, the signal of the power signal terminal PVDD is transmitted to the driving transistor DT, and the driving transistor DT generates a driving current to drive the light emitting element 30 to emit light. It should be noted that the above sequence is only for illustration, and the present disclosure does not limit this. In some other embodiments of the present disclosure, the driving sequence may also be deformed to a certain extent, for example, the second reset transistor may also be turned on in the data writing phase, and the present disclosure does not limit this.

[0073] Considering that the driving transistor is a transistor used to generate a driving current in the pixel driving circuit 00, and has a high requirement for current transmission efficiency, when the first transistor T0 includes the driving transistor DT, the driving transistor DT has the characteristics of the first transistor T0. When the first transistor T0 is an oxide transistor or a dual-gate dual-channel oxide transistor, it has a high mobility and current transmission efficiency, which is beneficial to improving the driving efficiency of the light-emitting element. In addition, considering that the first reset transistor T3 and the threshold compensation transistor T2 are both transistors directly connected to the gate of the driving transistor, if the leakage current of one of the first reset transistor T3 and the threshold compensation transistor T2 is large, the influence on the gate potential of the driving transistor DT will be large, and the change of the gate potential of the driving transistor DT will affect the magnitude of the driving current finally outputted, and affect the light-emitting accuracy of the light-emitting element 30. If the first transistor T0 in the embodiment of the present disclosure includes at least one of the first reset transistor T3 and the threshold compensation transistor T2, since the first transistor T0 is an oxide transistor, the leakage current is small, which is beneficial to reduce or avoid the influence of the leakage current of the first reset transistor T3 or the threshold compensation transistor T2 on the gate potential of the driving transistor, and improve the output accuracy of the pixel driving circuit.

[0074] When the first transistor T0 includes a driving transistor DT, and when the first transistor T0 includes one of a threshold compensation transistor T2 and a first reset transistor T3, the connection relationship between the two gates of the first transistor T0 may be designed differently, which will be described in detail below.

[0075] Fig. 9 FIG. 1 is a schematic diagram of a structure of a driving transistor in an embodiment of the present disclosure. Please refer to FIG. Figure 7 and Fig. 9In an optional embodiment of the present disclosure, the first transistor T0 includes a driving transistor DT, the first gate G1 of the driving transistor DT is connected to the first node N1, and the second gate G2 of the driving transistor DT is connected to the data line DA. When the driving transistor DT is embodied as a dual-gate dual-channel transistor, its first gate G1 and the second gate G2 can be connected to different potentials, specifically, the first gate G1 is connected to the first node N1 in the pixel driving circuit 00, and the second gate G2 is connected to the data line DA in the display panel. Considering that the driving transistor is an oxide transistor, when the driving transistor includes the first gate G1 and the second gate G2, if the first gate G1 and the second gate G2 are of equal potential, when the driving transistor DT is in the on state for a long time, the first gate G1 and the second gate G2 both have a positive bias electric field and gate stress, thereby increasing the threshold offset of the driving transistor DT, which may affect the accuracy of the output current of the driving transistor. In the present embodiment, when the second gate G2 of the driving transistor DT is connected to the data line DA, the potential of the data line DA is usually lower, and the second gate G2 will not generate a positive bias electric field. Only the first gate G1 generates a positive bias electric field. Compared with the method of equal potentials of the first gate G1 and the second gate G2, it is beneficial to reduce the threshold voltage offset of the driving transistor, thereby helping to improve the accuracy of the driving current output by the driving transistor.

[0076] Fig.10 FIG. 1 is a schematic diagram of a structure of a threshold compensation transistor or a first reset transistor in an embodiment of the present disclosure. Fig.11 Shown with Fig.10 For the top view of the first transistor T0 in FIG. Fig.10 and Fig.11 In an optional embodiment of the present disclosure, the first transistor T0 includes a threshold compensation transistor T2 and / or a first reset transistor T3, and the first gate G1 and the second gate G2 of the threshold compensation transistor T2 and / or the first reset transistor T3 are electrically connected. Optionally, the first gate G1 and the second gate G2 are electrically connected through a connection hole k0.

[0077] Considering that the threshold compensation transistor T2 and the first reset transistor T3 in the pixel driving circuit are both switch transistors, the two are only turned on at a specific stage, for example, the threshold compensation transistor T2 is turned on when the gate of the driving transistor DT is threshold compensated, and the first reset transistor T3 is turned on when the gate of the driving transistor DT is reset, and the two do not need to be turned on for a long time. When the first transistor T0 includes this type of transistor, the first gate G1 and the second gate G2 are electrically connected in this embodiment, so that the first gate G1 and the second gate G2 have the same potential, which is conducive to increasing the mobility and on-state current of this type of transistor, ensuring that the transistor is quickly turned on when it needs to be turned on, thereby facilitating improving the response rate of the pixel driving circuit.

[0078] Fig.12 FIG. 1 is another schematic diagram of the structure of the pixel driving circuit provided by the embodiment of the present disclosure, Figure 7 The difference is Fig.12 Each transistor in the pixel driving circuit shown embodies the structure of the first transistor T0 mentioned in the embodiment of the present disclosure.

[0079] Please refer to Fig.12 In an optional embodiment of the present disclosure, the pixel driving circuit also includes a first switch control transistor T4 and a second switch control transistor T5, the first electrode J1 of the first switch control transistor T4 is connected to the power signal terminal PVDD, and the second electrode J2 is connected to the second node N2; the first electrode J1 of the second switch control transistor T5 is connected to the third node N3, and the second electrode J2 is connected to the light emitting element 30; the first transistor T0 includes a first switch control transistor T4 and a second switch control transistor T5.

[0080] The first switch control transistor T4 and the second switch control transistor T5 are used to be turned on in the light emitting stage, so that a current path is formed between the power signal terminal PVDD and the light emitting element 30, and the driving current generated by the driving transistor DT is transmitted to the light emitting element 30. The first switch control transistor T4 and the second switch control transistor T5 are both switch transistors. When the first transistor T0 includes the first switch control transistor T4 and the second switch control transistor T5, it can be used as follows Fig.10 The structure shown is thus beneficial for increasing the mobility and on-state current of this type of transistor, ensuring that the transistor is turned on quickly when it needs to be turned on, thereby facilitating improving the response rate of the pixel driving circuit.

[0081] When all transistors in the pixel driving circuit of the embodiment of the present disclosure are embodied as first transistors, that is, when they are all oxide transistors, each transistor in the pixel driving circuit is embodied as a high-mobility transistor and has the characteristics of low leakage current, and at the same time, the transistors in the display area achieve large-area structural uniformity, which is conducive to achieving low power consumption and good display uniformity. In addition, when the transistors in the pixel driving circuit are all embodied as oxide transistors, compared with the method of doping other types of transistors, the process is more simplified, which is conducive to reducing the overall production cost.

[0082] Fig.13 Shown Figure 1 Another AA cross-section of the display panel, please refer to Fig.13In an optional embodiment of the present disclosure, the first semiconductor layer 20 includes a first sublayer 61 and a second sublayer 62, the resistivity of the second sublayer 62 is lower than the resistivity of the first sublayer 61, the main body B0 is located in the first sublayer 61, and the first protrusion B1 and the second protrusion B2 are located in the second sublayer 62; the array layer 10 also includes at least one capacitor C, the first electrode 01 of the capacitor C is at least located in the second sublayer 62, and the second electrode 02 of the capacitor C is at least located in the first metal layer m1.

[0083] Fig.14 FIG. 1 is a schematic diagram of a film layer forming a capacitor C in a display panel in the related art, please refer to FIG. Fig.14 In the related art, a capacitor metal layer mc is introduced between the first metal layer m1 and the second metal layer m2, wherein the capacitor metal layer mc is isolated from the first metal layer m1 by an insulating isolation layer 91. At this time, the two plates of the capacitor C are located on the capacitor metal layer mc and the first metal layer m1 respectively. It can be seen that when the capacitor metal layer mc is added to form the capacitor C structure, the insulating isolation layer 91 will be added accordingly, which increases the number of manufacturing processes and the number of required masks. Please refer to Fig.13 , and when the first semiconductor layer 20 is introduced into the display panel in the embodiment of the present disclosure, since the second sub-layer 62 with lower resistivity is introduced into the first semiconductor layer 20, the second sub-layer 62 can be used to set the second protrusion B2, and the second sub-layer 62 can also be used as a plate of the capacitor C to form a capacitor structure with another plate located in the first metal layer m1. In this way, there is no need to introduce additional capacitor metal layer mc and insulating isolation layer 91 into the display panel, which is conducive to simplifying the overall structure of the panel, and also helps to save the mask process required for making the capacitor metal layer mc and the insulating isolation layer 91, thereby helping to simplify the overall manufacturing process of the display panel.

[0084] Fig.15 Shown Figure 1 Another AA cross-sectional view of the display panel, Fig.16 Shown Fig.15 A connection diagram of capacitor C, please refer to Fig.15 and Fig.16In an optional embodiment of the present disclosure, the array layer 10 includes a first signal line X1 disposed in a different layer from the first electrode plate 01, and the first electrode plate 01 is electrically connected to the first signal line X1 through a connection hole k11; the array layer 10 includes a second signal line X2 disposed in the same layer as the second electrode plate 02, and the second electrode plate 02 is electrically connected to the second signal line X2. In order to form a capacitor C, it is necessary to provide an electrical signal to the first electrode plate 01 and the second electrode plate 02 of the capacitor C respectively. In this embodiment, the first electrode plate 01 of the capacitor C is electrically connected to the first signal line X1, and the electrical signal is obtained through the first signal line X1, and the second electrode plate 02 of the capacitor C is electrically connected to the second signal line X2, and the electrical signal is obtained through the second signal line X2. Optionally, in the display panel, the material of the first metal layer m1 is mainly Mo, and the material of the second metal layer m2 is Ti-Al-Ti. Due to the characteristics of the material itself, the impedance of the first metal layer m1 is greater than the impedance of the second metal layer m2, that is, the resistivity of the first metal layer m1 is greater than the resistivity of the second metal layer m2, and the conductive effect of the second metal layer m2 is better than the conductive effect of the first metal layer m1. In the embodiment of the present disclosure, the first signal line X1 connected to the first electrode plate 01 can be set in the second metal layer m2. When the first signal line X1 is used to provide an electrical signal to the first electrode plate 01, it is beneficial to improve the transmission efficiency of the electrical signal. The first electrode plate 01 and the first signal line X1 can be electrically connected by punching. It should be noted that this embodiment is only described by taking the first signal line X1 as an example of setting the second metal layer m2, but it is not limited to this. In some other embodiments of the present disclosure, the first signal line X1 can also be set in other feasible metal film layers. In addition, since the second electrode plate 02 of the capacitor C is located in the first metal layer m1, when the second signal line X2 electrically connected to the second electrode plate 02 is set in the first metal layer m1, the two can be electrically connected without drilling, which is conducive to simplifying the manufacturing process.

[0085] Please continue to refer to Fig.13 and Fig.15 In an optional embodiment of the present disclosure, along a direction perpendicular to the plane where the substrate 00 is located, the first metal layer m1 and the first semiconductor layer 20 are isolated by a gate insulating layer 81. Fig.14 As shown in the structure of the related art, the embodiment of the present disclosure sets the first electrode 01 of the capacitor C on the second sublayer 62 of the first semiconductor layer 20, omitting the insulating isolation layer 91 on the side of the first metal layer m1 facing away from the substrate 00, so that only one gate insulating layer 81 is included between the first metal layer m1 and the first semiconductor layer 20. This is beneficial to reducing the distance between the first metal layer m1 and the first semiconductor layer 20, that is, it is beneficial to reduce the distance between the two electrodes of the capacitor C, thereby simplifying the film layer of the display panel while increasing the capacity of the capacitor C.

[0086] Please continue to refer to Fig.13 and Fig.15 In an optional embodiment of the present disclosure, along a direction perpendicular to the plane where the substrate 00 is located, no other metal layer is included between the first metal layer m1 and the second metal layer m2. Fig.14 Compared with the structure in the related art shown in the figure, when the first electrode 01 and the second electrode 02 of the capacitor C are respectively arranged on the first semiconductor layer 20 and the first metal layer m1, there is no need to introduce a capacitor metal layer mc between the first metal layer m1 and the second metal layer m2, which is beneficial to simplify the metal film layer in the display panel, reduce the mask process, simplify the overall panel manufacturing process, and reduce production costs.

[0087] Fig.17 The figure is a flow chart of a method for manufacturing a display panel provided by an embodiment of the present disclosure. Based on the same inventive concept, the present disclosure also provides a method for manufacturing a display panel, including:

[0088] S01. Provide a substrate 00.

[0089] S02, please refer to Fig.18 , a first sublayer 61 in the first semiconductor layer 20 is formed on one side of the substrate 00, and a second sublayer 62 in the first semiconductor layer 20 is formed on a side of the first sublayer 61 away from the substrate 00, wherein, Fig.18 The figure shows a schematic diagram of a structure of manufacturing the first semiconductor layer 20 in the manufacturing method of the display panel provided by the embodiment of the present disclosure. It should be noted that when the display panel includes the auxiliary metal layer m0, before manufacturing the first semiconductor layer 20, the step of manufacturing the auxiliary metal layer m0 on the substrate 00 is also included.

[0090] S03, please refer to Fig.19 , removing at least a portion of the first sublayer 61 and the second sublayer 62 to form a first active layer P1 of the first transistor T0, the first active layer P1 including a main body B0 located in the first sublayer 61 and a first convex portion B1 and a second convex portion B2 located in the second sublayer 62, wherein, Fig.19 The figure shows a schematic diagram of a structure of forming a first convex portion B1 and a second convex portion B2 in the method for manufacturing a display panel provided by an embodiment of the present disclosure, wherein the resistivity of the first convex portion B1 and the second convex portion B2 is less than the resistivity of the main body portion B0.

[0091] S04, please refer to Fig. 20 , a gate insulating layer 81 is formed on the side of the second sub-layer 62 facing away from the substrate 00; wherein, Fig. 20 FIG. 8 is a schematic diagram showing a structure for manufacturing a gate insulating layer 81 .

[0092] S05, please refer to Fig.21, a first metal layer m1 is formed on the side of the gate insulating layer 81 away from the substrate 00, and a gate of the first transistor T0 is formed on the first metal layer m1; wherein, Fig.21 FIG. 1 is a schematic diagram showing a structure for manufacturing the first metal layer m1.

[0093] S06, please refer to Fig. 22 , an interlayer insulating layer 82 is formed on the side of the first metal layer m1 away from the substrate 00; wherein, Fig. 22 FIG. 8 is a schematic diagram showing a structure for manufacturing an interlayer insulating layer 82 .

[0094] S07, please refer to Fig.23 , using the first convex portion B1 and the second convex portion B2 as an alignment structure, forming a first connection hole K1 and a second connection hole K2 on the interlayer insulating layer 82 and the gate insulating layer 81, so that the first connection hole K1 exposes the first convex portion B1, and the second connection hole K2 exposes the second convex portion B2; wherein, Fig.23 The figure shows a structural schematic diagram of manufacturing the first connection hole K1 and the second connection hole K2. In this way, taking the first protrusion B1 and the second protrusion B2 as references, the first connection hole K1 is formed directly above the first protrusion B1 to expose the first protrusion B1, and the second connection hole K2 is formed directly above the second protrusion B2 to expose the second protrusion B2, without introducing other reference objects, which is conducive to simplifying the manufacturing process of the first connection hole K1 and the second connection hole K2.

[0095] S08, please refer to Fig.24 A second metal layer m2 is formed on the side of the interlayer insulating layer away from the substrate 00 to form a first electrode J1 and a second electrode J2 of the first transistor T0, so that the first electrode J1 is electrically connected to the first protruding portion B1 through a connecting hole, and the second electrode J2 is electrically connected to the second protruding portion B2 through a connecting hole, wherein, Fig.24 The figure shows a structural schematic diagram of manufacturing the first pole J1 and the second pole J2.

[0096] It should be noted that after the first pole J1 and the second pole J2 are manufactured, other required film layers can be manufactured on the side of the first pole J1 and the second pole J2 facing away from the substrate 00 as needed, and this disclosure does not make any specific limitation on this.

[0097] In the manufacturing method of the display panel provided by the embodiment of the present disclosure, when manufacturing the first semiconductor layer 20, the first sub-layer 61 and the second sub-layer 62 are formed, the resistivity of the second sub-layer 62 is less than the resistivity of the first sub-layer 61, the main body B0 of the first active layer P1 in the first transistor T0 is formed on the first sub-layer 61, and the first convex portion B1 and the second convex portion B2 are formed on the second sub-layer 62, so that the first convex portion B1 and the second convex portion B2 have conductive properties. After the first metal layer m1 and the interlayer insulating layer 82 are subsequently manufactured, the first convex portion B1 and the second convex portion B2 can be used as references to manufacture the first connection hole K1 and the second connection hole K2, so that the first connection hole K1 exposes the first convex portion B1, and the second connection hole K2 exposes the second convex portion B2, so as to facilitate the subsequent electrical connection between the first pole J1 and the first convex portion B1 and the electrical connection between the second pole J2 and the second convex portion B2. It can be seen that in the embodiment of the present disclosure, a second sublayer 62 with lower resistivity is introduced when manufacturing the first semiconductor layer 20, so that the first protrusion B1 and the second protrusion B2 located in the second sublayer 62 have conductive properties, and there is no need to introduce an ion implantation process to change the resistivity of the source region and the drain region in the first active layer P1, thereby eliminating the ion implantation process in the production process and avoiding increasing the investment in equipment required for the ion implantation process, which is beneficial to simplifying the process of display products and reducing production costs.

[0098] In an optional embodiment of the present disclosure, in the above step S02, the first sub-layer 61 and the second sub-layer 62 are continuously formed in the same vacuum film-forming chamber. That is, after the first sub-layer 61 is formed in the pinhole film-forming chamber, there is no need to take out the semi-finished product that has been formed, but the second sub-layer 62 is continuously formed on the first sub-layer 61. This method avoids the process of taking out the semi-finished product and then performing other operations, which is conducive to simplifying the overall manufacturing process of the display panel and improving production efficiency.

[0099] In an optional embodiment of the present disclosure, in the above step S02, when making the second sub-layer 62, the film forming parameters of the vacuum film forming chamber are adjusted so that the In content when making the second sub-layer 62 is higher than the In content when making the first sub-layer 61. In this way, only the film forming parameters need to be adjusted without taking out the semi-finished product, and the first sub-layer 61 and the second sub-layer 62 can be continuously made in the same vacuum chamber, which is conducive to simplifying the manufacturing process. In addition, when making the second sub-layer 62, increasing the In content can reduce the resistivity of the second sub-layer 62, improve the conductivity of the second sub-layer 62, and make the second sub-layer 62 have conductive properties. In this way, the conductive effect of the second sub-layer 62 can be achieved without introducing ion implantation equipment and ion implantation process, which effectively saves the manufacturing cost, and is also conducive to simplifying the manufacturing process and improving production efficiency.

[0100] Please continue to refer to Figures 18 to 24In an optional embodiment of the present disclosure, while forming the first active layer P1 of the first transistor T0, the first plate 01 of the capacitor C is formed by the first sublayer 61 and the second sublayer; while forming the gate of the first transistor T0 on the first metal layer m1, the second plate 02 of the capacitor C is formed by the first metal layer m1; along the direction perpendicular to the plane where the substrate 00 is located, the first plate 01 overlaps with the second plate 02. In the process of making the first semiconductor layer 20 in the present disclosure embodiment, in addition to forming the first active layer P1 of the first transistor T0, the first plate 01 of the capacitor C is formed by the first sublayer 61 and the second sublayer 62, and the first plate 01 of the capacitor C can be provided by providing an electrical signal to the second sublayer 62 with a conductive function. When the first metal layer m1 is subsequently made, the second plate 02 of the capacitor C is formed. In this way, the capacitor C can be made without introducing additional production processes and masks in the display panel, which is conducive to further simplifying the film structure of the display panel, simplifying the production process, improving production efficiency, and reducing production costs.

[0101] Fig.25 FIG. 1 is a schematic diagram of manufacturing a first protruding portion B1 and a second protruding portion B2 in a method for manufacturing a display panel provided in an embodiment of the present disclosure. Fig.26 FIG. 1 is another schematic diagram of manufacturing the first convex portion B1 and the second convex portion B2 in the manufacturing method of the display panel provided in the embodiment of the present disclosure. In an optional implementation manner of the present disclosure, in the above step S03, the method of removing at least a portion of the first sub-layer 61 and the second sub-layer 62 is: please refer to Fig.25 , remove it using a halftone mask process, or, refer to Fig.26 , and removed separately using two mask processes.

[0102] Please refer to Fig.25After forming the first sub-layer 61 and the second sub-layer 62, a photoresist PR is introduced on the side of the second sub-layer 62 away from the substrate 00, and a half-tone mask YM0 is introduced on the side of the photoresist away from the substrate 00 for exposure. The transmittance of the half-tone mask YM0 in different areas is different. For example, the transmittance in the channel area is low (for example, the transmittance is 50% to 60%), so as to ensure that the second sub-layer 62 in the channel area Q0 domain can be completely etched, while the first sub-layer 61 in the channel area Q0 domain is retained. For the source and drain areas on the left and right sides of the channel, and the area where the capacitor is located, the transmittance of the mask is 0%, and the first sub-layer 61 and the second sub-layer 62 need to be retained. The transmittance of other areas of the mask is 100%, so as to achieve the complete removal of the first sub-layer 61 and the second sub-layer 62 in other areas. After the exposure process, the photoresist is developed, and the sub-layers to be removed are removed by a wet etching process. Then the photoresist is stripped to form the required main body B0, the first convex part B1 and the second convex part B2, and the first electrode plate 01 of the capacitor. By using the half-tone mask process, only one etching process is required to form the required structure, which is conducive to simplifying the overall production process of the display panel.

[0103] In addition to using the half-tone mask process, a conventional mask process can also be introduced to form the first raised portion B1 and the second raised portion B2. For example, please refer to Fig.26 , a photoresist PR is formed on the side of the second sub-layer 62 away from the substrate 00, and a first conventional mask YM1 is introduced on the side of the photoresist PR away from the substrate 00 for exposure. The first conventional mask YM1 only includes an opaque area and a fully transparent area. After the exposure process, the photoresist is developed, and the second sub-layer 62 in the source region, the drain region, and other regions other than the capacitor region is removed by a wet etching process, and only the second sub-layer 62 in the source region, the drain region, and the capacitor region is retained, and then the photoresist is stripped. Then, a whole surface photoresist PR is formed on the side of the second sub-layer 62 away from the substrate 00, and a second conventional mask YM2 is introduced for exposure. Similarly, the second conventional mask YM2 only includes a fully transparent region and an opaque region. After the exposure process, the photoresist is developed, and the first sublayer 61 in the channel region, the source region, the drain region, and other regions other than the capacitor region is removed by a wet etching process, and the first sublayer 61 in the channel region, the source region, the drain region, and the capacitor region is retained, and then the photoresist is stripped, thereby forming the required main body B0, the first convex portion B1, the second convex portion B2, and the first electrode plate 01 of the capacitor C. By adopting this process, two conventional mask plates are introduced, and the structure required by the embodiment of the present disclosure can also be formed, and the present disclosure does not specifically limit this.

[0104] Based on the same inventive concept, the present disclosure also provides a display device, Fig. 27 FIG. 1 is a schematic diagram of a structure of a display device provided in an embodiment of the present disclosure. Please refer to FIG. Fig. 27 , the display device 200 includes the display panel 100 in any of the above embodiments. The display device 200 provided in the embodiment of the present disclosure may be any electronic device with a display function, such as a tablet computer with a display function, a display cabinet display product, a television, or a vehicle-mounted display device. The display device 200 provided in the embodiment of the present disclosure has the beneficial effects of the display panel 100 provided in the embodiment of the present disclosure. For details, please refer to the specific description of the display panel 100 in the above embodiments, which will not be repeated in this embodiment.

[0105] Understandably, Fig. 27 Only a rectangular structure is used to illustrate the display device. In some other embodiments of the present disclosure, the display device 200 may also be circular, elliptical or any other feasible shape, and the present disclosure does not specifically limit this.

[0106] It should be noted that, in this article, relational terms such as "first" and "second" are only used to distinguish one entity or operation from another entity or operation, and do not necessarily require or imply any such actual relationship or order between these entities or operations. Moreover, the terms "include", "comprise" or any other variants thereof are intended to cover non-exclusive inclusion, so that a process, method, article or device including a series of elements includes not only those elements, but also other elements not explicitly listed, or also includes elements inherent to such process, method, article or device. In the absence of further restrictions, the elements defined by the sentence "comprise a ..." do not exclude the existence of other identical elements in the process, method, article or device including the elements.

[0107] The above description is only a specific embodiment of the present disclosure, so that those skilled in the art can understand or implement the present disclosure. Various modifications to these embodiments will be apparent to those skilled in the art, and the general principles defined herein may be implemented in other embodiments without departing from the spirit or scope of the present disclosure. Therefore, the present disclosure will not be limited to the embodiments described herein, but will conform to the widest scope consistent with the principles and novel features disclosed herein.

Claims

1. A display panel, characterized in that: include: A substrate and an array layer, wherein the array layer is located on one side of the substrate, the array layer comprises a first semiconductor layer, a first metal layer and a second metal layer, the first metal layer is located on a side of the first semiconductor layer away from the substrate, and the second metal layer is located on a side of the first metal layer away from the substrate; The array layer includes a first transistor, a first active layer of the first transistor is located in the first semiconductor layer, and a first pole and a second pole of the first transistor are located in the second metal layer; the first active layer includes a main body, a first protruding portion and a second protruding portion, the first protruding portion and the second protruding portion are located on a side of the main body facing the second metal layer and in contact with the main body, the first pole is electrically connected to the first protruding portion through a first connecting hole, and the second pole is electrically connected to the second protruding portion through a second connecting hole.

2. The display panel according to claim 1, characterized in that: The resistivity of the first protrusion and the second protrusion is smaller than the resistivity of the main body.

3. The display panel according to claim 1, characterized in that: The thickness of the first protrusion is greater than or equal to the thickness of the main body, and the thickness of the second protrusion is greater than or equal to the thickness of the main body.

4. The display panel according to claim 3, characterized in that: The thickness of the first convex portion and the second convex portion is H1, and the thickness of the main body portion is H2, H1=(1+k)×H2, wherein 0≤k≤20%.

5. The display panel according to claim 4, characterized in that: The thickness of the main body is 25nm≤H2≤30nm.

6. The display panel according to claim 1, characterized in that: Along the direction perpendicular to the substrate, the orthographic projection of the first connection hole on the plane where the substrate is located is located within the orthographic projection range of the first protrusion on the plane where the substrate is located, and the orthographic projection of the second connection hole on the plane where the substrate is located is located within the orthographic projection range of the second protrusion on the plane where the substrate is located.

7. The display panel according to claim 1, characterized in that: The first active layer includes a channel region and a first region and a second region located on both sides of the channel region, the first protrusion is located in the first region, the second protrusion is located in the second region, and along a direction perpendicular to the substrate, the first protrusion and the second protrusion do not overlap with the channel region.

8. The display panel according to claim 1, characterized in that: The first convex portion and the second convex portion include at least one of ITO, IZO and IGZO; the main body portion includes at least one of IGZO, IGZTO, IGO and IZTO.

9. The display panel according to claim 1, characterized in that: The array layer comprises an auxiliary metal layer, the auxiliary metal layer is located on a side of the first active layer facing the substrate, and the auxiliary metal layer overlaps the first active layer along a direction perpendicular to the substrate; The gate of the first transistor includes a first gate and a second gate, the first gate is located in the first metal layer, and the second gate is located in the auxiliary metal layer.

10. The display panel according to claim 9, characterized in that: The display panel includes a plurality of pixel driving circuits, the pixel driving circuit includes a driving transistor, a data writing transistor, a threshold compensation transistor and a first reset transistor, wherein the gate of the driving transistor is connected to the first node, the first electrode is connected to the second node, and the second electrode is connected to the third node; the first electrode of the data writing transistor is connected to the data line, and the second electrode is connected to the second node; the first electrode of the threshold compensation transistor is connected to the third node, and the second electrode is connected to the second node; the first electrode of the first reset transistor is connected to the first reset signal line, and the second electrode is connected to the first node; The first transistor includes at least one of the drive transistor, the threshold compensation transistor, and the first reset transistor.

11. The display panel according to claim 10, characterized in that: The first transistor includes the driving transistor, a first gate of the driving transistor is connected to the first node, and a second gate of the driving transistor is connected to the data line.

12. The display panel according to claim 10, characterized in that: The first transistor includes a threshold compensation transistor and / or the first reset transistor, and a first gate and the second gate of the threshold compensation transistor and / or the first reset transistor are electrically connected.

13. The display panel according to claim 10, characterized in that: The pixel driving circuit further includes a first switch control transistor and a second switch control transistor, wherein the first electrode of the first switch control transistor is connected to the power signal terminal, and the second electrode is connected to the second node; the first electrode of the second switch control transistor is connected to the third node, and the second electrode is connected to the light emitting element; The first transistor includes the first switch control transistor and the second switch control transistor.

14. The display panel according to claim 1, characterized in that: The first semiconductor layer includes a first sub-layer and a second sub-layer, the main body is located in the first sub-layer, and the first convex portion and the second convex portion are located in the second sub-layer; The array layer further includes at least one capacitor, wherein a first electrode plate of the capacitor is at least located in the second sub-layer, and a second electrode plate of the capacitor is at least located in the first metal layer.

15. The display panel according to claim 14, characterized in that: The array layer includes a first signal line arranged in a different layer from the first electrode plate, and the first electrode plate is electrically connected to the first signal line through a connection hole; the array layer includes a second signal line arranged in the same layer as the second electrode plate, and the second electrode plate is electrically connected to the second signal line.

16. The display panel according to claim 14, characterized in that: Along a direction perpendicular to the plane where the substrate is located, the first metal layer and the first semiconductor layer are isolated by a gate insulating layer.

17. The display panel according to claim 14, characterized in that: Along a direction perpendicular to the plane where the substrate is located, no other metal layer is included between the first metal layer and the second metal layer.

18. A method for manufacturing a display panel, characterized in that: include: providing a substrate; Forming a first sublayer in the first semiconductor layer on one side of the substrate, and forming a second sublayer in the first semiconductor layer on a side of the first sublayer facing away from the substrate; Removing at least a portion of the first sublayer and the second sublayer to form a first active layer of the first transistor, wherein the first active layer includes a main body portion located in the first sublayer and a first convex portion and a second convex portion located in the second sublayer; forming a gate insulating layer on a side of the second sub-layer facing away from the substrate; Manufacturing a first metal layer on a side of the gate insulating layer facing away from the substrate, and forming a gate of a first transistor on the first metal layer; forming an interlayer insulating layer on a side of the first metal layer facing away from the substrate; Using the first protrusion and the second protrusion as alignment structures, forming a first connection hole and a second connection hole on the interlayer insulating layer and the gate insulating layer, so that the first connection hole exposes the first protrusion, and the second connection hole exposes the second protrusion; A second metal layer is fabricated on a side of the interlayer insulating layer away from the substrate to form a first electrode and a second electrode of the first transistor, so that the first electrode is electrically connected to the first protrusion through the connection hole, and the second electrode is electrically connected to the second protrusion through the connection hole.

19. The manufacturing method according to claim 18, characterized in that: The first sub-layer and the second sub-layer are formed by continuous film forming in the same vacuum film forming chamber.

20. The manufacturing method according to claim 19, characterized in that: When manufacturing the second sub-layer, the film forming parameters of the vacuum film forming chamber are adjusted so that the In content when manufacturing the second sub-layer is higher than the In content when manufacturing the first sub-layer.

21. The method according to claim 18, characterized in that: While forming the first active layer of the first transistor, the first sublayer and the second sublayer are also used to form a first plate of a capacitor; while the first metal layer forms the gate of the first transistor, the first metal layer is also used to form a second plate of the capacitor; along a direction perpendicular to the plane where the substrate is located, the first plate overlaps with the second plate.

22. The manufacturing method according to claim 18, characterized in that: The method for removing at least a portion of the first sub-layer and the second sub-layer is: removing them by using a half-tone mask process, or removing them by using two mask processes respectively.

23. A display device, characterized in that: The display panel comprises any one of claims 1 to 17.

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