Display device

Abstract

The invention provides a display device. The display device includes: a substrate including first to Nth pixel circuit regions arranged in a first direction; an initialization voltage wiring disposed on the substrate, extending in a second direction crossing the first direction, and overlapping any one of the first to Nth pixel circuit regions; a driving voltage wiring disposed on the substrate, extending in the second direction, and adjacent to the initialization voltage wiring in the first direction; and a data wiring disposed on the substrate, extending in the second direction, and spaced apart from the initialization voltage wiring across the driving voltage wiring in the first direction.

Description

Technical Field

[0001] The present invention relates to a display device. More particularly, the present invention relates to a display device for providing visual information. Background Art

[0002] With the development of information technology, the importance of display devices as a connection medium between users and information has attracted attention. For example, the use of display devices such as liquid crystal display devices (LCD), organic light emitting display devices (OLED), plasma display panel devices (PDP), quantum dot display devices, etc. is increasing.

[0003] The display device may include a pixel that generates light, and the pixel may include a light-emitting element. The light-emitting element may output light based on a driving current. As the resolution of the display device increases, parasitic capacitance may be formed between wirings included in the pixel. The parasitic capacitance may cause a problem of reduced display quality of the display device such as observed spots. Summary of the invention

[0004] An object of the present invention is to provide a display device with improved display quality.

[0005] However, the purpose of the present invention is not limited to the above-mentioned purpose, and various extensions can be made without departing from the concept and scope of the present invention.

[0006] In order to achieve the aforementioned purpose of the present invention, a display device according to an embodiment of the present invention may include: a substrate, including a first pixel circuit area to an N-th (wherein N is a natural number greater than 1) pixel circuit area arranged along a first direction; an initialization voltage wiring, arranged on the substrate, extending along a second direction intersecting the first direction, and overlapping with any one of the first pixel circuit area to the N-th pixel circuit area; a driving voltage wiring, arranged on the substrate, extending along the second direction, and adjacent to the initialization voltage wiring along the first direction; and a data wiring, arranged on the substrate, extending along the second direction, and separated from the initialization voltage wiring by the driving voltage wiring along the first direction.

[0007] In one embodiment, the display device may further include: a first pixel circuit to an N-th pixel circuit, respectively arranged in the first pixel circuit area to the N-th pixel circuit area, wherein each of the first pixel circuit to the N-th pixel circuit may include: a driving transistor, providing a driving current; a first switching transistor, providing a data voltage to the driving transistor; and a second switching transistor, providing an initialization voltage to the driving transistor.

[0008] In one embodiment, the gate electrode of the first switch transistor and the gate electrode of the second switch transistor may receive the same signal.

[0009] In one embodiment, the driving voltage wiring may overlap with each of the first pixel circuit region to the Nth pixel circuit region, and the driving voltage wiring overlapping with the N-1th pixel circuit region may provide a driving voltage to the driving transistor included in the Nth pixel circuit.

[0010] In one embodiment, the display device may further include: a common voltage wiring arranged on the substrate and extending along the second direction, wherein the driving voltage wiring, the data wiring and the common voltage wiring may be arranged in order along the first direction.

[0011] In one embodiment, the driving voltage wiring and the common voltage wiring may be arranged at the same layer as each other.

[0012] In one embodiment, the driving voltage wiring and the common voltage wiring may be arranged at different layers from each other.

[0013] In one embodiment, the display device may further include: an active pattern arranged on the substrate and overlapping with the first pixel circuit area to the Nth pixel circuit area; a first conductive layer arranged on the active pattern and including a gate electrode; and a second conductive layer arranged on the first conductive layer.

[0014] In one embodiment, the second conductive layer may include the driving voltage wiring and the common voltage wiring.

[0015] In one embodiment, the display device may further include: a third conductive layer arranged on the second conductive layer, wherein the second conductive layer may include the driving voltage wiring, and the third conductive layer may include the common voltage wiring.

[0016] In an embodiment, the active pattern may include an oxide semiconductor.

[0017] In order to achieve the aforementioned purpose of the present invention, a display device according to another embodiment of the present invention may include: a substrate, including a first pixel circuit area to an N-th (wherein N is a natural number greater than 1) pixel circuit area arranged along a first direction; an initialization voltage wiring, arranged on the substrate, extending along a second direction intersecting the first direction, and overlapping with any one of the first pixel circuit area to the N-th pixel circuit area; a common voltage wiring, arranged on the substrate, extending along the second direction, and adjacent to the initialization voltage wiring along the first direction; and a data wiring, arranged on the substrate, extending along the second direction, and separated from the initialization voltage wiring along the first direction via the common voltage wiring.

[0018] In one embodiment, the display device may further include: a first pixel circuit to an N-th pixel circuit, respectively arranged in the first pixel circuit area to the N-th pixel circuit area, wherein each of the first pixel circuit to the N-th pixel circuit may include: a driving transistor, providing a driving current; a first switching transistor, providing a data voltage to the driving transistor; and a second switching transistor, providing an initialization voltage to the driving transistor.

[0019] In one embodiment, the gate electrode of the first switch transistor and the gate electrode of the second switch transistor may receive the same signal.

[0020] In one embodiment, the display device may further include: a driving voltage wiring arranged on the substrate and extending along the second direction, wherein the common voltage wiring, the data wiring and the driving voltage wiring may be arranged in order along the first direction.

[0021] In one embodiment, the driving voltage wiring may overlap with each of the first pixel circuit region to the Nth pixel circuit region, and the driving voltage wiring overlapping with the Nth pixel circuit region may provide a driving voltage to the driving transistor included in the Nth pixel circuit.

[0022] In one embodiment, the driving voltage wiring and the common voltage wiring may be arranged at the same layer as each other.

[0023] In one embodiment, the display device may further include: an active pattern arranged on the substrate and overlapping with the first pixel circuit area to the Nth pixel circuit area; a first conductive layer arranged on the active pattern and including a gate electrode; and a second conductive layer arranged on the first conductive layer.

[0024] In one embodiment, the second conductive layer may include the driving voltage wiring and the common voltage wiring.

[0025] A display device according to an embodiment of the present invention may include an initialization voltage wiring, a driving voltage wiring adjacent to the initialization voltage wiring along a first direction, and a data wiring separated from the initialization voltage wiring via the driving voltage wiring along the first direction.

[0026] As the data wiring is separated from the initialization voltage wiring via the driving voltage wiring along the first direction, parasitic capacitance formed between the initialization voltage wiring and the data wiring can be reduced, thereby reducing the occurrence of horizontal crosstalk in the display device and improving the display quality of the display device.

[0027] However, the effects of the present invention are not limited to the above-mentioned effects, and various extensions can be made without departing from the concept and scope of the present invention. BRIEF DESCRIPTION OF THE DRAWINGS

[0028] Figure 1 is a plan view showing a display device according to an embodiment of the present invention.

[0029] Figure 2 It is shown Figure 1 A block diagram of a display device.

[0030] Figure 3 It is used to describe the Figure 1 A circuit diagram of a sub-pixel in a display device.

[0031] Figure 4 It is shown Figure 1 A cross-sectional view of a display device.

[0032] Figures 5 to 8 It is shown that the Figure 1 and Figure 3 Schematic diagram of the arrangement of pixels in a display device.

[0033] Fig. 9 is a cross-sectional view showing a display device according to another embodiment of the present invention.

[0034] Figures 10 to 12 It is shown that the Fig. 9 Schematic diagram of the arrangement of pixels in a display device.

[0035] Fig.13 is a cross-sectional view showing a display device according to still another embodiment of the present invention.

[0036] Fig.14 and Fig.15 It is shown that the Fig.13 Schematic diagram of the arrangement of pixels in a display device.

[0037] Description of Reference Numerals

[0038] DD, DD2, DD3: Display device PXA(N): Nth pixel circuit area

[0039] 1230, 2230, 3220: Initialization voltage wiring

[0040] 1240, 2210, 3230: Drive voltage wiring

[0041] 1250, 2250, 3240: Data cabling

[0042] 1210, 2240, 3320: Common voltage wiring

[0043] DATA: data voltage VINT: initialization voltage

[0044] ACT, ACT': Active pattern GE: Gate electrode

[0045] CL1, CL1': first conductive layer CL2, CL2', CL2": second conductive layer

[0046] CL3”: The third conductive layer DETAILED DESCRIPTION

[0047] Hereinafter, embodiments of the present invention will be described in more detail with reference to the accompanying drawings. The same reference numerals are used for the same components in the accompanying drawings, and repeated descriptions of the same components are omitted. The present invention can be implemented in many different forms and is not limited to the embodiments described herein.

[0048] Figure 1 is a plan view showing a display device according to an embodiment of the present invention.

[0049] In this specification, a plane may be defined as a first direction DR1 and a second direction DR2 intersecting the first direction DR1. For example, the first direction DR1 and the second direction DR2 may be perpendicular to each other. The display device DD and various components or layers included in the display device DD may have a thickness extending along a third direction intersecting the plane. In other words, the third direction may be perpendicular to each of the first direction DR1 and the second direction DR2.

[0050] Reference Figure 1, a display device DD according to an embodiment of the present invention may include a display area DA and a peripheral area PA. The display area DA may be defined as an area that generates light or displays an image by adjusting the transmittance of light provided from an external light source. The peripheral area PA may be located around the display area DA. For example, the peripheral area PA may surround at least a portion of the display area DA. The peripheral area PA may be defined as an area where no image is displayed.

[0051] A plurality of pixels PX may be arranged in the display area DA. Each pixel PX may generate light according to a driving signal. The pixels PX may be repeatedly arranged along a first direction DR1 and a second direction DR2. In other words, the pixels PX may be arranged along a plurality of rows and a plurality of columns.

[0052] Each pixel PX may include a first sub-pixel SPX1, a second sub-pixel SPX2, and a third sub-pixel SPX3. The first sub-pixel SPX1 may generate light of a first color, the second sub-pixel SPX2 may generate light of a second color, and the third sub-pixel SPX3 may generate light of a third color. For example, the first color may be red, the second color may be green, and the third color may be blue. However, the present invention is not limited thereto. Each of the first sub-pixel SPX1, the second sub-pixel SPX2, and the third sub-pixel SPX3 may receive a Figure 2 The gate signal GS, the driving voltage ELVDD, the common voltage ELVSS and the initialization voltage VINT.

[0053] The display area DA may include a plurality of pixel circuit areas PXA. Each pixel circuit area PXA may be arranged with a driving voltage wiring (eg, Figure 2 driving voltage wiring 1240), common voltage wiring (eg, Figure 2 Common voltage wiring 1210), data wiring (eg, Figure 2 data wiring 1250), initialization voltage wiring (eg, Figure 2 For example, the pixel circuit regions PXA may be repeatedly arranged along the first direction DR1 and the second direction DR2. In other words, the pixel circuit regions PXA may be arranged along a plurality of rows and a plurality of columns. Each pixel PX may overlap any one of the pixel circuit regions PXA.

[0054] In one embodiment, the display area DA may include a first pixel circuit area PXA(1) to an N-th pixel circuit area PXA(N) arranged along a first direction DR1. For example, the first pixel circuit area PXA(1) may represent a pixel circuit area located in the first column. The N-th pixel circuit area PXA(N) may represent a pixel circuit area located in the N-th column. The N+1-th pixel circuit area PXA(N+1) may represent a pixel circuit area located in the N+1-th column. The N+1-th pixel circuit area PXA(N+1) and the N-th pixel circuit area PXA(N) may be adjacent to each other along the first direction DR1.

[0055] The first pixel circuit area PXA(1) to the N-th pixel circuit area PXA(N) may be respectively arranged with the first pixel circuit to the N-th pixel circuit. Each of the first pixel circuit to the N-th pixel circuit may include a first sub-pixel circuit, a second sub-pixel circuit and a third sub-pixel circuit. The first sub-pixel circuit may be connected to the light-emitting element of the first sub-pixel SPX1. Accordingly, the first sub-pixel circuit may provide a first driving current to the light-emitting element of the first sub-pixel SPX1. The second sub-pixel circuit may be connected to the light-emitting element of the second sub-pixel SPX2. Accordingly, the second sub-pixel circuit may provide a second driving current to the light-emitting element of the second sub-pixel SPX2. The third sub-pixel circuit may be connected to the light-emitting element of the third sub-pixel SPX3. Accordingly, the third sub-pixel circuit may provide a third driving current to the light-emitting element of the third sub-pixel SPX3.

[0056] Figure 2 It is shown Figure 1 A block diagram of a display device.

[0057] Reference Figure 2 The display device DD may include a display panel DP, a data driving part DDV, a gate driving part GDV, a control part CON and a voltage supply part VP.

[0058] The display panel DP may include a plurality of pixels PX. Each pixel PX may receive a gate signal GS through a gate wiring GL. Each pixel PX may receive a data voltage DATA through a data wiring 1250, and may receive an initialization voltage VINT through an initialization voltage wiring 1230. The data voltage DATA may be written to each pixel PX in response to the gate signal GS, and the initialization voltage VINT may be written to each pixel PX in response to the gate signal GS.

[0059] The control unit CON may receive input image data IDAT and a control signal CTRL from an external host processor (e.g., a graphics processing unit (GPU)). For example, the input image data IDAT may include red image data, green image data, and blue image data. The control signal CTRL may include a vertical synchronization signal, a horizontal synchronization signal, an input data enable signal, a main clock signal, etc. The control unit CON may generate a gate control signal GCTRL, a data control signal DCTRL, and output image data ODAT based on the input image data IDAT and the control signal CTRL.

[0060] The data driving part DDV may generate a data voltage DATA based on the output image data ODAT and the data control signal DCTRL. For example, the data driving part DDV may generate a data voltage DATA corresponding to the output image data ODAT, and may output the data voltage DATA to the data wiring 1250 in response to the data control signal DCTRL. The data control signal DCTRL may include an output data enable signal, a horizontal start signal, and a load signal.

[0061] The gate driving unit GDV may generate a gate signal GS based on the gate control signal GCTRL. The gate driving unit GDV may output the gate signal GS to the gate wiring GL. For example, the gate signal GS may include a gate-on voltage that turns on the transistor and a gate-off voltage that turns off the transistor. The gate control signal GCTRL may include a vertical start signal and a gate clock signal.

[0062] The voltage supply unit VP may provide a driving voltage ELVDD, a common voltage ELVSS, and an initialization voltage VINT to each pixel PX. The driving voltage ELVDD may be provided to each pixel PX through the driving voltage wiring 1240. The common voltage ELVSS may be provided through the common voltage wiring 1210 and a common electrode (eg, Figure 4 The initialization voltage VINT may be provided to each pixel PX through the initialization voltage wiring 1230.

[0063] Figure 3 It is used to describe the Figure 1 A circuit diagram of a sub-pixel in a display device.

[0064] Reference Figure 3 The first sub-pixel SPX1 may include the first sub-pixel circuit and a light emitting element LD. The first sub-pixel circuit may include a first transistor T1, a second transistor T2, a third transistor T3 and a storage capacitor CST. The first sub-pixel circuit provides the first driving current to the light emitting element LD, and the light emitting element LD may generate light based on the first driving current. Figure 1 The second sub-pixel SPX2 and the third sub-pixel SPX3 may include substantially the same sub-pixel circuit as the first sub-pixel SPX1. Therefore, the following description will focus on the first sub-pixel SPX1.

[0065] The first transistor T1 may include a gate electrode, a first electrode, and a second electrode. The gate electrode of the first transistor T1 may be connected to the second transistor T2. The first electrode of the first transistor T1 may receive a driving voltage ELVDD. The second electrode of the first transistor T1 may be connected to the light emitting element LD. The first transistor T1 may generate the first driving current based on the driving voltage ELVDD and the data voltage DATA. For example, the first transistor T1 may be referred to as a driving transistor.

[0066] The second transistor T2 may include a gate electrode, a first electrode, and a second electrode. The gate electrode of the second transistor T2 may receive a gate signal GS. The second transistor T2 may be turned on or off in response to the gate signal GS. The first electrode of the second transistor T2 may receive a data voltage DATA. The second electrode of the second transistor T2 may be connected to the first transistor T1. During a period in which the second transistor T2 is turned on, the second transistor T2 may transmit the data voltage DATA to the first transistor T1. For example, the second transistor T2 may be referred to as a first switching transistor.

[0067] The third transistor T3 may include a gate electrode, a first electrode, and a second electrode. The gate electrode of the third transistor T3 may receive a gate signal GS. The third transistor T3 may be turned on or off in response to the gate signal GS. The first electrode of the third transistor T3 may be connected to the first transistor T1. The second electrode of the third transistor T3 may receive an initialization voltage VINT. During a period in which the third transistor T3 is turned on, the third transistor T3 may transmit the initialization voltage VINT to the first transistor T1. For example, the third transistor T3 may be referred to as a second switching transistor.

[0068] In one embodiment, the gate electrode of the first switch transistor and the gate electrode of the second switch transistor may receive the same signal as each other. In other words, the gate electrode of the second transistor T2 and the gate electrode of the third transistor T3 may receive the same signal as each other. For example, the gate electrode of the second transistor T2 and the gate electrode of the third transistor T3 may receive the same gate signal GS as each other.

[0069] In one embodiment, each of the first transistor T1, the second transistor T2, and the third transistor T3 may be an NMOS transistor. Accordingly, the active pattern of each of the first transistor T1, the second transistor T2, and the third transistor T3 may include an oxide semiconductor. The gate signal GS for turning on each of the second transistor T2 and the third transistor T3 may have a high level. However, the present invention is not limited thereto, and each of the first transistor T1, the second transistor T2, and the third transistor T3 may also be a PMOS transistor.

[0070] The storage capacitor CST may include a first electrode and a second electrode. The first electrode of the storage capacitor CST may be connected to the gate electrode of the first transistor T1. The second electrode of the storage capacitor CST may be connected to the first electrode of the third transistor T3. The storage capacitor CST may maintain the voltage level of the gate electrode of the first transistor T1 during the inactive period of the gate signal GS.

[0071] The light emitting element LD may include a first electrode and a second electrode. The first electrode of the light emitting element LD may be connected to the second electrode of the first transistor T1. The second electrode of the light emitting element LD may receive a common voltage ELVSS. The light emitting element LD may emit light having a brightness corresponding to the first driving current. The light emitting element LD may include an organic light emitting element using an organic substance as a light emitting layer, an inorganic light emitting element using an inorganic substance as a light emitting layer, and the like.

[0072] Figure 4 It is shown Figure 1 A cross-sectional view of a display device.

[0073] Reference Figure 4 , the display device DD may include a substrate SUB, a circuit layer CL, a light emitting element LD, a pixel definition film PDL and an encapsulation layer TFE. The circuit layer CL may include a lower electrode layer BML, a buffer layer BUF, an active pattern ACT, a gate insulating layer GI, a first conductive layer CL1, a protective layer PVX and a via insulating layer VIA. The lower electrode layer BML may include a first lower electrode BE1 and a second lower electrode BE2. The first conductive layer CL1 may include a first electrode E1, a second electrode E2 and a gate electrode GE. The light emitting element LD may include a pixel electrode PE, a light emitting layer EML and a common electrode CE.

[0074] The substrate SUB may include a transparent or opaque substance. The substrate SUB may be formed using a transparent resin substrate. As an example of the transparent resin substrate, a polyimide substrate or the like may be cited. In this case, the polyimide substrate may include a first organic layer, a first barrier layer, a second organic layer, and the like. Optionally, the substrate SUB may also include a quartz substrate, a synthetic quartz substrate, a calcium fluoride substrate, a fluorine-doped quartz substrate, a sodalime substrate, a non-alkali glass substrate, and the like. These may be used alone or in combination with one another.

[0075] A lower electrode layer BML may be arranged on the substrate SUB. The lower electrode layer BML may include a metal, an alloy, a metal nitride, a conductive metal oxide, a transparent conductive substance, etc. As examples of materials that can be used as the lower electrode layer BML, silver (Ag), silver-containing alloys, molybdenum (Mo), molybdenum-containing alloys, aluminum (Al), aluminum-containing alloys, aluminum nitride (AlN), tungsten (W), tungsten nitride (WN), copper (Cu), nickel (Ni), chromium (Cr), chromium nitride (CrN), titanium (Ti), tantalum (Ta), platinum (Pt), scandium (Sc), indium tin oxide (ITO), indium zinc oxide (IZO), etc. may be included. These may be used alone or in combination with each other.

[0076] The lower electrode layer BML may include a first lower electrode BE1 and a second lower electrode BE2. The first lower electrode BE1 and the second lower electrode BE2 may be separated from each other. In one embodiment, the first lower electrode BE1 and the second lower electrode BE2 may be provided with different kinds of electrical signals.

[0077] A buffer layer BUF may be disposed on the substrate SUB and the lower electrode layer BML. The buffer layer BUF may prevent metal atoms or impurities from diffusing from the substrate SUB to the upper structure (e.g., the active pattern ACT, the first conductive layer CL1, etc.). Furthermore, when the surface of the substrate SUB is uneven, the buffer layer BUF may improve the flatness of the surface of the substrate SUB. The buffer layer BUF may include an inorganic insulating material. As an example of the inorganic insulating material that may be used as the buffer layer BUF, silicon oxide (SiO x ), silicon nitride (SiN x ), silicon oxynitride (SiO x N y ) etc. These may be used alone or in combination with each other.

[0078] An active pattern ACT may be arranged on the buffer layer BUF. The active pattern ACT may include an oxide semiconductor, a silicon semiconductor, an organic semiconductor, etc. In one embodiment, the active pattern ACT may include an oxide semiconductor. For example, the oxide semiconductor may include indium (In), gallium (Ga), tin (Sn), zirconium (Zr), vanadium (V), hafnium (Hf), cadmium (Cd), germanium (Ge), chromium (Cr), titanium (Ti) and zinc (Zn), etc. These may be used alone or in combination with each other. The active pattern ACT may include a first conductor area DI1, a second conductor area DI2 and a channel area CHA located between the first conductor area DI1 and the second conductor area DI2. In other words, the first conductor area DI1 and the second conductor area DI2 may be separated from each other by the channel area CHA.

[0079] For example, each of the first and second conductor regions DI1 and DI2 may be a doped region doped with impurities, and the channel region CHA may be a non-doped region or a region doped at a lower concentration than the first and second conductor regions DI1 and DI2 .

[0080] In one embodiment, during the process of etching the first conductive layer CL1 and the gate insulating layer GI in the manufacturing process of the display device DD, a portion of the active pattern ACT not covered by the gate insulating layer GI may be removed. Accordingly, an opening OP penetrating the active pattern ACT in the thickness direction may be defined in a portion of the active pattern ACT. However, in this case, by bypassing the opening OP, the channel area CHA may be electrically connected to the first conductor area DI1, and the channel area CHA may be electrically connected to the second conductor area DI2.

[0081] A gate insulating layer GI may be disposed on the buffer layer BUF and the active pattern ACT. The gate insulating layer GI may expose a portion of the active pattern ACT. The gate insulating layer GI may include an inorganic insulating material. As an example of the inorganic insulating material that may be used as the gate insulating layer GI, silicon oxide (SiO x ), silicon nitride (SiN x ), silicon oxynitride (SiO x N y ) etc. These may be used alone or in combination with each other. The gate insulating layer GI may electrically insulate the active pattern ACT from the gate electrode GE.

[0082] A first conductive layer CL1 may be disposed on the lower electrode layer BML, the active pattern ACT, and the gate insulating layer GI. The first conductive layer CL1 may include a first electrode E1, a second electrode E2, and a gate electrode GE. The first electrode E1, the second electrode E2, and the gate electrode GE may be spaced apart from each other.

[0083] The first electrode E1 may be electrically connected to the first lower electrode BE1. Specifically, the first electrode E1 may be electrically connected to the first lower electrode BE1 through a contact hole penetrating the buffer layer BUF and the gate insulating layer GI. Furthermore, the first electrode E1 may be electrically connected to the first conductor region DI1. Specifically, the first electrode E1 may be electrically connected to a portion of the first conductor region DI1 that is not covered by the gate insulating layer GI.

[0084] The gate electrode GE may overlap the channel area CHA of the active pattern ACT on a plane.

[0085] The second electrode E2 may be electrically connected to the second lower electrode BE2. Specifically, the second electrode E2 may be electrically connected to the second lower electrode BE2 through a contact hole penetrating the buffer layer BUF and the gate insulating layer GI. Furthermore, the second electrode E2 may be electrically connected to the second conductor region DI2. Specifically, the second electrode E2 may be electrically connected to a portion of the second conductor region DI2 that is not covered by the gate insulating layer GI.

[0086] The first conductive layer CL1 may include a metal, an alloy, a metal nitride, a conductive metal oxide, a transparent conductive material, etc. These may be used alone or in combination with each other. The first conductive layer CL1 may have a single layer or a multilayer structure. In one embodiment, the first conductive layer CL1 may include at least one of molybdenum (Mo), aluminum (Al), copper (Cu) and titanium (Ti), and have a multilayer structure. For example, the first conductive layer CL1 may have a three-layer structure of Ti / Al / Ti. However, the present invention is not limited thereto.

[0087] In one embodiment, the first electrode E1, the second electrode E2, the gate electrode GE and the active pattern ACT may define a thin film transistor TFT. For example, the thin film transistor TFT may correspond to Figure 3 The first transistor T1 is configured as a first transistor T1. That is, the thin film transistor TFT can perform the role of a driving transistor. The gate electrode GE can perform the role of a gate electrode of the thin film transistor TFT, and the first electrode E1 and the second electrode E2 can perform the roles of a source electrode and a drain electrode of the thin film transistor TFT.

[0088] A protective layer PVX may be disposed on the buffer layer BUF and the first conductive layer CL1. The protective layer PVX may cover the first electrode E1, the second electrode E2, and the gate electrode GE. Furthermore, the protective layer PVX may cover a portion of the active pattern ACT that is not covered by the gate insulating layer GI. The protective layer PVX may include an inorganic insulating material. Examples of the inorganic insulating material that may be used as the protective layer PVX include silicon oxide (SiO x ), silicon nitride (SiN x ), silicon oxynitride (SiOx N y ) etc. These may be used alone or in combination with each other.

[0089] A via insulating layer VIA may be arranged on the protective layer PVX. The via insulating layer VIA may include an organic insulating material. As an example of the organic insulating material that can be used as the via insulating layer VIA, a photoresist, a polyacryl-based resin, a polyimide-based resin, a polyamide-based resin, a siloxane-based resin, an epoxy-based resin, etc. may be included. These may be used alone or in combination with each other.

[0090] A pixel electrode PE may be arranged on the via insulating layer VIA. The pixel electrode PE may be electrically connected to the first electrode E1 through a contact hole penetrating the via insulating layer VIA and the protective layer PVX. Accordingly, the pixel electrode PE may be electrically connected to the thin film transistor TFT. For example, the pixel electrode PE may be a reflective electrode, a semi-transmissive electrode, or a transmissive electrode. The pixel electrode PE may include a metal, an alloy, a metal nitride, a conductive metal oxide, a transparent conductive material, and the like. These may be used alone or in combination with each other. For example, the pixel electrode PE may perform the role of an anode electrode.

[0091] In one embodiment, the pixel electrode PE may include a reflective film including at least one of silver (Ag), magnesium (Mg), aluminum (Al), platinum (Pt), palladium (Pd), gold (Au), nickel (Ni), neodymium (Nd), iridium (Ir) and chromium (Cr). In addition, the pixel electrode PE may include a reflective film such as indium tin oxide (ITO), indium zinc oxide (IZO), zinc oxide (ZnO), indium oxide (InO x ), indium gallium oxide (IGO), aluminum zinc oxide (AZO), etc. These can be used alone or in combination with each other.

[0092] The pixel electrode PE may have a single-layer or multi-layer structure. In one embodiment, the pixel electrode PE may include the reflective film and a transparent or semi-transparent electrode arranged on the reflective film. In another embodiment, the pixel electrode PE may include the reflective film and a transparent or semi-transparent electrode arranged below the reflective film. For example, the pixel electrode PE may have a three-layer structure of ITO / Ag / ITO. However, the present invention is not limited thereto.

[0093] A pixel definition film PDL may be arranged on the via insulating layer VIA. The pixel definition film PDL may cover the edge of the pixel electrode PE and expose a portion of the upper surface of the pixel electrode PE. The pixel definition film PDL may include an organic insulating material and / or an inorganic insulating material. As examples of the organic insulating material that can be used as the pixel definition film PDL, photoresists, polyacrylic resins, polyimide resins, polyamide resins, siloxane resins, epoxy resins, etc. may be included. These may be used alone or in combination with each other.

[0094] A light-emitting layer EML may be arranged on the pixel electrode PE. The light-emitting layer EML may emit light having a specific color (e.g., red, green, and blue). In one embodiment, the light-emitting layer EML may include at least one of an organic light-emitting substance and a quantum dot. For example, the light-emitting layer EML may include an organic light-emitting substance including a fluorescent substance or a phosphorescent substance that emits red light, green light, blue light, or white light. For example, the light-emitting layer EML may have a single-layer structure including one light-emitting layer. Optionally, the light-emitting layer EML may also have a tandem structure.

[0095] A common electrode CE may be arranged on the pixel definition film PDL and the light emitting layer EML. The common electrode CE covers the pixel definition film PDL and the light emitting layer EML, and may be arranged with a uniform thickness along the contours of the pixel definition film PDL and the light emitting layer EML. The common electrode CE may include metal, alloy, metal nitride, conductive metal oxide, transparent conductive material, etc. These may be used alone or in combination with each other. For example, the common electrode CE may perform the role of a cathode electrode.

[0096] Accordingly, a light emitting element LD including the pixel electrode PE, the light emitting layer EML and the common electrode CE may be formed.

[0097] An encapsulation layer TFE may be arranged on the common electrode CE. The encapsulation layer TFE may prevent impurities, moisture, etc. from penetrating into the light emitting element LD from the outside. The encapsulation layer TFE may include at least one inorganic encapsulation layer and at least one organic encapsulation layer. For example, the inorganic encapsulation layer may include silicon oxide (SiO x ), silicon nitride (SiN x ), silicon oxynitride (SiO x N y ) etc. These can be used alone or in combination with each other. For example, the organic encapsulation layer may include a high molecular cured material such as polyacrylate.

[0098] The display device DD of the present invention is limited to an organic light emitting display device (OLED) for explanation, but the configuration of the present invention is not limited thereto. In other embodiments, the display device DD may also include a liquid crystal display device (LCD), a field emission display device (FED), a plasma display panel device (PDP), an electrophoretic display device (EPD), an inorganic light emitting display device (ILED), or a quantum dot display device.

[0099] Figures 5 to 8 It is shown that the Figure 1 and Figure 3 For example, Figures 5 to 8 It is shown Figure 4 FIG. 1 is a layout diagram of a circuit layer CL. The first pixel circuit to the N-th pixel circuit respectively arranged in the first pixel circuit area PXA(1) to the N-th pixel circuit area PXA(N) may have substantially the same shape as each other. Therefore, the following description will focus on the N-th pixel circuit arranged in the N-th pixel circuit area PXA(N). Figures 5 to 8 At least a part of the constituent elements shown in may be connected to each other between the pixel circuits.

[0100] Reference Figure 1 , Figure 3 and Figure 5 , a lower electrode layer BML may be arranged on the substrate SUB. The lower electrode layer BML may include a first lower pattern BOP1, a second lower pattern BOP2, and a third lower pattern BOP3. The first lower pattern BOP1, the second lower pattern BOP2, and the third lower pattern BOP3 may be spaced apart from each other. Each of the first lower pattern BOP1, the second lower pattern BOP2, and the third lower pattern BOP3 may be spaced apart from each other. Figure 4 Corresponding to the second lower electrode BE2.

[0101] Further references Figure 6 , a buffer layer BUF may be disposed on the lower electrode layer BML.

[0102] The buffer layer BUF may include an inorganic insulating material. As an example of the inorganic insulating material that can be used as the buffer layer BUF, silicon oxide (SiO x ), silicon nitride (SiN x ), silicon oxynitride (SiO x N y ) etc. These may be used alone or in combination with each other.

[0103] An active pattern ACT may be disposed on the buffer layer BUF. The active pattern ACT may include a first active pattern ACT1, a second active pattern ACT2, and a third active pattern ACT3. Hereinafter, the first active pattern ACT1 will be mainly described.

[0104] The first active pattern ACT1 may be an active pattern for driving the light emitting element LD included in the first sub-pixel SPX1. The first active pattern ACT1 may include a first main body portion ACT1-BP, a first independent portion ACT1-IP, and a first main body portion ACT1(N+1) of the N+1th pixel circuit. The first independent portion ACT1-IP may be spaced apart from the first main body portion ACT1-BP. Although not shown in FIG. Figure 6 , but the portion having substantially the same shape as the first main body portion ACT1(N+1) of the N+1th pixel circuit may be adjacent to the first main body portion ACT1-BP along the first direction DR1. Similarly, the portion having substantially the same shape as the first main body portion ACT1-BP may be adjacent to the first main body portion ACT1(N+1) of the N+1th pixel circuit along the first direction DR1.

[0105] The second active pattern ACT2 may be an active pattern for driving the light emitting element LD included in the second sub-pixel SPX2. The second active pattern ACT2 may include a second body portion ACT2-BP, a second independent portion ACT2-IP, and a second body portion ACT2(N+1) of the N+1th pixel circuit.

[0106] The third active pattern ACT3 may be an active pattern for driving the light emitting element LD included in the third sub-pixel SPX3. The third active pattern ACT3 may include a third main portion ACT3-BP, a third independent portion ACT3-IP, and a third main portion ACT3(N+1) of the N+1th pixel circuit.

[0107] In an embodiment, each of the first active pattern ACT1 , the second active pattern ACT2 , and the third active pattern ACT3 may include an oxide semiconductor.

[0108] Further references Figure 7, a gate insulating layer GI may be disposed on the active pattern ACT and may cover the active pattern ACT.

[0109] The gate insulating layer GI may include an inorganic insulating material. As an example of an inorganic insulating material that can be used as the gate insulating layer GI, silicon oxide (SiO x ), silicon nitride (SiN x ), silicon oxynitride (SiO x N y ) etc. These may be used alone or in combination with each other.

[0110] The first conductive layer CL1 may be disposed on the gate insulating layer GI. The first conductive layer CL1 may include a first gate pattern 1110, a second gate pattern 1120, a third gate pattern 1130, a fourth gate pattern 1140, a fifth gate pattern 1150, a sixth gate pattern 1160, a seventh gate pattern 1170, and an eighth gate pattern 1180. The first gate pattern 1110, the second gate pattern 1120, the third gate pattern 1130, the fourth gate pattern 1140, the fifth gate pattern 1150, the sixth gate pattern 1160, the seventh gate pattern 1170, and the eighth gate pattern 1180 may be disposed on the same layer and may include the same material. The first conductive layer CL1 may include a metal, an alloy, a metal nitride, a conductive metal oxide, a transparent conductive material, etc. These may be used alone or in combination with each other.

[0111] The first conductive layer CL1 may at least partially overlap the active pattern ACT. The portion where the first conductive layer CL1 overlaps the active pattern ACT may define a portion of the transistor.

[0112] The first gate pattern 1110 may extend in the first direction DR1 . A driving voltage ELVDD may be supplied to the first gate pattern 1110 .

[0113] The second gate pattern 1120 may be spaced apart from the first gate pattern 1110. The second gate pattern 1120 may include a first portion 1121 extending in the first direction DR1 and a second portion 1122 extending in the second direction DR2. A gate signal GS may be provided to the second gate pattern 1120. For example, the second gate pattern 1120 may correspond to Figure 2 The gate wiring GL.

[0114] The second portion 1122 of the second gate pattern 1120 may overlap with each of the first independent portion ACT1-IP, the second independent portion ACT2-IP, and the third independent portion ACT3-IP. A portion of the second portion 1122 of the second gate pattern 1120 overlapping with the first independent portion ACT1-IP may correspond to the gate electrode of the second transistor T2 of the first sub-pixel circuit. A portion of the second portion 1122 of the second gate pattern 1120 overlapping with the second independent portion ACT2-IP may correspond to the gate electrode of the second transistor T2 of the second sub-pixel circuit. A portion of the second portion 1122 of the second gate pattern 1120 overlapping with the third independent portion ACT3-IP may correspond to the gate electrode of the second transistor T2 of the third sub-pixel circuit.

[0115] The second portion 1122 of the second gate pattern 1120 may overlap each of the first body portion ACT1-BP, the second body portion ACT2-BP, and the third body portion ACT3-BP. A portion of the second portion 1122 of the second gate pattern 1120 overlapping the first body portion ACT1-BP may correspond to the gate electrode of the third transistor T3 of the first sub-pixel circuit. A portion of the second portion 1122 of the second gate pattern 1120 overlapping the second body portion ACT2-BP may correspond to the gate electrode of the third transistor T3 of the second sub-pixel circuit. A portion of the second portion 1122 of the second gate pattern 1120 overlapping the third body portion ACT3-BP may correspond to the gate electrode of the third transistor T3 of the third sub-pixel circuit.

[0116] The third gate pattern 1130 may be spaced apart from the second gate pattern 1120. The third gate pattern 1130 may include a 3-1st gate pattern 1131, a 3-2nd gate pattern 1132, and a 3-3rd gate pattern 1133.

[0117] The 3-1st gate pattern 1131 may overlap the first body portion ACT1-BP. A portion of the 3-1st gate pattern 1131 overlapping the first body portion ACT1-BP may correspond to a gate electrode of the first transistor T1 of the first sub-pixel circuit.

[0118] The 3-1st gate pattern 1131 may overlap the first lower pattern BOP1. In a region where the first lower pattern BOP1 and the 3-1st gate pattern 1131 overlap, the first lower pattern BOP1 and the 3-1st gate pattern 1131 may form a storage capacitor CST of the first sub-pixel circuit.

[0119] The 3-2nd gate pattern 1132 may overlap the second body portion ACT2-BP. A portion of the 3-2nd gate pattern 1132 overlapping the second body portion ACT2-BP may correspond to a gate electrode of the first transistor T1 of the second sub-pixel circuit.

[0120] The 3-2nd gate pattern 1132 may overlap the second lower pattern BOP2. In a region where the second lower pattern BOP2 and the 3-2nd gate pattern 1132 overlap, the second lower pattern BOP2 and the 3-2nd gate pattern 1132 may form a storage capacitor CST of the second sub-pixel circuit.

[0121] The 3-3rd gate pattern 1133 may overlap the third body portion ACT3-BP. A portion of the 3-3rd gate pattern 1133 overlapping the third body portion ACT3-BP may correspond to a gate electrode of the first transistor T1 of the third sub-pixel circuit.

[0122] The 3-3rd gate pattern 1133 may overlap the third lower pattern BOP3. In a region where the third lower pattern BOP3 and the 3-3rd gate pattern 1133 overlap, the third lower pattern BOP3 and the 3-3rd gate pattern 1133 may form a storage capacitor CST of the third sub-pixel circuit.

[0123] The fourth gate pattern 1140 may be spaced apart from the third gate pattern 1130. The data voltage DATA may be provided to the fourth gate pattern 1140. For example, the fourth gate pattern 1140 may be referred to as a data connection electrode. The fourth gate pattern 1140 may include a 4-1st gate pattern 1141, a 4-2nd gate pattern 1142, and a 4-3rd gate pattern 1143. The data voltage DATA may include a red data voltage, a green data voltage, and a blue data voltage.

[0124] The red data voltage may be provided to the 4-1st gate pattern 1141. The 4-1st gate pattern 1141 may be connected to the first independent part ACT1-IP through a contact hole. Accordingly, the red data voltage may be provided to the second transistor T2 of the first sub-pixel circuit.

[0125] The green data voltage may be provided to the 4-2nd gate pattern 1142. The 4-2nd gate pattern 1142 may be connected to the second independent part ACT2-IP through a contact hole. Accordingly, the green data voltage may be provided to the second transistor T2 of the second sub-pixel circuit.

[0126] The blue data voltage may be provided to the 4-3rd gate pattern 1143. The 4-3rd gate pattern 1143 may be connected to the third independent part ACT3-IP through a contact hole. Accordingly, the blue data voltage may be provided to the second transistor T2 of the third sub-pixel circuit.

[0127] The fifth gate pattern 1150 may be spaced apart from the fourth gate pattern 1140. The fifth gate pattern 1150 may be provided with a driving voltage ELVDD. For example, the fifth gate pattern 1150 may be referred to as a driving voltage connection electrode. The fifth gate pattern 1150 may include a 5-1st gate pattern 1151, a 5-2nd gate pattern 1152, and a 5-3rd gate pattern 1153.

[0128] The 5-1th gate pattern 1151 may be connected to the first body portion ACT1(N+1) of the N+1th pixel circuit through a contact hole. Accordingly, the 5-1th gate pattern 1151 may provide a driving voltage ELVDD to the first transistor T1 of the first sub-pixel circuit included in the N+1th pixel circuit.

[0129] The 5-2nd gate pattern 1152 may be connected to the second body portion ACT2(N+1) of the N+1th pixel circuit through a contact hole. Accordingly, the 5-2nd gate pattern 1152 may provide a driving voltage ELVDD to the first transistor T1 of the second sub-pixel circuit included in the N+1th pixel circuit.

[0130] The 5-3rd gate pattern 1153 may be connected to the third body portion ACT3(N+1) of the N+1th pixel circuit through a contact hole. Accordingly, the 5-3rd gate pattern 1153 may provide a driving voltage ELVDD to the first transistor T1 of the third sub-pixel circuit included in the N+1th pixel circuit.

[0131] The sixth gate pattern 1160 may be spaced apart from the fifth gate pattern 1150. The sixth gate pattern 1160 may provide a driving current to the light emitting element LD. For example, the sixth gate pattern 1160 may be referred to as a lower light emitting element connection electrode. The sixth gate pattern 1160 may include a 6-1st gate pattern 1161, a 6-2nd gate pattern 1162, and a 6-3rd gate pattern 1163.

[0132] The 6-1st gate pattern 1161 may be connected to the first body portion ACT1-BP through the contact hole. Accordingly, the 6-1st gate pattern 1161 may provide the first driving current to the light emitting element LD included in the first sub-pixel SPX1.

[0133] The 6-2nd gate pattern 1162 may be connected to the second body portion ACT2-BP through the contact hole. Accordingly, the 6-2nd gate pattern 1162 may provide the second driving current to the light emitting element LD included in the second sub-pixel SPX2.

[0134] The 6-3rd gate pattern 1163 may be connected to the third body part ACT3-BP through the contact hole. Accordingly, the 6-3rd gate pattern 1163 may provide the third driving current to the light emitting element LD included in the third sub-pixel SPX3.

[0135] The seventh gate pattern 1170 may be spaced apart from the sixth gate pattern 1160. The initialization voltage VINT may be provided to the seventh gate pattern 1170. For example, the seventh gate pattern 1170 may be referred to as an initialization voltage connection electrode. The seventh gate pattern 1170 may include a 7-1st gate pattern 1171 and a 7-2nd gate pattern 1172.

[0136] The 7-1st gate pattern 1171 may be connected to the first main body portion ACT1-BP through a contact hole. Accordingly, the initialization voltage VINT may be provided to the third transistor T3 of the first sub-pixel circuit. Furthermore, the 7-1st gate pattern 1171 may be connected to the second main body portion ACT2-BP through a contact hole. Accordingly, the initialization voltage VINT may be provided to the third transistor T3 of the second sub-pixel circuit.

[0137] The 7-2nd gate pattern 1172 may be connected to the third body portion ACT3-BP through a contact hole. Accordingly, the initialization voltage VINT may be provided to the third transistor T3 of the third sub-pixel circuit.

[0138] The eighth gate pattern 1180 may extend in the first direction DR1 and may be spaced apart from the seventh gate pattern 1170. The eighth gate pattern 1180 may be supplied with a common voltage ELVSS.

[0139] Further references Figure 8 , the protective layer (e.g., Figure 4 A protection layer PVX) may be disposed on the first conductive layer CL1, and a via insulating layer VIA may be disposed on the protection layer.

[0140] The protective layer may include an inorganic insulating material. Examples of the inorganic insulating material that can be used as the protective layer include silicon oxide (SiO x ), silicon nitride (SiN x ), silicon oxynitride (SiO x N y) and the like. These can be used alone or in combination with each other. The via insulating layer VIA may include an organic insulating substance. Examples of the organic insulating substance that can be used as the via insulating layer VIA may include photoresists, polyacrylic resins, polyimide resins, acrylic resins, and the like. These can be used alone or in combination with each other.

[0141] The second conductive layer CL2 may be arranged on the via insulating layer VIA. The second conductive layer CL2 may include a common voltage wiring 1210, a light emitting element connection electrode 1220, an initialization voltage wiring 1230, a driving voltage wiring 1240, and a data wiring 1250. The common voltage wiring 1210, the light emitting element connection electrode 1220, the initialization voltage wiring 1230, the driving voltage wiring 1240, and the data wiring 1250 may be arranged in the same layer and may include the same substance. The second conductive layer CL2 may include a metal, an alloy, a metal nitride, a conductive metal oxide, a transparent conductive substance, etc. These may be used alone or in combination with each other.

[0142] The common voltage wiring 1210 may extend in the second direction DR2. The common voltage wiring 1210 may be connected to the eighth gate pattern 1180 through a contact hole. Accordingly, the common voltage ELVSS may be provided to the common voltage wiring 1210.

[0143] The light emitting element connection electrode 1220 may provide the driving current to the light emitting element LD. For example, the light emitting element connection electrode 1220 may be referred to as an upper light emitting element connection electrode. The light emitting element connection electrode 1220 may include a first light emitting element connection electrode 1221 , a second light emitting element connection electrode 1222 , and a third light emitting element connection electrode 1223 .

[0144] The first light emitting element connection electrode 1221 may be connected to the 6-1th gate pattern 1161 through a contact hole. Accordingly, the first light emitting element connection electrode 1221 may provide the first driving current to the light emitting element LD included in the first sub-pixel SPX1.

[0145] The second light emitting element connection electrode 1222 may be connected to the 6-2 th gate pattern 1162 through a contact hole. Accordingly, the second light emitting element connection electrode 1222 may provide the second driving current to the light emitting element LD included in the second sub-pixel SPX2.

[0146] The third light emitting element connection electrode 1223 may be connected to the 6-3rd gate pattern 1163 through the contact hole. Accordingly, the third light emitting element connection electrode 1223 may provide the third driving current to the light emitting element LD included in the third sub-pixel SPX3.

[0147] The initialization voltage wiring 1230 may extend in the second direction DR2 and may be spaced apart from the light emitting element connection electrode 1220. The initialization voltage VINT may be supplied to the initialization voltage wiring 1230. The initialization voltage wiring 1230 may be connected to the 7-1st gate pattern 1171 and the 7-2nd gate pattern 1172 through the contact hole. Accordingly, the initialization voltage VINT may be supplied to the 7-1st gate pattern 1171 and the 7-2nd gate pattern 1172.

[0148] The driving voltage wiring 1240 may extend in the second direction DR2 and may be adjacent to the initialization voltage wiring 1230 in the first direction DR1. The driving voltage wiring 1240 may be connected to the first gate pattern 1110 through a contact hole. Accordingly, the driving voltage ELVDD may be provided to the driving voltage wiring 1240.

[0149] In one embodiment, the driving voltage wiring 1240 overlapping the Nth pixel circuit area PXA(N) may provide the driving voltage ELVDD to the first transistor T1 included in the N+1th pixel circuit.

[0150] The driving voltage wiring 1240 may be connected to the 5-1th gate pattern 1151 through a contact hole. Accordingly, the driving voltage wiring 1240 may provide the driving voltage ELVDD to the 5-1th gate pattern 1151. Specifically, the driving voltage wiring 1240 may provide the driving voltage ELVDD to the first transistor T1 of the first sub-pixel circuit included in the N+1th pixel circuit through the 5-1th gate pattern 1151.

[0151] The driving voltage wiring 1240 may be connected to the 5-2nd gate pattern 1152 through a contact hole. Accordingly, the driving voltage wiring 1240 may provide the driving voltage ELVDD to the 5-2nd gate pattern 1152. Specifically, the driving voltage wiring 1240 may provide the driving voltage ELVDD to the first transistor T1 of the second sub-pixel circuit included in the N+1th pixel circuit through the 5-2nd gate pattern 1152.

[0152] The driving voltage wiring 1240 may be connected to the 5-3rd gate pattern 1153 through the contact hole. Accordingly, the driving voltage wiring 1240 may provide the driving voltage ELVDD to the 5-3rd gate pattern 1153. Specifically, the driving voltage wiring 1240 may provide the driving voltage ELVDD to the first transistor T1 of the third sub-pixel circuit included in the N+1th pixel circuit through the 5-3rd gate pattern 1153.

[0153] Each of the data wirings 1250 may extend in the second direction DR2. The data wirings 1250 may be spaced apart from the initialization voltage wiring 1230 in the first direction DR1 via the driving voltage wiring 1240. The data wirings 1250 may include a first data wiring 1251, a second data wiring 1252, and a third data wiring 1253.

[0154] The red data voltage may be provided to the first data wiring 1251. The first data wiring 1251 may be connected to the 4-1st gate pattern 1141 through a contact hole. Accordingly, the red data voltage may be provided to the 4-1st gate pattern 1141.

[0155] The green data voltage may be provided to the second data wiring 1252. The second data wiring 1252 may be connected to the 4-2nd gate pattern 1142 through a contact hole. Accordingly, the green data voltage may be provided to the 4-2nd gate pattern 1142.

[0156] The blue data voltage may be provided to the third data wiring 1253. The third data wiring 1253 may be connected to the 4-3rd gate pattern 1143 through a contact hole. Accordingly, the blue data voltage may be provided to the 4-3rd gate pattern 1143.

[0157] In one embodiment, the common voltage wiring 1210, the driving voltage wiring 1240, and the data wiring 1250 may be arranged in the order of the driving voltage wiring 1240, the data wiring 1250, and the common voltage wiring 1210 along the first direction DR1. Figure 8 Although not shown in the figure, the common voltage wiring 1210 overlapping the N+1 pixel circuit area PXA(N+1) and the data wiring 1250 overlapping the N pixel circuit area PXA(N) may be adjacent to each other along the first direction DR1. For example, the common voltage wiring 1210, the driving voltage wiring 1240, and the data wiring 1250 may be arranged in the order of the driving voltage wiring 1240, the first data wiring 1251, the third data wiring 1253, the second data wiring 1252, and the common voltage wiring 1210 overlapping the N+1 pixel circuit area PXA(N+1) along the first direction DR1.

[0158] In a conventional display device, when the initialization voltage wiring 1230 and the data wiring 1250 are arranged adjacent to each other, parasitic capacitance may be formed between the initialization voltage wiring 1230 and the data wiring 1250. Due to the parasitic capacitance, horizontal crosstalk occurs, and thus a problem of reduced display quality may occur.

[0159] A display device DD according to an embodiment of the present invention may include: an initialization voltage wiring 1230; a driving voltage wiring 1240 adjacent to the initialization voltage wiring 1230 along a first direction DR1; and a data wiring 1250 separated from the initialization voltage wiring 1230 via the driving voltage wiring 1240 along the first direction DR1. Since the data wiring 1250 is separated from the initialization voltage wiring 1230 via the driving voltage wiring 1240 along the first direction DR1, parasitic capacitance formed between the initialization voltage wiring 1230 and the data wiring 1250 may be reduced. That is, the driving voltage wiring 1240 is arranged between the initialization voltage wiring 1230 and the data wiring 1250, so that the formation of the parasitic capacitance may be suppressed. Accordingly, the occurrence of horizontal crosstalk in the display device DD may be reduced, and the display quality of the display device DD may be improved.

[0160] Fig. 9 is a cross-sectional view showing a display device according to another embodiment of the present invention. Figures 10 to 12 It is shown that the Fig. 9 For example, Figures 10 to 12 It is shown Fig. 9 The first pixel circuit to the N-th pixel circuit respectively arranged in the first pixel circuit area PXA(1) to the N-th pixel circuit area PXA(N) may have substantially the same shape as each other. Therefore, the following description will be centered on the N-th pixel circuit arranged in the N-th pixel circuit area PXA(N). Figures 10 to 12 At least a part of the constituent elements shown in may be connected to each other between the pixel circuits.

[0161] Reference Fig. 9 , a display device DD2 according to another embodiment of the present invention may include a substrate SUB, a circuit layer CL', a light emitting element LD, a pixel definition film PDL and an encapsulation layer TFE. The circuit layer CL' may include a lower electrode layer BML, a buffer layer BUF, an active pattern ACT', a gate insulating layer GI, a first conductive layer CL1', a protective layer PVX and a via insulating layer VIA. The lower electrode layer BML may include a first lower electrode BE1 and a second lower electrode BE2. The first conductive layer CL1' may include a first electrode E1, a second electrode E2 and a gate electrode GE. The light emitting element LD may include a pixel electrode PE, a light emitting layer EML and a common electrode CE.

[0162] The display device DD2 can be similar to the reference device except that the shape of the circuit layer CL' is arranged on the plane. Figures 1 to 8 Specifically, the display device DD2 is substantially the same as the display device DD2 described above. Specifically, the display device DD2 is different from the display device DD2 in that the drive voltage wiring (eg, Fig.122210) and common voltage wiring (eg, Fig.12 The common voltage wiring 2240) can be used in conjunction with the reference Figures 1 to 8 The display device DD described above is substantially the same. Figures 1 to 8 The display device DD describes the repeated content.

[0163] Reference Figure 1 , Figure 3 and Fig.10 , a lower electrode layer BML may be disposed on the substrate SUB, a buffer layer BUF may be disposed on the lower electrode layer BML, and an active pattern ACT′ may be disposed on the buffer layer BUF.

[0164] The lower electrode layer BML may include a first lower pattern BOP1, a second lower pattern BOP2, and a third lower pattern BOP3. The first lower pattern BOP1, the second lower pattern BOP2, and the third lower pattern BOP3 may be spaced apart from each other. Each of the first lower pattern BOP1, the second lower pattern BOP2, and the third lower pattern BOP3 may correspond to Fig. 9 The second lower electrode BE2.

[0165] The active pattern ACT' may include a first active pattern ACT1', a second active pattern ACT2', and a third active pattern ACT3'.

[0166] The first active pattern ACT1' may be an active pattern for driving the light emitting element LD included in the first sub-pixel SPX1. The first active pattern ACT1' may include a first body portion ACT1'-BP and a first independent portion ACT1'-IP.

[0167] The second active pattern ACT2' may be an active pattern for driving the light emitting element LD included in the second sub-pixel SPX2. The second active pattern ACT2' may include a second body portion ACT2'-BP and a second independent portion ACT2'-IP.

[0168] The third active pattern ACT3 ′ may be an active pattern for driving the light emitting element LD included in the third sub-pixel SPX3 The third active pattern ACT3 ′ may include a third body portion ACT3 ′-BP and a third independent portion ACT3 ′-IP.

[0169] Further references Fig.11 , the gate insulating layer GI may be disposed on the active pattern ACT' and may cover the active pattern ACT'. The first conductive layer CL1' may be disposed on the gate insulating layer GI.

[0170] The first conductive layer CL1′ may include a first gate pattern 2110, a second gate pattern 2120, a third gate pattern 2130, a fourth gate pattern 2140, a fifth gate pattern 2150, a sixth gate pattern 2160, and a seventh gate pattern 2170. The first gate pattern 2110, the second gate pattern 2120, the third gate pattern 2130, the fourth gate pattern 2140, the fifth gate pattern 2150, the sixth gate pattern 2160, and the seventh gate pattern 2170 may be disposed on the same layer and may include the same material.

[0171] The first conductive layer CL1' may at least partially overlap the active pattern ACT'. The portion where the first conductive layer CL1' and the active pattern ACT' overlap may define a portion of the transistor.

[0172] The first gate pattern 2110 may include a first portion 2111 extending along the first direction DR1 and a second portion 2112 extending along the second direction DR2. A gate signal GS may be provided to the first gate pattern 2110. For example, the first gate pattern 2110 may correspond to Figure 2 The gate wiring GL.

[0173] The second portion 2112 of the first gate pattern 2110 may overlap with each of the first independent portion ACT1'-IP, the second independent portion ACT2'-IP, and the third independent portion ACT3'-IP. A portion of the second portion 2112 of the first gate pattern 2110 overlapping with the first independent portion ACT1'-IP may correspond to the gate electrode of the second transistor T2 of the first sub-pixel circuit. A portion of the second portion 2112 of the first gate pattern 2110 overlapping with the second independent portion ACT2'-IP may correspond to the gate electrode of the second transistor T2 of the second sub-pixel circuit. A portion of the second portion 2112 of the first gate pattern 2110 overlapping with the third independent portion ACT3'-IP may correspond to the gate electrode of the second transistor T2 of the third sub-pixel circuit.

[0174] The second portion 2112 of the first gate pattern 2110 may overlap each of the first body portion ACT1'-BP, the second body portion ACT2'-BP, and the third body portion ACT3'-BP. A portion of the second portion 2112 of the first gate pattern 2110 overlapping the first body portion ACT1'-BP may correspond to the gate electrode of the third transistor T3 of the first sub-pixel circuit. A portion of the second portion 2112 of the first gate pattern 2110 overlapping the second body portion ACT2'-BP may correspond to the gate electrode of the third transistor T3 of the second sub-pixel circuit. A portion of the second portion 2112 of the first gate pattern 2110 overlapping the third body portion ACT3'-BP may correspond to the gate electrode of the third transistor T3 of the third sub-pixel circuit.

[0175] The second gate pattern 2120 may be spaced apart from the first gate pattern 2110. The driving voltage ELVDD may be provided to the second gate pattern 2120. For example, the second gate pattern 2120 may be referred to as a driving voltage connection electrode. The second gate pattern 2120 may include a 2-1st gate pattern 2121, a 2-2nd gate pattern 2122, and a 2-3rd gate pattern 2123.

[0176] The 2-1st gate pattern 2121 may be connected to the first body portion ACT1'-BP through a contact hole. Accordingly, the 2-1st gate pattern 2121 may provide a driving voltage ELVDD to the first transistor T1 of the first sub-pixel circuit. In other words, the 2-1st gate pattern 2121 may provide a driving voltage ELVDD to the first transistor T1 of the first sub-pixel circuit included in the Nth pixel circuit.

[0177] The 2-2 gate pattern 2122 may be connected to the second body portion ACT2'-BP through a contact hole. Accordingly, the 2-2 gate pattern 2122 may provide a driving voltage ELVDD to the first transistor T1 of the second sub-pixel circuit. In other words, the 2-2 gate pattern 2122 may provide a driving voltage ELVDD to the first transistor T1 of the second sub-pixel circuit included in the Nth pixel circuit.

[0178] The 2-3rd gate pattern 2123 may be connected to the third body portion ACT3'-BP through a contact hole. Accordingly, the 2-3rd gate pattern 2123 may provide a driving voltage ELVDD to the first transistor T1 of the third sub-pixel circuit. In other words, the 2-3rd gate pattern 2123 may provide a driving voltage ELVDD to the first transistor T1 of the third sub-pixel circuit included in the Nth pixel circuit.

[0179] The third gate pattern 2130 may be spaced apart from the second gate pattern 2120. The third gate pattern 2130 may include a 3-1st gate pattern 2131, a 3-2nd gate pattern 2132, and a 3-3rd gate pattern 2133.

[0180] The 3-1st gate pattern 2131 may overlap with the first body portion ACT1'-BP. A portion of the 3-1st gate pattern 2131 overlapping with the first body portion ACT1'-BP may correspond to the gate electrode of the first transistor T1 of the first sub-pixel circuit. Also, the 3-1st gate pattern 2131 may overlap with the first lower pattern BOP1. In the region where the first lower pattern BOP1 and the 3-1st gate pattern 2131 overlap, the first lower pattern BOP1 and the 3-1st gate pattern 2131 may form a storage capacitor CST of the first sub-pixel circuit.

[0181] The 3-2nd gate pattern 2132 may overlap with the second body portion ACT2'-BP. A portion of the 3-2nd gate pattern 2132 overlapping with the second body portion ACT2'-BP may correspond to the gate electrode of the first transistor T1 of the second sub-pixel circuit. Also, the 3-2nd gate pattern 2132 may overlap with the second lower pattern BOP2. In the region where the second lower pattern BOP2 and the 3-2nd gate pattern 2132 overlap, the second lower pattern BOP2 and the 3-2nd gate pattern 2132 may form a storage capacitor CST of the second sub-pixel circuit.

[0182] The 3-3rd gate pattern 2133 may overlap with the third body portion ACT3'-BP. A portion of the 3-3rd gate pattern 2133 overlapping with the third body portion ACT3'-BP may correspond to the gate electrode of the first transistor T1 of the third sub-pixel circuit. Also, the 3-3rd gate pattern 2133 may overlap with the third lower pattern BOP3. In the region where the third lower pattern BOP3 and the 3-3rd gate pattern 2133 overlap, the third lower pattern BOP3 and the 3-3rd gate pattern 2133 may form a storage capacitor CST of the third sub-pixel circuit.

[0183] The fourth gate pattern 2140 may be spaced apart from the third gate pattern 2130. The data voltage DATA may be provided to the fourth gate pattern 2140. For example, the fourth gate pattern 2140 may be referred to as a data connection electrode. The fourth gate pattern 2140 may include a 4-1st gate pattern 2141, a 4-2nd gate pattern 2142, and a 4-3rd gate pattern 2143. The data voltage DATA may include a red data voltage, a green data voltage, and a blue data voltage.

[0184] The red data voltage may be provided to the 4-1st gate pattern 2141. The 4-1st gate pattern 2141 may be connected to the first independent part ACT1'-IP through a contact hole. Accordingly, the red data voltage may be provided to the second transistor T2 of the first sub-pixel circuit.

[0185] The green data voltage may be provided to the 4-2nd gate pattern 2142. The 4-2nd gate pattern 2142 may be connected to the second independent portion ACT2'-IP through a contact hole. Accordingly, the green data voltage may be provided to the second transistor T2 of the second sub-pixel circuit.

[0186] The blue data voltage may be provided to the 4-3rd gate pattern 2143. The 4-3rd gate pattern 2143 may be connected to the third independent part ACT3'-IP through a contact hole. Accordingly, the blue data voltage may be provided to the second transistor T2 of the third sub-pixel circuit.

[0187] The fifth gate pattern 2150 may be spaced apart from the fourth gate pattern 2140. The fifth gate pattern 2150 may provide a driving current to the light emitting element LD. For example, the fifth gate pattern 2150 may be referred to as a lower light emitting element connection electrode. The fifth gate pattern 2150 may include a 5-1st gate pattern 2151, a 5-2nd gate pattern 2152, and a 5-3rd gate pattern 2153.

[0188] The 5-1st gate pattern 2151 may be connected to the first body portion ACT1 ′-BP through the contact hole. Accordingly, the 5-1st gate pattern 2151 may provide the first driving current to the light emitting element LD included in the first sub-pixel SPX1 .

[0189] The 5-2nd gate pattern 2152 may be connected to the second body portion ACT2 ′-BP through the contact hole. Accordingly, the 5-2nd gate pattern 2152 may provide the second driving current to the light emitting element LD included in the second sub-pixel SPX2.

[0190] The 5-3rd gate pattern 2153 may be connected to the third body portion ACT3 ′-BP through the contact hole. Accordingly, the 5-3rd gate pattern 2153 may provide a third driving current to the light emitting element LD included in the third sub-pixel SPX3.

[0191] The sixth gate pattern 2160 may be spaced apart from the fifth gate pattern 2150. The initialization voltage VINT may be provided to the sixth gate pattern 2160. For example, the sixth gate pattern 2160 may be referred to as an initialization voltage connection electrode. The sixth gate pattern 2160 may include a 6-1st gate pattern 2161 and a 6-2nd gate pattern 2162.

[0192] The 6-1st gate pattern 2161 may be connected to the first main body portion ACT1'-BP through a contact hole. Accordingly, the initialization voltage VINT may be provided to the third transistor T3 of the first sub-pixel circuit. Furthermore, the 6-1st gate pattern 2161 may be connected to the second main body portion ACT2'-BP through a contact hole. Accordingly, the initialization voltage VINT may be provided to the third transistor T3 of the second sub-pixel circuit.

[0193] The 6-2nd gate pattern 2162 may be connected to the third body portion ACT3'-BP through the contact hole. Accordingly, the initialization voltage VINT may be provided to the third transistor T3 of the third sub-pixel circuit.

[0194] The seventh gate pattern 2170 may extend in the first direction DR1 and may be spaced apart from the sixth gate pattern 2160. The seventh gate pattern 2170 may be supplied with a driving voltage ELVDD.

[0195] Despite Fig.11 Although not shown, the first conductive layer CL1 ′ may further include an eighth gate pattern extending in the first direction DR1 and supplied with the common voltage ELVSS.

[0196] Further references Fig.12 , the protective layer (e.g., Fig. 9 A protective layer PVX of a first conductive layer CL1' may be arranged on the first conductive layer CL1', a via insulating layer VIA may be arranged on the protective layer, and a second conductive layer CL2' may be arranged on the via insulating layer VIA. The second conductive layer CL2' may include a driving voltage wiring 2210, a light emitting element connecting electrode 2220, an initialization voltage wiring 2230, a common voltage wiring 2240, and a data wiring 2250. The driving voltage wiring 2210, the light emitting element connecting electrode 2220, the initialization voltage wiring 2230, the common voltage wiring 2240, and the data wiring 2250 may be arranged on the same layer and may include the same substance.

[0197] The driving voltage wiring 2210 may extend in the second direction DR2. The driving voltage wiring 2210 may be connected to the seventh gate pattern 2170 through a contact hole. Accordingly, the driving voltage ELVDD may be provided to the driving voltage wiring 2210.

[0198] In one embodiment, the driving voltage wiring 2210 overlapping the Nth pixel circuit area PXA(N) may provide the driving voltage ELVDD to the first transistor T1 included in the Nth pixel circuit.

[0199] The driving voltage wiring 2210 may be connected to the 2-1st gate pattern 2121 through a contact hole. Accordingly, the driving voltage wiring 2210 may provide the driving voltage ELVDD to the 2-1st gate pattern 2121. Specifically, the driving voltage wiring 2210 may provide the driving voltage ELVDD to the first transistor T1 of the first sub-pixel circuit included in the Nth pixel circuit through the 2-1st gate pattern 2121.

[0200] The driving voltage wiring 2210 may be connected to the 2-2nd gate pattern 2122 through a contact hole. Accordingly, the driving voltage wiring 2210 may provide the driving voltage ELVDD to the 2-2nd gate pattern 2122. Specifically, the driving voltage wiring 2210 may provide the driving voltage ELVDD to the first transistor T1 of the second sub-pixel circuit included in the Nth pixel circuit through the 2-2nd gate pattern 2122.

[0201] The driving voltage wiring 2210 may be connected to the 2-3rd gate pattern 2123 through a contact hole. Accordingly, the driving voltage wiring 2210 may provide the driving voltage ELVDD to the 2-3rd gate pattern 2123. Specifically, the driving voltage wiring 2210 may provide the driving voltage ELVDD to the first transistor T1 of the third sub-pixel circuit included in the Nth pixel circuit through the 2-3rd gate pattern 2123.

[0202] The light emitting element connection electrode 2220 may provide the driving current to the light emitting element LD. For example, the light emitting element connection electrode 2220 may be referred to as an upper light emitting element connection electrode. The light emitting element connection electrode 2220 may include a first light emitting element connection electrode 2221 , a second light emitting element connection electrode 2222 , and a third light emitting element connection electrode 2223 .

[0203] The first light emitting element connection electrode 2221 may be connected to the 3-1 th gate pattern 2131 through a contact hole. Accordingly, the first light emitting element connection electrode 2221 may provide the first driving current to the light emitting element LD included in the first sub-pixel SPX1.

[0204] The second light emitting element connection electrode 2222 may be connected to the 3-2 th gate pattern 2132 through a contact hole. Accordingly, the second light emitting element connection electrode 2222 may provide the second driving current to the light emitting element LD included in the second sub-pixel SPX2.

[0205] The third light emitting element connection electrode 2223 may be connected to the 3-3rd gate pattern 2133 through the contact hole. Accordingly, the third light emitting element connection electrode 2223 may provide the third driving current to the light emitting element LD included in the third sub-pixel SPX3.

[0206] The initialization voltage wiring 2230 may extend in the second direction DR2 and may be spaced apart from the light emitting element connection electrode 2220. The initialization voltage VINT may be supplied to the initialization voltage wiring 2230. The initialization voltage wiring 2230 may be connected to the 6-1st gate pattern 2161 and the 6-2nd gate pattern 2162 through the contact hole. Accordingly, the initialization voltage VINT may be supplied to the 6-1st gate pattern 2161 and the 6-2nd gate pattern 2162.

[0207] The common voltage wiring 2240 may extend in the second direction DR2 and may be adjacent to the initialization voltage wiring 2230 in the first direction DR1. The common voltage wiring 2240 may be provided with a common voltage ELVSS.

[0208] Each of the data wirings 2250 may extend in the second direction DR2. The data wirings 2250 may be separated from the initialization voltage wiring 2230 in the first direction DR1 via the common voltage wiring 2240. The data wirings 2250 may include a first data wiring 2251, a second data wiring 2252, and a third data wiring 2253.

[0209] The red data voltage may be provided to the first data wiring 2251. The first data wiring 2251 may be connected to the 4-1th gate pattern 2141 through a contact hole. Accordingly, the red data voltage may be provided to the 4-1th gate pattern 2141.

[0210] The green data voltage may be provided to the second data wiring 2252. The second data wiring 2252 may be connected to the 4-2nd gate pattern 2142 through a contact hole. Accordingly, the green data voltage may be provided to the 4-2nd gate pattern 2142.

[0211] The blue data voltage may be provided to the third data wiring 2253. The third data wiring 2253 may be connected to the 4-3rd gate pattern 2143 through a contact hole. Accordingly, the blue data voltage may be provided to the 4-3rd gate pattern 2143.

[0212] Since the data wiring 2250 is separated from the initialization voltage wiring 2230 via the common voltage wiring 2240 along the first direction DR1, the parasitic capacitance formed between the initialization voltage wiring 2230 and the data wiring 2250 can be reduced. That is, the common voltage wiring 2240 is arranged between the initialization voltage wiring 2230 and the data wiring 2250, so that the formation of the parasitic capacitance can be suppressed. Accordingly, the occurrence of horizontal crosstalk in the display device DD2 can be reduced, and the display quality of the display device DD2 can be improved.

[0213] When compared with the display device DD according to an embodiment of the present invention, compared with the display device DD in which the driving voltage wiring 1240 suppresses the formation of the parasitic capacitance, in the display device DD2 according to another embodiment of the present invention, the common voltage wiring 2240 can suppress the formation of the parasitic capacitance.

[0214] In one embodiment, the driving voltage wiring 2210, the common voltage wiring 2240, and the data wiring 2250 may be arranged in the order of the common voltage wiring 2240, the data wiring 2250, and the driving voltage wiring 2210 along the first direction DR1. Fig.12 Although not shown, the driving voltage wiring 2210 overlapping the N+1 pixel circuit region PXA(N+1) and the data wiring 2250 overlapping the N pixel circuit region PXA(N) may be adjacent to each other along the first direction DR1. For example, the driving voltage wiring 2210, the common voltage wiring 2240, and the data wiring 2250 may be arranged in the order of the common voltage wiring 2240, the first data wiring 2251, the third data wiring 2253, the second data wiring 2252, and the driving voltage wiring 2210 overlapping the N+1 pixel circuit region PXA(N+1) along the first direction DR1.

[0215] Fig.13 is a cross-sectional view showing a display device according to still another embodiment of the present invention.

[0216] Reference Fig.13 According to another embodiment of the present invention, a display device DD3 may include a substrate SUB, a circuit layer CL", a light-emitting element LD, a pixel definition film PDL and an encapsulation layer TFE. The circuit layer CL" may include a lower electrode layer BML, a buffer layer BUF, an active pattern ACT, a gate insulating layer GI, a first conductive layer CL1, a protective layer PVX, a first via insulating layer VIA1, a connecting electrode LCE and a second via insulating layer VIA2. The lower electrode layer BML may include a first lower electrode BE1 and a second lower electrode BE2. The first conductive layer CL1 may include a first electrode E1, a second electrode E2 and a gate electrode GE. The light-emitting element LD may include a pixel electrode PE, a light-emitting layer EML and a common electrode CE. In the following, the contents described with reference to FIG. 3 are omitted or simplified. Figures 1 to 4 The display device DD describes the repeated content.

[0217] A first via insulating layer VIA1 may be arranged on the protective layer PVX. The first via insulating layer VIA1 may include an organic insulating material. A connecting electrode LCE may be arranged on the first via insulating layer VIA1. The connecting electrode LCE may be electrically connected to the first electrode E1 through a contact hole that passes through the first via insulating layer VIA1 and the protective layer PVX. Accordingly, the connecting electrode LCE may electrically connect the thin film transistor TFT and the light emitting element LD. For example, the connecting electrode LCE may include a metal, an alloy, a metal nitride, a conductive metal oxide, a transparent conductive material, etc. These may be used alone or in combination with each other.

[0218] A second via insulating layer VIA2 may be disposed on the first via insulating layer VIA1. The second via insulating layer VIA2 may cover the connection electrode LCE. The second via insulating layer VIA2 may include an organic insulating substance.

[0219] A pixel electrode PE may be disposed on the second via insulating layer VIA2 and connected to the connection electrode LCE through a contact hole penetrating the second via insulating layer VIA2.

[0220] Fig.14 and Fig.15 It is shown that the Fig.13 For example, Fig.14 and Fig.15 It is shown Fig.13 Layout diagram of the circuit layer CL". The following description will focus on the Nth pixel circuit arranged in the Nth pixel circuit area PXA(N). Fig.14 and Fig.15 At least a part of the constituent elements shown in may be connected to each other between pixel circuits.

[0221] The display device DD3 may be similar to the reference 2 except that it further includes a third conductive layer CL3″ disposed on the second conductive layer CL2″, the second conductive layer CL2″ includes a driving voltage wiring 3230, and the third conductive layer CL3″ includes a common voltage wiring 3320. Figures 5 to 8 The display devices DD described are substantially identical.

[0222] That is, the lower electrode layer BML of the display device DD3 can be connected to Figure 5 The lower electrode layer BML of the display device DD shown in FIG. 1 is substantially the same as that of the display device DD3. Figure 6 The active pattern ACT of the display device DD shown in FIG. 1 is substantially the same as that of the active pattern ACT of the display device DD shown in FIG. Figure 7 The first conductive layer CL1 of the display device DD shown in FIG. Figures 5 to 7The display device DD describes the repeated content.

[0223] Reference Figure 1 , Figure 3 , Figure 7 and Fig.14 , the protection layer may be disposed on the first conductive layer CL1, and the first via insulating layer VIA1 may be disposed on the protection layer. The second conductive layer CL2 ″ may be disposed on the first via insulating layer VIA1.

[0224] The second conductive layer CL2″ may include a first light emitting element connection electrode 3210, an initialization voltage wiring 3220, a driving voltage wiring 3230, and a data wiring 3240. The first light emitting element connection electrode 3210, the initialization voltage wiring 3220, the driving voltage wiring 3230, and the data wiring 3240 may be arranged in the same layer and may include the same material.

[0225] The first light emitting element connection electrode 3210 may provide a driving current to the light emitting element LD. For example, the first light emitting element connection electrode 3210 may be referred to as an intermediate light emitting element connection electrode. The first light emitting element connection electrode 3210 may include a 1-1st light emitting element connection electrode 3211, a 1-2nd light emitting element connection electrode 3212, and a 1-3rd light emitting element connection electrode 3213.

[0226] The 1-1 light emitting element connection electrode 3211 can be connected to the Figure 7 The 6-1st gate pattern 1161. Accordingly, the 1-1st light emitting element connection electrode 3211 may provide the first driving current to the light emitting element LD included in the first sub-pixel SPX1.

[0227] The 1-2 light emitting element connection electrode 3212 can be connected to the Figure 7 The 6-2 th gate pattern 1162. Accordingly, the 1-2 th light emitting element connection electrode 3212 can provide the second driving current to the light emitting element LD included in the second sub-pixel SPX2.

[0228] The 1st to 3rd light emitting element connection electrode 3213 can be connected to the Figure 7 The 6-3rd gate pattern 1163. Accordingly, the 1-3rd light emitting element connection electrode 3213 can provide the third driving current to the light emitting element LD included in the third sub-pixel SPX3.

[0229] The initialization voltage wiring 3220 may extend in the second direction DR2 and may be spaced apart from the first light emitting element connection electrode 3210. The initialization voltage VINT may be provided to the initialization voltage wiring 3220. The initialization voltage wiring 3220 may be connected to the first light emitting element connection electrode 3210 through a contact hole. Figure 7The 7-1st gate pattern 1171 and the 7-2nd gate pattern 1172 are provided. Figure 7 The 7-1st gate pattern 1171 and the 7-2nd gate pattern 1172.

[0230] The driving voltage wiring 3230 may extend in the second direction DR2 and may be adjacent to the initialization voltage wiring 3220 in the first direction DR1. The driving voltage wiring 3230 may be connected to the initialization voltage wiring 3220 through a contact hole. Figure 7 The first gate pattern 1110 is formed by a first gate electrode 1110. Accordingly, the driving voltage ELVDD may be provided to the driving voltage wiring 3230.

[0231] In one embodiment, the driving voltage wiring 3230 overlapping the Nth pixel circuit area PXA(N) may provide the driving voltage ELVDD to the first transistor T1 included in the N+1th pixel circuit.

[0232] The driving voltage wiring 3230 can be connected to the Figure 7 The driving voltage wiring 3230 may provide the driving voltage ELVDD to the 5-1st gate pattern 1151 , the 5-2nd gate pattern 1152 , and the 5-3rd gate pattern 1153 .

[0233] Each data wiring 3240 may extend in the second direction DR2. The data wiring 3240 may be spaced apart from the initialization voltage wiring 3220 in the first direction DR1 via the driving voltage wiring 3230. The data wiring 3240 may include a first data wiring 3241, a second data wiring 3242, and a third data wiring 3243.

[0234] A red data voltage may be provided to the first data wiring 3241. The first data wiring 3241 may be connected to the Figure 7 The 4-1 gate pattern 1141. Accordingly, the red data voltage may be provided to Figure 7 The 4-1 gate pattern 1141.

[0235] A green data voltage may be provided to the second data wiring 3242. The second data wiring 3242 may be connected to the Figure 7 The 4-2 gate pattern 1142. Accordingly, the green data voltage may be provided to Figure 7 The 4-2 gate pattern 1142.

[0236] A blue data voltage may be provided to the third data wiring 3243. The third data wiring 3243 may be connected to the Figure 7The 4-3 gate pattern 1143. Accordingly, the blue data voltage may be provided to Figure 7 The 4-3 gate pattern 1143.

[0237] Since the data wiring 3240 is separated from the initialization voltage wiring 3220 via the driving voltage wiring 3230 along the first direction DR1, it is possible to reduce parasitic capacitance formed between the initialization voltage wiring 3220 and the data wiring 3240. That is, the driving voltage wiring 3230 is arranged between the initialization voltage wiring 3220 and the data wiring 3240, thereby suppressing the formation of the parasitic capacitance.

[0238] Further references Fig.15 , the second via insulating layer VIA2 may be disposed on the second conductive layer CL2″, and the third conductive layer CL3″ may be disposed on the second via insulating layer VIA2. The third conductive layer CL3″ may include a second light emitting element connecting electrode 3310 and a common voltage wiring 3320. The second light emitting element connecting electrode 3310 and the common voltage wiring 3320 may be disposed on the same layer and may include the same substance.

[0239] The second light emitting element connection electrode 3310 may provide the driving current to the light emitting element LD. For example, the second light emitting element connection electrode 3310 may be referred to as an upper light emitting element connection electrode. The second light emitting element connection electrode 3310 may include a 2-1st light emitting element connection electrode 3311, a 2-2nd light emitting element connection electrode 3312, and a 2-3rd light emitting element connection electrode 3313.

[0240] The 2-1st light emitting element connection electrode 3311 may be connected to the 1-1st light emitting element connection electrode 3211 through a contact hole. Accordingly, the 2-1st light emitting element connection electrode 3311 may provide the first driving current to the light emitting element LD included in the first sub-pixel SPX1.

[0241] The 2-2nd light emitting element connection electrode 3312 may be connected to the 1-2nd light emitting element connection electrode 3212 through a contact hole. Accordingly, the 2-2nd light emitting element connection electrode 3312 may provide the second driving current to the light emitting element LD included in the second sub-pixel SPX2.

[0242] The 2-3rd light emitting element connection electrode 3313 may be connected to the 1-3rd light emitting element connection electrode 3213 through a contact hole. Accordingly, the 2-3rd light emitting element connection electrode 3313 may provide the third driving current to the light emitting element LD included in the third sub-pixel SPX3.

[0243] The common voltage wiring 3320 may extend in the second direction DR2 and may be spaced apart from the second light emitting element connection electrode 3310. The common voltage wiring 3320 may be connected to the second light emitting element connection electrode 3310 through a contact hole. Figure 7 The eighth gate pattern 1180 is formed. Accordingly, the common voltage ELVSS may be provided to the common voltage wiring 3320.

[0244] In one embodiment, the driving voltage wiring 3230 and the common voltage wiring 3320 may be arranged at different layers from each other. For example, the second conductive layer CL2 ″ may include the driving voltage wiring 3230 , and the third conductive layer CL3 ″ may include the common voltage wiring 3320 .

[0245] When compared with the display device DD according to an embodiment of the present invention, the second conductive layer CL2 includes Figure 8 Compared with the common voltage wiring 1210, in a display device DD3 according to another embodiment of the present invention, the third conductive layer CL3" may include a common voltage wiring 3320. That is, in the display device DD3, the second conductive layer CL2 may not include the common voltage wiring 3320. Accordingly, since the space utilization rate of the circuit layer CL" is relatively increased, the resolution of the display device DD3 can be relatively increased.

[0246] The above description is made with reference to the exemplary embodiments of the present invention, but anyone with ordinary knowledge in the technical field to which the present invention belongs will understand that various modifications and changes can be made to the present invention without departing from the concept and scope of the present invention as described in the claims.

[0247] Industrial Applicability

[0248] The present invention can be applied to various display devices that can be equipped with a display device. For example, the present invention can be applied to various display devices such as vehicle display devices, ship display devices, aircraft display devices, portable communication devices, display devices for demonstration or information transmission, medical display devices, etc.

Claims

1. A display device, comprising: A substrate, comprising a first pixel circuit region to an N-th pixel circuit region arranged along a first direction, wherein N is a natural number greater than 1; an initialization voltage wiring, arranged on the substrate, extending along a second direction intersecting the first direction, and overlapping any one of the first pixel circuit region to the Nth pixel circuit region; a driving voltage wiring arranged on the substrate, extending along the second direction, and adjacent to the initialization voltage wiring along the first direction; and The data wiring is arranged on the substrate, extends along the second direction, and is separated from the initialization voltage wiring via the driving voltage wiring along the first direction.

2. The display device according to claim 1, further comprising: The first pixel circuit to the Nth pixel circuit are arranged in the first pixel circuit area to the Nth pixel circuit area, respectively. Wherein, each of the first pixel circuit to the Nth pixel circuit comprises: A driving transistor provides a driving current; a first switching transistor, providing a data voltage to the driving transistor; and The second switch transistor provides an initialization voltage to the driving transistor.

3. The display device according to claim 2, wherein: A gate electrode of the first switch transistor and a gate electrode of the second switch transistor receive the same signal as each other.

4. The display device according to claim 2, wherein: The driving voltage wiring overlaps each of the first pixel circuit region to the Nth pixel circuit region, The driving voltage wiring overlapping the N-1th pixel circuit region supplies a driving voltage to the driving transistor included in the Nth pixel circuit.

5. The display device according to claim 1, further comprising: a common voltage wiring, arranged on the substrate and extending along the second direction, The common voltage wiring, the driving voltage wiring and the data wiring are arranged in the order of the driving voltage wiring, the data wiring and the common voltage wiring along the first direction.

6. The display device according to claim 5, wherein: The driving voltage wiring and the common voltage wiring are arranged in the same layer as each other.

7. The display device according to claim 5, wherein: The driving voltage wiring and the common voltage wiring are arranged at different layers from each other.

8. The display device according to claim 5, further comprising: an active pattern, arranged on the substrate and overlapping the first pixel circuit region to the Nth pixel circuit region; a first conductive layer disposed on the active pattern and including a gate electrode; and The second conductive layer is arranged on the first conductive layer.

9. The display device according to claim 8, wherein: The second conductive layer includes the driving voltage wiring and the common voltage wiring.

10. The display device according to claim 8, further comprising: A third conductive layer is arranged on the second conductive layer, wherein the second conductive layer includes the driving voltage wiring, The third conductive layer includes the common voltage wiring.

11. The display device according to claim 8, wherein: The active pattern includes an oxide semiconductor.

12. A display device, comprising: A substrate, comprising a first pixel circuit region to an N-th pixel circuit region arranged along a first direction, wherein N is a natural number greater than 1; an initialization voltage wiring, arranged on the substrate, extending along a second direction intersecting the first direction, and overlapping any one of the first pixel circuit region to the Nth pixel circuit region; a common voltage wiring arranged on the substrate, extending along the second direction, and adjacent to the initialization voltage wiring along the first direction; and The data wiring is arranged on the substrate, extends along the second direction, and is separated from the initialization voltage wiring via the common voltage wiring along the first direction.

13. The display device according to claim 12, further comprising: The first pixel circuit to the Nth pixel circuit are arranged in the first pixel circuit area to the Nth pixel circuit area, respectively. Wherein, each of the first pixel circuit to the Nth pixel circuit comprises: A driving transistor provides a driving current; a first switching transistor, providing a data voltage to the driving transistor; and The second switch transistor provides an initialization voltage to the driving transistor.

14. The display device according to claim 13, wherein: A gate electrode of the first switch transistor and a gate electrode of the second switch transistor receive the same signal as each other.

15. The display device according to claim 13, further comprising: a driving voltage wiring, arranged on the substrate and extending along the second direction, The driving voltage wiring, the common voltage wiring and the data wiring are arranged in the order of the common voltage wiring, the data wiring and the driving voltage wiring along the first direction.

16. The display device according to claim 15, wherein: The driving voltage wiring overlaps each of the first pixel circuit region to the Nth pixel circuit region, The driving voltage wiring overlapping the Nth pixel circuit region supplies a driving voltage to the driving transistor included in the Nth pixel circuit.

17. The display device according to claim 15, wherein: The driving voltage wiring and the common voltage wiring are arranged in the same layer as each other.

18. The display device according to claim 15, further comprising: an active pattern, arranged on the substrate and overlapping the first pixel circuit region to the Nth pixel circuit region; a first conductive layer disposed on the active pattern and including a gate electrode; and The second conductive layer is arranged on the first conductive layer.

19. The display device according to claim 18, wherein: The second conductive layer includes the driving voltage wiring and the common voltage wiring.

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