Method of manufacturing heat dissipation adhesive layer for display device and display device

Abstract

The invention discloses a method of manufacturing a heat dissipation adhesive layer for a display device and the display device. The method of manufacturing a heat-dissipating adhesive layer for a display device includes: providing a pad, a first coating layer on the pad, and a heat-dissipating layer on the first coating layer; forming a mask dam surrounding the heat dissipation layer; and forming a second coating layer inside the mask dam.

Description

[0001] CROSS-REFERENCE TO RELATED APPLICATIONS

[0002] This application claims priority to and all rights and benefits derived from Korean Patent Application No. 10-2023-0127652 filed in the Korean Intellectual Property Office on September 25, 2023, the contents of which are incorporated herein by reference in their entirety. Technical Field

[0003] The present disclosure relates to a display device and a method of manufacturing a heat dissipation adhesive layer for the display device. Background Art

[0004] As the information society develops, the demand for display devices has increased and diversified. Display devices include liquid crystal displays (LCDs), field emission displays (FEDs), and light emitting displays (LEDs). Light emitting displays include organic light emitting displays whose light emitting elements are organic light emitting diode elements and inorganic light emitting displays whose light emitting elements are inorganic light emitting diode elements.

[0005] Light-emitting displays are widely used in mobile electronic devices such as smart phones and are susceptible to external impacts. In addition, when excessive heat is generated from a light-emitting element or a driver chip that drives the light-emitting element or other components, there is a risk of damage to the light-emitting element. In order to protect the display device from such risks, a cover plate having various functions such as a heat dissipation function and a buffering function may be attached to the lower surface of the display panel as a member. Summary of the invention

[0006] Aspects of the present disclosure provide a display device capable of minimizing a peeling phenomenon of a heat dissipation layer and a method of manufacturing a heat dissipation adhesive layer for the display device.

[0007] Aspects of the present disclosure also provide a display device capable of preventing a step of a heat dissipation layer from being observed and a method of manufacturing a heat dissipation adhesive layer for the display device.

[0008] However, aspects of the present disclosure are not limited to the aspects set forth herein. The above and other aspects of the present disclosure will become more apparent to those skilled in the art to which the present disclosure pertains by referring to the detailed description of the present disclosure given below.

[0009] An embodiment of a method of manufacturing a heat dissipation adhesive layer for a display device includes providing a gasket, a first coating layer on the gasket, and a heat dissipation layer on the first coating layer; forming a mask dam surrounding the heat dissipation layer; and forming a second coating layer inside the mask dam.

[0010] In an embodiment, the heat dissipation layer includes a body portion and an opening hole penetrating the heat dissipation layer.

[0011] In an embodiment, the second coating fills the open pores.

[0012] In an embodiment, the upper surface of the second coating layer includes a ridge portion overlapping the body portion and a valley portion overlapping the opening hole.

[0013] In an embodiment, a height difference between the ridge portion and the valley portion is 5 μm or less.

[0014] In an embodiment, the second coating layer includes a flat portion and an inclined portion provided on one side of the flat portion.

[0015] In an embodiment, the upper surface of the second coating layer includes a ridge portion and a valley portion located at a lower level than the ridge portion, and in the flat portion, a height difference between the ridge portion and the valley portion is 5 μm or less.

[0016] In an implementation, the method of manufacturing a heat dissipation adhesive layer for a display device may further include cutting the second coating layer along an inner side of the mask dam.

[0017] In an embodiment, the cut line of the second coating overlaps with the flat portion of the second coating.

[0018] In an embodiment, an upper surface of the second coating layer is higher than an upper surface of the mask dam.

[0019] In an embodiment, the second coating covers at least a portion of an upper surface of the mask dam.

[0020] In an embodiment, the thickness of the mask dam is greater than or equal to the thickness of the heat dissipation layer.

[0021] In an embodiment, the mask dam is disposed directly on the upper surface of the first coating layer.

[0022] In an embodiment, the mask dam is disposed directly on the upper surface of the liner and surrounds the first coating layer.

[0023] In an embodiment, an inner side surface of the mask dam is spaced apart from a side surface of the first coating layer.

[0024] An embodiment of the display device includes a display panel and a lower panel component, the lower panel component includes a heat dissipation adhesive layer and is arranged on the rear surface of the display panel, wherein the heat dissipation adhesive layer includes a first coating layer, a heat dissipation layer arranged on the first coating layer, and a second coating layer covering the heat dissipation layer, and the upper surface of the second coating layer is a flat surface.

[0025] In an embodiment, the upper surface of the second coating layer includes a ridge portion and a valley portion, and the ridge portion is located at a higher level than the valley portion.

[0026] In an embodiment, a height difference between the ridge portion and the valley portion is 10% or less of the thickness of the second coating layer.

[0027] In an embodiment, a height difference between the ridge portion and the valley portion is 5 μm or less.

[0028] In an embodiment, the panel lower member further includes a shielding layer, an adhesive layer, and a buffer layer, the adhesive layer is disposed on the shielding layer, the buffer layer is disposed on the adhesive layer, and the heat dissipation adhesive layer is disposed on the buffer layer.

[0029] With the display device and the method of manufacturing the display device according to the embodiments of the present disclosure, it is possible to minimize the peeling phenomenon of the heat dissipation layer.

[0030] With the display device and the method of manufacturing the display device according to the embodiments of the present disclosure, it is possible to prevent the step of the heat dissipation layer from being observed.

[0031] The effects of the present disclosure are not limited to the aforementioned effects, and various other effects are included in this specification. BRIEF DESCRIPTION OF THE DRAWINGS

[0032] The above and other aspects and features of the present disclosure will become more apparent by describing in detail embodiments of the present disclosure with reference to the accompanying drawings, in which:

[0033] Figure 1 is a perspective view showing an electronic device according to an embodiment;

[0034] Figure 2 is a perspective view showing a display device included in an electronic device according to an embodiment;

[0035] Figure 3 is a cross-sectional view showing a display device according to an embodiment;

[0036] Figure 4 is a cross-sectional view showing a display panel according to an embodiment;

[0037] Figure 5 is a cross-sectional view showing a panel lower member according to an embodiment;

[0038] Figure 6 is a plan view showing a heat dissipation adhesive layer according to an embodiment;

[0039] Figure 7 It is along Figure 6 A cross-sectional view taken along the line X1-X1';

[0040] Figure 8 yes Figure 7 An enlarged view of area A in FIG.

[0041] Fig. 9 is a diagram showing a graph of flatness of a heat dissipation adhesive layer according to the related art;

[0042] Fig.10 is a diagram showing a graph of flatness of a heat dissipation adhesive layer according to an embodiment;

[0043] Fig.11 is a flowchart showing a method of manufacturing a heat dissipation adhesive layer for a display device according to an embodiment;

[0044] Fig.12 It is shown Fig.11 A cross-sectional view of S100 in FIG.

[0045] Fig.13 It is shown Fig.11 A cross-sectional view of the S200 in FIG.

[0046] Fig.14 It is shown Fig.11 A cross-sectional view of the S300 in FIG.

[0047] Fig.15 It is shown Fig.11 The plan view of the S400 in the figure;

[0048] Fig.16 It is shown Fig.11 A cross-sectional view of the S400 in FIG.

[0049] Fig.17 is a cross-sectional view showing S400_1 of a method of manufacturing a heat dissipation adhesive layer for a display device according to another embodiment;

[0050] Fig.18 is a cross-sectional view showing S400_2 of a method for manufacturing a heat dissipation adhesive layer for a display device according to still another embodiment;

[0051] Fig.19 It is shown Fig.11 A cross-sectional view of the S500 in FIG.

[0052] Fig. 20 is a cross-sectional view showing S500_1 of a method of manufacturing a heat dissipation adhesive layer for a display device according to another embodiment;

[0053] Fig.21 is a cross-sectional view showing S500_2 of a method for manufacturing a heat dissipation adhesive layer for a display device according to still another embodiment;

[0054] Fig. 22 It is shown Fig.11 A cross-sectional view of the S600 in FIG.

[0055] Fig.23 It is shown Fig.11 A cross-sectional view of the S600. DETAILED DESCRIPTION

[0056] The present invention will now be described more fully hereinafter with reference to the accompanying drawings showing preferred embodiments of the present invention. However, the present invention may be implemented in different forms and should not be construed as being limited to the embodiments set forth herein. On the contrary, these embodiments are provided so that this disclosure will be thorough and complete, and the scope of the present invention will be fully communicated to those skilled in the art.

[0057] It will also be understood that when a layer is referred to as being 'on' another layer or substrate, it can be directly on the other layer or substrate, or intervening layers may also be present. The same reference numerals refer to the same components throughout the specification.

[0058] Hereinafter, embodiments of the present disclosure will be described in detail with reference to the accompanying drawings.

[0059] Figure 1 is a perspective view showing an electronic device according to an embodiment.

[0060] refer to Figure 1 , the electronic device 1 displays a moving image or a still image. The electronic device 1 may refer to all electronic devices that provide a display screen. For example, the electronic device 1 may include a television, a laptop computer, a monitor, a billboard, an Internet of Things (IoT) device, a mobile phone, a smart phone, a tablet personal computer (PC), an electronic watch, a smart watch, a watch phone, a head-mounted display, a mobile communication terminal, an electronic notebook, an electronic book, a portable multimedia player (PMP), a navigation device, a game console, a digital camera, a camcorder, and the like that provide a display screen.

[0061] The electronic device 1 may include a display device 10 (see Figure 2 ). Examples of display devices may include inorganic light emitting displays, organic light emitting displays, quantum dot light emitting displays, plasma display panels, field emission displays, and the like. Hereinafter, a case where an organic light emitting display is applied as an example of a display device will be described by way of example, but the present disclosure is not limited thereto, and if applicable, the same technical spirit may be applied to other display devices.

[0062] The shape of the electronic device 1 may be modified in various ways. For example, the electronic device 1 may have a shape such as a rectangular shape with a width greater than a length, a rectangular shape with a length greater than a width, a square shape, a quadrilateral shape with rounded corners (vertices), other polygonal shapes, or a circular shape. The shape of the display area DA of the electronic device 1 may also be similar to the overall shape of the electronic device 1. Figure 1 , the electronic device 1 having a rectangular shape having a greater length in the second direction DR2 has been shown.

[0063] In the drawings, the first direction DR1 and the second direction DR2 are respectively horizontal directions and intersect each other. For example, the first direction DR1 and the second direction DR2 may be orthogonal to each other. In addition, the third direction DR3 may be a vertical direction intersecting (e.g., orthogonal to) the first direction DR1 and the second direction DR2. In this specification, the direction indicated by the arrows of the first direction DR1, the second direction DR2, and the third direction DR3 may be referred to as one side, and the direction opposite to the one side may be referred to as the other side.

[0064] The electronic device 1 may include a display area DA and a non-display area NDA. The display area DA is an area where a picture can be displayed, and the non-display area NDA is an area where a picture is not displayed. The display area DA may also be referred to as an active area, and the non-display area NDA may also be referred to as a non-active area. The display area DA may occupy approximately the center of the electronic device 1.

[0065] The display area DA may include a first display area DA1, a second display area DA2, and a third display area DA3. The second display area DA2 and the third display area DA3 may be components CMP (see FIG. 1 ) provided to add various functions to the electronic device 1. Figure 3 ) area.

[0066] Figure 2 is a perspective view showing a display device included in an electronic device according to an embodiment.

[0067] refer to Figure 2 According to the electronic device 1 of the embodiment (for example, referring to Figure 1 ) may include a display device 10. The display device 10 may provide a screen displayed on the electronic device 1. In a plan view, the display device 10 may have a shape similar to that of the electronic device 1. For example, the display device 10 may have a shape similar to a rectangular shape having short sides in a first direction DR1 and long sides in a second direction DR2. Corners where the short sides in the first direction DR1 and the long sides in the second direction DR2 intersect may be rounded with a curvature, but are not limited thereto, and may also be at right angles. In a plan view, the shape of the display device 10 is not limited to a rectangular shape, and may be a shape similar to other polygonal shapes, a circular shape, or an elliptical shape.

[0068] The display device 10 may include a display panel 100 , a display driver DIC, a circuit board PCB, and a touch driver TIC.

[0069] The display panel 100 may include a main area MA and a sub area SBA.

[0070] The main area MA may include a display area DA including pixels displaying an image and a non-display area NDA disposed around the display area DA. The display area DA may include a first display area DA1, a second display area DA2, and a third display area DA3. The display area DA may emit light from a plurality of emission areas or a plurality of opening areas. For example, the display panel 100 may include a pixel circuit including a switching element, a pixel defining film defining an emission area or an opening area, and a self-luminous element.

[0071] For example, the self-luminous element may include at least one of an organic light emitting diode (organic LED, OLED) including an organic light emitting layer, a quantum dot LED including a quantum dot light emitting layer, an inorganic LED including an inorganic semiconductor, and a micro LED, but is not limited thereto.

[0072] The non-display area NDA may be an area outside the display area DA. The non-display area NDA may be defined as an edge area of ​​the main area MA of the display panel 100. The non-display area NDA may include a gate driver supplying a gate signal to a gate line and a fan-out line connecting the display driver DIC and the display area DA to each other.

[0073] The sub-region SBA may be a region extending from one side of the main region MA. The sub-region SBA may include a flexible material that may be bent, folded, and curled. For example, when the sub-region SBA is bent, the sub-region SBA may overlap the main region MA in the thickness direction (third direction DR3). The sub-region SBA may include a display driver DIC and a pad component connected to a circuit board PCB. In another embodiment, the sub-region SBA may be omitted, and the display driver DIC and the pad component may be disposed in the non-display area NDA.

[0074] The display driver DIC may output signals and voltages for driving the display panel 100. The display driver DIC may supply data voltages to data lines. The display driver DIC may supply power voltages to power lines and supply gate control signals to gate drivers. The display driver DIC may be formed as an integrated circuit (IC) and mounted on the display panel 100 in a chip on glass (COG) manner, a chip on plastic (COP) manner, or an ultrasonic bonding manner. As another example, the display driver DIC may be mounted on a circuit board PCB.

[0075] The circuit board PCB may be attached to the pad part of the display panel 100 using an adhesive member. As an example, the adhesive member may be a non-conductive film (NCF). As another example, the adhesive member may be an anisotropic conductive film (ACF) or a self-assembled anisotropic conductive paste (SAP).

[0076] The leads of the circuit board PCB may be electrically connected to the pad part of the display panel 100. The circuit board PCB may be a flexible printed circuit board, a rigid printed circuit board, or a flexible film such as a chip on film.

[0077] The touch driver TIC may be mounted on a circuit board PCB. The touch driver TIC may be connected to a touch sensing unit of the display panel 100. The touch driver TIC may supply a touch drive signal to a plurality of touch electrodes of the touch sensing unit and sense the amount of capacitance change between the plurality of touch electrodes. For example, the touch drive signal may be a pulse signal having a predetermined frequency. The touch driver TIC may determine whether an input has occurred and calculate input coordinates based on the amount of capacitance change between the plurality of touch electrodes. The touch driver TIC may be formed as an integrated circuit (IC).

[0078] Figure 3 is a cross-sectional view showing a display device according to an embodiment.

[0079] refer to Figure 3 , the display device 10 may include a display panel 100 , an optical member 200 , a window member 300 , a lower film 400 , a panel lower member 500 , and a cover spacer 600 .

[0080] The display panel 100 may include a substrate SUB, a display layer DU, and a touch sensing layer TSU (eg, a touch layer). The display layer DU may include a thin film transistor layer TFTL (eg, a circuit layer), a light emitting element layer EML, and a thin film encapsulation layer TFEL.

[0081] The substrate SUB may be a base substrate or a base member. The substrate SUB may be a flexible substrate that can be bent, folded, and curled. For example, the substrate SUB may include a polymer resin such as polyimide (PI), but is not limited thereto. In another embodiment, the substrate SUB may include a glass material or a metal material.

[0082] The thin film transistor layer TFTL may be disposed on the substrate SUB. The thin film transistor layer TFTL may include a plurality of thin film transistors constituting a pixel circuit of a pixel. The thin film transistor layer TFTL may further include a gate line, a data line, a power line, a gate control line, a fan-out line connecting the display driver DIC and the data line to each other, and a lead connecting the display driver DIC and the pad part to each other.

[0083] Each of the thin film transistors may include a semiconductor region, a source electrode, a drain electrode, and a gate electrode. For example, when the gate driver is formed on one side of the non-display area NDA of the display panel 100, the gate driver may include a thin film transistor.

[0084] The thin film transistor layer TFTL may be disposed in the display area DA, the non-display area NDA, and the sub-area SBA. In some embodiments, the thin film transistor, the gate line, the data line, and the power line of each of the pixels in the thin film transistor layer TFTL may be disposed in the display area DA, but is not limited thereto. In some embodiments, the gate control line and the fan-out line of the thin film transistor layer TFTL may be disposed in the non-display area NDA, but is not limited thereto. In some embodiments, the lead line of the thin film transistor layer TFTL may be disposed in the sub-area SBA, but is not limited thereto.

[0085] The light emitting element layer EML may be disposed on the thin film transistor layer TFTL. The light emitting element layer EML may include a plurality of light emitting elements each including a first electrode, a second electrode, and a light emitting layer emitting light, and a pixel defining film defining pixels. The plurality of light emitting elements in the light emitting element layer EML may be disposed in the display area DA.

[0086] The thin film encapsulation layer TFEL may cover the upper surface and the side surface of the light emitting element layer EML and may protect the light emitting element layer EML. The thin film encapsulation layer TFEL may include at least one inorganic film and at least one organic film for encapsulating the light emitting element layer EML.

[0087] The touch sensing layer TSU may be directly disposed on the thin film encapsulation layer TFEL. For example, the touch sensing layer TSU may be directly disposed on the thin film encapsulation layer TFEL and embedded in the display panel 100. The touch sensing layer TSU may include a plurality of touch electrodes for sensing the touch of a user in a capacitive manner and a touch line connecting the plurality of touch electrodes and the touch driver TIC to each other. For example, the touch sensing layer TSU may sense the touch of a user in a mutual capacitance manner or a self-capacitance manner.

[0088] In another embodiment, the touch sensing layer TSU may be disposed on a separate substrate disposed on the display layer DU. In this case, the substrate supporting the touch sensing layer TSU may be a base member encapsulating the display layer DU.

[0089] A plurality of touch electrodes in the touch sensing layer TSU may be disposed in a touch sensor region overlapping the display area DA. A touch line of the touch sensing layer TSU may be disposed in a touch peripheral region overlapping the non-display area NDA.

[0090] The optical member 200 may be disposed on the display panel 100 to reduce external light reflection. The optical member 200 may be a polarizing film. The optical member 200 may include a first base member, a linear polarizer, a phase delay film such as a λ / 4 plate (quarter wave plate), and a second base member. The first base member, the phase delay film, the linear polarizer, and the second base member in the optical member 200 may be stacked on the display panel 100 in sequence.

[0091] The window member 300 may be disposed on the optical member 200. The window member 300 may cover the display panel 100. The shape of the window member 300 may correspond to the shape of the display panel 100. The window member 300 may protect the display panel 100 from external impact and provide an input surface for a user.

[0092] The window member 300 may have a transparent property so that light generated from the display panel 100 can be transmitted through the window member 300. The window member 300 may include glass or plastic. In some embodiments, when the window member 300 includes glass, the window member 300 may include chemical ion-substituted tempered glass. In another embodiment, when the window member 300 includes plastic, the window member 300 may include a polyimide (PI) film.

[0093] The lower film 400 may be disposed on the lower surface of the display panel 100. The lower film 400 may be disposed between the display panel 100 and the panel lower member 500. The lower film 400 may support the display panel 100.

[0094] The lower film 400 may include a first lower film and a second lower film spaced apart from each other along the second direction DR2. For example, the first lower film may be disposed in the main area MA of the display panel 100, and the second lower film may be disposed in the sub-area SBA of the display panel 100. The lower film 400 may not be disposed in the area where the display panel 100 is bent in the sub-area SBA. The first lower film and the second lower film may face each other in the third direction DR3 when the display panel 100 is bent. The first lower film and the second lower film may overlap each other in the third direction DR3 when the display panel 100 is bent.

[0095] In an embodiment, the lower film 400 may include polyethylene terephthalate (PET), polyimide (PI), polycarbonate (PC), polyethylene (PE), polypropylene (PP), polysulfone (PSF), polymethyl methacrylate (PMMA), triacetyl cellulose (TAC), cycloolefin, etc.

[0096] The panel lower member 500 may be disposed on the lower surface of the lower film 400. The panel lower member 500 may perform a heat dissipation function, an electromagnetic wave shielding function, a buffering function, a strength enhancement function, and the like. Figure 5 The detailed structure and function of the panel lower member 500 are described in detail.

[0097] When the display panel 100 is bent, the cover spacer 600 can control the bending degree of the display panel 100 by compensating for the height difference between the panel lower member 500 and the sub-area SBA of the display panel 100. For example, by adjusting the thickness of the cover spacer 600, the panel lower member 500 and the sub-area SBA of the display panel 100 can be adjusted to be close to or away from each other in the third direction DR3. Accordingly, the bending degree of the area where the display panel 100 is bent can be controlled.

[0098] In an embodiment, the cover spacer 600 may include a material having elasticity or a material capable of performing a supporting function. As an example, the cover spacer 600 may include a thermoplastic elastomer, polystyrene, polyolefin, polyurethane thermoplastic elastomer, etc. As another example, the cover spacer 600 may include polycarbonate (PC), polyimide (PI), polyethylene terephthalate (PET), etc.

[0099] The display device 10 may further include a display driver DIC, a circuit board PCB, and a touch driver TIC disposed in the sub-area SBA of the display panel 100 .

[0100] The display driver DIC, the circuit board PCB, and the touch driver TIC may be disposed in the sub area SBA. The display driver DIC, the circuit board PCB, and the touch driver TIC may overlap the main area MA in the third direction DR3 by bending the display panel 100 .

[0101] The above referenced Figure 2 The display driver DIC, the circuit board PCB, and the touch driver TIC are described, and thus descriptions thereof will be omitted.

[0102] The display device 10 may further include a through hole TH located in the second display area DA2 or the third display area DA3 and a component CMP disposed in the through hole TH.

[0103] The through hole TH may provide a space in which the component CMP may be disposed. Figure 3 4 shows that the through hole TH penetrates the panel lower member 500 , the lower film 400 , and the substrate SUB, but the present disclosure is not limited thereto. For example, the through hole TH may further penetrate at least one of the display layer DU, the touch sensing layer TSU, and the optical member 200 .

[0104] The component CMP may be disposed in the through hole TH. The component CMP may include an electronic component. For example, the component CMP may be an electronic component that uses light or sound. For example, the electronic component may include a sensor such as an infrared sensor that receives light, a camera that receives light and captures an image, a sensor that outputs and senses light or sound to measure a distance or recognize a fingerprint, a small lamp that outputs light, a speaker that outputs sound, and the like. The electronic component that uses light may use light of various wavelengths such as visible light, infrared light, and ultraviolet light. In some embodiments, the through hole TH may be a transmission area that can transmit light or sound output from the component CMP to the outside or light or sound traveling from the outside toward the electronic component.

[0105] Figure 4 is a cross-sectional view showing a display panel according to an embodiment.

[0106] refer to Figure 4 , the display panel 100 may be an organic light emitting display panel including a plurality of light emitting elements LEL each including an organic light emitting layer 172. However, the display panel 100 is not limited thereto, and may also be a light emitting display panel such as a quantum dot light emitting display panel including a quantum dot light emitting layer, an inorganic light emitting display panel including an inorganic semiconductor, and a micro or nano light emitting display panel using a micro or nano light emitting diode (micro LED or nano LED). Hereinafter, for the convenience of explanation, the case where the display panel 100 is an organic light emitting display panel will be described by way of example.

[0107] The display panel 100 may include a substrate SUB, a display layer DU, and a touch sensing layer TSU.

[0108] The substrate SUB may include a first substrate SUB1 and a second substrate SUB2.

[0109] In an implementation, the first substrate SUB1 may include a hard material, and the second substrate SUB2 may include a soft material. For example, the first substrate SUB1 may include glass, and the second substrate SUB2 may include a polymer resin, but the present disclosure is not limited thereto.

[0110] In another embodiment, the first substrate SUB1 and the second substrate SUB2 may include the same material. For example, both the first substrate SUB1 and the second substrate SUB2 may include a hard material or a soft material.

[0111] In some embodiments, the substrate SUB may further include a buffer film disposed between the first substrate SUB1 and the second substrate SUB2. The buffer film may prevent moisture and oxygen from penetrating into the light-emitting element layer EML from the outside. The buffer film may be made of an inorganic material, such as a silicon nitride layer, a silicon oxynitride layer, a silicon oxide layer, a titanium oxide layer, and an aluminum oxide layer. Alternatively, the buffer film may be formed as a multilayer film in which a plurality of layers of the silicon nitride layer, the silicon oxynitride layer, the silicon oxide layer, the titanium oxide layer, and the aluminum oxide layer are alternately stacked.

[0112] The display layer DU may include a thin film transistor layer TFTL (eg, a circuit layer), a light emitting element layer EML, and a thin film encapsulation layer TFEL.

[0113] The thin film transistor layer TFTL (eg, circuit layer) may include a first buffer film BF1, a thin film transistor TFT, a gate insulating film 130, a first interlayer insulating film 141, a capacitor Cst, a second interlayer insulating film 142, a first data metal layer, a first organic film 160, a second data metal layer, and a second organic film 180.

[0114] The first buffer film BF1 may be disposed on the substrate SUB. The first buffer film BF1 may prevent moisture and oxygen from penetrating into the light emitting element layer EML from the outside. The first buffer film BF1 may be made of an inorganic material such as a silicon nitride layer, a silicon oxynitride layer, a silicon oxide layer, a titanium oxide layer, and an aluminum oxide layer. Alternatively, the first buffer film BF1 may be formed as a multilayer film in which a plurality of layers among the silicon nitride layer, the silicon oxynitride layer, the silicon oxide layer, the titanium oxide layer, and the aluminum oxide layer are alternately stacked.

[0115] An active layer including a channel region TCH, a source region TS, and a drain region TD of the thin film transistor TFT may be disposed on the first buffer film BF1. The active layer may be made of polycrystalline silicon (e.g., low temperature polycrystalline silicon), single crystal silicon, amorphous silicon, or an oxide semiconductor material. When the active layer includes polycrystalline silicon or an oxide semiconductor material, the source region TS and the drain region TD in the active layer may be conductive regions doped with ions or impurities to have conductivity.

[0116] The gate insulating film 130 may be disposed on the active layer of the thin film transistor TFT. The gate insulating film 130 may be formed as an inorganic film such as a silicon nitride layer, a silicon nitride oxide layer, a silicon oxide layer, a titanium oxide layer, or an aluminum oxide layer.

[0117] A first gate metal layer including a gate electrode TG of the thin film transistor TFT, a first capacitor electrode CAE1 of the capacitor Cst, and a scan line may be disposed on the gate insulating film 130. The gate electrode TG of the thin film transistor TFT may overlap with the channel region TCH in the third direction DR3. The first gate metal layer may be formed as a single layer or multiple layers made of any one of molybdenum (Mo), aluminum (Al), chromium (Cr), gold (Au), titanium (Ti), nickel (Ni), neodymium (Nd), and copper (Cu), or an alloy thereof.

[0118] The first interlayer insulating film 141 may be disposed on the first gate metal layer. The first interlayer insulating film 141 may be formed as an inorganic film such as a silicon nitride layer, a silicon oxynitride layer, a silicon oxide layer, a titanium oxide layer, or an aluminum oxide layer. The first interlayer insulating film 141 may include a plurality of inorganic films.

[0119] The second gate metal layer including the second capacitor electrode CAE2 of the capacitor Cst may be disposed on the first interlayer insulating film 141. The second capacitor electrode CAE2 may overlap with the first capacitor electrode CAE1 in the third direction DR3. Therefore, the capacitor Cst may be formed by the first capacitor electrode CAE1, the second capacitor electrode CAE2, and an inorganic insulating dielectric film disposed between the first capacitor electrode CAE1 and the second capacitor electrode CAE2 and serving as a dielectric film. The second gate metal layer may be formed as a single layer or multiple layers made of any one of molybdenum (Mo), aluminum (Al), chromium (Cr), gold (Au), titanium (Ti), nickel (Ni), neodymium (Nd), and copper (Cu), or an alloy thereof.

[0120] The second interlayer insulating film 142 may be disposed on the second gate metal layer. The second interlayer insulating film 142 may be formed as an inorganic film such as a silicon nitride layer, a silicon oxynitride layer, a silicon oxide layer, a titanium oxide layer, or an aluminum oxide layer. The second interlayer insulating film 142 may include a plurality of inorganic films.

[0121] A first data metal layer including a first connection electrode CE1 and a data line may be disposed on the second interlayer insulating film 142. The first connection electrode CE1 may be connected to the drain region TD through a first connection contact hole CT1 penetrating the gate insulating film 130, the first interlayer insulating film 141, and the second interlayer insulating film 142. The first data metal layer may be formed as a single layer or multiple layers made of any one of molybdenum (Mo), aluminum (Al), chromium (Cr), gold (Au), titanium (Ti), nickel (Ni), neodymium (Nd), and copper (Cu), or an alloy thereof.

[0122] A first organic film 160 for planarizing a step due to the thin film transistor TFT may be disposed on the first connection electrode CE1. The first organic film 160 may be formed as an organic film made of acrylic resin, epoxy resin, phenol resin, polyamide resin, polyimide resin, or the like.

[0123] The second data metal layer including the second connection electrode CE2 may be disposed on the first organic film 160. The second data metal layer may be connected to the first connection electrode CE1 through a second contact hole CT2 penetrating the first organic film 160. The second data metal layer may be formed as a single layer or multiple layers made of any one of molybdenum (Mo), aluminum (Al), chromium (Cr), gold (Au), titanium (Ti), nickel (Ni), neodymium (Nd), and copper (Cu), or an alloy thereof.

[0124] The second organic film 180 may be disposed on the second connection electrode CE2. The second organic film 180 may be formed as an organic film made of acrylic resin, epoxy resin, phenol resin, polyamide resin, polyimide resin, or the like.

[0125] Meanwhile, the second data metal layer including the second link electrode CE2 and the second organic film 180 may be omitted.

[0126] The light emitting element layer EML is disposed on the thin film transistor layer TFTL. The light emitting element layer EML may include a light emitting element LEL and a pixel defining film 190 .

[0127] Each of the light emitting elements LEL may include a pixel electrode 171, a light emitting layer 172, and a common electrode 173. Each of the emission areas EA refers to a region where the pixel electrode 171, the light emitting layer 172, and the common electrode 173 are sequentially stacked and holes from the pixel electrode 171 and electrons from the common electrode 173 are recombined with each other in the light emitting layer 172 to emit light. In this case, the pixel electrode 171 may be an anode, and the common electrode 173 may be a cathode.

[0128] A pixel electrode layer including a pixel electrode 171 may be formed on the second organic film 180. The pixel electrode 171 may be connected to the second connection electrode CE2 through a third connection hole CT3 penetrating the second organic film 180. The pixel electrode layer may be formed as a single layer or multiple layers made of any one of molybdenum (Mo), aluminum (Al), chromium (Cr), gold (Au), titanium (Ti), nickel (Ni), neodymium (Nd), and copper (Cu), or an alloy thereof.

[0129] In a top emission structure based on the emission of light from the light emitting layer 172 toward the common electrode 173, the pixel electrode 171 may be formed as a single layer made of molybdenum (Mo), titanium (Ti), copper (Cu), or aluminum (Al) or as a stacked structure of aluminum and titanium (Ti / Al / Ti), a stacked structure of aluminum and indium tin oxide (ITO) (ITO / Al / ITO), an APC alloy, and a stacked structure of an APC alloy and ITO (ITO / APC / ITO) to increase reflectivity. The APC alloy is an alloy of silver (Ag), palladium (Pd), and copper (Cu).

[0130] The pixel defining film 190 is used to define the emission area EA of the pixel. To this end, the pixel defining film 190 may be formed on the second organic film 180 to expose a partial area of ​​the pixel electrode 171. The pixel defining film 190 may cover the edge of the pixel electrode 171. The pixel defining film 190 may be disposed in the third contact hole CT3. That is, the third contact hole CT3 may be filled with the pixel defining film 190. The pixel defining film 190 may be formed as an organic film made of acrylic resin, epoxy resin, phenolic resin, polyamide resin, polyimide resin, etc.

[0131] The spacer 191 may be disposed on the pixel defining film 190. The spacer 191 may be used to support a mask in the process of manufacturing the light emitting layer 172. The spacer 191 may be formed as an organic film made of acrylic resin, epoxy resin, phenolic resin, polyamide resin, polyimide resin, or the like.

[0132] The light emitting layer 172 is formed on the pixel electrode 171. The light emitting layer 172 may include an organic material that emits light of a predetermined color. For example, the light emitting layer 172 may include a hole transport layer, an organic material layer, and an electron transport layer. The organic material layer may include a host and a dopant. The organic material layer may include a material that emits a predetermined light, and may be formed using a phosphorescent material or a fluorescent material.

[0133] The common electrode 173 is formed on the light emitting layer 172. The common electrode 173 may be formed to cover the light emitting layer 172. The common electrode 173 may be a common layer commonly formed in the plurality of emission areas EA. A covering layer may be formed on the common electrode 173.

[0134] In the top emission structure, the common electrode 173 may be made of a transparent conductive material (TCO) such as ITO or indium zinc oxide (IZO) through which light can be transmitted, or a semi-transmissive conductive material such as magnesium (Mg), silver (Ag), or an alloy of magnesium (Mg) and silver (Ag). When the common electrode 173 is made of a semi-transmissive conductive material, the emission efficiency can be increased by the microcavity.

[0135] The thin film encapsulation layer TFEL may be disposed on the light emitting element layer EML. The thin film encapsulation layer TFEL may include at least one inorganic film (e.g., a first encapsulation inorganic film TFE1 and / or a second encapsulation inorganic film TFE3) to prevent oxygen or moisture from penetrating into the light emitting element layer EML. In addition, the thin film encapsulation layer TFEL may include at least one organic film (e.g., an encapsulation organic film TFE2) to protect the light emitting element layer EML from foreign substances such as dust. For example, the thin film encapsulation layer TFEL may include a first encapsulation inorganic film TFE1, an encapsulation organic film TFE2, and a second encapsulation inorganic film TFE3.

[0136] The first encapsulation inorganic film TFE1 may be disposed on the common electrode 173, the encapsulation organic film TFE2 may be disposed on the first encapsulation inorganic film TFE1, and the second encapsulation inorganic film TFE3 may be disposed on the encapsulation organic film TFE2. The first encapsulation inorganic film TFE1 and the second encapsulation inorganic film TFE3 may be formed as a multilayer film in which one or more inorganic films of a silicon nitride layer, a silicon oxynitride layer, a silicon oxide layer, a titanium oxide layer, and an aluminum oxide layer are alternately stacked. The encapsulation organic film TFE2 may be an organic film made of acrylic resin, epoxy resin, phenolic resin, polyamide resin, polyimide resin, etc.

[0137] The touch sensing layer TSU may be disposed on the thin film encapsulation layer TFEL. The touch sensing layer TSU may include a second buffer film BF2, a first connection part BE1, a first sensor insulating film TINS1, sensor electrodes TE and RE, and a second sensor insulating film TINS2.

[0138] The second buffer film BF2 may be disposed on the thin film encapsulation layer TFEL. The second buffer film BF2 may include at least one inorganic film. For example, the second buffer film BF2 may be formed as a multilayer film in which one or more inorganic films of a silicon nitride layer, a silicon oxynitride layer, a silicon oxide layer, a titanium oxide layer, and an aluminum oxide layer are alternately stacked. The second buffer film BF2 may be omitted.

[0139] The first connection part BE1 may be disposed on the second buffer film BF2. The first connection part BE1 may be formed as a single layer made of molybdenum (Mo), titanium (Ti), copper (Cu), or aluminum (Al) or as a stack structure of aluminum and titanium (Ti / Al / Ti), a stack structure of aluminum and ITO (ITO / Al / ITO), an APC alloy, and a stack structure of an APC alloy and ITO (ITO / APC / ITO).

[0140] The first sensor insulating film TINS1 may be disposed on the first connection part BE1. The first sensor insulating film TINS1 may be formed as an inorganic film such as a silicon nitride layer, a silicon nitride oxide layer, a silicon oxide layer, a titanium oxide layer, or an aluminum oxide layer.

[0141] The sensor electrodes TE and RE (i.e., the driving electrode TE and the sensing electrode RE) may be disposed on the first sensor insulating film TINS1. In addition, a dummy pattern may be disposed on the first sensor insulating film TINS1. The driving electrode TE, the sensing electrode RE, and the dummy pattern do not overlap with the emission area EA. Each of the driving electrode TE, the sensing electrode RE, and the dummy pattern may be formed as a single layer made of molybdenum (Mo), titanium (Ti), copper (Cu), or aluminum (Al) or as a stacked structure of aluminum and titanium (Ti / Al / Ti), a stacked structure of aluminum and ITO (ITO / Al / ITO), an APC alloy, and a stacked structure of an APC alloy and ITO (ITO / APC / ITO).

[0142] The second sensor insulating film TINS2 may be disposed on the driving electrode TE, the sensing electrode RE, and the dummy pattern. The second sensor insulating film TINS2 may include at least one of an inorganic film and an organic film. The inorganic film may be a silicon nitride layer, a silicon oxynitride layer, a silicon oxide layer, a titanium oxide layer, or an aluminum oxide layer. The organic film may be made of acrylic resin, epoxy resin, phenolic resin, polyamide resin, or polyimide resin.

[0143] Figure 5 is a cross-sectional view showing a panel lower member according to an embodiment.

[0144] remove Figure 3 In addition, reference Figure 5 , the panel lower member 500 may include at least one functional layer. The functional layer may be a layer that performs a heat dissipation function, an electromagnetic wave shielding function, a buffering function, a strength enhancement function, a supporting function, an adhesive function, and the like. The functional layer may be a sheet layer made of a sheet, a film layer made of a film, a film layer, a coating, a panel, a plate, and the like. One functional layer may be formed as a single layer or as a plurality of stacked films or a plurality of coatings. For example, the functional layer may be a supporting substrate, a heat dissipation layer, an electromagnetic wave shielding layer, a shock absorbing layer, a coupling layer, and the like.

[0145] In some embodiments, the panel lower member 500 may include a shielding layer 510 , an adhesive layer 520 , a buffer layer 530 , and a heat dissipation adhesive layer 540 .

[0146] The shielding layer 510 may shield electromagnetic waves. The shielding layer 510 may include a material that shields electromagnetic waves and has excellent thermal conductivity. For example, the shielding layer 510 may include a metal film made of copper, nickel, iron, silver, etc.

[0147] The adhesive layer 520 may be disposed between the shielding layer 510 and the buffer layer 530. The adhesive layer 520 may couple the shielding layer 510 and the buffer layer 530 to each other. In an embodiment, the adhesive layer 520 may include a polymer material classified as a silicone-based polymer material, a urethane-based polymer material, a SU polymer having a silicone-urethane hybrid structure, an acrylic polymer material, an isocyanate-based polymer material, a polyvinyl alcohol-based polymer material, a gelatin-based polymer material, a vinyl-based polymer material, a latex-based polymer material, a polyester-based polymer material, a water-based polyester-based polymer material, and the like.

[0148] The buffer layer 530 may be disposed on the adhesive layer 520. The buffer layer 530 may prevent the display device 10 from being damaged by absorbing external impact. The buffer layer 530 may be formed as a single layer or a plurality of stacked films.

[0149] In an embodiment, the buffer layer 530 may include a material capable of elastic deformation. For example, the buffer layer 530 may include a thermoplastic elastomer, polystyrene, polyolefin, polyurethane thermoplastic elastomer, polyamide, synthetic rubber, polydimethylsiloxane, polybutadiene, polyisobutylene, poly(styrene-butadiene-styrene), polyurethane, polychloroprene, polyethylene, silicone, etc. and combinations thereof.

[0150] The heat dissipation adhesive layer 540 may be disposed on the buffer layer 530. The heat dissipation adhesive layer 540 may be disposed between the buffer layer 530 and the lower film 400. In some embodiments, when the lower film 400 is omitted, the heat dissipation adhesive layer 540 may be disposed between the buffer layer 530 and the display panel 100.

[0151] The heat dissipation adhesive layer 540 may couple the panel lower member 500 and the lower film 400 to each other or couple the panel lower member 500 and the display panel 100 to each other. The heat dissipation adhesive layer 540 may prevent heat generated by a plurality of components such as an application chip, a camera, or a battery component disposed under the panel lower member 500 from reaching the display panel 100.

[0152] In some embodiments, the heat dissipation adhesive layer 540 may include an adhesive material and a material having an excellent heat dissipation function. For example, the heat dissipation adhesive layer 540 may include a heat dissipation layer 542 including a heat dissipation material and a coating layer surrounding the heat dissipation layer 542 and including an adhesive material.

[0153] Will refer to later Figure 6 etc. describe the heat dissipation adhesive layer 540 .

[0154] Figure 6 is a plan view showing a heat dissipation adhesive layer according to an embodiment. Figure 7 It is along Figure 6 A cross-sectional view taken along line X1-X1'. Figure 8 yes Figure 7 Magnified view of area A in FIG.

[0155] remove Figure 5 In addition, reference Figures 6 to 8 , the heat dissipation adhesive layer 540 according to the embodiment may include a first coating layer 541, a heat dissipation layer 542, and a second coating layer 543. The heat dissipation adhesive layer 540 may have a structure in which the heat dissipation layer 542 is surrounded by the first coating layer 541 and the second coating layer 543. For example, the upper and lower surfaces and the side surface of the heat dissipation layer 542 may be surrounded by the first coating layer 541 and the second coating layer 543. However, the present disclosure is not limited thereto, and at least a portion of the upper and lower surfaces and the side surface of the heat dissipation layer 542 may also be exposed to the outside without being surrounded by the first coating layer 541 and the second coating layer 543.

[0156] The first coating 541 and the second coating 543 may include an adhesive or viscous material. The first coating 541 and the second coating 543 may include a thermosetting resin or an ultraviolet curable resin, but are not limited thereto. For example, the first coating 541 and the second coating 543 may include at least one of an epoxy resin, a phenoxy resin, an amino resin, a polyester resin, and a polyurethane resin as a curable resin. The first coating 541 and the second coating 543 according to the present embodiment can prevent the peeling and decomposition of the heat dissipation layer 542, such as the heat dissipation layer 542 splitting or breaking into a layered structure due to intermolecular repulsion.

[0157] In an embodiment, the first coating layer 541 and the second coating layer 543 may include a highly heat-resistant heat dissipation adhesive having excellent thermal conductivity and heat dissipation characteristics. Accordingly, the heat emitted by the heat dissipation layer 542 may be easily released to the outside through the first coating layer 541 and the second coating layer 543.

[0158] In some embodiments, the first coating layer 541 and the second coating layer 543 may include the same material. However, the present disclosure is not limited thereto, and the first coating layer 541 and the second coating layer 543 may include different materials.

[0159] In some embodiments, the first coating layer 541 and the second coating layer 543 may further include a light blocking material. For example, the first coating layer 541 and the second coating layer 543 may include a black pigment such as carbon black or a black dye. The first coating layer 541 and the second coating layer 543 according to the present embodiment may prevent the components disposed under the heat dissipation adhesive layer 540 from being observed through the display surface by further including a light blocking material.

[0160] The first coating layer 541 may support the heat dissipation layer 542. The first coating layer 541 may be disposed between the heat dissipation layer 542 and the buffer layer 530. The first coating layer 541 may couple the heat dissipation adhesive layer 540 and the buffer layer 530 to each other. The first coating layer 541 may contact the lower surface of the heat dissipation layer 542.

[0161] The second coating layer 543 may cover the heat dissipation layer 542. In some embodiments, the second coating layer 543 may cover the upper surface of the heat dissipation layer 542. In some embodiments, the second coating layer 543 may cover the side surface of the heat dissipation layer 542. The second coating layer 543 may contact the upper surface and the side surface of the heat dissipation layer 542.

[0162] In some embodiments, an embossed shape may be formed on the upper surface of the second coating layer 543. In the case where the embossed shape is formed on the upper surface of the second coating layer 543, when the heat dissipation adhesive layer 540 is attached to the lower film 400 or the lower portion of the display panel 100, the embossed shape of the upper surface of the second coating layer 543 may serve as a wind tunnel to minimize bubbles on the interface. Figure 7 and Figure 8 As shown in FIG. 5 , when the heat dissipation adhesive layer 540 is completely attached to the lower film 400 or the lower portion of the display panel 100 , the embossed shape of the upper surface of the second coating layer 543 may collapse and become flat.

[0163] The heat dissipation layer 542 may be disposed on the first coating layer 541. The heat dissipation layer 542 may be interposed between the first coating layer 541 and the second coating layer 543. The heat dissipation layer 542 may be surrounded by the first coating layer 541 and the second coating layer 543.

[0164] The heat dissipation layer 542 may include a material having excellent thermal conductivity and heat dissipation characteristics. For example, the heat dissipation layer 542 may include at least one of graphite and carbon nanotubes.

[0165] In some embodiments, the heat dissipation layer 542 may include an opening hole OP and a body portion BD. In a plan view, the body portion BD may surround the opening hole OP.

[0166] The opening hole OP may be a through hole penetrating the heat dissipation layer 542 in the third direction DR3. The opening hole OP may be filled with the first coating layer 541 or the second coating layer 543 or a combination of both. The heat dissipation layer 542 according to the present embodiment may have a high peel strength by including the opening hole OP.

[0167] Figure 6 2 has shown that the opening hole OP has a circular shape in a plan view, but the present disclosure is not limited thereto. For example, the shape of the opening hole OP in a plan view may be modified to various shapes such as a polygonal shape (such as a quadrilateral shape, or an elliptical shape).

[0168] In an embodiment, the number of the opening holes OP may be multiple. Figure 6 As shown in FIG. 1 , a plurality of opening holes OP may be disposed to be spaced apart from each other along a matrix direction. Figure 6 It has been shown that five opening holes OP are arranged along the first direction DR1 which is the short side direction (row direction), and seven opening holes OP are arranged along the second direction DR2 which is the long side direction (column direction), but the present disclosure is not limited to this. In another embodiment, the plurality of opening holes OP may be arranged in a zigzag shape or randomly, and the number of the opening holes OP may also be variously modified.

[0169] In some embodiments, Figure 6 As shown in FIG. 5 , the heat dissipation layer 542 may be smaller than the first coating layer 541 and the second coating layer 543 in a plan view. For example, the heat dissipation adhesive layer 540 may include a first area ARA1 where the heat dissipation layer 542 is provided and a second area ARA2 where the heat dissipation layer 542 is not provided. The first area ARA1 may be surrounded by the second area ARA2. In the second area ARA2, the heat dissipation layer 542 may not be provided, and only the first coating layer 541 and the second coating layer 543 may be provided.

[0170] In some embodiments, the heat dissipation adhesive layer 540 may include a through hole TH disposed in the second area ARA2. The through hole TH of the heat dissipation adhesive layer 540 may be a hole penetrating the first coating layer 541 and the second coating layer 543 in the third direction DR3. The through hole TH of the heat dissipation adhesive layer 540 may be a reference Figure 3 The second display area DA2 and the third display area DA3 described (see Figure 3 ) is a portion of the through hole TH.

[0171] In an implementation, the thickness of the heat dissipation adhesive layer 540 may be about 20 μm to 120 μm, but is not limited thereto. Each of the thickness TH1 of the first coating layer 541 and the thickness TH3 of the second coating layer 543 may be about 10 μm to 60 μm, but is not limited thereto.

[0172] In some embodiments, the thickness TH2 of the heat dissipation layer 542 may be smaller than the thickness TH3 of the second coating layer 543. For example, the thickness TH2 of the heat dissipation layer 542 may be about 5 μm to 50 μm, but is not limited thereto.

[0173] In the display device 10 according to the present embodiment, the heat dissipation adhesive layer 540 may include several height steps between the upper surface of the first coating layer 541 and the upper surface of the heat dissipation layer 542. For example, such a height difference may be formed due to the height difference between the upper surface of the first coating layer 541 formed to the thickness TH2 of the heat dissipation layer 542 and the upper surface of the heat dissipation layer 542. Such a height step may be located at the boundary between the first area ARA1 and the second area ARA2 and the boundary between the body portion BD and the opening hole OP.

[0174] like Figure 7 As shown in FIG. 1 , in some embodiments, the thickness TH4 of the second coating layer 543 overlapping the main portion BD of the heat dissipation layer 542 may be smaller than the thickness TH3 of the second coating layer 543 disposed on the first coating layer 541. For example, the thickness TH4 of the second coating layer 543 overlapping the main portion BD of the heat dissipation layer 542 may be smaller than the thickness TH3 of the second coating layer 543 not overlapping the main portion BD of the heat dissipation layer 542. The thickness TH4 of the second coating layer 543 overlapping the main portion BD of the heat dissipation layer 542 may be smaller than the thickness TH3 of the second coating layer 543 disposed in the second area ARA2 and the thickness TH3 of the second coating layer 543 overlapping the opening hole OP.

[0175] In the display device 10 according to the present embodiment, the upper surface of the second coating layer 543 may be a substantially flat surface. Figure 8 As shown in FIG. 5 , the second coating layer 543 may include a ridge portion CRS and a valley portion VAL. The ridge portion CRS of the second coating layer 543 may overlap with the body portion BD of the heat dissipation layer 542 in the third direction DR3, and the valley portion VAL of the second coating layer 543 may overlap with the opening hole OP of the heat dissipation layer 542 or the second area ARA2 in the third direction DR3.

[0176] In some embodiments, the height difference H1 between the ridge portion CRS and the valley portion VAL may be within about 10% of the thickness TH3 of the second coating layer 543. As an example, the height difference H1 between the ridge portion CRS and the valley portion VAL may be within about 5 μm. When the height difference H1 between the ridge portion CRS and the valley portion VAL is within about 5 μm, the step between the ridge portion CRS and the valley portion VAL may not be observed from the outside. In this specification, the upper surface of the second coating layer 543 being substantially flat may mean that the height difference H1 between the ridge portion CRS and the valley portion VAL is within about 5 μm or less.

[0177] In the display device 10 according to the present embodiment, in the method S1 for manufacturing the display device described later, the second coating layer 543 may be formed by applying a liquid resin on the first coating layer 541 and the heat dissipation layer 542. In this case, the ridge portion CRS and the valley portion VAL may be formed due to a height step caused by the thickness TH2 of the heat dissipation layer 542. In the display device 10 according to the present embodiment, by minimizing the height difference H1 between the ridge portion CRS and the valley portion VAL, it is possible to prevent the step between the ridge portion CRS and the valley portion VAL of the second coating layer 543 from being observed from the outside. This will be referred to later. Fig.11 et al. by a method for manufacturing a display device S1 (see Fig.11 ) describes a method for minimizing the height difference H1 between the ridge portion CRS and the valley portion VAL.

[0178] Fig. 9 is a diagram showing a graph of flatness of a heat dissipation adhesive layer according to the related art. Fig.10 is a diagram showing a graph of flatness of a heat dissipation adhesive layer according to an embodiment.

[0179] remove Figures 6 to 8 In addition, reference Fig. 9 and Fig.10 , Fig. 9 shows the flatness of the upper surface of the heat dissipation adhesive layer 540 according to the related art, and Fig.10 The flatness of the upper surface of the heat dissipation adhesive layer 540 according to the embodiment is shown. The heat dissipation adhesive layer 540 according to the embodiment is formed by the method S1 for manufacturing a display device described later (see Fig.11 ) is manufactured. The heat dissipation adhesive layer 540 according to the related art is manufactured by the method S1 for manufacturing a display device described later (see Fig.11 ) in the absence of a mask dam MSD (e.g., reference Fig.15 ) is manufactured by forming a second coating 543.

[0180] like Fig. 9 As shown in the figure of FIG. 5 , the height difference H1 between the ridge portion CRS and the valley portion VAL of the heat dissipation adhesive layer 540 according to the related art may be about 20 μm. Fig.10 As shown in the graph of , a height difference H1 between the ridge portion CRS and the valley portion VAL of the heat dissipation adhesive layer 540 according to the present embodiment may be less than about 5 μm.

[0181] As such, in the display device 10 according to the present embodiment, by minimizing the height difference H1 between the ridge portion CRS and the valley portion VAL, it is possible to prevent the ridge portion CRS and the valley portion VAL of the second coating layer 543 from being observed from the outside.

[0182] In the following, reference will be made to Fig.11 etc. describe a method of manufacturing a heat dissipation adhesive layer for a display device according to an embodiment for minimizing the height difference H1 between the ridge portion CRS and the valley portion VAL.

[0183] Fig.11 is a flowchart illustrating a method of manufacturing a heat dissipation adhesive layer for a display device according to an embodiment. Fig.12 It is shown Fig.11 A cross-sectional view of the S100 in FIG. Fig.13 It is shown Fig.11 A cross-sectional view of the S200. Fig.14 It is shown Fig.11 A cross-sectional view of the S300 in FIG. Fig.15 It is shown Fig.11 A plan view of the S400. Fig.16 It is shown Fig.11 A cross-sectional view of the S400. Fig.17 is a cross-sectional view showing S400_1 of a method of manufacturing a heat dissipation adhesive layer for a display device according to another embodiment. Fig.18 is a cross-sectional view illustrating S400_2 of a method of manufacturing a heat dissipation adhesive layer for a display device according to still another embodiment. Fig.19 It is shown Fig.11 A cross-sectional view of the S500. Fig. 20 is a cross-sectional view illustrating S500_1 of a method of manufacturing a heat dissipation adhesive layer for a display device according to another embodiment. Fig.21 is a cross-sectional view illustrating S500_2 of a method of manufacturing a heat dissipation adhesive layer for a display device according to still another embodiment. Fig. 22 It is shown Fig.11 A cross-sectional view of the S600. Fig.23 It is shown Fig.11 A cross-sectional view of the S600.

[0184] refer to Figures 11 to 23 According to an embodiment, a method S1 for manufacturing a display device may include: providing a pad (S100); forming a first coating layer on the pad (S200); forming a heat dissipation layer on the first coating layer (S300); forming a mask dam surrounding the heat dissipation layer (S400); forming a second coating layer in an inner space of the mask dam (S500); and forming a heat dissipation adhesive layer by cutting the first coating layer and the second coating layer along an inner side (e.g., an inner surface) of the mask dam (S600).

[0185] like Fig.12As shown in FIG. 1 , when providing the liner ( S100 ), a liner LNR may be provided. In the step of manufacturing and carrying the heat dissipation adhesive layer 540 , the liner LNR may be a supporting film for supporting the first coating layer 541 and the second coating layer 543 or a protective film for maintaining the bonding strength of the first coating layer 541 and the second coating layer 543 .

[0186] In some embodiments, the liner LNR may be a release film type. For example, the liner LNR may include polyethylene terephthalate (PET), polycarbonate (PC), polyimide (PI), paper, etc. In order to increase the release force of the liner LNR, a silicone solution treatment may be performed on the upper surface of the liner LNR or a release coating including a silicone resin may be formed on the upper surface of the liner LNR, but the present disclosure is not limited thereto.

[0187] like Fig.13 As shown in FIG. 2 , when forming the first coating layer on the liner ( S200 ), the first coating layer 541 may be formed on the liner LNR.

[0188] The first coating 541 may be applied to the liner LNR using an application device AM. In an embodiment, the first coating 541 may be applied to the liner LNR in liquid form and then cured by heat or ultraviolet rays. In another embodiment, the first coating 541 may be cured naturally.

[0189] For example, the application device AM may apply the first ink I1 onto the liner LNR. The first ink I1 may be cured by a separate heating device or an ultraviolet irradiation device. Accordingly, a first coating layer 541 may be formed on the liner LNR.

[0190] In some embodiments, the application device AM may be one of a slot coating device, an inkjet device, and a dispensing device.

[0191] In an embodiment, the first ink I1 and the first coating layer 541 may include at least one of epoxy resin, phenoxy resin, amino resin, polyester resin, and polyurethane resin as a curable resin, but are not limited thereto.

[0192] like Fig.14 As shown in FIG. 5 , when forming the heat dissipation layer on the first coating layer (S300), the heat dissipation layer 542 may be formed on the first coating layer 541. The heat dissipation layer 542 may include at least one of graphite and carbon nanotubes.

[0193] In an embodiment, when the heat dissipation layer 542 includes graphite, the heat dissipation layer 542 may be formed by coating the first coating layer 541 with a graphene oxide slurry. The graphene oxide slurry may be reduced by heating, and the heat dissipation layer 542 may be formed by lowering the temperature of the reduced graphite to crystallize the graphite. In another embodiment, the heat dissipation layer 542 may be formed by directly carbonizing an organic insulating material such as polyimide (PI).

[0194] In some embodiments, after forming the heat dissipation layer 542, an opening hole OP penetrating the heat dissipation layer 542 may be formed. By punching the heat dissipation layer 542, an opening hole OP penetrating the heat dissipation layer 542 in the third direction DR3 may be formed. Accordingly, the opening hole OP and the body portion BD surrounding the opening hole OP may be formed.

[0195] like Figures 15 to 18 As shown in FIG. 5 , when forming the mask dam surrounding the heat dissipation layer ( S400 ), the mask dam MSD may be disposed to surround the heat dissipation layer 542 .

[0196] like Fig.15 , in a plan view, the mask dam MSD may surround the heat dissipation layer 542. The mask dam MSD may include an inner space MSDa in which the heat dissipation layer 542 is disposed. The inner side surface of the mask dam MSD may be spaced apart from the outer side surface of the heat dissipation layer 542. In a plan view, the inner side surface of the mask dam MSD may surround the outer side surface of the heat dissipation layer 542. In a plan view, the size of the mask dam MSD may be less than or equal to the size of the pad LNR.

[0197] In an embodiment, if Fig.16 As shown in FIG. 5 , the mask dam MSD may be disposed on the first coating layer 541. In another embodiment, as shown in FIG. Fig.17 and Fig.18 As shown in FIG. 5 , the mask dam MSD may be disposed on the pad LNR and may be disposed to surround the first coating layer 541 and the heat dissipation layer 542. Fig.17 As shown in FIG. 1 , the inner surface of the mask dam MSD may be in direct contact with the outer surface of the first coating layer 541, or as shown in FIG. Fig.18 As shown in FIG. 5 , the inner side surface of the mask dam MSD may be disposed outside the outer side surface of the first coating layer 541 and spaced apart from the outer side surface of the first coating layer 541 .

[0198] like Figures 19 to 21 As shown in FIG. 5 , when the second coating layer is formed in the inner space of the mask dam ( S500 ), the second coating layer 543 may be formed in the inner space MSDa of the mask dam MSD.

[0199] The second coating 543 may be applied to the inner space MSDa of the mask dam MSD using an application device AM. In an embodiment, the second coating 543 may be applied to the inner space MSDa of the mask dam MSD in a liquid form and then cured by heat or ultraviolet rays. In another embodiment, the second coating 543 may be naturally cured.

[0200] For example, the application device AM may apply the second ink I2 to the inner space MSDa of the mask dam MSD. The second ink I2 may be cured by a separate heating device or an ultraviolet irradiation device. Accordingly, the second coating layer 543 may be formed in the inner space MSDa of the mask dam MSD.

[0201] In an embodiment, the second ink 12 and the second coating layer 543 may include at least one of epoxy resin, phenoxy resin, amino resin, polyester resin, and polyurethane resin as a curable resin, but are not limited thereto.

[0202] In an embodiment, if Fig.19 As shown in FIG. 5 , when the mask dam MSD is disposed on the first coating layer 541, or as Fig. 20 , when the inner side surface of the mask dam MSD is in direct contact with the side surface (i.e., the outer side surface) of the first coating layer 541, the second coating layer 543 may be provided on the first coating layer 541. For example, the second coating layer 543 may be in contact with the upper surface of the first coating layer 541, the side surface and the upper surface of the heat dissipation layer 542, and the inner side surface of the mask dam MSD.

[0203] In another embodiment, Fig.21 , when the mask dam MSD is disposed on the pad LNR and is spaced apart from the outer side surface of the first coating layer 541, the second coating layer 543 may be disposed on the pad LNR. For example, the second coating layer 543 may be in contact with the upper surface of the pad LNR, the outer side surface of the first coating layer 541, the side surface and the upper surface of the heat dissipation layer 542, and the inner side surface of the mask dam MSD.

[0204] In some embodiments, the thickness MSD_TH of the mask dam MSD may be greater than or equal to the thickness 542_TH of the heat dissipation layer 542. By making the thickness MSD_TH of the mask dam MSD greater than or equal to the thickness 542_TH of the heat dissipation layer 542, the reference Figure 8 It is possible to minimize the height difference H1 between the ridge portion CRS and the valley portion VAL of the second coating layer 543 as described in FIG. Fig. 20 and Fig.21 As shown in FIG. 5 , when the mask dam MSD is disposed on the pad LNR, the thickness MSD_TH of the mask dam MSD may be greater than or equal to the sum of the thickness 541_TH of the first coating layer 541 and the thickness 542_TH of the heat dissipation layer 542 .

[0205] For example, by setting the mask dam MSD, it is possible to prevent the second ink I2 in liquid form from spreading in the first direction DR1 and the second direction DR2. Accordingly, even if there is a height step between the body portion BD and the opening hole OP, the second ink I2 can be uniformly spread on the body portion BD and the opening hole OP. Accordingly, even if there is a difference between the thickness 543_TH1 of the second coating layer 543 disposed on the body portion BD and the thickness 543_TH2 of the second coating layer 543 disposed in the opening hole OP, the upper surface of the second coating layer 543 can become substantially flat.

[0206] In some embodiments, due to other intermolecular attraction such as surface tension, the second coating layer 543 may include a flat portion FLA and an inclined portion SLA. For example, the second coating layer 543 may be substantially flat at the center, and the inclination angle of the inclined surface may deepen toward the outside. In an embodiment, the flat portion FLA may refer to a ridge portion CRS (see Figure 8 ) and the valley part VAL (see Figure 8 ) between the height difference H1 (see Figure 8 ) is within about 10% of the thickness of the second coating layer 543, and the inclined portion SLA may refer to a ridge portion CRS (see Figure 8 ) and the valley part VAL (see Figure 8 ) between the height difference H1 (see Figure 8 ) exceeds about 10% of the thickness of the second coating layer 543.

[0207] In some embodiments, the second coating layer 543 may be formed to overflow the inner space MSDa of the mask dam MSD. For example, the upper surface of the second coating layer 543 may be located at a higher level than the upper surface of the mask dam MSD. The second coating layer 543 may cover at least a portion of the upper surface of the mask dam MSD. In the method S1 for manufacturing a display device according to the present embodiment, the inclined portion SLA is located on the upper surface of the mask dam MSD so that the upper surface of the second coating layer 543 may be formed to be relatively flat.

[0208] like Fig. 22 and Fig.23 As shown in FIG. 5 , when the heat dissipation adhesive layer is formed by cutting the first coating layer and the second coating layer along the inner side of the mask ( S600 ), the heat dissipation adhesive layer 540 can be formed by cutting the pad LNR, the first coating layer 541 and the second coating layer 543 located inside the mask dam MSD.

[0209] For example, the first coating layer 541 and the second coating layer 543 may be cut using a cutting member CM. The cutting line CL of the cutting member CM may be located inside the inner surface of the mask dam MSD. The cutting line CL of the cutting member CM may be surrounded by the inner surface of the mask dam MSD in a plan view and may surround the heat dissipation layer 542.

[0210] In some embodiments, the cutting line CL of the cutting member CM may overlap with the flat portion FLA. Accordingly, the upper surface of the second coating layer 543 of the heat dissipation adhesive layer 540 may be substantially flat, and the ridge portion CRS of the second coating layer 543 (see Figure 8 ) and valley portion (see Figure 8 ) is observed from the outside.

[0211] After the cutting process, the mask dam MSD and the cut pad LNR together with the outer portions of the first coating layer 541 and the second coating layer 543 may be removed.

[0212] In some embodiments, a separate gasket LNR may be further provided on the second coating layer 543. By providing the gasket LNR on the upper and lower surfaces of the heat dissipation adhesive layer 540, the adhesive strength of the first coating layer 541 and the second coating layer 543 may be maintained when the heat dissipation adhesive layer 540 is carried.

[0213] When the mask dam MSD is provided in the process of forming the second coating layer 543 according to the method S1 for manufacturing the display device of the present embodiment, the ridge portion CRS (see Figure 8 ) and the valley part VAL (see Figure 8 ) between the height difference H1 (see Figure 8 ) may be within about 3 μm. Accordingly, the ridge portion CRS (see Figure 8 ) and the valley part VAL (see Figure 8 ) between the height difference H1 (see Figure 8 ) is formed within 5 μm, and thus, a step between the ridge portion CRS and the valley portion VAL may not be observed from the outside.

[0214] While the present disclosure has been described with reference to the embodiments thereof, it will be apparent to those skilled in the art that various changes and modifications can be made thereto without departing from the scope and spirit of the disclosure as set forth in the appended claims.

Claims

1. A method for manufacturing a heat dissipation adhesive layer for a display device, comprising: Providing a liner, a first coating on the liner, and a heat dissipation layer on the first coating; forming a mask dam surrounding the heat dissipation layer; as well as A second coating layer is formed inside the mask dam.

2. The method for manufacturing a heat dissipation adhesive layer for a display device according to claim 1, wherein: The heat dissipation layer includes a main body portion and an opening hole penetrating the heat dissipation layer.

3. The method for manufacturing a heat dissipation adhesive layer for a display device according to claim 2, wherein: The second coating fills the open pores.

4. The method for manufacturing a heat dissipation adhesive layer for a display device according to claim 3, wherein: The upper surface of the second coating layer includes a ridge portion overlapping the body portion and a valley portion overlapping the opening hole.

5. The method for manufacturing a heat dissipation adhesive layer for a display device according to claim 4, wherein: A height difference between the ridge portion and the valley portion is 5 μm or less.

6. The method for manufacturing a heat dissipation adhesive layer for a display device according to claim 1, wherein: The second coating layer includes a flat portion and an inclined portion provided on one side of the flat portion.

7. The method for manufacturing a heat dissipation adhesive layer for a display device according to claim 6, wherein: The upper surface of the second coating layer includes a ridge portion and a valley portion located at a lower level than the ridge portion, and In the flat portion, a height difference between the ridge portion and the valley portion is 5 μm or less.

8. The method for manufacturing a heat dissipation adhesive layer for a display device according to claim 6, further comprising: The second coating layer is cut along an inner side of the mask dam.

9. The method for manufacturing a heat dissipation adhesive layer for a display device according to claim 8, wherein: The cutting line of the second coating layer overlaps the flat portion of the second coating layer.

10. The method for manufacturing a heat dissipation adhesive layer for a display device according to claim 1, wherein: An upper surface of the second coating layer is higher than an upper surface of the mask dam.

11. The method for manufacturing a heat dissipation adhesive layer for a display device according to claim 10, wherein: The second coating layer covers at least a portion of the upper surface of the mask dam.

12. The method for manufacturing a heat dissipation adhesive layer for a display device according to claim 1, wherein: The thickness of the mask dam is greater than or equal to the thickness of the heat dissipation layer.

13. The method for manufacturing a heat dissipation adhesive layer for a display device according to claim 1, wherein: The mask dam is disposed directly on an upper surface of the first coating layer.

14. The method for manufacturing a heat dissipation adhesive layer for a display device according to claim 1, wherein: The mask dam is directly disposed on an upper surface of the liner and surrounds the first coating layer.

15. The method for manufacturing a heat dissipation adhesive layer for a display device according to claim 14, wherein: An inner side surface of the mask dam is spaced apart from a side surface of the first coating layer.

16. A display device, comprising: Display panel; as well as a panel lower member, the panel lower member including a heat dissipation adhesive layer and disposed on a rear surface of the display panel, The heat dissipation adhesive layer includes a first coating layer, a heat dissipation layer disposed on the first coating layer, and a second coating layer covering the heat dissipation layer, and The upper surface of the second coating layer is a flat surface.

17. The display device according to claim 16, wherein: The upper surface of the second coating layer includes ridge portions and valley portions, and The ridge portion is located at a higher level than the valley portion.

18. The display device according to claim 17, wherein: A height difference between the ridge portion and the valley portion is 10% or less of a thickness of the second coating layer.

19. The display device according to claim 18, wherein: The height difference between the ridge portion and the valley portion is 5 μm or less.

20. The display device according to claim 16, wherein: The panel lower component further comprises: Shielding layer; an adhesive layer disposed on the shielding layer, and a buffer layer disposed on the adhesive layer, and The heat dissipation adhesive layer is disposed on the buffer layer.

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