Display device

Abstract

A display device is provided. The display device includes a display module including pixels, signal lines electrically connected to the pixels, and signal pads electrically connected to the signal lines. The signal pad includes an insulating pattern disposed on the signal line and a conductive pattern electrically connected to the signal line. The conductive pattern includes a first portion including a mesh pattern and a second portion surrounding the first portion. At least a portion of the first portion is disposed on the insulating pattern.

Description

[0001] CROSS-REFERENCE TO RELATED APPLICATIONS

[0002] This application claims priority to and the benefit of Korean Patent Application No. 10-2023-0129483 filed in the Korean Intellectual Property Office on September 26, 2023, the entire contents of which are incorporated herein by reference. Technical Field

[0003] Embodiments relate to a pad area of ​​a display device and a method for manufacturing the display device. Background Art

[0004] The display device includes a display area activated in response to an electrical signal, and can sense an input applied from the outside through the display area while displaying various images to be provided to a user.

[0005] The display device includes a display panel and a circuit board. The display panel can be connected to the main board through the circuit board. The driving chip can be mounted on the display panel. Summary of the invention

[0006] Embodiments of the present disclosure provide a display device improved in bonding reliability and a method for manufacturing the display device.

[0007] According to an embodiment, a display device may include a display module, and the display module may include a pixel, a signal line electrically connected to the pixel, and a signal pad electrically connected to the signal line. The signal pad may include an insulating pattern arranged on the signal line and a conductive pattern electrically connected to the signal line. The conductive pattern may include a first portion including a grid pattern and a second portion surrounding the first portion. At least a portion of the first portion may be arranged on the insulating pattern.

[0008] The conductive pattern may include a conductive material, and the insulating pattern may include a polymer.

[0009] The grid pattern may include a plurality of first grid lines extending in a first direction and arranged in a second direction intersecting the first direction, and a plurality of second grid lines extending in the second direction and arranged in the first direction while intersecting the plurality of first grid lines.

[0010] The insulating pattern may be provided in plurality so as to include a plurality of insulating patterns, the first portion may be provided in plurality so as to include a plurality of first portions, and each of the plurality of first portions may be arranged on an associated insulating pattern among the plurality of insulating patterns.

[0011] The insulating pattern may be provided in plurality so as to include a plurality of insulating patterns, and the first portion may be disposed on the plurality of insulating patterns.

[0012] A plurality of insulating patterns may be arranged in a first direction, and each of the plurality of first grid lines may intersect with the plurality of insulating patterns when viewed in a plan view, and the plurality of second grid lines may include a plurality of line groups, and each of the plurality of line groups may intersect with a related insulating pattern among the plurality of insulating patterns when viewed in a plan view.

[0013] The insulating pattern may be provided in plurality so as to include a plurality of insulating patterns, and the plurality of insulating patterns may be arranged in at least one of the first direction and the second direction.

[0014] When viewed in a cross-sectional view, the insulating pattern may have a semicircular shape.

[0015] The display module may further include a pad insulating layer between the signal line and the conductive pattern, and the pad insulating layer may have a contact hole defined in the pad insulating layer, spaced apart from the insulating pattern, and overlapping a portion of the signal line.

[0016] The conductive pattern may contact the signal line through the contact hole, and the insulating pattern may be directly disposed on the pad insulating layer.

[0017] The pixel may include a light emitting element, a transistor electrically connected to the light emitting element and including a semiconductor pattern and a gate overlapping the semiconductor pattern, an upper electrode arranged on the gate, and a plurality of conductive layers electrically connected to the transistor, arranged on the upper electrode, and arranged in mutually different layers. A portion of the signal line arranged under the conductive pattern and the gate or the upper electrode may include the same material, and the conductive pattern and at least one of the plurality of conductive layers may include the same material.

[0018] The signal pad may further include a lower conductive pattern disposed under the conductive pattern and contacting the signal line through the contact hole, and the insulating pattern may be between the lower conductive pattern and the conductive pattern.

[0019] The pixel may include a light emitting element, a transistor electrically connected to the light emitting element and including a semiconductor pattern and a gate overlapping the semiconductor pattern, an upper electrode arranged on the gate, and a plurality of conductive layers electrically connected to the transistor, arranged on the upper electrode, and arranged in mutually different layers. A portion of the signal line arranged under the conductive pattern and the gate or the upper electrode may include the same material.

[0020] The lower conductive pattern and at least one of the multiple conductive layers (e.g., at least some of the conductive layers) may include the same material, and the conductive pattern and other conductive layers of the multiple conductive layers arranged on the at least one of the conductive layers (e.g., at least some of the conductive layers) may include the same material.

[0021] The display module may further include a thin film encapsulation layer disposed on the pixel and a sensing electrode disposed on the thin film encapsulation layer. The lower conductive pattern and at least one conductive layer of the plurality of conductive layers may include the same material, and the conductive pattern and the sensing electrode may include the same material.

[0022] The display module may further include a sensor insulating layer between the lower conductive pattern and the conductive pattern and in contact with the sensing electrode, and the conductive pattern may be in contact with the lower conductive pattern through an upper contact hole defined in the sensor insulating layer.

[0023] According to an embodiment of the present disclosure, a display device may include a display module, and the display module may include a pixel, a signal line electrically connected to the pixel, and a signal pad electrically connected to the signal line. The signal pad may include an insulating pattern arranged on the signal line and a conductive pattern electrically connected to the signal line. When viewed in a cross-sectional view, at least a portion of the conductive pattern may have a form of a plurality of protrusions protruding from the insulating pattern.

[0024] At least a portion of the conductive pattern may include a plurality of first grid lines extending in a first direction and arranged in a second direction intersecting the first direction, and a plurality of second grid lines extending in a second direction and arranged in the first direction while intersecting the plurality of first grid lines. When viewed in a cross-sectional view in the first direction, the plurality of first grid lines may provide a form of a plurality of protrusions, and when viewed in a cross-sectional view in the second direction, the plurality of second grid lines may provide a form of a plurality of protrusions.

[0025] According to an embodiment of the present disclosure, a method for manufacturing a display device may include: providing a preliminary signal pattern including an insulating pattern; depositing a preliminary conductive pattern on the preliminary signal pattern; and patterning the preliminary conductive pattern to form a conductive pattern at least partially including a mesh pattern. At least a portion of the mesh pattern may be arranged on the insulating pattern.

[0026] Patterning the preliminary conductive pattern may include: forming a photoresist pattern on the preliminary conductive pattern; etching a portion of the preliminary conductive pattern exposed from the photoresist pattern; and removing the photoresist pattern to form the signal pad. BRIEF DESCRIPTION OF THE DRAWINGS

[0027] The above and other aspects and features of the present disclosure will become apparent by describing in detail embodiments of the present disclosure with reference to the attached drawings.

[0028] Figure 1 is a schematic perspective view showing a display device according to an embodiment of the present disclosure.

[0029] Figure 2A and Figure 2B is an exploded schematic perspective view of a display device according to an embodiment of the present disclosure.

[0030] Figure 3 is a schematic cross-sectional view showing a display module according to an embodiment of the present disclosure.

[0031] Figure 4 is a schematic plan view showing a display panel according to an embodiment of the present disclosure.

[0032] Figure 5 is a schematic cross-sectional view of a display panel according to an embodiment of the present disclosure.

[0033] Fig. 6A is a schematic cross-sectional view of an input sensor according to an embodiment of the present disclosure.

[0034] Figure 6B is a schematic plan view of an input sensor according to an embodiment of the present disclosure.

[0035] Figure 6C is a schematic cross-sectional view of a bridge pattern of an input sensor according to an embodiment of the present disclosure.

[0036] Figure 7 is an enlarged exploded schematic perspective view showing a display device according to an embodiment of the present disclosure;

[0037] Fig. 8A is a schematic plan view showing a pad area according to an embodiment of the present disclosure.

[0038] Figure 8B is an enlarged schematic plan view showing a portion of a pad area according to an embodiment of the present disclosure.

[0039] Fig.9A and Fig. 9B is corresponding to Fig. 8A Schematic cross-sectional view of .

[0040] Fig.10 is a schematic cross-sectional view showing a bonding structure of a display device according to an embodiment of the present disclosure;

[0041] Fig.11A is a schematic plan view showing a pad area according to an embodiment of the present disclosure.

[0042] Fig. 11B is an enlarged schematic plan view showing a portion of a pad area according to an embodiment of the present disclosure.

[0043] Fig.12 is a schematic plan view showing a pad area according to an embodiment of the present disclosure.

[0044] Fig.13 is corresponding to Fig.12 Schematic cross-sectional view of .

[0045] Fig.14 is a schematic plan view showing a pad area according to an embodiment of the present disclosure.

[0046] Fig.15A and Fig. 15B is corresponding to Fig.14 Schematic cross-sectional view of .

[0047] Fig.16 is a schematic plan view showing a pad area according to an embodiment of the present disclosure.

[0048] Fig.17A and Fig. 17B is corresponding to Fig.16 Schematic cross-sectional view of .

[0049] 18A to 18E are schematic cross-sectional views illustrating some steps in a method for manufacturing a display device according to an embodiment of the present disclosure. DETAILED DESCRIPTION

[0050] The present disclosure will now be described more fully below with reference to the accompanying drawings showing embodiments. However, the present disclosure may be implemented in different forms and should not be construed as being limited to the embodiments set forth herein. Instead, these embodiments are provided so that the present disclosure will be thorough and complete, and will fully convey the scope of the present disclosure to those skilled in the art.

[0051] In the specification, the expression that a first component (or region, layer, portion, part, etc.) is on, “connected to” or “coupled to” a second component means that the first component is directly on, directly connected to or directly coupled to the second component, or means that a third component is interposed therebetween.

[0052] The same reference numerals will be assigned to the same components. In addition, in the drawings, the thickness, proportion, and size of components may be exaggerated to effectively describe the technical features.

[0053] For the purpose of its meaning and interpretation, in the specification and claims, the term "and / or" is intended to include any combination of the terms "and" and "or". For example, "A and / or B" may be understood to mean "A, B, or A and B". The terms "and" and "or" may be used in conjunction or disjunction and may be understood to be equivalent to "and / or".

[0054] For purposes of its meaning and interpretation, in the specification and claims, the phrase "at least one of" is intended to include the meaning of "at least one selected from the group of..." For example, "at least one of A and B" may be understood to mean "A, B, or A and B".

[0055] Although the terms "first," "second," etc., may be used to describe various components, the components should not be construed as being limited by the terms. The terms are used only to distinguish one component from another. For example, a first component may be referred to as a second component, and similarly, a second component may be referred to as a first component, without departing from the scope and spirit of the present disclosure. Unless the context clearly indicates otherwise, the singular is intended to include the plural.

[0056] In addition, the terms "under", "a lower portion", "above", and "an upper portion" are used to describe the relationship between components shown in the drawings. The terms are relative and are described with reference to the directions indicated in the drawings.

[0057] It will also be understood that the terms “comprises,” “comprising,” “includes,” or “including,” or “having” specify the presence of stated features, numbers, steps, operations, components, parts, or combinations thereof, but do not preclude the presence or addition of one or more other features, numbers, steps, operations, components, parts, and / or combinations thereof.

[0058] The term "overlap" or "overlapped" means that a first object may be above or below a second object, or to the side of the second object, and vice versa. In addition, the term "overlap" may include stacking, stacking, facing or facing, extending over, covering or partially covering, or any other suitable term as will be appreciated and understood by those of ordinary skill in the art.

[0059] The terms "face" and "facing" mean that the first element can be directly or indirectly opposite to the second element. In the case where a third element is placed between the first element and the second element, although still facing each other, the first element and the second element can be understood as indirectly opposite to each other.

[0060] When an element is described as "non-overlapping" another element, this may include the elements being spaced apart, offset, or separated from each other, or any other suitable terminology as would be appreciated and understood by one of ordinary skill in the art.

[0061] Unless otherwise defined or implied, all terms (including technical terms and scientific terms) used in the specification have the same meaning as those commonly understood by those skilled in the art to which the present disclosure belongs. In addition, unless explicitly defined herein, terms (such as those defined in commonly used dictionaries) should be interpreted as having a meaning consistent with the meaning in the context of the relevant technology and should not be interpreted in an idealized or overly formal sense.

[0062] "About," "approximately," "substantially," and similar words include the stated value and mean within an acceptable range of deviation for the particular value as determined by one of ordinary skill in the art, taking into account the errors associated with the measurements and with the measurement of a particular quantity (i.e., the limitations of the measurement system). For example, "about" may mean within one or more standard deviations, or within ±30%, ±20%, ±10%, ±5% of the stated value. In addition, the term "about" may also be used to indicate relative position (e.g., rotation "about" an axis).

[0063] Figure 1 is a schematic perspective view showing a display device DD according to an embodiment of the present disclosure; Figure 2A and Figure 2B is an exploded schematic perspective view of a display device DD according to an embodiment of the present disclosure.

[0064] For example, Figure 2B Shows Figure 2A The bending area BA shown in FIG.

[0065] Reference Figure 1 According to this specification, a cellular terminal is shown as an example of a display device DD. However, the display device DD may include a large display device such as a TV or a monitor, or a small or medium-sized display device such as a tablet computer, a car navigation, a game console, or a smart watch.

[0066] When viewed in a plan view, the display device DD has a rectangular shape having longer sides extending in a first direction DR1 and shorter sides extending in a second direction DR2 crossing (intersecting) the first direction DR1. However, the embodiment is not limited thereto, and when viewed in a plan view, the display device DD may have various shapes such as a circular shape or a polygonal shape.

[0067] Hereinafter, a direction substantially perpendicular to a plane defined by the first direction DR1 and the second direction DR2 is defined as a third direction DR3. In the specification, the meaning of "when viewed in a plan view" may mean "when viewed in the third direction DR3".

[0068] The display device DD may be rigid or flexible. "Flexible property" refers to a bendable property, and the flexible structure may include a structure ranging from a completely folded structure to a structure that is bent at the level of a few nanometers. For example, the flexible display device DD may include a bendable display device, a rollable display device, or a foldable display device.

[0069] The display device DD may display an image IM through a display surface DD-IS. The drawings show an icon image as an example of the image IM. The display surface DD-IS may be parallel to a plane defined by the first direction DR1 and the second direction DR2.

[0070] The display surface DD-IS may include a display area DD-DA for displaying an image IM and a non-display area DD-NDA adjacent to the display area DD-DA. The non-display area DD-NDA may be an area where the image IM is not displayed. However, the present disclosure is not limited thereto. The non-display area DD-NDA may be adjacent to any side of the display area DD-DA, or may be omitted.

[0071] Reference Figure 2A and Figure 2B , the display device DD may include a window WM, a display module DM and a receiving member BC.

[0072] The window WM may be arranged on the display module DM and may transmit an image provided from the display module DM to the outside. The window WM may include a transmission area TA and a non-transmission area NTA. The transmission area TA may have a Figure 1 The display areas DD-DA shown in the figure overlap and correspond to the form of the display areas DD-DA. Although not shown, the window WM may include a base layer and a functional layer arranged on the base layer. The functional layer may include a protective layer and an anti-fingerprint layer. The base layer of the window WM may include at least one of glass, sapphire and plastic. The base layer of the window WM may include an optically transparent material. For example, the base layer of the window WM may include glass or a plastic film, or may include a glass substrate and a plastic film connected by an adhesive.

[0073] The non-transmitting area NTA may have Figure 1 The non-display area DD-NDA shown in FIG. overlaps and corresponds to the form of the non-display area DD-NDA. The non-transmission area NTA may have a transmittance lower than that of the transmission area TA. The non-transmission area NTA may be defined by a frame pattern provided in a partial area of ​​the base layer of the window WM, and an area where the frame pattern is not arranged is defined as the transmission area TA. However, the present disclosure is not limited thereto, and the non-transmission area NTA may be omitted.

[0074] Although not shown, an anti-reflection layer may be arranged between the window WM and the display module DM. The anti-reflection layer may reduce the reflectivity of external light incident from the outside of the display device DD. The anti-reflection layer may include a plurality of color filters. The plurality of color filters may have a specific array. For example, the plurality of color filters may be arranged (arranged) based on the luminous colors of the pixels included in the display panel DP to be described below. In addition, the anti-reflection layer may also include a black matrix adjacent to the color filter.

[0075] According to an embodiment of the present disclosure, the display module DM may include a display panel DP and an input sensor ISU.

[0076] The display panel DP may include a liquid crystal display panel, an electrophoretic display panel, a micro-electromechanical system display panel, an electrowetting display panel, an organic light-emitting display panel, an inorganic light-emitting display panel, and / or a quantum dot light-emitting display panel. However, the present disclosure is not limited thereto. Hereinafter, the display panel DP will be described as an organic light-emitting display panel.

[0077] The input sensor ISU may include any one of a capacitive sensor, an optical sensor, an ultrasonic sensor, and an electromagnetic induction sensor. The input sensor ISU may be formed on the display panel DP through subsequent processes. As another example, the input sensor ISU may be manufactured separately and may be bonded to the display panel DP through an adhesive layer.

[0078] The display device DD may further include a driving chip DC disposed on the display panel DP. The display device DD may further include a circuit board PB disposed on the display panel DP. According to an embodiment, the circuit board PB may be a flexible circuit board, but the present disclosure is not limited thereto. For example, the circuit board PB may be rigid. The circuit board PB may electrically connect the display panel DP to a main circuit board (e.g., a main board).

[0079] The driving chip DC may include driving elements such as a data driving circuit to drive the pixels of the display panel DP. Figure 2A It is shown that the driver chip DC is mounted on the display panel DP, but the present disclosure is not limited thereto. For example, the driver chip DC may be mounted on the circuit board PB. According to an embodiment, the driver chip DC and the circuit board PB directly mounted on the display panel DP may be collectively referred to as electronic components. Hereinafter, the bonding structure between the display panel DP and the circuit board PB may be similarly applied to another electronic component other than the circuit board PB, such as the driver chip DC.

[0080] The display panel DP may include a bending area BA, a first non-bending area NBA1, and a second non-bending area NBA2. The first non-bending area NBA1 and the second non-bending area NBA2 may be spaced apart from each other. The bending area BA may be between the first non-bending area NBA1 and the second non-bending area NBA2.

[0081] The bending area BA may be defined as an area where the display panel DP is bent according to (or around) a virtual bending axis BX extending in the second direction DR2. The first non-bending area NBA1 may be defined as an area overlapping the transmission area TA, and the second non-bending area NBA2 may be defined as an area connected to the circuit board PB. In the case where the bending area BA is bent around the virtual bending axis BX, the circuit board PB and the driving chip DC may be bent toward the rear surface of the display panel DP and may be arranged below the rear surface of the display panel DP. Although not shown, additional components may be arranged to compensate for the step difference between the circuit board PB and the rear surface of the display panel DP caused by the bending area BA.

[0082] According to an embodiment, the width of the first non-bending area NBA1 in the second direction DR2 may be greater than the widths of the bending area BA and the second non-bending area NBA2. However, the present disclosure is not limited thereto. The width of the bending area BA in the second direction DR2 may be provided to decrease from the first non-bending area NBA1 to the second non-bending area NBA2, and the present disclosure is not limited to any one embodiment.

[0083] like Figure 2B As shown in , when a portion of the display panel DP is bent, the circuit board PB electrically bonded to the display panel DP may be disposed on the rear surface of the display panel DP.

[0084] The receiving member BC may receive the display module DM and may be coupled to the window WM. The circuit board PB may be arranged at an end of the display panel DP and may be electrically connected to the reference Figure 3 Although not shown, the display device DD may further include a main board, an electronic module, a camera module, or a power module mounted on the main board.

[0085] Although the above description has been made in the case where a cellular phone is used as the display device DD, as described above, various types of display devices may be provided as long as the display device DD includes at least electronic components bonded to each other. The display panel DP and the driver chip DC mounted on the display panel DP may correspond to mutually different electronic components, and the display device DD may be provided using the display panel DP and the driver chip DC. The display panel DP and the circuit board PB connected to the display panel DP may correspond to mutually different electronic components, and the display device DD may be provided using only the display panel DP and the circuit board PB. In addition, the display device DD may be provided using only a main board and an electronic module mounted on the main board. Hereinafter, the display device DD according to the present disclosure will be described with emphasis on the bonding structure between the display panel DP and the driver chip DC mounted on the display panel DP.

[0086] Figure 3is a schematic cross-sectional view showing a display module DM according to an embodiment of the present disclosure.

[0087] Reference Figure 3 The display panel DP may include a base layer BL, a circuit element layer DP-CL disposed on the base layer BL, a display element layer DP-OLED, and an upper insulating layer TFL. The input sensor ISU may be disposed on the upper insulating layer TFL.

[0088] The display panel DP may include a display area DP-DA and a non-display area DP-NDA. The display area DP-DA of the display panel DP may correspond to Figure 1 The display area DD-DA or Figure 2A The non-display area DP-NDA may correspond to the transmission area TA shown in FIG. Figure 1 The non-display area DD-NDA shown in Figure 2A The non-transmitting area NTA shown in FIG.

[0089] The base layer BL may include at least one plastic film. The base layer BL may be used as a flexible substrate, and may include a plastic substrate, a glass substrate, a metal substrate, and / or an organic / inorganic composite substrate.

[0090] The circuit element layer DP-CL may include at least one intermediate insulating layer and a circuit element. The intermediate insulating layer may include at least one intermediate inorganic layer and at least one intermediate organic layer. The circuit element may include a signal line and a driving circuit of a pixel. The insulating layer, the semiconductor layer and the conductive layer may be formed by a process such as a coating process or a deposition process. Thereafter, the insulating layer, the semiconductor layer and the conductive layer may be selectively patterned by photolithography and etching processes. Semiconductor patterns, conductive patterns and signal lines may be formed by these processes. Patterns formed in the same layer may be formed by the same process. In this specification, forming a pattern by the same process means that the pattern may include the same material and have the same stacking structure.

[0091] The display element layer DP-OLED may include a light emitting element. The display element layer DP-OLED may further include an organic layer such as a pixel defining film.

[0092] The upper insulating layer TFL may seal the display element layer DP-OLED. The upper insulating layer TFL may be arranged on the display element layer DP-OLED. The upper insulating layer TFL according to the embodiment may overlap with the display area DP-DA and the non-display area DP-NDA. The upper insulating layer TFL may overlap with at least a portion of the non-display area DP-NDA. For example, the upper insulating layer TFL may include a thin film encapsulation layer. The thin film encapsulation layer may include a stacked structure of an inorganic layer, an organic layer, and an inorganic layer. The upper insulating layer TFL may protect the display element layer DP-OLED from foreign matter such as moisture, oxygen, and dust particles. However, the present disclosure is not limited thereto. In addition to the thin film encapsulation layer, the upper insulating layer TFL may also include an additional insulating layer. For example, the upper insulating layer TFL may also include an optical insulating layer to control the refractive index.

[0093] According to an embodiment of the present disclosure, a package substrate may be provided instead of the upper insulating layer TFL. In this case, the package substrate may face the base layer BL, and the circuit element layer DP-CL and the display element layer DP-OLED may be between the package substrate and the base layer BL.

[0094] The input sensor ISU may be arranged directly on the display panel DP. In the specification, component "A" being arranged directly on component "B" means that no separate layer is arranged between component "A" and component "B". According to an embodiment, the input sensor ISU may be manufactured by a process subsequent to the process for the display panel DP. However, the technical spirit of the present disclosure is not limited thereto, and the input sensor ISU provided as a separate panel may be coupled to the display panel DP by an adhesive layer. For example, the input sensor ISU may be omitted.

[0095] Figure 4 is a schematic plan view showing a display panel DP according to an embodiment of the present disclosure.

[0096] Reference Figure 4 , the display panel DP may include pixels PX, a gate driving circuit GDC, signal lines SGL, and signal pads DP-PD.

[0097] A plurality of pixels PX may be arranged in the display area DP-DA. Each of the plurality of pixels PX may include a light emitting element and a driving circuit of the pixel connected thereto. According to an embodiment, the light emitting element may be an organic light emitting element. The gate driving circuit GDC may sequentially output a gate signal to a gate line GL to be described later. The transistor of the gate driving circuit GDC may be formed by the same process as that for the transistor of the pixel PX, such as a low temperature polycrystalline silicon (LTPS) process or a low temperature polycrystalline oxide (LTPO) process. The display panel DP may further include another driving circuit to drive an emission control signal to the pixel PX.

[0098] The signal line SGL may include a gate line GL, a data line DL, a power line PL, and a control signal line CSL. A plurality of gate lines GL may be respectively connected to related pixels PX among a plurality of pixels PX, and a plurality of data lines DL may be respectively connected to related pixels PX among a plurality of pixels PX. The power line PL may be connected to a plurality of pixels PX. The control signal line CSL may provide a control signal to a scan driving circuit (e.g., a gate driving circuit GDC).

[0099] The plurality of signal lines SGL may overlap the display area DP-DA and the non-display area DP-NDA. Each of the plurality of signal lines SGL may include a line portion LP. Although not shown, the signal line SGL may further include a pad portion. The line portion LP may overlap the display area DP-DA and the non-display area DP-NDA. The pad portion may be connected to an end of the line portion LP. Fig. 8A The connection between the pad portion and the line portion LP is described in detail in FIG.

[0100] The signal pad DP-PD may include first, second and third pads PD1, PD2 and PD3. An area where the first and second pads PD1 and PD2 are arranged may be defined as a first pad area PA1, and an area where the third pad PD3 is arranged may be defined as a second pad area PA2.

[0101] The first pad area PA1 may be Figure 2A The first pad area PA1 may include a first area B1 in which a first pad PD1 is arranged and a second area B2 in which a second pad PD2 is arranged. The first pad area PA1 and the second pad area PA2 may be arranged in the non-display area DP-NDA. The first pad area PA1 and the second pad area PA2 may be spaced apart from each other in the first direction DR1. Although a row of pads arranged in the first pad area PA1 is provided by way of example, the present disclosure is not limited thereto. For example, a plurality of pad rows may be arranged in the first pad area PA1.

[0102] Each of the plurality of first pads PD1 may be connected to an associated data line DL among the data lines DL. Although not shown, the first pad PD1 and the second pad PD2 may be electrically connected to each other. The second pad PD2 may be connected to the third pad PD3 through a connection signal line S-CL.

[0103] The circuit board PB may include a plurality of substrate bump electrodes PB-BP. The plurality of substrate bump electrodes PB-BP may be arranged in the second direction DR2. The substrate bump electrodes PB-BP of the circuit board PB may contact and be connected to the third pad PD3 of the second pad area PA2.

[0104] Figure 5is a schematic cross-sectional view showing a display panel DP according to an embodiment of the present disclosure.

[0105] Reference Figure 5 , the display panel DP may include a base layer BL, a circuit element layer DP-CL arranged on the base layer BL, a display element layer DP-OLED, and an upper insulating layer TFL. By way of example, the first transistor T1 and the second transistor T2 may be arranged as a driving circuit of a pixel.

[0106] A plurality of insulating layers are arranged on the top surface of the base layer BL. The plurality of insulating layers may include a barrier layer BRL and a buffer layer BFL. The plurality of insulating layers may also include a first insulating layer 10 to a sixth insulating layer 60. The barrier layer BRL may prevent foreign matter from penetrating from the outside. The barrier layer BRL may include at least one of a silicon oxide layer and a silicon nitride layer. The silicon oxide layer may include a plurality of silicon oxide layers, and the silicon nitride layer may include a plurality of silicon nitride layers, and the plurality of silicon oxide layers and the plurality of silicon nitride layers may be stacked on each other.

[0107] The buffer layer BFL may improve coupling force between the base layer BL and the semiconductor pattern and / or the conductive pattern. The buffer layer BFL may include at least one of a silicon oxide layer and a silicon nitride layer. The silicon oxide layer and the silicon nitride layer may be stacked on each other.

[0108] A semiconductor pattern ACP may be disposed on the buffer layer BFL. The semiconductor pattern ACP may include an amorphous or crystalline silicon semiconductor or a metal oxide semiconductor. Figure 5 As shown in , the semiconductor pattern ACP may include a first semiconductor region AC1 and a second semiconductor region AC2. The first semiconductor region AC1 may include a source region S1, a channel region A1, and a drain region D1 of a first transistor T1, and the second semiconductor region AC2 may include a source region S2, a channel region A2, and a drain region D2 of a second transistor T2. According to an embodiment, the first transistor T1 and the second transistor T2 may include different semiconductors. The second transistor T2 may include a second semiconductor region AC2 having a material different from that of the first semiconductor region AC1, and the first semiconductor region AC1 and the second semiconductor region AC2 may be arranged in different layers.

[0109] A first insulating layer 10 may be disposed on the buffer layer BFL. The first insulating layer 10 may cover the semiconductor pattern ACP. The first insulating layer 10 may be an inorganic layer, but the present disclosure is not limited thereto. A first conductive layer CL10 may be disposed on the first insulating layer 10. The first conductive layer CL10 may include a plurality of conductive patterns. The first conductive layer CL10 may include a gate G1 of a first transistor T1 and a gate G2 of a second transistor T2. The first conductive layer CL10 may include at least one of molybdenum (Mo) having excellent heat resistance, an alloy containing molybdenum (Mo), titanium (Ti), and an alloy containing titanium, but the present disclosure is not limited thereto. The first conductive layer CL10 may have a single-layer structure or a multi-layer structure.

[0110] A second insulating layer 20 covering the first conductive layer CL10 may be arranged on the first insulating layer 10. The second insulating layer 20 may be an inorganic layer, but the present disclosure is not limited thereto. A second conductive layer CL20 may be arranged on the second insulating layer 20. The second conductive layer CL20 may include a plurality of conductive patterns. The second conductive layer CL20 may include an upper electrode UE. The upper electrode UE may overlap with the gate G1 of the first transistor T1 and may be formed with an opening UE-OP. The upper electrode UE and the gate G1 of the first transistor T1 overlapping each other may define a capacitor.

[0111] A third insulating layer 30 covering the second conductive layer CL20 may be arranged on the second insulating layer 20. The third insulating layer 30 may be an inorganic layer, but the present disclosure is not limited thereto. A third conductive layer CL30 may be arranged on the third insulating layer 30. The third conductive layer CL30 may include a conductive pattern. The third conductive layer CL30 may include a connection electrode CNE-G3. The connection electrode CNE-G3 may be connected to the gate G1 of the first transistor T1 through a contact hole CH10 formed through the second insulating layer 20 and the third insulating layer 30. The contact hole CH10 may pass through the opening UE-OP. Another connection electrode CNE-G3 may be connected to the source region S2 of the second transistor T2 through a contact hole CH20 formed through the first insulating layer 10, the second insulating layer 20, and the third insulating layer 30. The third conductive layer CL30 may also include a plurality of connection electrodes (not shown).

[0112] A fourth insulating layer 40 covering the third conductive layer CL30 may be disposed on the third insulating layer 30. The fourth insulating layer 40 may be an inorganic layer, but the present disclosure is not limited thereto. A fourth conductive layer CL40 may be disposed on the fourth insulating layer 40. The fourth conductive layer CL40 may include a plurality of conductive patterns. The fourth conductive layer CL40 may include a connection electrode CNE-D1. The connection electrode CNE-D1 may be connected to the corresponding connection electrode CNE-G3 through contact holes CH11 and CH21 penetrating the fourth insulating layer 40, respectively. The fourth conductive layer CL40 may also include a plurality of connection electrodes (not shown).

[0113] A fifth insulating layer 50 covering the fourth conductive layer CL40 may be disposed on the fourth insulating layer 40. The fifth insulating layer 50 may be an inorganic layer, but the present disclosure is not limited thereto. A fifth conductive layer CL50 may be disposed on the fifth insulating layer 50. The fifth conductive layer CL50 may include a plurality of conductive patterns. According to an embodiment, the fifth conductive layer CL50 may include a data line DL. The data line DL may be connected to the corresponding connection electrode CNE-D1 through a contact hole CH22 formed through the fifth insulating layer 50. The fifth conductive layer CL50 may further include a plurality of connection electrodes (not shown).

[0114] A sixth insulating layer 60 covering the fifth conductive layer CL50 may be disposed on the fifth insulating layer 50. The sixth insulating layer 60 may be an organic layer, but the present disclosure is not limited thereto. A light emitting element LD may be disposed on the sixth insulating layer 60. A first electrode AE ​​of the light emitting element LD may be disposed on the sixth insulating layer 60. The first electrode AE ​​may be an anode, and a pixel defining layer PDL is disposed on the sixth insulating layer 60.

[0115] The opening OP of the pixel defining film PDL may expose at least a portion of the first electrode AE. The opening OP of the pixel defining film PDL may define a light emitting region. A light emitting layer EML may be disposed on the first electrode AE. Although a patterned light emitting layer EML is shown according to the embodiment, the light emitting layer EML may be commonly disposed on a plurality of pixels PX (see Figure 4 ). The commonly arranged light emitting layers EML may generate white light or blue light. In addition, the light emitting layer EML may have a multi-layer structure.

[0116] Although not shown, a hole transport layer may be further disposed between the first electrode AE ​​and the light emitting layer EML. A hole injection layer may be between the hole transport layer and the first electrode AE. The hole transport layer or the hole injection layer may be commonly disposed in a plurality of pixels PX (refer to Figure 4 )middle.

[0117] A second electrode CE may be disposed on the light emitting layer EML. Although not shown, an electron transport layer may be further disposed between the second electrode CE and the light emitting layer EML. An electron injection layer may be between the electron transport layer and the second electrode CE. The electron transport layer or the electron injection layer may be commonly disposed in a plurality of pixels PX (refer to Figure 4 )middle.

[0118] Fig. 6A is a schematic cross-sectional view of an input sensor ISU according to an embodiment of the present disclosure. Figure 6B is a schematic plan view of an input sensor ISU according to an embodiment of the present disclosure. Figure 6C is a cross-sectional view of a bridge pattern of an input sensor ISU according to an embodiment of the present disclosure. Figure 6C is along Figure 6BA cross-sectional view of the bridge pattern of the input sensor ISU taken along line XX'.

[0119] The input sensor ISU may include a first insulating layer (hereinafter referred to as a "first sensing insulating layer") IS-IL1, a first conductive pattern layer IS-CL1, a second insulating layer (hereinafter referred to as a "second sensing insulating layer") IS-IL2, a second conductive pattern layer IS-CL2, and a third insulating layer (hereinafter referred to as a "third sensing insulating layer") IS-IL3. The first sensing insulating layer IS-IL1 may be directly disposed on the upper insulating layer TFL.

[0120] According to an embodiment of the present disclosure, the first sensing insulating layer IS-IL1 and / or the third sensing insulating layer IS-IL3 may be omitted. In the case where the first sensing insulating layer IS-IL1 is omitted, the first conductive pattern layer IS-CL1 may be disposed on the uppermost insulating layer of the upper insulating layer TFL. The third sensing insulating layer IS-IL3 may be replaced with an adhesive layer or an insulating layer of an anti-reflection member disposed on the input sensor ISU.

[0121] The first conductive pattern layer IS-CL1 may include a plurality of first conductive patterns, and the second conductive pattern layer IS-CL2 may include a plurality of second conductive patterns. Hereinafter, the first conductive pattern layer IS-CL1 and the first conductive pattern are assigned the same reference numerals, and the second conductive pattern layer IS-CL2 and the second conductive pattern are assigned the same reference numerals.

[0122] Each of the plurality of first conductive patterns IS-CL1 and the plurality of second conductive patterns IS-CL2 may have a single-layer structure or a structure (multi-layer structure) in which multiple layers are stacked in the third direction DR3. The conductive pattern in the multi-layer structure may include at least two of the plurality of transparent conductive layers and the plurality of metal layers. The conductive pattern in the multi-layer structure may include a metal layer containing mutually different metals. The transparent conductive layer may include at least one of indium tin oxide (ITO), indium zinc oxide (IZO), zinc oxide (ZnO), indium tin zinc oxide (ITZO), PEDOT, metal nanowires, and graphene. The metal layer may include at least one of molybdenum (Mo), silver (Ag), titanium (Ti), copper (Cu), aluminum (Al), and alloys thereof. The details of the stacking structure of each of the first conductive pattern layer IS-CL1 and the second conductive pattern layer IS-CL2 will be described later.

[0123] According to an embodiment, each of the first sensing insulating layer IS-IL1, the second sensing insulating layer IS-IL2, and the third sensing insulating layer IS-IL3 may include at least one of an inorganic layer and an organic layer. According to an embodiment, the first sensing insulating layer IS-IL1, the second sensing insulating layer IS-IL2, and the third sensing insulating layer IS-IL3 may include an inorganic layer. The inorganic layer may include at least one of silicon oxide, silicon nitride, and silicon oxynitride.

[0124] According to an embodiment, at least one of the first sensing insulating layer IS-IL1, the second sensing insulating layer IS-IL2, and the third sensing insulating layer IS-IL3 may include an organic layer. For example, the third sensing insulating layer IS-IL3 may include an organic layer. The organic layer may include at least one of acrylic resin, methacrylic resin, polyisoprene, vinyl resin, epoxy resin, polyurethane resin, cellulose resin, siloxane resin, polyimide resin, polyamide resin, and naphthalene resin.

[0125] Reference Figure 6B and Figure 6C , the input sensor ISU may include a sensing area IS-DA and a non-sensing area IS-NDA adjacent to the sensing area IS-DA. The sensing area IS-DA and the non-sensing area IS-NDA may correspond to Figure 4 The display area DP-DA and the non-display area DP-NDA are shown in FIG.

[0126] The input sensor ISU may include sensing electrodes arranged in the sensing area IS-DA. The sensing electrodes may include first sensing electrodes (hereinafter referred to as "first electrodes") E1-1 to E1-5 and second sensing electrodes (hereinafter referred to as "second electrodes") E2-1 to E2-4 that are insulated and intersecting each other. The input sensor ISU includes first signal lines SL1 and second signal lines SL2, the first signal lines SL1 are arranged in the non-sensing area IS-NDA and are electrically connected to the first electrodes E1-1 to E1-5, and the second signal lines SL2 are electrically connected to the second electrodes E2-1 to E2-4. The first electrodes E1-1 to E1-5, the second electrodes E2-1 to E2-4, the first signal lines SL1 and the second signal lines SL2 may be connected by reference to Fig. 6A The described plurality of first conductive patterns IS-CL1 and the plurality of second conductive patterns IS-CL2 are defined by a combination thereof.

[0127] Each of the first electrodes E1-1 to E1-5 and the second electrodes E2-1 to E2-4 may include a plurality of conductive lines crossing each other. The plurality of conductive lines may define a plurality of openings, and each of the first electrodes E1-1 to E1-5 and the second electrodes E2-1 to E2-4 may have a mesh shape. Each of the plurality of openings may be defined to correspond to Figure 5The opening OP of the pixel definition film PDL shown in FIG.

[0128] Any one of the first electrodes E1-1 to E1-5 and the second electrodes E2-1 to E2-4 may have an overall shape. According to an embodiment, the first electrodes E1-1 to E1-5 having an overall shape are provided by way of example. The first electrodes E1-1 to E1-5 may include a sensing portion SP1 and a middle portion CP1. Portions of the plurality of second conductive patterns IS-CL2 may correspond to the first electrodes E1-1 to E1-5.

[0129] Each of the second electrodes E2-1 to E2-4 may include a sensing pattern SP2 and a bridge pattern CP2 (or a connection pattern). Figure 6B and Figure 6C As shown in , two adjacent sensing patterns SP2 can be connected to two bridge patterns CP2 through a contact hole CH-I formed through the second sensing insulating layer IS-IL2, but the number of bridge patterns is not limited thereto. Some of the plurality of second conductive patterns IS-CL2 may correspond to the plurality of sensing patterns SP2. Some of the plurality of first conductive patterns IS-CL1 may correspond to the plurality of bridge patterns CP2.

[0130] According to an embodiment, the bridge pattern CP2 may be composed of Fig. 6A The first conductive pattern IS-CL1 shown in FIG. 1 is formed, and the first electrodes E1-1 to E1-5 and the sensing pattern SP2 may be formed of a plurality of second conductive patterns IS-CL2, but the present disclosure is not limited thereto. The first electrodes E1-1 to E1-5 and the sensing pattern SP2 may be formed of Fig. 6A The plurality of first conductive patterns IS-CL1 shown in FIG. 8 is formed, and the plurality of bridge patterns CP2 may be formed of the plurality of second conductive patterns IS-CL2.

[0131] One of the first signal line SL1 and the second signal line SL2 can receive a transmission signal for sensing an external input from an external circuit, and the other of the first signal line SL1 and the second signal line SL2 can transmit the capacitance change between the first electrodes E1-1 to E1-5 and the second electrodes E2-1 to E2-4 to the external circuit in the form of a reception signal.

[0132] Some of the plurality of second conductive patterns IS-CL2 may correspond to the first signal line SL1 and the second signal line SL2. The first signal line SL1 and the second signal line SL2 may have a multi-layer structure and may include a first layer line formed by the plurality of first conductive patterns IS-CL1 and a second layer line formed by the plurality of second conductive patterns IS-CL2. The first layer line and the second layer line may be connected through a contact hole formed through the second sensing insulating layer IS-IL2.

[0133] Figure 7 is an enlarged exploded schematic perspective view of the first pad area PA1 and the second pad area PA2 of the display device DD according to an embodiment of the present disclosure. Figure 7 The driving chip DC and the circuit board PB are shown decomposed from the display panel DP. Figure 7 The first pad PD1, the second pad PD2, the connection signal line SCLn and the third pad PD3 can be connected to Figure 4 The first pad PD1, the second pad PD2, the connection signal line S-CL, and the third pad PD3 are the same, so the description thereof will be omitted or simplified.

[0134] Reference Figure 4 and Figure 7 , the driving chip DC may be bonded to the first pad area PA1 through the first adhesive layer CF1. The circuit board PB may be bonded to the second pad area PA2 through the second adhesive layer CF2. The first adhesive layer CF1 and the second adhesive layer CF2 may include a synthetic resin having adhesive properties. According to an embodiment, the first adhesive layer CF1 and the second adhesive layer CF2 may not include the conductive balls and may include only the synthetic resin having adhesive properties.

[0135] The driving chip DC may include a driving integrated circuit D-IC and a chip bump electrode DC-BP installed in the driving chip DC. The driving integrated circuit D-IC may include a top surface DC-US and a bottom surface DC-DS, and the bottom surface DC-DS may be a surface facing the first pad PD1 and the second pad PD2. The chip bump electrode DC-BP may be arranged on the bottom surface DC-DS of the driving integrated circuit D-IC.

[0136] The chip bump electrode DC-BP may include a plurality of first bumps BP1 electrically connected to the plurality of first pads PD1, respectively, and a plurality of second bumps BP2 electrically connected to the plurality of second pads PD2, respectively. The plurality of first bumps BP1 may be arranged in the second direction DR2, and the plurality of second bumps BP2 may be spaced apart from the plurality of first bumps BP1 in the first direction DR1 and may be arranged in the second direction DR2.

[0137] The driving chip DC may receive a first signal from the outside through the second pad PD2 and the second bump BP2. The driving chip DC may provide a second signal generated based on the first signal to the first pad PD1 through the first bump BP1. For example, the driving chip DC may include a data driving circuit. The first signal may be an image signal of a digital signal applied from the outside, and the second signal may be a data signal as an analog signal. The driving chip DC may generate an analog voltage corresponding to the grayscale value of the image signal. The data signal may be Figure 4 The data lines DL shown in FIG. 1 are provided to the pixels PX.

[0138] Although not shown, the first bump BP1 and the second bump BP2 may have a form protruding from the bottom surface DC-DS of the driving integrated circuit D-IC and exposed to the outside. When the first adhesive layer CF1 is cured, the first pad PD1 and the first bump BP1 may be fixed while in contact with each other, and the second pad PD2 and the second bump BP2 may be fixed while in contact with each other.

[0139] The circuit board PB may include a base layer P-BS and a substrate bump electrode PB-BP installed in the circuit board PB. The circuit board PB may include a top surface PB-US and a bottom surface PB-DS, and the bottom surface PB-DS may be a surface facing the third pad PD3. The substrate bump electrode PB-BP may be arranged on the bottom surface PB-DS of the base layer P-BS. A plurality of substrate bump electrodes PB-BP may be electrically connected to a plurality of third pads PD3, respectively. A plurality of substrate bump electrodes PB-BP may be arranged in a second direction DR2. The circuit board PB may provide image signals, driving voltages, and other control signals to the driving chip DC.

[0140] Although not shown, the substrate bump electrode PB-BP may have a form protruding from the bottom surface PB-DS of the base layer P-BS and exposed to the outside. When the second adhesive layer CF2 is cured, the third pad PD3 and the substrate bump electrode PB-BP may be fixed in contact with each other.

[0141] The electronic component may include a substrate and a bump electrode arranged under the substrate. In the case where the electronic component corresponds to a driving chip DC, the substrate may correspond to a driving integrated circuit D-IC of the driving chip DC, and the bump electrode may correspond to a chip bump electrode DC-BP. As another example, in the case where the electronic component corresponds to a circuit board PB, the substrate may correspond to a base layer P-BS of the circuit board PB, and the bump electrode may correspond to a substrate bump electrode PB-BP.

[0142] Fig. 8A is a schematic plan view of a pad region according to an embodiment of the present disclosure. Figure 8B is an enlarged schematic plan view showing a portion of a pad area according to an embodiment of the present disclosure. Fig.9A and Fig. 9B is corresponding to Fig. 8A sectional view of . Fig.10 is a schematic cross-sectional view illustrating a bonding structure of a display device DD according to an embodiment of the present disclosure. Fig.9A is along Fig. 8A A schematic cross-sectional view of the first pad area PA1 and the second pad area PA2 taken along the line AA', and Fig. 9B is along Fig. 8AFIG. 5 is a schematic cross-sectional view of the first pad area PA1 and the second pad area PA2 taken along line BB′.

[0143] Fig. 8A is a schematic plan view of a first pad area PA1 and a second pad area PA2 according to an embodiment of the present disclosure. Figure 8B is a plan view showing the first pad area PA1 and the second pad area PA2 according to an embodiment of the present disclosure. Fig.9A and Fig. 9B is corresponding to Fig. 8A sectional view of .

[0144] Fig.10 is a cross-sectional view showing a bonding structure of a display device DD according to an embodiment of the present disclosure.

[0145] Fig.9A is along Fig. 8A A cross-sectional view of the first pad area PA1 and the second pad area PA2 taken along the line AA', and Fig. 9B is along Fig. 8A BB' is a cross-sectional view of the first pad area PA1 and the second pad area PA2.

[0146] FIG. 8A to FIG. 10 The signal pads (or signal structures) shown in DP-PD can be used as reference Figure 4 and Figure 7 Any one of the described first to third pads PD1 to PD3. Fig. 8A The data line DL including the distal portion DL-E and the line portion DL-S having different widths is shown as an example of a signal line, but the present disclosure is not limited thereto. The signal line may be a signal line other than the data line DL, and may have a uniform width without distinguishing between the distal portion DL-E and the line portion DL-S.

[0147] Hereinafter, the first pad area PA1 and the second pad area PA2 will be described with a focus on the first pad area PA1 where the data line DL is arranged. Figure 4 ) instead of the data line DL, the description of the second pad area PA2 will be understood by referring to the description about the first pad area PA1.

[0148] Reference Fig. 8A The signal pad DP-PD may include a lower conductive pattern CL-L, a conductive pattern CL, and at least one insulating pattern SP. The lower conductive pattern CL-L may be connected to a distal end portion DL-E of the data line DL through at least one contact hole OP-C. Fig. 8A The signal pad DP-PD including two contact holes OP-C and two insulation patterns SP is shown.

[0149] When viewed in a plan view, the distal portion DL-E may have a form extending in the first direction DR1. In other words, the length or width of the distal portion DL-E in the first direction DR1 may be greater than the length or width of the distal portion DL-E in the second direction DR2.

[0150] When viewed in a plan view, the contact hole OP-C may overlap with the distal end portion DL-E. When viewed in a plan view, a portion of the lower conductive pattern CL-L may overlap with the contact hole OP-C.

[0151] According to an embodiment, a plurality of contact holes OP-C may be arranged to be spaced apart from each other in the first direction DR1. For example, a plurality of contact holes OP-C may be arranged at one side (or upper side) of the distal end portion DL-E in the first direction DR1 and at an opposite side (or lower side) of the distal end portion DL-E in the first direction DR1, respectively. The arrangement of the contact holes OP-C is not limited to one embodiment.

[0152] When viewed in a plan view, the insulating pattern SP may be arranged outside the contact hole OP-C. According to an embodiment, a plurality of insulating patterns SP may be arranged in the first direction DR1. The plurality of insulating patterns SP may be arranged to be spaced apart from each other in the first direction DR1. According to an embodiment, the plurality of insulating patterns SP may be between the contact hole OP-C arranged at one side of the distal end portion DL-E and the contact hole OP-C arranged at the opposite side of the distal end portion DL-E. The arrangement of the plurality of insulating patterns SP is not limited to the embodiment.

[0153] although Fig. 8A The insulating pattern SP having a rectangular shape when viewed in a plan view is shown, but the present disclosure is not limited thereto. When viewed in a plan view, the shape of the insulating pattern SP may be changed to another polygonal shape, a circular shape, an elliptical shape, rather than a rectangular shape. In addition, the shape of the insulating pattern SP when viewed in a plan view is not limited to the same.

[0154] According to an embodiment, the conductive pattern CL may include at least one first portion P1 and a second portion P2 adjacent to the first portion P1. According to an embodiment, the second portion P2 may surround the first portion P1 when viewed in a plan view. According to an embodiment, the first portion P1 may overlap with the associated insulating pattern SP. The number of first portions P1 may be provided corresponding to the number of insulating patterns SP. Fig. 8A It is shown that the conductive pattern CL includes two first portions P1 respectively overlapping the two insulating patterns SP.

[0155] Figure 8BAn enlarged portion of the conductive pattern CL is shown to describe the shape of the first portion P1 of the conductive pattern CL, and for convenience of description, the insulating pattern SP is shown together. Figure 8B A contact portion between the first portion P1 of the conductive pattern CL and the insulating pattern SP is shown.

[0156] Reference Figure 8B , the first portion P1 of the conductive pattern CL may be provided in a mesh shape. The first portion P1 of the conductive pattern CL may be referred to as a mesh portion, and the second portion P2 of the conductive pattern CL may be referred to as a peripheral portion.

[0157] The conductive pattern CL may include, in the first portion P1 , a plurality of first mesh lines MSL1 extending in the first direction DR1 and arranged in the second direction DR2 , and a plurality of second mesh lines MSL2 extending in the second direction DR2 , crossing the first mesh lines MSL1 , and arranged in the first direction DR1 .

[0158] Figure 8B It is illustrated that the plurality of first mesh lines MSL1 and the plurality of second mesh lines MSL2 all have the same width, but the present disclosure is not limited thereto. The first mesh lines MSL1 and / or the second mesh lines MSL2 may have a width that varies according to an arrangement direction.

[0159] Figure 8B It is shown that the plurality of first grid lines MSL1 and the plurality of second grid lines MSL2 are arranged to have a certain distance from each other, but the present disclosure is not limited thereto. The plurality of first grid lines MSL1 and / or the plurality of second grid lines MSL2 may be arranged to have a distance that changes according to an arrangement direction.

[0160] According to an embodiment, since the first portion P1 of the conductive pattern CL has a mesh shape, a portion of the insulating pattern SP may be exposed from the conductive pattern CL.

[0161] Reference Fig.9A and Fig. 9B , the distal end portion DL-E may be arranged on the first insulating layer 10. The distal end portion DL-E may be arranged Figure 5 The distal portion DL-E may be formed by the same process as the gates G1 and G2.

[0162] However, the position of the distal end portion DL-E is not limited thereto. The distal end portion DL-E may be arranged at a position corresponding to Figure 5 The upper electrode UE shown in Figure 5The third conductive layer CL30 shown in FIG. 1 may include the same material as the upper electrode UE or the connecting electrode CNE-G3 and may have the same structure as the upper electrode UE or the connecting electrode CNE-G3. One of the plurality of signal lines may be formed by the same process as the gates G1 and G2, and the other signal lines may be formed by the same process as the upper electrode UE or the connecting electrode CNE-G3 of the third conductive layer CL30.

[0163] The data line DL may be arranged on one layer to have an integral shape, but the present disclosure is not limited thereto. The data line DL may include a plurality of portions arranged on different layers. For example, the line portion DL-S may include two or more portions.

[0164] The lower conductive pattern CL-L may be disposed on the fourth insulating layer 40. The lower conductive pattern CL-L may be connected to the distal portion DL-E through a contact hole OP-C formed through the second insulating layer 20, the third insulating layer 30, and the fourth insulating layer 40. In other words, the lower conductive pattern CL-L may contact the distal portion DL-E through the contact hole OP-C. The second insulating layer 20, the third insulating layer 30, and the fourth insulating layer 40 may be connected to the display area DP-DA (see Figure 4 )of Figure 5 The second insulating layer 20, the third insulating layer 30 and the fourth insulating layer 40 shown in are formed by the same process. In the specification, the insulating layer arranged between the distal portion DL-E and the lower conductive pattern CL-L may be defined as a pad insulating layer IL-P. According to an embodiment, the second insulating layer 20, the third insulating layer 30 and the fourth insulating layer 40 may be defined as a pad insulating layer IL-P. The stacking structure of the pad insulating layer IL-P may be changed according to the stacking structure of the circuit element layer DP-CL. According to an embodiment, the contact hole OP-C may be defined in an insulating layer having a greater number than the second insulating layer 20, the third insulating layer 30 and the fourth insulating layer 40.

[0165] The lower conductive pattern CL-L and the distal portion DL-E may be separated from each other by a pad insulating layer IL-P (e.g., second insulating layer 20, third insulating layer 30, and fourth insulating layer 40). The pad insulating layer IL-P may be between the lower conductive pattern CL-L and the distal portion DL-E.

[0166] The conductive pattern CL may be disposed on the lower conductive pattern CL-L. A region of the conductive pattern CL in a non-overlapping region with the insulating pattern SP may contact the lower conductive pattern CL-L.

[0167] According to an embodiment, the lower conductive pattern CL-L may be connected to a conductive layer including a connection electrode (eg, Figure 5The conductive pattern CL may be formed by the same process as that of any one of the third conductive layer CL30 to the fifth conductive layer CL50 (of the embodiment of the present invention). Figure 5 The lower conductive pattern CL-L may be formed by the same process as the other conductive layers on the certain conductive layer among the third conductive layer CL30 to the fifth conductive layer CL50. Therefore, the lower conductive pattern CL-L may include the same material as the material of the certain conductive layer among the conductive layers including the connection electrodes, and the conductive pattern CL may include the same material as the other conductive layers among the conductive layers including the connection electrodes.

[0168] According to an embodiment, the lower conductive pattern CL-L may be formed by Figure 5 The fourth conductive layer CL40 is formed by the same process as that of the fourth conductive layer CL40, and the conductive pattern CL can be formed by Figure 5 The fifth conductive layer CL50 is formed by the same process. However, the present disclosure is not limited thereto. The distal portion DL-E, the lower conductive pattern CL-L and the conductive pattern CL may be Figure 5 The combination of different layers among the first conductive layer CL10 to the fifth conductive layer CL50 is provided in various ways. In addition, the combination of the conductive layers formed by the same process as the distal portion DL-E, the lower conductive pattern CL-L and the conductive pattern CL can be selected in various ways according to the stacking structure of the circuit element layer DP-CL.

[0169] The lower conductive pattern CL-L and the conductive pattern CL may include a conductive material. According to an embodiment, the lower conductive pattern CL-L and the conductive pattern CL may have a stack structure of Ti / Al / Ti, Ti / CU, Ti / ITO, Ti / Al, or Ti / Al / TiN. However, the materials and stack structures included in the lower conductive pattern CL-L and the conductive pattern CL are not limited to any one embodiment.

[0170] Although the drawings show that the edge of the conductive pattern CL is arranged outside and covers the edge of the lower conductive pattern CL-L, the present disclosure is not limited thereto. The edge of the conductive pattern CL may be substantially aligned with the edge of the lower conductive pattern CL-L.

[0171] When viewed in a cross-sectional view, the insulating pattern SP may be between the lower conductive pattern CL-L and the conductive pattern CL. The insulating pattern SP is disposed on the lower conductive pattern CL-L and may be partially covered by the conductive pattern CL. The insulating pattern SP may be directly disposed on the lower conductive pattern CL-L.

[0172] When viewed in a cross-sectional view, the insulating pattern SP may have a semicircular shape. The insulating pattern SP may include a bottom surface BS and a protruding surface PS, and when viewed in a cross-sectional view, the protruding surface PS of the insulating pattern SP may have a semicircular shape. According to an embodiment, the bottom surface BS of the insulating pattern SP may contact the lower conductive pattern CL-L. A portion of the conductive pattern CL may contact the protruding surface PS of the insulating pattern SP. The first portion P1 of the conductive pattern CL may contact a portion of the protruding surface PS of the insulating pattern SP, and the second portion P2 of the conductive pattern CL may contact a portion of the protruding surface PS of the insulating pattern SP and the top surface of the lower conductive pattern CL-L. A portion of the protruding surface PS of the insulating pattern SP may be exposed from the conductive pattern CL. According to an embodiment of the present disclosure, the second portion P2 of the conductive pattern CL may not contact the insulating pattern SP.

[0173] The insulating pattern SP may include a polymer. The insulating pattern SP may include a thermosetting polymer. However, the present disclosure is not limited thereto, and the insulating pattern SP may include a thermoplastic polymer.

[0174] According to an embodiment, the insulating pattern SP may be formed by the same process as an organic layer disposed on (or in) the circuit element layer DP-CL. Therefore, an additional process for forming the insulating pattern SP may not be required. For example, the insulating pattern SP may be formed by forming a first insulating layer 50 (see FIG. 5 ). Figure 5 However, the present disclosure is not limited thereto, and the combination of the connection electrodes formed by the same process as the lower conductive pattern CL-L and the conductive pattern CL may be formed according to the circuit element layer DP-CL (see Figure 5 Therefore, the insulating layer formed by the same process as the insulating pattern SP can be variously selected.

[0175] Fig. 9B The maximum width w (eg, the width of the bottom surface BS of the insulating pattern SP) and the height h of the insulating pattern SP are shown and can be variously set. The ratio between the maximum width w and the height h of the insulating pattern SP can be variously set.

[0176] A portion of the conductive pattern CL covering the insulating pattern SP may protrude from the lower conductive pattern CL-L in comparison with another portion of the conductive pattern CL. Fig. 9B The first grid line MSL1 is not aligned with the second grid line MSL2 (see Figure 8B ) is a cross-sectional view of the intersection of Fig. 9BAs shown in , each of the plurality of first mesh lines MSL1 may protrude in a direction away from the protruding surface PS of the insulating pattern SP when viewed in a cross-sectional view. Each of the plurality of first mesh lines MSL1 may be provided in the form of a protrusion protruding from the insulating pattern SP when viewed in a cross-sectional view.

[0177] According to an embodiment, an end portion of each of the plurality of first mesh lines MSL1 may have a circular shape when viewed in a cross-sectional view. However, the present disclosure is not limited thereto, and an end portion of each of the plurality of first mesh lines MSL1 may have an angled shape when viewed in a cross-sectional view.

[0178] Fig. 9B The first mesh line MSL1 is shown to provide protrusions having substantially the same protrusion length, but the present disclosure is not limited thereto. The protrusions provided by the first mesh line MSL1 may have protrusion lengths different from each other, for example, the protrusions may have protrusion lengths increasing outward from a central portion of the insulation pattern SP.

[0179] Even in the cross-section of the portion of the second grid line MSL2 that does not cross the first grid line MSL1, when viewed in the cross-sectional view, each of the plurality of second grid lines MSL2 protrudes in a direction away from the protruding surface PS of the insulating pattern SP, and may be provided in the cross-section in the form of a protrusion protruding from the insulating pattern SP. In other words, according to an embodiment, when viewed in the cross-sectional view in the first direction DR1, the plurality of first grid lines MSL1 may provide the form of a plurality of protrusions, and when viewed in the cross-sectional view in the second direction DR2, the plurality of second grid lines MSL2 may provide the form of a plurality of protrusions.

[0180] Fig.10 A driving chip DC is shown as an electronic component. Fig.10 The chip bump electrode DC-BP of the driving chip DC is shown (see Figure 7 ) is in contact with the conductive pattern CL.

[0181] The first bump BP1 of the driving chip DC can pass through the first adhesive layer CF1 (see Figure 7 ) contacts at least a portion of the first portion P1 of the conductive pattern CL. The first adhesive layer CF1 before curing may have a viscosity lower than that of the anisotropic conductive film. The anisotropic conductive film has a greater viscosity to facilitate alignment of the conductive balls.

[0182] Since the first portion P1 of the conductive pattern CL is arranged on the insulating pattern SP and protrudes toward the first bump BP1, the first portion P1 and the first bump BP1 can be in close contact with each other, and the contact resistance between the first portion P1 and the first bump BP1 can be reduced. Since the conductive balls are omitted, even if the signal pads DP-PD are densely provided, the short circuit defect caused by the conductive balls can be reduced. Since the accessibility between the signal pads DP-PD and the first bump BP1 is improved, the bonding pressure can be reduced. Since the bonding pressure is reduced, the physical damage to the display panel DP or the electronic components caused in the bonding process can be reduced.

[0183] According to an embodiment, since the portion of the conductive pattern CL including the mesh pattern in the signal pad DP-PD is arranged on the insulating pattern SP, the mesh pattern of the conductive pattern CL may have a form protruding from the insulating pattern SP. The insulating pattern SP may provide a high resilience against the bonding pressure. Therefore, the mesh pattern of the conductive pattern CL and the bump electrode (e.g., the first bump BP1) may be in close contact with each other.

[0184] In addition, since the mesh pattern of the conductive pattern CL is arranged on the insulating pattern SP, the mesh pattern of the conductive pattern CL may be provided in the form of a protrusion protruding from the insulating pattern SP. In other words, the first mesh line MSL1 (see FIG. 1 ) constituting the mesh pattern Figure 8B ) and the second grid line MSL2 (see Figure 8B ) may correspond to a protrusion of the insulating pattern SP. Therefore, during the bonding process, pressure may be provided to the first mesh line MSL1 (see Figure 8B ) and the second grid line MSL2 (see Figure 8B ) in each of the corresponding protrusions. Therefore, in the case where the entire portion of the insulating pattern SP is covered, the degree of extrusion in the conductive pattern CL covering the insulating pattern SP with a grid pattern may be increased. Therefore, the grid pattern of the conductive pattern CL may have a relatively large degree of stretching. Even after the bonding process is completed, the grid pattern of the conductive pattern CL maintains close contact with the bump electrode, thereby maintaining a stable electrical connection. More specifically, even after the bonding pressure is removed, the formation of a gap between the grid pattern of the conductive pattern CL and the bump electrode may be prevented, or the formation of the gap may be reduced. Therefore, the bonding resistance between the conductive pattern CL and the bump electrode may be reduced, and a display device DD having improved bonding reliability may be provided (see Figure 1 ).

[0185] Fig.11A is a schematic plan view of a first pad area PA1 and a second pad area PA2 according to an embodiment of the present disclosure. Fig. 11B1 is an enlarged schematic plan view showing a portion of a first pad area PA1 and a second pad area PA2 according to an embodiment of the present disclosure. In the following description, the same / similar reference numerals are assigned to Figures 1 to 10 For the same / similar parts described in the description, redundant description is omitted and the differences are described.

[0186] Reference Fig.11A According to an embodiment, the signal pad DP-PD may include a lower conductive pattern CL-L, a conductive pattern CL, and at least one insulating pattern SP.

[0187] The conductive pattern CL may include at least one first portion P1 and a second portion P2 adjacent to the first portion P1. When viewed in a plan view, the second portion P2 may surround the first portion P1. According to an embodiment, a plurality of insulating patterns SP may overlap the first portion P1. In other words, the first portion P1 may be arranged on the plurality of insulating patterns SP. Fig.11A It is shown that the conductive pattern CL includes the first portion P1 , the signal pads DP-PD include two insulating patterns SP arranged in the first direction DR1 , and the first portion P1 is commonly disposed on the two insulating patterns SP.

[0188] Fig. 11B An enlarged view of the first portion P1 of the conductive pattern CL is shown to describe a planar shape of the first portion P1 of the conductive pattern CL, and for convenience of description, an insulating pattern SP is shown together.

[0189] like Fig. 11B As shown in , the first portion P1 of the conductive pattern CL may be provided in the form of a mesh pattern. The mesh pattern of the first portion P1 may include a plurality of first mesh lines MSL1 extending in the first direction DR1 and arranged in the second direction DR2, and a plurality of second mesh lines MSL2 extending in the second direction DR2, crossing the plurality of first mesh lines MSL1, and arranged in the first direction DR1.

[0190] According to an embodiment, when viewed in a plan view, the first mesh line MSL1 may cross each of a plurality of insulating patterns SP arranged in a first direction DR1. The plurality of second mesh lines MSL2 may include a first group of lines MG1 and a second group of lines MG2. When viewed in a plan view, the first group of lines MG1 may cross an insulating pattern SP arranged at an upper side of the two insulating patterns SP. When viewed in a plan view, the second group of lines MG2 may cross an insulating pattern SP arranged at a lower side of the two insulating patterns SP.

[0191] The arrangement of the first mesh lines MSL1 and the second mesh lines MSL2 may be changed according to the number and arrangement of the insulating patterns SP. For example, in the case where the plurality of insulating patterns SP are arranged in the second direction DR2, the plurality of first mesh lines MSL1 may include a plurality of group lines. In the case where the plurality of insulating patterns SP are arranged along both the first direction DR1 and the second direction DR2, the plurality of first mesh lines MSL1 and the plurality of second mesh lines MSL2 may include a plurality of group lines.

[0192] This disclosure is not limited to Fig. 11B For example, the first mesh lines MSL1 and / or the second mesh lines MSL2 may be arranged even at portions where the insulating pattern SP may not be arranged, so that some of the first mesh lines MSL1 and / or the second mesh lines MSL2 may not cross the insulating pattern SP.

[0193] Fig.12 is a schematic plan view of a first pad area PA1 and a second pad area PA2 according to an embodiment of the present disclosure. Fig.13 is corresponding to Fig.12 Schematic cross-sectional view of . Fig.13 is along Fig.12 A cross-sectional view of the first pad area PA1 and the second pad area PA2 taken along the line CC'. In the following description, the same / similar reference numerals are assigned to Figures 1 to 10 For the same / similar parts described in the description, redundant description is omitted and the differences are described.

[0194] Reference Fig.12 , the signal pad DP-PD according to an embodiment may include a lower conductive pattern CL-L, a conductive pattern CL, and at least one insulating pattern SP.

[0195] According to an embodiment, the plurality of insulating patterns SP may be arranged in both the first direction DR1 and the second direction DR2. In other words, the plurality of insulating patterns SP may be arranged in the form of m rows and n columns ("m" and "n" are natural numbers of at least 2). Fig.12 It is shown that the signal pad DP-PD includes four insulation patterns SP, and the four insulation patterns SP are arranged in the form of two rows and two columns. The number of the insulation patterns SP is not limited thereto.

[0196] When viewed in a plan view, the conductive pattern CL may include a plurality of first portions P1 and a second portion P2 surrounding the plurality of first portions P1. Each of the plurality of first portions P1 may overlap with an associated insulating pattern SP. Each of the plurality of first portions P1 may overlap with an associated insulating pattern SP. Fig.12 It is shown that the conductive pattern CL includes four first portions P1 respectively arranged on four insulating patterns SP. The number of the first portions P1 may vary according to the number of the insulating patterns SP.

[0197] Each of the plurality of first portions P1 of the conductive pattern CL may be provided as a mesh pattern, as described above with reference to FIG. Figure 8B The mesh pattern of each of the plurality of first portions P1 may include a plurality of first mesh lines MSL1 extending in the first direction DR1 and arranged in the second direction DR2 (see Figure 8B ) and extending in the second direction DR2 and intersecting with a plurality of first grid lines MSL1 (see Figure 8B ) and arranged along the first direction DR1 (see Figure 8B ).

[0198] With the above Fig. 11B Similar to what is described in FIG. 1 , the conductive pattern CL may be provided such that the first portion P1 is arranged across the plurality of insulating patterns SP when viewed in a plan view, and the plurality of first mesh lines MSL1 (see FIG. 1 ) Fig. 11B ) and / or a plurality of second grid lines MSL2 (see Fig. 11B ) may include a plurality of group lines. In this case, the number of the insulating patterns SP crossing the first portion P1 when viewed in a plan view is not limited to any one embodiment.

[0199] Reference Fig.12 and Fig.13 When viewed on a cross section of the signal pad DP-PD in the first direction DR1, a plurality of insulating patterns SP arranged in the second direction DR2 may be arranged on the lower conductive pattern CL-L. In the following description, the same / similar reference numerals are assigned to the lower conductive pattern CL-L. Figures 1 to 11B For the same / similar parts described in the description, redundant description is omitted and the differences are described.

[0200] According to an embodiment, the mesh pattern of the conductive pattern CL may not exist between adjacent portions of the insulating pattern SP facing each other in the second direction DR2. In this case, when viewed in a cross-sectional view in the first direction DR1, the conductive pattern CL (specifically, the mesh pattern on the insulating pattern SP) may have an asymmetric shape with respect to a center line of the insulating pattern SP extending in the first direction DR1 (e.g., a shape asymmetric in the second direction DR2 with respect to a center line of the insulating pattern SP extending in the first direction DR1). However, Fig.13 For example, if the insulating patterns SP facing each other in the second direction DR2 are spaced apart from each other by a sufficient distance, the conductive pattern CL (specifically, the mesh pattern on the insulating pattern SP) may be provided to have a shape symmetrical in the second direction DR2 about a center line of the insulating pattern SP extending in the first direction DR1.

[0201] Fig.14 is a schematic plan view of a first pad area PA1 and a second pad area PA2 according to an embodiment of the present disclosure. Fig.15A and Fig. 15B is corresponding to Fig.14 sectional view of . Fig.15A is along Fig.14 A schematic cross-sectional view of the first pad area PA1 and the second pad area PA2 taken along the line DD', and Fig. 15B is along Fig.14 Schematic cross-sectional view of the first pad area PA1 and the second pad area PA2 taken along the line EE'. In the following description, the same / similar reference numerals are assigned to Figures 1 to 13 For the same / similar parts described in the description, redundant description is omitted and the differences are described.

[0202] Reference Figures 14 to 15B , the signal pad DP-PD according to the embodiment may include a conductive pattern CLa and at least one insulating pattern SP. In the case compared with the above embodiment, the signal pad DP-PD may not include a lower conductive pattern. The conductive pattern CLa may be connected to the distal end portion DL-E of the data line DL through at least one contact hole OP-C.

[0203] According to an embodiment, the conductive pattern CLa may cover a portion of the insulating pattern SP. The conductive pattern CLa may include at least one first portion P1a and a second portion P2a adjacent to the first portion P1a. The at least one first portion P1a may be spaced apart from the contact hole OP-C. When viewed in a plan view, the second portion P2a may surround the first portion P1a.

[0204] Fig.14 It is shown that the signal pad DP-PD includes two insulation patterns SP arranged in the first direction DR1, and the conductive pattern CLa includes two first portions P1a respectively overlapping the two insulation patterns SP.

[0205] Each of the plurality of first portions P1a of the conductive pattern CLa may be provided as Figure 8B The mesh pattern of each of the plurality of first portions P1a may include a plurality of first mesh lines MSL1 extending in the first direction DR1 and arranged in the second direction DR2 (see Figure 8B ) and extending in the second direction DR2 and intersecting with a plurality of first grid lines MSL1 (see Figure 8B ) and are arranged in the first direction DR1 (see Figure 8B ).

[0206] According to an embodiment, the conductive pattern CLa may be formed by contacting a conductive layer including a connection electrode (eg, Figure 5 The conductive pattern CLa may be formed by the same process as that of one of the third conductive layers CL30 to the fifth conductive layer CL50 in the conductive layer. Therefore, the conductive pattern CLa may include the same material as that of the one of the conductive layers including the connection electrode.

[0207] According to an embodiment, the conductive pattern CLa may be Figure 5 The fifth conductive layer CL50 in the embodiment is formed by the same process. However, the present disclosure is not limited thereto. The distal portion DL-E and the conductive pattern CLa may be Figure 5 The combination of different layers among the first conductive layer CL10 to the fifth conductive layer CL50 may be variously provided. In addition, the combination of the conductive layers formed by the same process as the distal end portion DL-E and the conductive pattern CLa may be variously provided according to the circuit element layer DP-CL (see Figure 5 )'s stacking structure can be selected in various ways.

[0208] When viewed in a cross-sectional view, the insulating pattern SP may be disposed between the pad insulating layer IL-P and the conductive pattern CLa. The insulating pattern SP may be disposed on the pad insulating layer IL-P and may be partially covered by the conductive pattern CLa.

[0209] According to an embodiment, a portion of the conductive pattern CLa covering the insulating pattern SP may further protrude from the conductive pattern CLa (eg, the remaining portion of the conductive pattern CLa) when compared with the remaining portion of the conductive pattern CLa. Fig. 15B shows a cross-sectional view of the signal pad DP-PD viewed in the first direction DR1, and Fig. 15B The first portion P1a of the conductive pattern CLa shown in FIG. 1 may be a plurality of first mesh lines MSL1. When viewed in a cross-sectional view, each of the plurality of first mesh lines MSL1 of the conductive pattern CLa may be provided in the form of a protrusion protruding from the insulating pattern SP. On a cross-section of the signal pad DP-PD viewed in the second direction DR2, the second mesh lines MSL2 of the conductive pattern CLa (see FIG. 1 ) may be provided in the form of a protrusion protruding from the insulating pattern SP. Figure 8B ) may be provided in the form of a plurality of protrusions protruding from the insulating pattern SP.

[0210] According to an embodiment, since the mesh pattern of the conductive pattern CLa is arranged on the insulating pattern SP in the signal pad DP-PD, the mesh pattern of the conductive pattern CLa may be provided in the form of a protrusion protruding from the insulating pattern SP. Therefore, during the bonding process, pressure may be applied to the conductive pattern CLa that is aligned with the first mesh line MSL1 (see FIG. Figure 8B ) and the second grid line MSL2 (see Figure 8B) corresponding to each of the protrusions. Therefore, in the case where the entire portion of the insulating pattern SP is covered, the degree of compression in the conductive pattern CLa covering the insulating pattern SP in a grid pattern may be increased. Therefore, the grid pattern of the conductive pattern CLa may have a relatively large degree of stretching. Even after the bonding process is completed, the grid pattern of the conductive pattern CLa maintains a stable electrical connection with the bump electrode. Therefore, the bonding resistance between the conductive pattern CLa and the bump electrode may be reduced, and a display device DD having improved bonding reliability may be provided (see Figure 1 ).

[0211] Fig.16 is a schematic plan view of a first pad area PA1 and a second pad area PA2 according to an embodiment of the present disclosure. Fig.17A and Fig. 17B is corresponding to Fig.16 sectional view of . Fig.17A is along Fig.16 A schematic cross-sectional view of the first pad area PA1 and the second pad area PA2 taken along the line FF', and Fig. 17B is along Fig.16 Schematic cross-sectional view of the first pad area PA1 and the second pad area PA2 taken along the line G-G'. In the following description, the same / similar reference numerals are assigned to the same Figures 1 to 13 For the same / similar parts described in the description, redundant description is omitted and the differences are described.

[0212] Reference Fig.16 According to an embodiment, the signal pad DP-PD may include a lower conductive pattern CL-Lb, a conductive pattern CLb, and at least one insulating pattern SP. The lower conductive pattern CL-Lb may be connected to the distal end portion DL-E of the data line DL through at least one contact hole OP-C. The conductive pattern CLb may contact the lower conductive pattern CL-Lb through at least one upper contact hole OP-Cb. Fig.16 , a signal pad DP-PD including two contact holes OP-C and an upper contact hole OP-Cb is shown.

[0213] The upper contact hole OP-Cb may overlap at least a portion of the distal portion DL-E. Fig.16 It is shown that the upper contact hole OP-Cb overlaps the entire portion of the distal end portion DL-E, but the present disclosure is not limited thereto. For example, the upper contact hole OP-Cb may be defined to overlap a portion of the distal end portion DL-E.

[0214] According to an embodiment, when viewed in a plan view, the contact hole OP-C may be arranged in the upper contact hole OP-Cb. However, the present disclosure is not limited thereto, and when viewed in a plan view, the contact hole OP-C and the upper contact hole OP-Cb may be arranged to be spaced apart from each other.

[0215] When viewed in a plan view, the insulating pattern SP may be spaced apart from the contact hole OP-C and may be disposed in the upper contact hole OP-Cb.

[0216] Fig.16 The conductive pattern CLb is shown to have an area larger than that of the lower conductive pattern CL-Lb when viewed in a plan view, but the present disclosure is not limited thereto. The conductive pattern CLb and the lower conductive pattern CL-Lb may have the same area, and edges of the conductive pattern CLb and the lower conductive pattern CL-Lb may be aligned with each other.

[0217] According to an embodiment, the conductive pattern CLb may cover a portion of the insulating pattern SP. When viewed in a plan view, the conductive pattern CLb may include at least one first portion P1b and a second portion P2b surrounding the at least one first portion P1b. Fig.16 It is shown that the conductive pattern CLb includes two first portions P1b respectively overlapping the two insulating patterns SP.

[0218] Each of the plurality of first portions P1b of the conductive pattern CLb may be provided as Figure 8B The mesh pattern of each of the plurality of first portions P1b may include a plurality of first mesh lines MSL1 extending in the first direction DR1 and arranged in the second direction DR2 (see Figure 8B ) and extending in the second direction DR2 and intersecting with a plurality of first grid lines MSL1 (see Figure 8B ) and are arranged in the first direction DR1 (see Figure 8B ).

[0219] Reference Fig.17A and Fig. 17B According to an embodiment, the lower conductive pattern CL-Lb may include a first layer CL-L1 and a second layer CL-L2. Since the insulating layer is not disposed between the first layer CL-L1 and the second layer CL-L2, the first layer CL-L1 and the second layer CL-L2 may be defined in the form of a single conductive pattern. The first layer CL-L1 and the second layer CL-L2 may not be connected to each other through a contact hole.

[0220] According to an embodiment, the first layer CL-L1 may be connected to a conductive layer including a connection electrode (eg, Figure 5 The second layer CL-L2 may be formed by the same process as a conductive layer including a third conductive layer CL30 to a fifth conductive layer CL50 (for example, Figure 5The first layer CL-L1 may include the same material as the conductive layer in the conductive layer including the connection electrode, and the second layer CL-L2 may include the same material as the other layers in the conductive layer including the connection electrode.

[0221] According to an embodiment, the first layer CL-L1 can be connected with Figure 5 The distal end portion DL-E, the first layer CL-L1 and the second layer CL-L2 may be formed by the same process as the fourth conductive layer CL40, and the second layer CL-L2 may be formed by the same process as the fifth conductive layer CL50. However, the present disclosure is not limited thereto. Figure 5 The combination of different layers among the first conductive layer CL10 to the fifth conductive layer CL50 may be variously provided. In addition, the combination of the conductive layers formed by the same process as the distal portion DL-E and the first layer CL-L1 and the second layer CL-L2 may be variously provided according to the circuit element layer DP-CL (see Figure 5 )'s stacking structure can be selected in various ways.

[0222] According to an embodiment, any one of the first layer CL-L1 and the second layer CL-L2 may be omitted. According to another embodiment of the present disclosure, the lower conductive pattern CL-Lb may be omitted.

[0223] although Fig.17A and Fig. 17B It is shown that the edge of the second layer CL-L2 is arranged outside the edge of the first layer CL-L1 and covers the edge of the first layer CL-L1, but the present disclosure is not limited thereto. The edge of the second layer CL-L2 may be substantially aligned with the edge of the first layer CL-L1.

[0224] According to an embodiment, the insulating layer between the lower conductive pattern CL-Lb and the conductive pattern CLb may be defined as an upper pad insulating layer IL-S. The upper contact hole OP-Cb may be defined in the upper pad insulating layer IL-S. According to an embodiment, the first sensing insulating layer IS-IL1 and the second sensing insulating layer IS-IL2 may be defined as an upper pad insulating layer IL-S. The first sensing insulating layer IS-IL1 and the second sensing insulating layer IS-IL2 may be connected to Figure 6B The sensing area IS-DA and the non-sensing area IS-NDA shown in FIG. overlap. Therefore, the first sensing insulating layer IS-IL1 and the second sensing insulating layer IS-IL2 may overlap with the first pad area PA1 and the second pad area PA2. According to an embodiment of the present disclosure, any one of the first sensing insulating layer IS-IL1 and the second sensing insulating layer IS-IL2 may be omitted.

[0225] According to an embodiment, the conductive pattern CLb may be Fig. 6A The second conductive pattern layer IS-CL2 and Figure 6C The sensing pattern SP2 is formed by the same process.

[0226] When viewed in a cross-sectional view, the insulating pattern SP may be between the lower conductive pattern CL-Lb and the conductive pattern CLb. The insulating pattern SP is disposed on the lower conductive pattern CL-Lb and may be partially covered by the conductive pattern CLb.

[0227] According to an embodiment, the insulating pattern SP may be formed by contacting the circuit element layer DP-CL (see Figure 5 ) or display element layer DP-OLED (see Figure 5 ) is formed by the same process as the organic layer on the fifth insulating layer 50. Therefore, an additional process for forming the insulating pattern SP may not be required. For example, the insulating pattern SP may be formed by the fifth insulating layer 50 (see Figure 5 ), the sixth insulating layer 60 (see Figure 5 ) and pixel definition film PDL (see Figure 5 However, the present disclosure is not limited thereto, and the combination of the conductive layers formed by the same process as the first layer CL-L1 and the second layer CL-L2 of the lower conductive pattern CL-Lb may be formed according to the circuit element layer DP-CL (see Figure 5 Therefore, even the insulating layer formed by the same process as the insulating pattern SP can be variously selected.

[0228] The conductive pattern CLb and the lower conductive pattern CL-Lb may be distinguished by the upper pad insulating layer IL-S (eg, the first sensing insulating layer IS-IL1 and the second sensing insulating layer IS-IL2). The upper pad insulating layer IL-S may be between the conductive pattern CLb and the lower conductive pattern CL-Lb and the insulating pattern SP.

[0229] A portion of the conductive pattern CLb covering the insulating pattern SP may protrude from the lower conductive pattern CL-Lb in comparison with another portion of the conductive pattern CLb. Fig. 17B shows a cross-sectional view of the signal pad DP-PD viewed in the first direction DR1, and Fig. 17B The first portion P1b of the conductive pattern CLb shown in FIG. 1 may be a plurality of first mesh lines MSL1. When viewed in a cross-sectional view, each of the plurality of first mesh lines MSL1 of the conductive pattern CLb may be provided in the form of a protrusion protruding from the insulating pattern SP. On a cross-section of the signal pad DP-PD viewed in the second direction DR2, the plurality of second mesh lines MSL2 of the conductive pattern CLb (see Figure 8B ) may also be provided in the form of a plurality of protrusions protruding from the insulating pattern SP.

[0230] According to an embodiment, by arranging the mesh pattern of the conductive pattern CLb on the insulating pattern SP in the signal pad DP-PD, the mesh pattern of the conductive pattern CLb may be provided in the form of a protrusion protruding from the insulating pattern SP. Therefore, during the bonding process, pressure may be applied to the conductive pattern CLb that is aligned with the first mesh line MSL1 (see FIG. Figure 8B ) and the second grid line MSL2 (see Figure 8B ) corresponding to each of the protrusions. Therefore, in the case where the entire portion of the insulating pattern SP is covered, the degree of compression in the conductive pattern CLb covering the insulating pattern SP in a grid pattern can be increased. Therefore, the grid pattern of the conductive pattern CLb can have a relatively large degree of stretching. Even after the bonding process is completed, the grid pattern of the conductive pattern CLb maintains close contact with the bump electrode, thereby maintaining a stable electrical connection. Therefore, the bonding resistance between the conductive pattern CLb and the bump electrode can be reduced, and a display device DD with improved bonding reliability can be provided (see Figure 1 ).

[0231] Hereinafter, a method for manufacturing a display device according to an embodiment will be described with reference to the accompanying drawings. In the following description of the method for manufacturing a display device according to an embodiment, repeated description of the display device according to the embodiment will be omitted to avoid redundancy.

[0232] 18A to 18E are schematic cross-sectional views illustrating some of the steps in a method for manufacturing a display device according to an embodiment of the present disclosure.

[0233] According to an embodiment of the present disclosure, a method for manufacturing a display device includes the following steps: providing a preliminary signal pattern including an insulating pattern; depositing a preliminary conductive pattern on the preliminary signal pattern; and patterning the preliminary conductive pattern to form a conductive pattern that at least partially includes a grid pattern, and arranging at least a portion of the grid pattern on the insulating pattern.

[0234] Reference Fig.18A , the method for manufacturing a display device according to an embodiment of the present disclosure may include providing a preliminary signal pattern DP-PDI.

[0235] The preliminary signal pattern DP-PDI may include a lower conductive pattern CL-L and an insulating pattern SP. The insulating pattern SP may be arranged and provided on the lower conductive pattern CL-L. According to an embodiment, the preliminary signal pattern DP-PDI may include only the insulating pattern SP. In this case, the insulating pattern SP may be arranged and provided on the pad insulating layer IL-P. According to another embodiment, an upper pad insulating layer IL-S (see Fig.17A and Fig. 17B ).

[0236] Reference Fig.18B , a method for manufacturing a display device according to an embodiment of the present disclosure may include forming a preliminary conductive pattern CL-I on the preliminary signal pattern DP-PDI.

[0237] The preliminary conductive pattern CL-I may be formed by a deposition process. The deposition process for the preliminary conductive pattern CL-I may be performed as a process of depositing a conductive material. For example, the deposition process for the preliminary conductive pattern CL-I may be performed by a chemical vapor deposition (CVD) scheme or a sputtering scheme.

[0238] According to embodiments, the preliminary conductive pattern CL-I may be deposited to have a substantially flat top surface.

[0239] Reference Fig.18C , Fig.18D and Fig. 9B According to an embodiment of the present disclosure, the method for manufacturing a display device may include the step of patterning the preliminary conductive pattern CL-I to form a conductive pattern CL. According to an embodiment, the step of patterning the preliminary conductive pattern CL-I may include forming a photoresist pattern PR on the preliminary conductive pattern CL-I (see Fig.18E ), the steps of etching a portion of the preliminary conductive pattern CL-I to form a conductive pattern CL and removing the photoresist pattern PR to form a signal pad DP-PD.

[0240] According to an embodiment, the step of forming the photoresist pattern PR may include the steps of forming a photoresist layer PRL on the preliminary conductive pattern CL-I, exposing the photoresist layer PRL, and developing the photoresist layer PRL to form the photoresist pattern PR.

[0241] First, refer to Fig.18C , a photoresist layer PRL may be formed by applying a photoresist material on the preliminary conductive pattern CL-I. Thereafter, a layer having a shape defined as the same as that for forming the conductive pattern CL (see Fig. 9B ) of the photoresist layer PRL. Thereafter, an exposure process of providing light on the mask MK may be performed. Through the exposure process, the light may pass through the plurality of opening portions OP-M and be irradiated to portions of the photoresist layer PRL corresponding to the plurality of opening portions OP-M, respectively.

[0242] According to an embodiment, the plurality of opening portions OP-M defined in the mask MK may include a first opening portion OP1-M and a second opening portion OP2-M. Although not shown, when viewed in a plan view, the first opening portion OP1-M may have a grid pattern shape, and the second opening portion OP2-M may be arranged outside the first opening portion OP1-M.

[0243] Afterwards, refer to Fig.18D and Fig.18E , a portion of the photoresist layer PRL overlapping the opening portion OP-M remains due to the developer provided by the development process, and the remaining portion of the photoresist layer PRL not irradiated with light may be removed due to overlapping with the mask MK, thereby forming a photoresist pattern PR.

[0244] According to an embodiment, the photoresist pattern PR may be formed of a first remaining portion P1-R of the photoresist layer PRL overlapping the first opening portion OP1-M and a second remaining portion P2-R of the photoresist layer PRL overlapping the second opening portion OP2-M. Although not shown, the first remaining portion P1-R may have a mesh pattern shape corresponding to the first opening portion OP1-M, and the second remaining portion P2-R may be arranged outside the first remaining portion P1-R.

[0245] Although the above description has been made about a positive photo process of forming a photoresist pattern PR corresponding to the opening portion OP-M of the mask MK from the photoresist layer PRL, the present disclosure is not limited thereto. For example, the photoresist pattern PR may be formed by a negative photo process of removing a portion of the mask MK corresponding to the opening portion OP-M.

[0246] Afterwards, refer to Fig.18E and Fig. 9B , the portion of the preliminary conductive pattern CL-I exposed from the photoresist pattern PR may be removed by an etching process to form the conductive pattern CL. The first portion P1 of the conductive pattern CL may be formed from the preliminary conductive pattern CL-I through the first remaining portion P1-R, and the second portion P2 of the conductive pattern CL may be formed from the preliminary conductive pattern CL-I through the second remaining portion P2-R. The photoresist pattern PR may remain on the conductive pattern CL. Thereafter, by a stripping process, the photoresist pattern PR remaining on the conductive pattern CL may be removed to form the signal pad DP-PD. By 18A to 18E The signal pad DP-PD formed by the manufacturing steps may have Fig. 9B The shape of the signal pad DP-PD is similar to that of the shape of the PD.

[0247] The thickness of the preliminary conductive pattern CL-I may be variously controlled. According to an embodiment of the present disclosure, the top surface of the portion of the preliminary conductive pattern CL-I in a non-overlapping state with the insulating pattern SP may be positioned lower than the insulating pattern SP. In other words, the portion of the preliminary conductive pattern CL-I in a non-overlapping state with the insulating pattern SP may have a thickness thinner than the thickness of the insulating pattern SP. According to an embodiment, the portion of the preliminary conductive pattern CL-I in a non-overlapping state with the insulating pattern SP may have a thickness of about 1 / 3 of the maximum thickness of the insulating pattern SP.

[0248] According to an embodiment of the present disclosure, a step of controlling the thickness of the preliminary conductive pattern CL-I before or after the etching process of the preliminary conductive pattern CL-I may be further included. According to another embodiment of the present disclosure, the thickness of the preliminary conductive pattern CL-I may be controlled during a deposition process for the preliminary conductive pattern CL-I, or the thickness of the preliminary conductive pattern CL-I may be controlled during an etching process for the preliminary conductive pattern CL-I.

[0249] According to the present disclosure, the insulating pattern in the signal pad of the display panel can make the conductive pattern of the signal pad protrude toward the electronic component. The display panel can be bonded to the electronic component without an anisotropic conductive film, and short-circuit failures due to conductive balls can be reduced. Since the bonding pressure can be reduced, physical damage to the display panel or electrical parts (e.g., electronic components) can be reduced during the bonding process.

[0250] According to the present disclosure, the signal pad may include a conductive pattern in a grid form covering a portion of the insulating pattern. When viewed in a cross-sectional view, the conductive pattern in a grid shape may be provided in the form of a protrusion protruding from the insulating pattern. Therefore, through the plurality of protrusions between the insulating pattern and the buffer electrode, the tensile strength may be further increased in the bonding process. Even after the bonding process is completed, close contact with the bump electrode may be maintained. Therefore, the signal pad may be stably electrically connected to the bump electrode. Therefore, a display device having improved bonding reliability may be provided.

[0251] According to the present disclosure, a display device including a signal pad having improved bonding reliability can be manufactured.

[0252] Although the embodiments of the present disclosure have been described for illustrative purposes, those skilled in the art will appreciate that various modifications and substitutions are possible without departing from the scope and spirit of the present disclosure. Therefore, the technical scope of the present disclosure is not limited to the detailed description of this specification.

[0253] While the present disclosure has been described with reference to the embodiments thereof, it will be apparent to one skilled in the art that various changes and modifications can be made thereto without departing from the spirit and scope of the present disclosure.

Claims

1. A display device, comprising: Display module, including: Pixels; a signal line electrically connected to the pixel; and a signal pad electrically connected to the signal line, Wherein, the signal pad comprises: an insulating pattern arranged on the signal line; and a conductive pattern electrically connected to the signal line, The conductive pattern comprises: a first portion comprising a grid pattern; and a second portion, the second portion surrounding the first portion, and At least a portion of the first portion is disposed on the insulation pattern.

2. The display device according to claim 1, wherein: The conductive pattern includes a conductive material, and The insulating pattern includes a polymer.

3. The display device according to claim 1, wherein: The grid pattern comprises: a plurality of first grid lines extending in a first direction and arranged in a second direction intersecting the first direction; and A plurality of second grid lines extend in the second direction and are arranged in the first direction while intersecting the plurality of first grid lines.

4. The display device according to claim 1, wherein: When viewed in a cross-sectional view, the insulating pattern has a semicircular shape.

5. The display device according to claim 1, wherein: The display module further includes a pad insulating layer between the signal line and the conductive pattern. The pad insulating layer has a contact hole defined in the pad insulating layer, spaced apart from the insulating pattern, and overlapping a portion of the signal line, The conductive pattern contacts the signal line through the contact hole, and The insulating pattern is directly disposed on the pad insulating layer.

6. The display device according to claim 5, wherein: The pixels include: Light emitting element; a transistor electrically connected to the light emitting element and including a semiconductor pattern and a gate overlapping the semiconductor pattern; an upper electrode disposed on the gate; and a plurality of conductive layers electrically connected to the transistor, arranged on the upper electrode and arranged in mutually different layers; A portion of the signal line disposed under the conductive pattern and the gate or the upper electrode include the same material, and The conductive pattern and at least one conductive layer of the plurality of conductive layers include a same material.

7. The display device according to claim 1, wherein: The display module further includes a pad insulating layer between the signal line and the conductive pattern. The pad insulating layer has a contact hole defined in the pad insulating layer, spaced apart from the insulating pattern, and overlapping a portion of the signal line, The signal pad further includes a lower conductive pattern disposed below the conductive pattern and contacting the signal line through the contact hole; The insulating pattern is between the lower conductive pattern and the conductive pattern, The pixels include: Light emitting element; a transistor electrically connected to the light emitting element and including a semiconductor pattern and a gate overlapping the semiconductor pattern; an upper electrode disposed on the gate; and a plurality of conductive layers electrically connected to the transistor, arranged on the upper electrode and arranged in mutually different layers, and A portion of the signal line disposed under the conductive pattern and the gate electrode or the upper electrode include the same material.

8. The display device according to claim 7, wherein: The lower conductive pattern and at least one of the plurality of conductive layers include the same material, and The conductive pattern and other conductive layers of the plurality of conductive layers disposed on the at least one conductive layer include the same material.

9. The display device according to claim 7, wherein: The display module further includes: a thin film encapsulation layer, wherein the thin film encapsulation layer is arranged on the pixel; a sensing electrode, wherein the sensing electrode is arranged on the thin film encapsulation layer, The lower conductive pattern and at least one conductive layer of the plurality of conductive layers include the same material, and The conductive pattern and the sensing electrode include the same material.

10. The display device according to claim 9, wherein: The display module further includes a sensor insulating layer between the lower conductive pattern and the conductive pattern and in contact with the sensing electrode, and The conductive pattern contacts the lower conductive pattern through an upper contact hole defined in the sensor insulating layer.

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