Phase change materials, phase change memory chips, storage devices and electronic devices

Abstract

This disclosure discloses a phase change material, a phase change memory chip, a memory device, and an electronic device, belonging to the field of semiconductor memory technology. The phase change material includes a Ge-Sb-Te phase change substrate and a first dopant element and a second dopant element doped into the Ge-Sb-Te phase change substrate. The first dopant element includes Hf, with an atomic percentage of 1.5%-6.5%; the second dopant element includes at least one of N, C, In, and Ga, with an atomic percentage of 1.0%-5%. This phase change material exhibits high adhesion while enabling the phase change device to possess properties such as a large read window and long lifetime.

Description

[0001] This application is a divisional application. The original application has the application number 2024103166182 and the original application date is March 19, 2024. The entire contents of the original application are incorporated herein by reference. Technical Field

[0002] This disclosure relates to the field of semiconductor memory technology, and in particular to phase change materials, phase change memory chips, memory devices, and electronic devices. Background Technology

[0003] Phase change memory (PCM) has advantages such as low latency and long fatigue life. It uses phase change materials as storage media. Phase change materials exhibit low resistivity in crystalline state and high resistivity in amorphous state. PCM realizes data storage and erasure based on the resistance difference between crystalline and amorphous states of phase change materials.

[0004] In related technologies, phase change memory includes multiple phase change memory cells. Each phase change memory cell includes a phase change material layer and barrier layers located on both sides of the phase change material layer. This sandwich structure composed of the phase change material layer and the barrier layers is subjected to significant stress during processes such as annealing and etching. This may cause interface peeling between the phase change material layer and other functional layers such as the barrier layers. This not only causes the phase change memory cell to malfunction, but also the material particles that fall off due to peeling can have adverse effects on the equipment.

[0005] It is evident that it is necessary to improve the interfacial adhesion between the phase change material layer and other functional layers in phase change memory.

[0006] Public content

[0007] On one hand, a phase change material is provided, the phase change material comprising a Ge-Sb-Te phase change substrate, a first dopant element and a second dopant element doped in the Ge-Sb-Te phase change substrate; the first dopant element comprises Hf element, and the first dopant element accounts for 1.5%-6.5% of the atomic percentage of the phase change material; the second dopant element comprises at least one selected from N element, C element, In element and Ga element, and the second dopant element accounts for 1.0%-5% of the atomic percentage of the phase change material.

[0008] The phase change material provided by the embodiments of the present disclosure can enhance the adhesion of the phase change material layer by further doping at least one of N element, C element, In element, and Ga element into the Ge-Sb-Te phase change base material doped with Hf element, achieve tight bonding between the phase change material layer and other adjacent functional layers, reduce the probability of interface peeling, increase the product yield of the phase change memory chip, and avoid pollution and interference to the production line and production equipment. In particular, by making the doping amount of Hf element be 1.5%-6.5%, and the doping amount of at least one of N element, C element, In element, and Ga element be 1.0%-5.0%, while achieving the improvement of the adhesion of the phase change material layer, it is also beneficial to make the phase change device have a large read window and high lifetime.

[0009] In some possible implementation manners, the phase change material further includes: a third doping element, and the third doping element includes at least one of O element, Si element, B element, Sn element, Bi element, Cd element, Pb element, Zr element, Zn element, Cr element, Al element, Sc element, Y element, Ta element, Ti element, Er element, Lu element, Ho element, Tm element, Dy element, Tb element, Ca element, Nd element, Pr element, Yb element, Ca element, Ce element. By further introducing a specific content of the third doping element into the phase change material, the purpose of optimizing the comprehensive performance of the phase change memory device can also be achieved.

[0010] In some possible implementation manners, the chemical general formula of the Ge-Sb-Te phase change base material is as follows: (GeTe 1-a ) x (Sb2Te 3-b ) 1-x , where x is the atomic percentage and 0 < x < 1, a and b are parameters related to the atomic number ratio, 0 < a ≤ 1, 0 < b ≤ 3, and a = 1 and b = 3 do not exist simultaneously; or, (GeTe 1-c ) x (Sb y Te 1-d ) 1-x , where x is the atomic percentage and 0 < x < 1, y, c and d are parameters related to the atomic number ratio, y ≥ 2, 0 < c ≤ 1, 0 < d ≤ 1, and c = 1 and d = 1 do not exist simultaneously.

[0011] By making the chemical general formula of the Ge-Sb-Te phase change base material as described above, the purpose is to ensure that the adhesion of the phase change material layer is stronger than that of the phase change material layer corresponding to the Ge-Sb-Te phase change base material.

[0012] On the other hand, a phase change material is provided. The phase change material includes a Ge-Sb-Te phase change base material, a first doping element and a second doping element doped in the Ge-Sb-Te phase change base material; the first doping element includes Hf element, and the atomic percentage of the first doping element in the phase change material is 1.5%-7%; the second doping element includes at least one of N element, C element, In element, and Ga element, and the atomic percentage of the second doping element in the phase change material is 1.0%-7%; the sum of the atomic percentages of the first doping element and the second doping element is greater than 4% and less than 10%.

[0013] For the phase change materials provided in the embodiments of the present disclosure, by further doping at least one of N element, C element, In element, and Ga element into the Ge-Sb-Te phase change base material doped with Hf element, the adhesion of the phase change material layer can be enhanced, the tight combination between the phase change material layer and other adjacent functional layers can be achieved, the interface peeling probability can be reduced, the product yield of the phase change memory chip can be increased, and the pollution and interference to the production line and production equipment can be avoided. In particular, by making the doping amount of Hf element be 1.5%-7%, and making the doping amount of at least one of N element, C element, In element, and Ga element be 1.0%-7%, and the sum of the atomic percentages of the two doping elements is greater than 4% and less than 10%, while improving the adhesion of the phase change material layer, it is also beneficial to make the phase change device have a large read window, high life and cycle stability.

[0014] In some possible implementation manners, the phase change material further includes: a third doping element, and the third doping element includes at least one of O element, Si element, B element, Sn element, Bi element, Cd element, Pb element, Zr element, Zn element, Cr element, Al element, Sc element, Y element, Ta element, Ti element, Er element, Lu element, Ho element, Tm element, Dy element, Tb element, Ca element, Nd element, Pr element, Yb element, Ca element, Ce element. By further introducing a specific content of the third doping element into the phase change material, the purpose of optimizing the comprehensive performance of the phase change memory device can also be achieved.

[0015] In some possible implementation manners, the chemical general formula of the Ge-Sb-Te phase change base material is as follows: (GeTe 1-a ) x (Sb2Te 3-b ) 1-x , where x is the atomic percentage and 0 < x < 1, a and b are parameters related to the atomic number ratio, 0 < a ≤ 1, 0 < b ≤ 3, and a = 1 and b = 3 do not exist simultaneously; or, (GeTe 1-c ) x (Sby Te 1-d ) 1-x , where x is the atomic percentage and 0 < x < 1, y, c, and d are parameters related to the ratio of the number of atoms, y ≥ 2, 0 < c ≤ 1, 0 < d ≤ 1, and c = 1 and d = 1 do not exist simultaneously.

[0016] By making the chemical general formula of the Ge-Sb-Te phase change substrate as described above, the purpose is to ensure that the adhesion force of the phase change material layer is stronger than that of the phase change material layer corresponding to the Ge-Sb-Te phase change substrate.

[0017] Furthermore, the chemical general formula of the Ge-Sb-Te phase change substrate is as follows: (GeTe 1-a ) x (Sb2Te 3-b ) 1-x , and 0.2 < x ≤ 0.4, or, (GeTe 1-c ) x (Sb y Te 1-d ) 1-x , and 0.2 < x ≤ 0.4.

[0018] The embodiments of the present disclosure further limit the chemical general formula of the Ge-Sb-Te phase change substrate as shown above, which is beneficial to making the phase change device have both low latency and high lifespan, and ensuring that the phase change material layer has high adhesion.

[0019] On the other hand, a phase change memory chip is provided. The phase change memory chip includes: a plurality of phase change memory cells, and the phase change memory cells include a phase change material layer, and the phase change material layer is prepared from the phase change material described in any one of the above.

[0020] For the phase change memory chip provided by the embodiments of the present disclosure, since its phase change material layer is prepared from the phase change material provided by the embodiments of the present disclosure, the phase change memory chip has all the advantages of the phase change material provided by the embodiments of the present disclosure.

[0021] In some possible implementation manners, the phase change memory cell further includes an adhesion layer, and the adhesion layer is stacked on at least one surface of the phase change material layer, and the adhesion layer is used to increase the adhesion force between the phase change material layer and an adjacent functional layer.

[0022] For the phase change memory chip provided by the embodiments of the present disclosure, not only the phase change material itself is improved, but also the structure of the phase change memory chip is improved by adding an adhesion layer to further enhance the adhesion force between the phase change material layer and an adjacent functional layer, significantly reduce the probability of interface peeling, thereby increasing the product yield of the phase change memory cell, and also avoiding pollution and interference to the production line.

[0023] In some possible implementations, the adhesive layer material used in the adhesive layer includes at least one of the nitride of the target element and the carbide of the target element;

[0024] The target element is selected from at least one of the elements W, Ti, Ge, Ta, Hf, In, Ga, Al, Cu, Co, and Mo.

[0025] In some possible implementations, the adhesive layer material used includes a Ge-Sb-Te phase change material doped with a fourth doping element, and the adhesive layer material is different from the phase change material.

[0026] The fourth doping element is selected from at least one of Hf, N, C, In, and Ga, and the fourth doping element accounts for 0.01%-20% of the atomic percentage of the adhesive layer material.

[0027] In some possible implementations, the phase change storage unit further includes a barrier layer, wherein the adhesion layer is located between the phase change material layer and the barrier layer to increase the adhesion between the phase change material layer and the barrier layer.

[0028] In some possible implementations, the barrier layer material used includes at least one of the following elements: W, Ti, Ge, Ta, Hf, In, Ga, Al, Cu, Co, and Mo, as well as nitrides and carbides.

[0029] In some possible implementations, the phase change storage unit further includes an electrode layer, and the adhesion layer is located between the phase change material layer and the electrode layer to increase the adhesion between the phase change material layer and the electrode layer.

[0030] In some possible implementations, the phase-change memory chip further includes: a plurality of gate transistor units, which are arranged in series with the phase-change memory unit.

[0031] In some possible implementations, the gate unit includes a gate layer, and the gate layer is made of at least one of S-based gate materials, Se-based gate materials, and Te-based gate materials.

[0032] In some possible implementations, the gate material further includes a fifth doping element, which is selected from at least one of the following elements: B, Al, Ga, In, C, Si, Ge, Sn, N, P, As, Sb, Bi, O, Au, Hf, Pd, Cu, Co, Ag, Pt, Sc, Ti, and Ta.

[0033] In another aspect, embodiments of this disclosure provide a storage device, the storage device including a controller and at least one phase-change memory chip as described above, the controller being used to store data to the phase-change memory chip.

[0034] This storage device (also known as a memory) can be configured to store various types of data, such as contact data, phone book data, messages, pictures, videos, and instruction data.

[0035] In another aspect, embodiments of this disclosure provide an electronic device, the electronic device including a processor and the aforementioned storage device, the processor being used to store data generated by the electronic device to the storage device.

[0036] This electronic device includes, but is not limited to: computers, mobile phones, music playback devices, digital broadcasting devices, messaging devices, game control devices, medical devices, fitness equipment, personal digital assistants, etc. Attached Figure Description

[0037] Figure 1 This is a schematic diagram of the delamination process between the phase change material layer and the barrier layer in related technologies.

[0038] Figure 2 The mean square displacement diagram of Hf element in Ge-Sb-Te phase change substrate;

[0039] Figure 3 The mean square displacement diagram of In element in Ge-Sb-Te phase change substrate;

[0040] Figure 4 The mean square displacement diagram of Ga element in Ge-Sb-Te phase change substrate;

[0041] Figure 5 A schematic diagram of the structure of an exemplary phase-change memory cell provided in an embodiment of this disclosure;

[0042] Figure 6 This is a schematic diagram of the structure of another exemplary phase-change memory cell provided in this embodiment of the disclosure;

[0043] Figure 7This is a schematic diagram of the structure of another exemplary phase-change memory cell provided in the embodiments of this disclosure;

[0044] Figure 8 This is a schematic diagram of the structure of another exemplary phase-change memory cell provided in the embodiments of this disclosure;

[0045] Figure 9 A schematic diagram of the structure of an exemplary phase-change memory chip provided in this disclosure embodiment;

[0046] Figure 10 This is a schematic diagram of the structure of another exemplary phase-change memory chip provided in this disclosure embodiment;

[0047] Figure 11 This is a schematic diagram of the structure of another exemplary phase-change memory chip provided in the embodiments of this disclosure;

[0048] Figure 12 This is a schematic diagram of the structure of another exemplary phase-change memory chip provided in this disclosure embodiment;

[0049] Figure 13 An array diagram of an exemplary phase-change memory chip provided in an embodiment of this disclosure;

[0050] Figure 14 This is a schematic diagram of the first fabrication step of the phase change memory chip provided in Example 1;

[0051] Figure 15 This is a schematic diagram of the second fabrication step of the phase-change memory chip provided in Example 1;

[0052] Figure 16 A schematic diagram of the third fabrication step of the phase-change memory chip provided in Example 1;

[0053] Figure 17 A schematic diagram of the fourth fabrication step of the phase-change memory chip provided in Example 1;

[0054] Figure 18 A schematic diagram of the fifth fabrication step of the phase-change memory chip provided in Example 1;

[0055] Figure 19 A schematic diagram of the sixth fabrication step of the phase-change memory chip provided in Example 1;

[0056] Figure 20 A schematic diagram of the seventh fabrication step of the phase-change memory chip provided in Example 1;

[0057] Figure 21 A schematic diagram of the eighth fabrication step of the phase-change memory chip provided in Example 1;

[0058] Figure 22A schematic diagram of the ninth fabrication step of the phase-change memory chip provided in Example 1;

[0059] Figure 23 A schematic diagram of the tenth fabrication step of the phase-change memory chip provided in Example 1;

[0060] Figure 24 This is a schematic diagram showing the relationship between the lifetime and SET state resistance of a phase-change memory chip provided in an embodiment of this disclosure.

[0061] The reference numerals in the attached figures represent:

[0062] 001, Storage cell; 002, Word line; 003, Bit line; 004, Substrate; 005, Mask layer; 100, Phase change material layer; 200, Adhesion layer; 300, Barrier layer; 400, Insulating layer; 401, First insulating layer; 402, Second insulating layer; 403, Third insulating layer; 404, Fourth insulating layer; 501, Top electrode; 502, Bottom electrode; 503, Intermediate electrode; 600, Gating layer; 701, First trench; 702, Second trench; 703, Third trench. Detailed Implementation

[0063] In the description of the embodiments of this disclosure, the terms "vertical direction," "horizontal direction," "top," "bottom," "upper," and "lower," etc., indicate the orientation or positional relationship based on the orientation or positional relationship shown in the accompanying drawings. They are used only for the convenience of describing the embodiments of this disclosure and for simplifying the description, and are not intended to indicate or imply that the device or element referred to must have a specific orientation, or be constructed and operated in a specific orientation. Therefore, they should not be construed as limitations on the embodiments of this disclosure. When the product is placed in different postures, the orientation may change; for example, "top" and "bottom" may be interchanged.

[0064] Phase change memory (PCM), also known as phase change memory chip, is a type of solid-state semiconductor non-volatile memory that uses phase change material as the storage medium. The phase change material can undergo reversible changes between crystalline and amorphous states. By utilizing the difference between the high and low resistivity of the phase change material in its amorphous and crystalline states, the PCM can store data "0" and "1".

[0065] The operation of a phase change memory (PCM) includes two processes: an erase (SET) operation and a write (RESET) operation. The SET process involves applying a wide, weak electrical pulse to heat the PCM, raising its temperature to between its crystallization and melting temperatures. The PCM crystallizes into an ordered state, forming a crystalline state with low resistivity, thus storing the data "0". The RESET process involves applying a narrow, strong electrical pulse to heat the PCM, raising its temperature above its melting temperature. The PCM melts into a disordered state, followed by a rapid cooling quenching process, transforming the molten PCM directly into an amorphous state with higher resistivity, thus storing the data "1".

[0066] In related technologies, phase-change memory includes multiple phase-change memory cells, as shown in the appendix. Figure 1 As shown, the phase change memory cell includes a phase change material layer 100 and barrier layers 300 located on both sides of the phase change material layer 100. This sandwich structure composed of the phase change material layer 100 and the barrier layers 300 undergoes numerous processes during the fabrication of the phase change memory, including annealing, patterning, etching, and protective layer covering. This subjects it to significant stress, which may lead to delamination between the interface of the phase change material layer 100 and other functional layers such as the barrier layers 300 (see...). Figure 1 This not only renders the phase change memory cells in the peeled-off areas unusable (e.g., the interface between the phase change material layer and the barrier layer peels off, preventing them from bonding), but also causes adverse effects on production equipment due to the detached material particles (e.g., contaminating the production line, interfering with normal equipment operation). Therefore, it is necessary to improve the interfacial adhesion between the phase change material layer and other functional layers.

[0067] The first embodiment of this disclosure provides a phase change material comprising a Ge-Sb-Te phase change substrate and a first dopant element and a second dopant element doped into the Ge-Sb-Te phase change substrate. The first dopant element comprises Hf, and the first dopant element accounts for 1.5%-6.5% of the atomic percentage of the phase change material; the second dopant element comprises at least one selected from N, C, In, and Ga, and the second dopant element accounts for 1.0%-5.0% of the atomic percentage of the phase change material.

[0068] Examples of the atomic percentage of the first dopant element Hf in the phase change material include, but are not limited to: 1.5%, 1.6%, 1.7%, 1.8%, 1.9%, 2%, 2.1%, 2.2%, 2.3%, 2.4%, 2.5%, 2.6%, 2.7%, 2.8%, 2.9%, 3%, 3.1%, 3.2%, 3.3%, 3.4%, 3.5%, 3.6%, 3.7%, 3.8%, 3.9%, 4%, 4.1%, 4.2%, 4.3%, 4.4%, 4.5%, 4.6%, 4.7%, etc.

[0069] 4.8%, 4.9%, 5%, 5.1%, 5.2%, 5.3%, 5.4%, 5.5%, 5.6%, 5.7%, 5.8%, 5.9%, 6%, 6.1%, 6.2%, 6.3%, 6.4%, 6.5%, etc.

[0070] Examples of the atomic percentage of the second dopant element in the phase change material include, but are not limited to: 1%, 1.1%, 1.2%, 1.3%, 1.4%, 1.5%, 1.6%, 1.7%, 1.8%, 1.9%, 2%, 2.1%, 2.2%, 2.3%, 2.4%, 2.5%, 2.6%, 2.7%, etc.

[0071] 2.8%, 2.9%, 3%, 3.1%, 3.2%, 3.3%, 3.4%, 3.5%, 3.6%, 3.7%, 3.8%, 3.9%, 4%, 4.1%, 4.2%, 4.3%, 4.4%, 4.5%, 4.6%, 4.7%, 4.8%, 4.9%, 5%, etc.

[0072] The second doping element can be one of N, C, In, or Ga. For example, the second doping element can be N, C, In, or Ga. Alternatively, the second doping element can be a combination of any two or any three of N, C, In, or Ga elements, or include all four elements simultaneously.

[0073] The phase change material provided in this disclosure improves the adhesion between the phase change material layer and other functional layers by doping the Ge-Sb-Te phase change substrate with Hf element and at least one of N element, C element, In element and Ga element. The principle of improving adhesion is described below.

[0074] (1) When the second doping element is N or C, N or C can bond with Hf, thereby introducing HfN or HfC compounds into the phase change material. The introduced HfN or HfC compounds do not match the lattice constant of the Ge-Sb-Te phase change substrate (e.g., the lattice constant of HfN is 0.452 nm and the lattice constant of HfC is 0.463 nm). They do not match the lattice constant of the Ge-Sb-Te phase change substrate (e.g., the lattice constant of Ge1Sb4Te6 is 0.612 nm), thereby introducing additional grain boundaries, reducing the grain size of the phase change material, reducing the roughness of the phase change material, increasing the contact area and bonding force between the phase change material layer and other functional layers, and thus increasing the adhesion of the phase change material layer.

[0075] Further research revealed that when the atomic percentage of N or C elements is between 1.0% and 5.0%, a large read window can be further ensured for the phase change device. The relevant principle is as follows: For the operation of a 1S1R type phase change memory chip, the threshold voltage for opening the selector unit + crystalline phase change memory unit is VtS, and the threshold voltage for opening the selector unit + amorphous phase change memory unit is VtR. The read window is VtR - VtS. It can be seen that the size of the read window is proportional to the difference between the high resistance and low resistance of the phase change material layer.

[0076] On the one hand, HfN and HfC compounds can increase the high resistivity of phase change materials, which is beneficial for increasing the read window of phase change devices. On the other hand, if Hf is doped alone into the Ge-Sb-Te phase change substrate, it will easily be oxidized to form HfOx during the fabrication process due to contact with O or other oxidizing substances. The resistivity of HfOx is greater than that of the phase change material, which will increase the low resistivity of the phase change material to some extent, thus reducing the read window of the phase change device. However, HfN and HfC compounds have melting points of 3310℃ and 3900℃, respectively, and have high chemical stability, making them less likely to react with O and other elements, reducing the oxidation probability of Hf and thus ensuring a large read window for the phase change device.

[0077] However, the effect of N or C elements on the read window of a phase change device is related to their doping amount in the phase change material. The embodiments of this disclosure have confirmed through relevant experiments that when the atomic percentage of Hf element is greater than 6.5% (not within the limited range of 1.5% to 6.5%), and the atomic percentage of N or C element is greater than 5.0% (not within the limited range of 1% to 5%), the read window of the phase change device will deteriorate.

[0078] For example, the "related experiments" mentioned above are shown below:

[0079] This disclosure provides a type of phase change material in which the Ge-Sb-Te phase change substrate is doped with Hf and N elements. The atomic percentage ratio of each element in the general chemical formula of the Ge-Sb-Te phase change substrate satisfies Ge:Sb:Te = 1:4:6 (which can be abbreviated as Ge1Sb4Te6, GeSbTe146, or GST146). While keeping other parameters constant, the doping amounts of Hf and N elements were varied to test the low resistance of the phase change material layer in the crystalline state and the high resistance in the amorphous state. The relevant test parameters and results are shown in Table 1.

[0080] Table 1

[0081]

[0082] As can be seen from phase change materials 1 and 3 in Table 1, by further doping N elements into the Ge-Sb-Te phase change substrate doped with Hf elements, the high resistance of the phase change material layer can be improved, which is beneficial to increasing the read window size.

[0083] As shown in Table 1, for phase change material 2, when the Hf doping concentration is 6.5% and the N doping concentration is 5%, its crystallization temperature is 35°C higher than that of phase change material 1 (undoped N) in Table 1, its low resistance is more than 100 times higher than that of phase change material 4 (Hf 2% + N 2%) in Table 1, and more than 5 times higher than that of phase change material 3 (Hf 4% + N 4%) in Table 1. This indicates a certain degree of read window degradation. It is evident that when the atomic percentage of Hf is greater than 6.5% and the atomic percentage of N or C is greater than 5.0%, the crystallization temperature will further increase. Under certain downstream device processing heat treatment conditions, this will lead to an increase in the low resistance of the phase change material layer, thereby causing a decrease in the read window of the phase change device. As can be seen, by making the atomic percentage of Hf element 1.5% to 6.5% and the atomic percentage of N element or C element greater than 1% to 5%, the present disclosure embodiment is of great significance for ensuring that the phase change device has a large read window.

[0084] In addition, as mentioned above, the HfN and HfC compounds have melting points of 3310℃ and 3900℃ respectively, exhibiting high chemical stability.

[0085] It is evident that the high melting points of HfN and HfC compounds enable them to remain stable during the melting process (approximately 600°C) of the phase change material RESET.

[0086] Furthermore, the stable HfN and HfC compound clusters hinder elemental segregation and phase separation in the GeSbTe phase change substrate, which is beneficial for the phase change device to have a long lifespan.

[0087] (2) When the second dopant element is In or Ga, In and Ga readily form metal-metal bonds with metal elements such as Hf, thereby enhancing the bonding force between the phase change material layer and other functional layers. This is because In and Ga have low melting points (<200℃) compared to other room-temperature solid metal elements, giving them strong diffusion capabilities. Consequently, In and Ga readily form metal-metal bonds with other metal elements in the functional layers, forming alloys and improving the adhesion between the phase change material and other functional layers containing metal elements. For example, the "other functional layers" mentioned here can be the barrier layer or adhesion layer involved in the phase change memory chip described below.

[0088] Based on first principles, this disclosure calculates the mean square displacements of Hf, In, and Ga elements in a Ge-Sb-Te phase change substrate, as shown in the attached figure. Figure 2 - Appendix Figure 4 As shown, the mean square displacement of In and Ga elements in the Ge-Sb-Te phase change substrate system is relatively large, indicating that In and Ga elements are more likely to diffuse under ambient temperature conditions, which facilitates their alloying with other metal elements in the functional layers.

[0089] For example, when other functional layers contain metal elements such as W, Ti, Ge, Ta, Hf, In, Ga, Al, Cu, Co, and Mo, In and Ga can easily combine with these metal elements to form alloys and metal-metal bonds, thereby improving the adhesion between the phase change material and other functional layers and increasing the adhesion of the phase change material layers.

[0090] This disclosure also includes tests on the adhesion between the phase change material layer and the W electrode for some phase change materials doped with In and those not doped with In, as shown in Table 2. These phase change materials are: (a) Hf-GeSbTe phase change material, which refers to a Ge1Sb4Te6 phase change substrate with Hf as the sole dopant and an atomic percentage of 5%; (b) In-GeSbTe phase change material, which refers to a Ge1Sb4Te6 phase change substrate with In as the sole dopant and an atomic percentage of 3%; and (c) InHf-GeSbTe phase change material, which refers to a Ge1Sb4Te6 phase change substrate with both Hf and In as the sole dopant and an atomic percentage of 3% and 2%, respectively.

[0091] Table 2

[0092] Test object Adhesion (au) Hf-GeSbTe / W electrode 1 InHf-GeSbTe / W electrode 1.32 In-GeSbTe / W electrode 1.2

[0093] As shown in Table 2, when the atomic percentage of In meets the specified range of 1% to 5%, the InHf-GeSbTe phase change material layer doped with both Hf and In has a higher adhesion to the W electrode compared to the Hf-GeSbTe phase change material layer doped with Hf alone and the In-GeSbTe phase change material layer doped with In alone. This improves the interfacial adhesion and thus increases the adhesion of the phase change material layer.

[0094] Further research revealed that when In or Ga elements are co-doped with Hf elements into the GeSbTe phase change substrate, the phase change device can still maintain a high lifetime. To support this conclusion, the embodiments of this disclosure also tested the bonding strength between Hf, In, and Ga elements and Ge, Sb, and Te elements, as well as their self-bonding strength. The unit of bonding strength is kJ / mol, and the test results are shown in Table 3.

[0095] Table 3

[0096]

[0097] As shown in Table 3, Hf, In, and Ga elements can form covalent bonds with themselves, as well as with Ge, Sb, and Te elements, with similar strengths. Therefore, if In or Ga elements are doped into the Ge-Sb-Te phase change substrate alone, In or Ga elements easily form solid solutions with the Ge-Sb-Te phase change substrate. After electrical operation, it is impossible to prevent the segregation of Ge, Sb, and Te elements, resulting in a low lifespan of the phase change device. However, the phase change material provided in this embodiment introduces In and / or Ga elements into the Ge-Sb-Te phase change substrate, as well as Hf elements. The resulting HfIn alloy or HfGa alloy has a high melting point and can stably remain during the melting process (approximately 600°C) of the phase change material during RESET. Furthermore, the stable HfIn and HfGa alloy clusters also hinder the elemental segregation and phase separation of the Ge-Sb-Te phase change substrate, which is beneficial for the phase change device to have a high lifespan. Of course, as mentioned above, when other functional layers adjacent to the phase change material layer contain Hf elements, HfIn alloy or HfGa alloy is also extremely beneficial for enhancing the adhesion of the phase change material layer.

[0098] In summary, the phase change material provided by the embodiments of the present disclosure can enhance the adhesion of the phase change material layer, achieve tight bonding between the phase change material layer and other adjacent functional layers, reduce the probability of interface peeling, increase the product yield of the phase change memory chip, and avoid pollution and interference to the production line and production equipment by further doping at least one of N element, C element, In element, and Ga element into the Ge-Sb-Te phase change substrate doped with Hf element. In particular, by making the doping amount of Hf element be 1.5%-6.5% and the doping amount of at least one of N element, C element, In element, and Ga element be 1.0%-5.0%, while achieving the improvement of the adhesion of the phase change material layer, it is also beneficial to make the phase change device have a large read window and high lifetime.

[0099] In some implementation manners, the phase change material provided by the embodiments of the present disclosure further includes: a third doping element, and the third doping element includes at least one of O element, Si element, B element, Sn element, Bi element, Cd element, Pb element, Zr element, Zn element, Cr element, Al element, Sc element, Y element, Ta element, Ti element, Er element, Lu element, Ho element, Tm element, Dy element, Tb element, Ca element, Nd element, Pr element, Yb element, Ca element, Ce element. By further introducing a specific content of the third doping element into the phase change material, the purpose of optimizing the comprehensive performance of the phase change memory device can also be achieved. Among them, the atomic percentage of the third doping element in the phase change material is 0.01%-10%.

[0100] For the Ge-Sb-Te phase change substrate, the chemical general formula of its Ge-Sb-Te compound can be shown as any of the following chemical general formulas:

[0101] Chemical general formula one, (GeTe 1-a ) x (Sb2Te 3-b ) 1-x , where x is the atomic percentage and 0 < x < 1, a and b are parameters related to the atomic number ratio, 0 < a ≤ 1, 0 < b ≤ 3, and a = 1 and b = 3 do not exist simultaneously. For example, for the compound GeTe 1-a , it means that the atomic number ratio of Ge element to Te element is 1:(1 - a), and for Sb2Te 3-b , it means that the atomic number ratio of Sb element to Te element is 2:(3 - b). Of course, it is not excluded that in the compound GeTe 1-a , the atomic numbers of Ge element and Te element are 1 and 1 - a respectively, and in the compound Sb2Te 3-b , the atomic numbers of Sb element and Te element are 2 and 3 - b respectively.

[0102] Chemical general formula II, (GeTe 1-c ) x (Sb y Te 1-d ) 1-x , where x is the atomic percentage and 0 < x < 1, y, c, and d are parameters related to the atomic number ratio, y ≥ 2, 0 < c ≤ 1, 0 < d ≤ 1, and c = 1 and d = 1 do not exist simultaneously. For example, for the compound GeTe 1-c , it means that the atomic number ratio of Ge element to Te element is 1:1 - c, and for Sb y Te 1-d , it means that the atomic number ratio of Sb element to Te element is y:1 - d. Of course, it is not excluded that in the compound GeTe 1-c , the atomic numbers of Ge element and Te element are 1 and 1 - c respectively, and in the compound Sb y Te 1-d , the atomic numbers of Sb element and Te element are y and 1 - d respectively.

[0103] Exemplarily, the values of a include but are not limited to: 0.1, 0.15, 0.2, 0.25, 0.3, 0.35, 0.4, 0.45, 0.5, 0.55, 0.6, 0.65, 0.7, 0.75, 0.8, 0.85, 0.9, 0.95, 1, etc.

[0104] The values of b include but are not limited to: 0.1, 0.2, 0.3, 0.4, 0.5, 0.6, 0.7, 0.8, 0.9, 1, 1.1, 1.2, 1.3, 1.4, 1.5, 1.6, 1.7, 1.8, 1.9, 2, 2.1, 2.2, 2.3, 2.4, 2.5, 2.6, 2.7, 2.8, 2.9, 3, etc.

[0105] The values of y include but are not limited to: 2, 2.1, 2.2, 2.3, 2.4, 2.5, 2.6, 2.7, 2.8, 2.9, 3, 3.1, 3.2, 3.3, 3.4, 3.5, 3.6, 3.7, 3.8, 3.9, 4, 4.1, 4.2, 4.3, 4.4, 4.5, 4.6, 4.7, 4.8, 4.9, 5, 6, 7, 8, 9, 10, etc.

[0106] The values of c include but are not limited to: 0.1, 0.15, 0.2, 0.25, 0.3, 0.35, 0.4, 0.45, 0.5, 0.55, 0.6, 0.65, 0.7, 0.75, 0.8, 0.85, 0.9, 0.95, 1, etc.

[0107] The values of d include but are not limited to: 0.1, 0.15, 0.2, 0.25, 0.3, 0.35, 0.4, 0.45, 0.5, 0.55, 0.6, 0.65, 0.7, 0.75, 0.8, 0.85, 0.9, 0.95, 1, etc.

[0108] In the embodiments of the present disclosure, by making the chemical general formula of the Ge-Sb-Te phase change substrate as described above, the purpose is to ensure that the adhesion force of the phase change material layer obtained based on the Ge-Sb-Te phase change substrate of the embodiments of the present disclosure is stronger than that of the phase change material layer obtained from other Ge-Sb-Te phase change substrates. This is because GeTe, Sb2Te3, and Sb y Te (y≥2) are all stable compounds with stable chemical composition ratios. Considering that Te单质 is a typical two-dimensional material, after Te-Te bonding, a layered structure is formed, and the interlayer is bonded by van der Waals forces, resulting in poor adhesion. At the same time, the melting point of Sb2Te3 (620°C) is higher than that of Te单质 (450°C). At the high temperature during the phase change process, Te is more likely to precipitate to form Te单质 two-dimensional material, resulting in poor adhesion. In the embodiments of the present disclosure, making a, b, c, and d all greater than 0 can make the Ge-Sb-Te phase change substrate in a state of lacking Te compared to the above-mentioned stable compounds. By appropriately reducing the content of Te element, it is ensured that the adhesion force of the phase change material layer is stronger than that of the phase change material layer corresponding to the Ge-Sb-Te phase change substrate.

[0109] To support the above conclusion, relevant adhesion force tests were conducted in the embodiments of the present disclosure. The test results show that the adhesion force between the Te-lacking Ge-Sb-Te phase change substrate and the W electrode is 1.14 a.u., and the adhesion force between the non-Te-lacking Ge-Sb-Te phase change substrate and the W electrode is 1 a.u. It can be seen that the Te-lacking Ge-Sb-Te phase change substrate has stronger adhesion force than the non-Te-lacking Ge-Sb-Te phase change substrate.

[0110] In some examples, for the first chemical general formula of the Ge-Sb-Te phase change substrate, (GeTe 1-a ) x (Sb2Te 3-b ) 1-x , where 0.2 < x ≤ 0.4. For the second chemical general formula of the Ge-Sb-Te phase change substrate, (GeTe 1-c ) x (Sb y Te 1-d ) 1-x , where 0.2 < x ≤ 0.4.

[0111] For example, the values ​​of x include, but are not limited to: 0.22, 0.23, 0.24, 0.25, 0.26, 0.27, 0.28, 0.29, 0.3, 0.31, 0.32, 0.33, 0.34, 0.35, 0.36, 0.37, 0.38, 0.39, 0.4, etc.

[0112] By making the general chemical formula of the Ge-Sb-Te phase change substrate as shown above, it is not only possible to ensure that the adhesion of the phase change material layer is strong enough, but also to accelerate the delay of the phase change device and improve its lifespan.

[0113] The phase change materials provided in this disclosure exist in forms including, but not limited to, alloys, compounds, combinations of elements and compounds, and combinations of elements and alloys. Phase change material layers are prepared based on these various forms of phase change materials.

[0114] For example, one form of phase change material is a combination of a Ge-Sb-Te ternary compound / alloy, a single element or compound of Hf, and at least one single element or compound of N, C, In, and Ga. In this case, the corresponding amounts of each of the aforementioned single elements or compounds are provided according to the atomic percentage of each element in the phase change material. The Ge-Sb-Te ternary compound / alloy, the single element or compound of Hf, and at least one single element or compound of N, C, In, and Ga can be used independently without mixing. Alternatively, these three materials can be mixed and smelted to form a phase change material in the form of a compound or alloy.

[0115] Of course, it cannot be ruled out that phase change materials can also exist in the following forms: a combination of elemental Ge, elemental Sb, elemental Te, elemental Hf, and at least one corresponding element from N, C, In, and Ga. Based on the atomic percentage of each element in the phase change material, appropriate amounts of each element are provided according to a specific ratio; these specific amounts of elements do not need to be mixed and can exist independently. Alternatively, these specific amounts of elements can be mixed and formed into a compound or alloy form of the phase change material through melting.

[0116] A second embodiment of this disclosure also provides a phase change material, comprising a Ge-Sb-Te phase change substrate and a first dopant and a second dopant doped in the Ge-Sb-Te phase change substrate. The first dopant includes Hf, and the first dopant accounts for 1.5%-7% of the atomic percentage of the phase change material; the second dopant includes at least one selected from N, C, In, and Ga, and the second dopant accounts for 1.0%-7% of the atomic percentage of the phase change material; furthermore, the sum of the atomic percentages of the first dopant and the second dopant is greater than 4% and less than 10%.

[0117] Examples of the atomic percentage of the first dopant element Hf in the phase change material include, but are not limited to: 1.5%, 1.6%, 1.7%, 1.8%, 1.9%, 2%, 2.1%, 2.2%, 2.3%, 2.4%, 2.5%, 2.6%, 2.7%, 2.8%, 2.9%, 3%, 3.1%, 3.2%, 3.3%, 3.4%, 3.5%, 3.6%, 3.7%, 3.8%, 3.9%, 4%, 4.1%, 4.2%, 4.3%, 4.4%, 4.5%, 4.6%, 4.7%, etc.

[0118] 4.8%, 4.9%, 5%, 5.1%, 5.2%, 5.3%, 5.4%, 5.5%, 5.6%, 5.7%, 5.8%, 5.9%, 6%, 6.1%, 6.2%, 6.3%, 6.4%, 6.5%, 6.6%, 6.7%, 6.8%, 6.9%, etc.

[0119] Examples of the atomic percentage of the second dopant element in the phase change material include, but are not limited to: 1%, 1.1%, 1.2%, 1.3%, 1.4%, 1.5%, 1.6%, 1.7%, 1.8%, 1.9%, 2%, 2.1%, 2.2%, 2.3%, 2.4%, 2.5%, 2.6%, 2.7%, etc.

[0120] 2.8%, 2.9%, 3%, 3.1%, 3.2%, 3.3%, 3.4%, 3.5%, 3.6%, 3.7%, 3.8%, 3.9%, 4%, 4.1%, 4.2%,

[0121] 4.3%, 4.4%, 4.5%, 4.6%, 4.7%, 4.8%, 4.9%, 5%, 5.1%, 5.2%, 5.3%, 5.4%, 5.5%, 5.6%, 5.7%,

[0122] 5.8%, 5.9%, 6%, 6.1%, 6.2%, 6.3%, 6.4%, 6.5%, 6.6%, 6.7%, 6.8%, 6.9%, etc.

[0123] The sum of the atomic percentages of the first dopant and the second dopant can be 4.5%, 5%, 5.5%, 6%, 6.5%, 7%, 7.5%, 8%, 8.5%, 9%, 9.5%, etc.

[0124] The second doping element can be one of N, C, In, or Ga. For example, the second doping element can be N, C, In, or Ga. Alternatively, the second doping element can be a combination of any two or any three of N, C, In, or Ga elements, or include all four elements simultaneously.

[0125] Regarding the principles of using N, C, In, or Ga as the second doping element to enhance the adhesion of the phase change material layer, please refer to the relevant principle description in the phase change material involved in the first embodiment above, which will not be repeated here.

[0126] Compared with the phase change material involved in the first embodiment, the atomic percentage content of N, C, In or Ga elements in the phase change material involved in the second embodiment is increased (atomic percentage is 1.0%-7%).

[0127] In this type of phase change material layer, the doping concentrations of the first and second doping elements need to be controlled at 7% or less. This ensures that the phase change material layer has strong adhesion while also ensuring that the phase change device has high and stable high resistance, thereby improving the read window and cycle stability of the phase change device. Additionally, it ensures that the phase change device has high and stable low resistance, thereby improving the lifespan and cycle stability of the phase change device.

[0128] The reasons are as follows:

[0129] Research has found that when the atomic percentages of the first and second doping elements are each greater than 7%, side effects occur, leading to performance degradation in phase change devices, such as read window and lifetime.

[0130] Taking nitrogen (N) as the second dopant element and referring to the data in Table 5 of Example 5, it can be seen that when the atomic percentage of Hf is too high (greater than 7%), the high resistance of the phase change device decreases, leading to a smaller read window. Furthermore, the high resistance becomes unstable during cycling, making it prone to segregation, which in turn makes the phase change device susceptible to fatigue failure. When the atomic percentage of N is too high (greater than 7%), the low resistance of the phase change device increases abnormally and becomes unstable during cycling, continuously decreasing during fatigue. This may be related to the increased likelihood of thermoelectric accumulation leading to segregation during operation.

[0131] As shown in Table 5, when the atomic percentage of Hf is 8% (exceeding the upper limit of 7%), the high resistance of the phase-change memory chip decreases, but it becomes unstable during cycling. When the atomic percentage of N is 8% (exceeding the upper limit of 7%), the low resistance of the phase-change memory chip increases, but it becomes unstable during cycling. Therefore, in this embodiment, the atomic percentages of Hf and N are each less than or equal to 7%, thereby ensuring that the phase-change device has both a high and stable high resistance and a high and stable low resistance.

[0132] In addition, in this type of phase change material, the sum of the atomic percentages of the first dopant element and the second dopant element needs to be greater than 4% and less than 10%. This ensures that the phase change material layer has strong adhesion while also enabling the phase change device to have high lifespan and cycle stability.

[0133] The reasons are as follows:

[0134] Studies have found that for this type of phase change material, the lifetime of the phase change device is closely related to the doping concentration of Hf and the second dopant element. Performance analysis of the phase change device reveals that its low resistance is directly proportional to its final fatigue life. Figure 24 As shown, within a certain range, the higher the low resistance of a phase change device (PCD), the better its fatigue characteristics. The low resistance of a PCD is mainly determined by the low resistance of the phase change material layer and its crystallization temperature. Figure 24 The values ​​of the x and y coordinates are obtained by normalizing and taking the logarithm.

[0135] Taking N as the second doping element as an example and referring to the data in Table 1, it can be seen that when the doping concentration of Hf and N elements increases, the low resistance and crystallization temperature of the phase change material layer will increase accordingly (see phase change material 3 and phase change material 4 in Table 1). As a result, the low resistance of the phase change device will also increase, thus the phase change device will have a longer lifespan.

[0136] Therefore, to ensure a longer lifespan for phase change devices, the low resistance of the phase change material layer needs to be as high as possible while maintaining a certain read window. In Table 1, phase change material 4 has an atomic percentage of 2% Hf and 2% N, and phase change material 1 has an atomic percentage of 4% Hf and 0% N. The low resistance of the corresponding phase change material layers for both is approximately 400 ohms, which is far less than 1 kΩ, and the sum of the atomic percentages of Hf and N in both is 4%. Therefore, this embodiment of the present disclosure specifies that the sum of the atomic percentages of Hf and N is greater than 4%, meaning that the sum of the atomic percentages of the first and second doping elements is greater than 4%, which is essential for imparting high lifespan characteristics to the phase change device.

[0137] The sum of the doping concentrations of the first and second dopants is not necessarily better the higher it is. Studies have confirmed that when the sum of the doping concentrations of the first and second dopants exceeds 10%, it can cause side effects, leading to instability in the cycling process of the phase change device. This includes abnormally high low resistance and instability during cycling, specifically a continuous decrease during cycling. This may be due to the phase change material layer being more prone to thermoelectric accumulation and segregation during operation. Taking N as the second dopant as an example and referring to the data in Table 5 of Example 5, it can be seen that when the atomic percentage of Hf is 6.5% and the atomic percentage of N is 5%, the low resistance increases abnormally and instability occurs during cycling because the sum of their atomic percentages exceeds 10%. Therefore, it is desirable that the sum of the atomic percentages of Hf and N be less than 10%.

[0138] In summary, the phase change material provided in this disclosure, by further doping at least one of N, C, In, and Ga elements into a Ge-Sb-Te phase change substrate doped with Hf, can enhance the adhesion of the phase change material layer, achieve a tight bond between the phase change material layer and adjacent functional layers, reduce the probability of interface peeling, increase the product yield of the phase change memory chip, and avoid pollution and interference to the production line and equipment. Specifically, by setting the Hf doping amount to 1.5%-7%, and the doping amount of at least one of N, C, In, and Ga elements to 1.0%-7%, and the sum of the atomic percentages of the two doping elements to be greater than 4% and less than 10%, the adhesion of the phase change material layer is improved, while also enabling the phase change device to have a large read window, long lifetime, and cycle stability.

[0139] In some implementations, the phase change material provided in this disclosure further includes a third dopant element, which includes at least one of the following: O, Si, B, Sn, Bi, Cd, Pb, Zr, Zn, Cr, Al, Sc, Y, Ta, Ti, Er, Lu, Ho, Tm, Dy, Tb, Ca, Nd, Pr, Yb, Ca, and Ce. By further introducing a specific amount of the third dopant element into the phase change material, the overall performance of the phase change memory device can also be optimized. The third dopant element accounts for 0.01%-10% of the atomic percentage of the phase change material.

[0140] For Ge-Sb-Te phase change substrates, the general chemical formula of their Ge-Sb-Te compounds can be shown as any of the following general chemical formulas:

[0141] Chemical general formula one, (GeTe) 1-a )x (Sb2Te 3-b ) 1-x , where x is the atomic percentage and 0 < x < 1, a and b are parameters related to the atomic number ratio, 0 < a ≤ 1, 0 < b ≤ 3, and a = 1 and b = 3 do not exist simultaneously.

[0142] Chemical general formula two, (GeTe 1-c ) x (Sb y Te 1-d ) 1-x , where x is the atomic percentage and 0 < x < 1, y, c, and d are parameters related to the atomic number ratio, y ≥ 2, 0 < c ≤ 1, 0 < d ≤ 1, and c = 1 and d = 1 do not exist simultaneously.

[0143] Regarding the chemical general formula one and chemical general formula two of the Ge - Sb - Te phase - change substrate involved above, for the exemplary values of each parameter and the related explanations, reference can be made to the relevant descriptions in the phase - change material involved in the first embodiment above, and details will not be repeated here.

[0144] In the embodiments of the present disclosure, by making the chemical general formula of the Ge - Sb - Te phase - change substrate as described above, the purpose is to ensure that the adhesion force of the phase - change material layer obtained based on the Ge - Sb - Te phase - change substrate of the embodiments of the present disclosure is stronger than that of the phase - change material layers obtained from other Ge - Sb - Te phase - change substrates. This is because GeTe, Sb2Te3, Sb y Te (y ≥ 2) are all stable compounds with stable chemical composition ratios. Considering that Te单质 is a typical two - dimensional material, after Te - Te bonding, a layered structure is formed, and the intermolecular force between layers is van der Waals force, resulting in poor adhesion. At the same time, the melting point of Sb2Te3 (620 °C) is higher than that of Te单质 (450 °C). At high temperatures during the phase - change process, Te is more likely to precipitate to form Te单质 two - dimensional material, leading to poor adhesion. In the embodiments of the present disclosure, making a, b, c, and d all greater than 0 can make the Ge - Sb - Te phase - change substrate in a state of lacking Te compared with the above - mentioned stable compounds. By appropriately reducing the content of Te element, it is ensured that the adhesion force of the phase - change material layer is strong enough.

[0145] In addition, regarding the relevant adhesion force test of the above - mentioned Ge - Sb - Te phase - change substrate, reference can still be made to the relevant descriptions in the phase - change material involved in the first embodiment above, and details will not be repeated here.

[0146] In some examples, for the chemical general formula one of the Ge - Sb - Te phase - change substrate, (GeTe 1-a ) x (Sb2Te 3-b ) 1-x It should be noted that "Te单质" in the original text is not a standard chemical term. It might be a specific name in the original context. Here it is directly translated as "Te单质" for the sake of following the translation rules. If there is a more accurate chemical name, it should be used for a more accurate translation., where 0.2 < x ≤ 0.4, for the second chemical general formula of the Ge-Sb-Te phase change substrate, (GeTe 1-c ) x (Sb y Te 1-d ) 1-x , where 0.2 < x ≤ 0.4.

[0147] Exemplarily, the values of x include but are not limited to: 0.22, 0.23, 0.24, 0.25, 0.26, 0.27, 0.28, 0.29, 0.3, 0.31, 0.32, 0.33, 0.34, 0.35, 0.36, 0.37, 0.38, 0.39, 0.4, etc.

[0148] For the first or second chemical general formula of the Ge-Sb-Te phase change substrate corresponding to 0.2 < x ≤ 0.4, another expression of the corresponding chemical general formula can also be as follows: Ge x Sb y Te 1-x-y , where x and y both represent the atomic percentages of the corresponding elements, and 6% < x < 15%, 35% < y < 45% (it can also be Ge x Sb y Te 100-x-y , where x and y are both the mass parts of the corresponding atoms, 6 < x < 15, 35 < y < 45).

[0149] For example, on the basis of satisfying the above chemical general formula, in the Ge-Sb-Te phase change substrate, the ratio of the atomic percentage contents of Ge element, Sb element and Te element includes but is not limited to: 1:4:5, 1:4:6, 1:4:7, etc. The corresponding GeSbTe compounds are respectively abbreviated as GeSbTe145 (or Ge1Sb4Te5, GST145), GeSbTe146 (or Ge1Sb4Te6, GST146), GeSbTe147 (or Ge1Sb4Te7, GST147).

[0150] By making the chemical general formula of the Ge-Sb-Te phase change substrate as shown above, not only is the adhesion force of the phase change material layer ensured to be strong enough, but it is also beneficial to reduce the time delay of the phase change device and improve the lifespan of the phase change device.

[0151] This disclosure presents an embodiment that investigates the effects of the content of Ge and Sb elements in the Ge-Sb-Te phase change substrate on adhesion, latency, and lifetime. The test results show that the atomic percentage of Sb is an important factor determining the speed of the phase change device. Sb has a low crystallization temperature and a fast growth rate. Therefore, the atomic percentage of Sb is positively correlated with the SET performance of the phase change device. Theoretically, the higher the atomic percentage of Sb, the shorter the latency of the phase change device.

[0152] Experiments have shown that when the atomic percentage of Sb in the Ge-Sb-Te phase change substrate is greater than 35% (corresponding to x ≤ 0.4 in the above stoichiometry ratio), the low crystallization temperature and fast growth rate of elemental Sb allow the phase change device delay to reach below 100 ns. However, a higher Sb atomic percentage is not always better. When the Sb atomic percentage in the Ge-Sb-Te phase change substrate exceeds 45% (corresponding to x > 0.2 in the above stoichiometry ratio), the amount of stable compounds formed by Sb and Te bonds is relatively reduced, resulting in a relatively excessive amount of elemental Sb with poor stability, which leads to a certain reduction in the lifetime of the phase change device. Therefore, limiting the Sb atomic percentage to greater than 35% and less than 45% is beneficial for achieving both low delay and high lifetime in phase change devices.

[0153] For Ge, experiments have shown that when the atomic percentage of Ge is greater than 15%, its high concentration can slow down the latency of the phase change device to some extent. When the atomic percentage of Ge is less than 6% (corresponding to x > 0.2 in the above stoichiometry), its low concentration will reduce the adhesion of the phase change material layer, thus making it too difficult to optimize the mass production process. Therefore, limiting the atomic percentage of Ge to greater than 6% and less than 15% helps ensure high adhesion of the phase change material layer and low latency of the phase change device.

[0154] Furthermore, the form in which the phase change material exists provided in the second embodiment can still be referred to the relevant descriptions in the phase change material involved in the first embodiment, and will not be repeated here.

[0155] As can be seen, the embodiments of this disclosure identify the corresponding coupling relationship between different elements and key device performance (speed, lifetime, window, adhesion) in the phase change material, and adjust the stoichiometric ratio of each element to achieve balanced optimization of the phase change memory chip performance, thereby ensuring that the overall performance of the phase change memory chip is more superior.

[0156] This disclosure also provides a phase change memory chip, which includes a plurality of phase change memory cells. Each phase change memory cell includes a phase change material layer 100, which is prepared from the phase change material described in any of the above embodiments.

[0157] Phase change memory chips can also be called phase change memory. The phase change memory chip provided in this disclosure embodiment is based on its phase change material layer 100 being prepared from the phase change material provided in this disclosure embodiment, so that the phase change memory chip has all the advantages of the phase change material provided in this disclosure embodiment.

[0158] Phase-change memory cells are disposed on substrate 004, as shown in the attached figure in some examples. Figure 5 As shown, the phase change memory cell includes, in addition to the phase change material layer 100, a top electrode 501, a bottom electrode 502, and an insulating layer 400. The substrate 004, bottom electrode 502, phase change material layer 100, and top electrode 501 are sequentially stacked in a bottom-to-top direction, and the insulating layer 400 at least covers the outer side of the phase change material layer 100.

[0159] In other examples, the phase change memory cell, in addition to the phase change material layer 100 described above, includes, as shown in the attached... Figure 6 As shown, it also includes a top electrode 501, a bottom electrode 502, an insulating layer 400, and a barrier layer 300. Along the bottom-up direction, the substrate 004, the bottom electrode 502, the barrier layer 300, the phase change material layer 100, the barrier layer 300, and the top electrode 501 are stacked sequentially, and the insulating layer 400 covers at least the outer side of the phase change material layer 100 and the barrier layer 300.

[0160] For example, the barrier layer material used in the barrier layer 300 includes at least one of the following elements: W, Ti, Ge, Ta, Hf, In, Ga, Al, Cu, Co, Mo, nitrides of the above elements, and carbides of the above elements.

[0161] Taking the second doping element in the phase change material layer 100 as N or C as an example, the N or C element can bond with the aforementioned metal element in the barrier layer 300 to form a non-metal-metal ionic bond, thereby increasing the bonding force between the adhesion layer 200 and the barrier layer 300 and reducing the probability of the interface peeling off during the process.

[0162] Furthermore, as shown in the appendix Figure 7 and attached Figure 8 As shown, the phase change storage unit provided in this embodiment of the present disclosure further includes an adhesion layer 200, which is stacked on at least one surface of the phase change material layer 100. The adhesion layer 200 is used to increase the adhesion between the phase change material layer 100 and adjacent functional layers.

[0163] For example, an adhesion layer 200 may be provided on the surface of the phase change material layer 100 facing the top electrode 501, or on the surface of the phase change material layer 100 facing the bottom electrode 502, or on the two opposite surfaces of the phase change material layer 100 respectively.

[0164] An adhesion layer 200 is added to at least one surface of the phase change material layer 100 to increase the adhesion between the phase change material layer 100 and the adjacent functional layer, wherein the adjacent functional layer may be a barrier layer 300 or an electrode layer.

[0165] As can be seen, the phase change memory chip provided in this embodiment not only improves the phase change material itself, but also improves the structure of the phase change memory chip by adding an adhesion layer 200 to further enhance the adhesion between the phase change material layer 100 and the adjacent functional layer, significantly reducing the probability of interface peeling, thereby increasing the product yield of the phase change memory cell, and also avoiding pollution and interference to the production line.

[0166] The adhesion layer 200 is prepared using an adhesion layer raw material. In some implementations, the adhesion layer raw material includes at least one of the following: a nitride of the target element and a carbide of the target element. The target element is selected from at least one of the following elements: W, Ti, Ge, Ta, Hf, In, Ga, Al, Cu, Co, and Mo. For example, if the target element is W, the adhesion layer raw material can be either tungsten nitride or tungsten carbide.

[0167] When the second doping element in the phase change material layer 100 is N or C, the N or C element can form a non-metal-metal ionic bond with the target element in the adhesion layer 200, thereby increasing the bonding force between the adhesion layer 200 and the phase change material layer 100, enhancing the interfacial adhesion, and reducing the probability of the interface peeling off during the processing.

[0168] When the second doping element in the phase change material layer 100 is In or Ga, In or Ga can combine with the target element in the adhesion layer 200 to form an alloy, forming a metal-metal bond, which improves the bonding force between the adhesion layer 200 and the phase change material layer 100, enhances the interface adhesion, and reduces the probability of the interface peeling off during the process.

[0169] It is evident that by using the aforementioned adhesive layer material, the interfacial bonding ability and adhesion between the phase change material layer and the adhesive layer can be achieved, preventing the phase change material layer from detaching from the barrier layer interface and thus reducing the device yield.

[0170] To demonstrate stronger interfacial adhesion in phase change memory chips with adhesion layers, this disclosure provides several types of phase change materials for adhesion force testing, as shown below: (d) HfGST, which refers to a Ge1Sb4Te6 phase change substrate with a single Hf element doped at 3% atomic percentage; (e) NHfGST, which refers to a Ge1Sb4Te6 phase change substrate with simultaneous Hf and N elements doped at 3% and 2% atomic percentages, respectively. The adhesion force between the phase change material layer and the W electrode corresponding to these phase change materials was tested, and the test results are shown in Table 2.

[0171] The adhesion between the phase change material layers corresponding to these phase change materials and the W electrode and the W2N material adhesion layer were tested, and the test results are shown in Table 4.

[0172] Table 4

[0173] Test object Adhesion force extreme value (N) Median adhesion force (N) NHfGST / W electrode 2118 1408 HfGST / W electrode 1847 1272 <![CDATA[NHfGST / Adhesion layer W2N]]> 2234 1435

[0174] As shown in Table 4, given that the atomic percentages of Hf and N elements meet their respective defined atomic percentage ranges, it is evident that, compared to a phase change material layer solely doped with Hf, the adhesion between the phase change material layer simultaneously doped with Hf and N elements and the W electrode in this application is significantly greater than that between the phase change material layer without N doping and the W electrode. Furthermore, the adhesion between the phase change material layer simultaneously doped with Hf and N elements and the W electrode is slightly less than that between the phase change material layer simultaneously doped with Hf and N elements and the adhesion layer W2N. Therefore, by further increasing the adhesion layer, the interfacial adhesion of the phase change material layer can be further improved.

[0175] In other implementations, the adhesive layer material includes a Ge-Sb-Te phase change material doped with a fourth dopant element, which differs from the phase change material used in the phase change material layer. The fourth dopant element is selected from at least one of Hf, N, C, In, and Ga, and its atomic percentage in the adhesive layer material is 0.01%-20%, or more specifically, 0.01%-10%.

[0176] The general chemical formula of the Ge-Sb-Te phase change material involved can be shown below: (GeTe 1-a ) x (Sb2Te 3-b ) 1-x, where \(0 \lt x \lt 1\), \(0 \lt a \leq 1\), \(0 \lt b \leq 3\), and \(a = 1\) and \(b = 3\) do not exist simultaneously (here, \(x\), \(a\), and \(b\) are parameters representing atomic percentages). Alternatively, the chemical general formula of the Ge-Sb-Te phase change material can also be shown as follows: (GeTe 1-c ) x (Sb y Te 1-d ) 1-x , where \(0 \lt x \lt 1\), \(y \geq 2\), \(0 \lt c \leq 1\), \(0 \lt d \leq 1\), and \(c = 1\) and \(d = 1\) do not exist simultaneously (here, \(x\), \(y\), \(c\), and \(d\) are parameters representing atomic percentages).

[0177] For example, the simplified formulas of some applicable adhesion layer raw materials can be shown as follows: NHfGeSbTe, CHfGeSbTe, InHfGeSbTe, GaHfGeSbTe, HfGeSbTe, NGeSbTe, CGeSbTe, InGeSbTe, GaGeSbTe, etc.

[0178] The doping amount of the fourth doping element in the Ge-Sb-Te phase change material is within the above range, making the Ge-Sb-Te phase change material doped with the fourth doping element different from the phase change material in the phase change material layer 100, mainly playing an interface adhesion role.

[0179] As described above, the adhesion layer 200 is located between the phase change material layer 100 and the adjacent functional layer. Here, the adjacent functional layer can be the barrier layer 300 or an electrode layer (including at least one of the top electrode 501 and the bottom electrode 502).

[0180] In one scheme, the phase change memory cell includes a barrier layer 300, and the adhesion layer 200 is located between the phase change material layer 100 and the barrier layer 300, for increasing the adhesion force between the phase change material layer 100 and the barrier layer 300.

[0181] The barrier layer 300 plays a role in preventing the elements in the phase change material layer 100 from diffusing into the electrode layer. The adhesion layer 200 is located between the phase change material layer 100 and the barrier layer 300, effectively preventing peeling between the phase change material layer 100 and the barrier layer 300.

[0182] In some examples, as shown Figure 7 , the number of the barrier layers 300 is two, and the two barrier layers 300 are respectively located on the opposite sides of the phase change material layer 100. In this case, the number of the adhesion layers 200 can also be two. One adhesion layer 200 is located between the first surface of the phase change material layer 100 and one barrier layer 300, and the other adhesion layer 200 is located between the second surface of the phase change material layer 100 and the other barrier layer 300.

[0183] For example, the barrier layer 300 uses a barrier layer material including at least one of the following elements: W, Ti, Ge, Ta, Hf, In, Ga, Al, Cu, Co, Mo, nitrides of the above elements, and carbides of the above elements. Of course, the barrier layer material is different from the adhesive layer material.

[0184] When the second doping element in the phase change material layer 100 is N or C, the N or C element can form non-metal-metal ionic bonds with the metal element in the barrier layer 300, thereby increasing the bonding force between the barrier layer 300 and the phase change material layer 100, enhancing the interface adhesion, and reducing the probability of the interface peeling off during the processing.

[0185] When the second doping element in the phase change material layer 100 is In or Ga, In or Ga can combine with the metal element in the barrier layer 300 to form an alloy, forming a metal-metal bond, which improves the bonding force between the barrier layer 300 and the phase change material layer 100, enhances the interface adhesion, and reduces the probability of the interface peeling off during the process.

[0186] In accordance with the above-described scheme, the phase change memory cell, in addition to the phase change material layer 100, adhesion layer 200, and barrier layer 300, may also include a top electrode 501, a bottom electrode 502, and an insulating layer 400. One example is, as shown in the attached... Figure 7 As shown, along the bottom-up direction, the substrate 004, bottom electrode 502, barrier layer 300, adhesion layer 200, phase change material layer 100, adhesion layer 200, barrier layer 300, and top electrode 501 are stacked in sequence, and the insulating layer 400 covers at least the outside of the phase change material layer 100, adhesion layer 200, and barrier layer 300.

[0187] In some examples, the thickness of the barrier layer 300 and the adhesive layer 200 is independently 1nm to 8nm, including but not limited to: 1nm, 2nm, 3nm, 4nm, 5nm, 6nm, 7nm, 8nm, etc. For example, the thickness of both the barrier layer 300 and the adhesive layer 200 can be 2nm.

[0188] Another approach is to include an electrode layer in the phase change memory cell, with an adhesion layer 200 located between the phase change material layer 100 and the electrode layer to increase the adhesion between them. The adhesion layer 200, located between the phase change material layer 100 and the corresponding electrode layer, effectively prevents peeling between them.

[0189] In accordance with the above-described scheme, the phase change memory cell, in addition to the phase change material layer 100 and the adhesion layer 200, may also include a top electrode 501, a bottom electrode 502, and an insulating layer 400. One example is, as shown in the attached diagram... Figure 8 As shown, along the bottom-up direction, the substrate 004, bottom electrode 502, adhesion layer 200, phase change material layer 100, adhesion layer 200 and top electrode 501 are stacked in sequence, and the insulating layer 400 covers at least the outside of the phase change material layer 100 and the adhesion layer 200.

[0190] The phase change memory cells mentioned above have structures including, but not limited to, the following: confined structure, T-structure, U-groove structure, L-shaped structure, etc.

[0191] In some implementations, the phase-change memory chip provided in this disclosure further includes: a plurality of selector units, which are arranged in series with the phase-change memory unit. The selector units are used as switching devices for the phase-change memory unit, thereby effectively suppressing leakage current generated during the operation of the phase-change memory chip.

[0192] See Figure 9 The selection tube unit includes a selection layer 600. The selection tube material used in the selection layer 600 includes at least one of S-based selection tube materials, Se-based selection tube materials, and Te-based selection tube materials. The aforementioned S-based, Se-based, and Te-based selection tube materials can all be some known or commercially available selection materials, which will not be listed individually here. The aforementioned selection tube materials can be binary compounds, ternary compounds, or other multi-component compounds containing more elements.

[0193] Furthermore, the selector material also includes a fifth doping element, which is selected from at least one of the following elements: B, Al, Ga, In, C, Si, Ge, Sn, N, P, As, Sb, Bi, O, Au, Hf, Pd, Cu, Co, Ag, Pt, Sc, Ti, and Ta. The fifth doping element accounts for 0.01%-20% of the atomic percentage of the selector material, and more specifically, 0.01%-10%.

[0194] In some examples, the fifth doping element includes at least one of B, Al, Ga, In, C, Si, Ge, Sn, N, P, As, Sb, Bi, and O, and also includes at least one of Au, Hf, Pd, Cu, Co, Ag, Pt, Sc, Ti, and Ta.

[0195] By doping the gate material with a fifth doping element, the gate layer 600 can have the advantages of low leakage current, strong thermal stability, and long cycle life.

[0196] The thickness of the gate layer 600 can range from 10nm to 50nm, for example, 1nm, 2nm, 3nm, 4nm, 5nm, 6nm, 7nm, 8nm, 9nm, 10nm, 15nm, 20nm, 25nm, 30nm, 35nm, 40nm, 45nm, 50nm, etc. The thickness of the gate layer 600 can be determined based on the electrical properties of the phase-change memory cells connected in series with it, to ensure that the gate transistor cells maintain the desired switching characteristics.

[0197] In some examples, such as the attached Figure 9 - Appendix Figure 12 As shown, the gate unit may only include the gate layer 600, and the gate layer 600 may be integrated into the phase change memory unit. The gate layer 600 and the phase change material layer 100 in the phase change memory unit can be connected in series through the intermediate electrode 503.

[0198] In some examples, the gate transistor unit and the corresponding phase-change memory unit are independent (not shown in the figure). In such examples, the gate transistor unit may include a substrate, a bottom electrode, a gate layer, and a top electrode stacked sequentially from bottom to top, and the gate layer is also covered with an insulating layer. The electrode layer of the gate transistor unit and the electrode layer of the corresponding phase-change memory unit can be connected in series by means of wires (e.g., copper interconnects).

[0199] The phase change memory chip provided in this embodiment can be prepared by thin film deposition, photolithography, etching and other processes. The multiple functional layers in the phase change memory chip, such as phase change material layer 100, adhesion layer 200, barrier layer 300, and gate layer 600, can all be prepared by thin film deposition.

[0200] For example, some applicable thin film deposition processes include, but are not limited to, atomic layer deposition (ALD), physical vapor deposition (PVD), chemical vapor deposition (CVD), etc. As further examples, plasma enhanced chemical vapor deposition (PECVD), magnetron sputtering, electron beam evaporation, etc. can be used to prepare the above-mentioned functional layers.

[0201] Magnetron sputtering is a physical vapor deposition process with advantages such as ease of control, large coating area, strong adhesion, and wide applicability. Exemplarily, embodiments of this disclosure can use magnetron sputtering to form various functional layers. The sputtering gases used in the magnetron sputtering process include, but are not limited to, at least one of: argon (Ar), krypton (Kr), xenon (Xe), neon (Ne), and nitrogen (N2).

[0202] The substrate 004 involved in the aforementioned phase change memory unit and some selector units includes, but is not limited to: silicon dioxide substrate, silicon carbide substrate, silicon wafer substrate, sapphire substrate, diamond substrate, etc.

[0203] The electrodes (top electrode 501, bottom electrode 502, and intermediate electrode 503) involved in the aforementioned phase change memory unit and some gate transistor units are made of materials including, but not limited to: titanium tungsten (TiW, for example, Ti3W7), tungsten (W), aluminum (Al), titanium nitride (TiN), titanium (Ti), tantalum (Ta), silver (Ag), platinum (Pt), carbon (C), copper (Cu), ruthenium (Ru), gold (Au), cobalt (Co), chromium (Cr), nickel (Ni), iridium (Ir), palladium (Pd), rhodium (Rh), etc.

[0204] The above-mentioned electrode materials can be deposited into corresponding electrode layers using processes such as physical vapor deposition (PVD) (e.g., magnetron sputtering).

[0205] The insulating layer 400 involved in the aforementioned phase change memory unit and some selector units serves to provide insulation and thermal isolation. The insulating and thermal insulation materials used include, but are not limited to, silicon nitride (Si3N4), silicon carbide (SiC), and silicon dioxide (SiO2). Chemical vapor deposition (CVD) processes, such as plasma-enhanced chemical vapor deposition (PECVD), can be used to deposit the aforementioned insulating and thermal insulation materials into the insulating layer 400.

[0206] In some examples, such as the attached Figure 9 - Appendix Figure 12 As shown, the insulating layer 400 includes a first insulating layer 401 and a second insulating layer 402. The first insulating layer 401 covers at least the outer surface of the phase change material layer 100, and may further cover the outer surfaces of the barrier layer 300, the adhesion layer 200, and the top electrode 501. The second insulating layer 402 covers the outer surface of the first insulating layer 401.

[0207] For example, the first insulating layer 401 is silicon nitride (Si3N4), silicon carbide (SiC), etc., and its thickness is greater than 1 nm, for example, 2 nm to 3 nm. The second insulating layer 402 is a compound formed by Si element and at least one of N element, C element, and O element, for example, at least one of silicon nitride (Si3N4), silicon carbide (SiC), and silicon dioxide (SiO2), and its thickness is greater than 1 nm, for example, 2 nm to 3 nm.

[0208] By providing a first insulating layer 401 and a second insulating layer 402 from the inside out on the outside of the phase change material layer 100, the purpose of optimizing insulation and thermal isolation is achieved.

[0209] In some examples, such as the attached Figure 9 - Appendix Figure 12 As shown, the insulating layer includes a third insulating layer 403 and a fourth insulating layer 404. The third insulating layer 403 covers at least the outer surface of the gate layer 600, and may further cover the outer surfaces of the intermediate electrode 503 and the bottom electrode 502. The fourth insulating layer 404 covers the outer surface of the third insulating layer 403.

[0210] For example, the third insulating layer 403 is silicon nitride (Si3N4), silicon carbide (SiC), etc., and its thickness is greater than 1 nm, for example, 2 nm to 3 nm. The fourth insulating layer 404 is a compound formed by Si element and at least one of N element, C element, and O element, for example, at least one of silicon nitride (Si3N4), silicon carbide (SiC), and silicon dioxide (SiO2), and its thickness is greater than 1 nm.

[0211] For example, the thickness of the fourth insulating layer 404 in a single-layer structure can be 2 nm to 3 nm. In some examples, the fourth insulating layer 404 can also be configured as a two-layer structure that covers the entire structure from the inside out, with the two layers made of different materials. For the fourth insulating layer 404 in a double-layer structure, the thickness can be 2 nm to 15 nm.

[0212] By setting a third insulating layer 403 and a fourth insulating layer 404 from the inside to the outside of the gate layer 600, the purpose of optimizing insulation and thermal isolation is achieved.

[0213] The phase-change memory chip structures provided in this disclosure include, but are not limited to, 1S1R (One Selector One Resistor) structure and 1SnR (One Selector n Resistor) structure. For a 1S1R phase-change memory chip, one selector unit controls one phase-change memory cell. For a 1SNR phase-change memory chip, one selector unit controls N phase-change memory cells simultaneously.

[0214] In some examples, the phase-change memory chip structure involved in the embodiments of this disclosure can be a 1S1R structure, where each group of series-connected selector units and phase-change memory units is defined as a memory sub-unit 001, as shown in the attached figure. Figure 13 As shown, the 1S1R type phase-change memory chip includes multiple memory sub-cells 001, multiple word lines 002, and multiple bit lines 003. Of course, the phase-change memory chip also includes peripheral control circuitry.

[0215] Multiple storage sub-cells 001 constitute a phase-change memory array. The multiple storage sub-cells 001 are arranged in an array. Multiple word lines 002 are distributed in parallel and spaced apart. Each word line 002 can extend inward along a first direction. Multiple bit lines 003 are distributed in parallel and spaced apart. Each bit line 003 can extend inward along a second direction. There is an angle between the first direction and the second direction. The angle is greater than 0° and less than or equal to 90°.

[0216] For example, if the angle between the first direction and the second direction is 90°, multiple word lines 002 can be arranged in rows and multiple bit lines 003 can be arranged in columns. The multiple rows of word lines 002 and multiple rows of bit lines 003 cooperate to form an array that adapts to multiple memory sub-cells 001. Each memory sub-cell 001 is located within a matrix sub-cell composed of word lines 002 and bit lines 003 (i.e., located in the overlapping area of ​​word lines 002 and bit lines 003). Each memory sub-cell 001 is connected to the bit line 003 of the corresponding column through its top electrode 501, and each memory sub-cell 001 is connected to the word line 002 of the corresponding row through its bottom electrode 502.

[0217] In application, multiple word lines 002 arranged in rows are connected to row selection circuit A1, which in turn is driven by row voltage control circuit B1; multiple bit lines 003 arranged in columns are connected to column selection circuit A2, which in turn is driven by column voltage control circuit B2. Read / write circuit C receives commands from the processor and connects to either row voltage control circuit B1 or column voltage control circuit B2. Thus, read / write circuit C, by receiving commands from the processor, controls row selection circuit A1 or column selection circuit A2 via row voltage control circuit B1 or column voltage control circuit B2, thereby performing read / write operations on the phase-change memory cells in the selected memory sub-cell 001.

[0218] During the read and write operations of the phase-change memory cell, the selector transistor unit is used as a switching device. When the memory sub-cell 001 is not simultaneously selected by the row selection circuit A1 and the column selection circuit A2, its corresponding selector transistor unit is in the off state to avoid leakage current affecting other cells.

[0219] The phase-change memory chip provided in this disclosure can be stacked in three dimensions to form an N-layer structure (N≥1) in the vertical direction, thereby achieving a storage density of 4F for the three-dimensional stacked memory. 2 *N, where F is the semiconductor process feature size.

[0220] The following describes, in conjunction with a phase-change memory chip including a gating layer 600, wherein the gating layer 600 is integrated into the phase-change memory cell, some phase-change memory chip structures provided in the embodiments of this disclosure are described exemplarily.

[0221] As an example, see Appendix Figure 9 The example illustrates a 1S1R type phase-change memory chip, which is disposed on a substrate 004. The 1S1R type phase-change memory chip includes multiple memory sub-cells 001, multiple word lines 002, and multiple bit lines 003. The multiple memory sub-cells 001 are arranged in an array, the multiple word lines 002 are arranged in rows, and the multiple bit lines 003 are arranged in columns. Each memory sub-cell 001 is connected to the bit line 003 of the corresponding column through its top electrode 501, and is connected to the word line 002 of the corresponding row through its bottom electrode 502.

[0222] Each storage sub-cell 001 includes a bottom electrode 502, a selection layer 600, an intermediate electrode 503, a barrier layer 300, a phase change material layer 100, a barrier layer 300, and a top electrode 501 arranged sequentially from bottom to top. Adjacent storage sub-cells 001 are isolated by insulating layers. Specifically, for each storage sub-cell 001, the outer surfaces of its barrier layer 300, phase change material layer 100, barrier layer 300, and top electrode 501 are sequentially covered by a first insulating layer 401 and a second insulating layer 402 from the inside to the outside, and the outer surfaces of its bottom electrode 502, selection layer 600, and intermediate electrode 503 are sequentially covered by a third insulating layer 403 and a fourth insulating layer 404 from the inside to the outside.

[0223] The phase change memory chip provided in Example 1 uses an improved phase change material in its phase change material layer 100 as provided in the above-disclosed embodiments, which can effectively improve the adhesion between the phase change material layer 100 and the barrier layer 300.

[0224] As an example two, see Appendix Figure 10 The example illustrates a 1S1R type phase-change memory chip, which is disposed on a substrate 004. The 1S1R type phase-change memory chip includes multiple memory sub-cells 001, multiple word lines 002, and multiple bit lines 003. The multiple memory sub-cells 001 are arranged in an array, the multiple word lines 002 are arranged in rows, and the multiple bit lines 003 are arranged in columns. Each memory sub-cell 001 is connected to the bit line 003 of the corresponding column through its top electrode 501, and is connected to the word line 002 of the corresponding row through its bottom electrode 502.

[0225] Each storage sub-unit 001 includes a bottom electrode 502, a gate layer 600, an intermediate electrode 503, a barrier layer 300, an adhesion layer 200, a phase change material layer 100, an adhesion layer 200, a barrier layer 300, and a top electrode 501 arranged sequentially from bottom to top. Adjacent storage sub-units 001 are isolated by insulating layers. Specifically, for each storage sub-unit 001, the outer surfaces of its barrier layer 300, adhesion layer 200, phase change material layer 100, adhesion layer 200, barrier layer 300, and top electrode 501 are sequentially covered by a first insulating layer 401 and a second insulating layer 402 from the inside to the outside, and the outer surfaces of its bottom electrode 502, gate layer 600, and intermediate electrode 503 are sequentially covered by a third insulating layer 403 and a fourth insulating layer 404 from the inside to the outside.

[0226] The phase change memory chip provided in Example 2 has, on the one hand, a phase change material layer 100 using the improved phase change material provided in the above-disclosed embodiments, and on the other hand, an adhesion layer 200 is added between the phase change material layer 100 and the barrier layer 300, which can further enhance the adhesion between the phase change material layer 100 and the barrier layer 300.

[0227] As an example three, see Appendix Figure 11 The example illustrates a 1S1R type phase-change memory chip, which is disposed on a substrate 004. The 1S1R type phase-change memory chip includes multiple memory sub-cells 001, multiple word lines 002, and multiple bit lines 003. The multiple memory sub-cells 001 are arranged in an array, the multiple word lines 002 are arranged in rows, and the multiple bit lines 003 are arranged in columns. Each memory sub-cell 001 is connected to the bit line 003 of the corresponding column through its top electrode 501, and is connected to the word line 002 of the corresponding row through its bottom electrode 502.

[0228] Each storage sub-cell 001 includes a bottom electrode 502, a gate layer 600, an intermediate electrode 503, a barrier layer 300, a phase change material layer 100, an adhesion layer 200, a barrier layer 300, and a top electrode 501 arranged sequentially from bottom to top. Adjacent storage sub-cells 001 are isolated by insulating layers. Specifically, for each storage sub-cell 001, the outer surfaces of its barrier layer 300, phase change material layer 100, adhesion layer 200, barrier layer 300, and top electrode 501 are sequentially covered by a first insulating layer 401 and a second insulating layer 402 from the inside to the outside, and the outer surfaces of its bottom electrode 502, gate layer 600, and intermediate electrode 503 are sequentially covered by a third insulating layer 403 and a fourth insulating layer 404 from the inside to the outside.

[0229] The phase change memory chip provided in Example 3 has, on the one hand, a phase change material layer 100 using the improved phase change material provided in the above-disclosed embodiments, and on the other hand, an adhesion layer 200 is added to the side of the phase change material layer 100 near the top electrode 501, which can further enhance the adhesion between the phase change material layer 100 and the barrier layer 300.

[0230] Of course, the phase change memory chip provided in Example 3 can also have an adhesion layer 200 added to the side of the phase change material layer 100 near the gate layer 600 to increase the bonding force between the phase change material layer 100 and the barrier layer 300 on the side near the gate layer 600.

[0231] As an example four, see Appendix Figure 12 The example illustrates a 1S1R type phase-change memory chip, which is disposed on a substrate 004. The 1S1R type phase-change memory chip includes multiple memory sub-cells 001, multiple word lines 002, and multiple bit lines 003. The multiple memory sub-cells 001 are arranged in an array, the multiple word lines 002 are arranged in rows, and the multiple bit lines 003 are arranged in columns. Each memory sub-cell 001 is connected to the bit line 003 of the corresponding column through its top electrode 501, and is connected to the word line 002 of the corresponding row through its bottom electrode 502.

[0232] Each storage sub-unit 001 includes a bottom electrode 502, a gate layer 600, an intermediate electrode 503, an adhesion layer 200, a phase change material layer 100, an adhesion layer 200, and a top electrode 501 arranged sequentially from bottom to top. Adjacent storage sub-units 001 are isolated by insulating layers. Specifically, for each storage sub-unit 001, the outer surfaces of its adhesion layer 200, phase change material layer 100, adhesion layer 200, and top electrode 501 are sequentially covered by a first insulating layer 401 and a second insulating layer 402 from the inside to the outside, and the outer surfaces of its bottom electrode 502, gate layer 600, and intermediate electrode 503 are sequentially covered by a third insulating layer 403 and a fourth insulating layer 404 from the inside to the outside.

[0233] The phase change memory chip provided in Example 4 has, on the one hand, a phase change material layer 100 using the improved phase change material provided in the above-disclosed embodiments, and on the other hand, an adhesion layer 200 is added between the phase change material layer 100 and the electrode layer, which can further enhance the adhesion between the phase change material layer 100 and the electrode layer.

[0234] This disclosure, in conjunction with any of the phase change materials mentioned above, provides an exemplary description of the structural arrangement and fabrication process of some 1S1R type phase change memory chips.

[0235] As an example (1), a 1S1R type phase-change memory chip is provided, which is arranged on a silicon oxide substrate 004. The 1S1R type phase-change memory chip includes multiple memory sub-cells 001, multiple word lines 002, and multiple bit lines 003, as shown in the attached figure. Figure 9 As shown, each storage sub-cell 001 includes a bottom electrode 502, a gate layer 600, an intermediate electrode 503, a barrier layer 300, a phase change material layer 100, a barrier layer 300, and a top electrode 501, stacked sequentially from bottom to top. Adjacent storage sub-cells 001 are isolated by an insulating layer. Multiple storage sub-cells 001 are arranged in an array, multiple word lines 002 are arranged in rows, and multiple bit lines 003 are arranged in columns. Each storage sub-cell 001 is connected to the bit line 003 of the corresponding column through its top electrode 501, and connected to the word line 002 of the corresponding row through its bottom electrode 502.

[0236] For example, word line 002 and bit line 003 are both made of tungsten (W), top electrode 501, bottom electrode 502, and intermediate electrode 503 are all made of carbon (C), and barrier layer 300 is made of tungsten (W). The gate material used in gate layer 600 is currently commercially available SiGeAsSe gate material. The phase change material of phase change material layer 100 can be the phase change material described in the first embodiment above.

[0237] The fabrication process of the 1S1R type phase-change memory chip is as follows:

[0238] As attached Figure 14 As shown, a thin-film precursor for a phase-change memory chip is provided. The thin-film precursor includes, from bottom to top, a substrate 004, a word line 002 layer, a bottom electrode 502, a gate layer 600, an intermediate electrode 503, a barrier layer 300, a phase-change material layer 100, a top electrode 501, and a mask layer 005. The mask layer 005 primarily protects the underlying material layers from the influence of etching and other processes.

[0239] As attached Figure 15 As shown, a first patterning process is performed on the thin film precursor to form a first trench 701. The first patterning process includes photolithography and etching. In the vertical direction (i.e., Figure 15 In the Z-axis direction, the first trench 701 penetrates from top to bottom through the mask layer 005, the top electrode 501, the barrier layer 300, the phase change material layer 100, and the barrier layer 300 to expose the intermediate electrode 503. In the first horizontal direction (i.e., Figure 15 In the X-axis direction, the first trench 701 is arranged in multiple intervals to form multiple first storage cell precursors.

[0240] As attached Figure 16As shown, insulating material is filled into the first trench 701 to form an insulating layer. This includes sequentially filling the first trench 701 with a first insulating material and a second insulating material. The first insulating material forms a first insulating layer 401 and covers the surface of the corresponding first memory cell precursor, while the second insulating material forms a second insulating layer 402 and covers the surface of the first insulating layer 401. The first insulating layer 401 is made of silicon nitride, and the second insulating layer 402 is made of silicon dioxide. Both materials prevent the phase change material layer 100 from being affected by subsequent etching processes.

[0241] As attached Figure 17 As shown, a second patterning process is then performed, causing the first trench 701 to extend downwards in the vertical direction to form a second trench 702. This second patterning process includes photolithography and etching.

[0242] In the vertical direction, the second trench 702 passes through the mask layer 005, top electrode 501, barrier layer 300, phase change material layer 100, barrier layer 300, intermediate electrode 503, gate layer 600, bottom electrode 502, and word line 002 from top to bottom. In the first horizontal direction, multiple second trenches 702 are arranged at intervals to form multiple second memory cell precursors.

[0243] As attached Figure 18 As shown, filling the second trench 702 with insulating material to form an insulating layer includes: sequentially filling the second trench 702 with a third insulating material and a fourth insulating material; the third insulating material forms a third insulating layer 403 and covers the surface of the corresponding second memory cell precursor; the fourth insulating material forms a fourth insulating layer 404 and covers the surface of the third insulating layer 403, resulting in an integral third memory cell precursor. The third insulating layer 403 is made of silicon nitride, and the fourth insulating layer 404 is made of silicon dioxide. Both provide insulation and mechanical support between different second memory cell precursors.

[0244] As attached Figure 19 As shown, the third memory cell precursor is polished to remove the mask layer 005 and expose the top electrode 501. Then, bit lines 003 and a new mask layer 005 are sequentially formed on the surface of the top electrode 501 to obtain an integral fourth memory cell precursor. The cross-sectional structure of the fourth memory cell precursor along the second horizontal direction is shown in the attached figure. Figure 20 As shown. The section along the second horizontal direction is also known as the attached section. Figure 19 The cross section shown by the dashed line AB, in the second horizontal direction, is... Figure 20 The Y-axis direction is perpendicular to the aforementioned X-axis direction.

[0245] As attached Figure 21As shown, a third patterning process is performed on the fourth memory cell precursor to form a third trench 703. This third patterning process includes photolithography and etching. In the vertical direction, the third trench 703 sequentially penetrates from top to bottom through the mask layer 005, bit line layer 003, top electrode 501, barrier layer 300, phase change material layer 100, and barrier layer 300 to expose the intermediate electrode 503. In the second horizontal direction, multiple third trenches 703 are arranged at intervals to form multiple fifth memory cell precursors.

[0246] As attached Figure 22 As shown, filling the third trench 703 with insulating material to form an insulating layer includes: sequentially filling the third trench 703 with a first insulating material and a second insulating material, the first insulating material forming a first insulating layer 401 and covering the corresponding surface of the fifth memory cell precursor, and the second insulating material forming a second insulating layer 402 and covering the surface of the first insulating layer 401, to obtain an integral sixth memory cell precursor.

[0247] Further details are attached. Figure 22 As shown, the sixth memory cell precursor undergoes a fourth patterning process, causing the third trench 703 to extend downwards in the vertical direction to form a fourth trench. This fourth patterning process includes photolithography and etching. In the vertical direction, the fourth trench sequentially penetrates from top to bottom through the mask layer 005, bit line 003 layer, top electrode 501, barrier layer 300, phase change material layer 100, barrier layer 300, intermediate electrode 503, gate layer 600, and bottom electrode 502 to expose the word line 002. In the second horizontal direction, multiple fourth trenches are arranged at intervals to form multiple seventh memory cell precursors.

[0248] As attached Figure 22 As shown, filling the fourth trench with insulating material to form an insulating layer includes: sequentially filling the fourth trench with a third insulating material and a fourth insulating material, the third insulating material forming a third insulating layer 403 and covering the corresponding surface of the seventh memory cell precursor, and the fourth insulating material forming a fourth insulating layer 404 and covering the surface of the third insulating layer 403, to obtain an integrated eighth memory cell precursor.

[0249] As attached Figure 23 As shown, the eighth memory cell precursor is polished to remove the third insulating layer 403 and the fourth insulating layer 404 above the mask layer 005 and the bit line 003, so as to expose the bit line 003, thereby preparing the phase change memory chip provided in Example 1.

[0250] The phase change memory chip provided in Embodiment 1 effectively improves the bonding force between the phase change material layer 100 and the barrier layer 300 by improving the phase change material, preventing the peeling and falling off between layers and resulting in a decrease in the yield of the phase change memory chip. At the same time, the improved phase change material still helps the phase change memory chip to have advantages such as a large read window, low latency, and high lifetime characteristics.

[0251] For the phase change memory chips involved in this type of example, the bonding force between the phase change material layer 100 and the barrier layer 300 is effectively improved by improving the phase change material, preventing the peeling and falling off between layers and resulting in a decrease in the yield of the phase change memory chip. At the same time, the improved phase change material still helps the phase change memory chip to have advantages such as a large read window and high lifetime characteristics.

[0252] As Example (2), a type of 1S1R phase change memory chip is provided. The 1S1R phase change memory chip involved in this type of example includes multiple memory sub-units 001, multiple word lines 002, and multiple bit lines 003. As shown in the attached Figure 10 figure, each memory sub-unit 001 includes a bottom electrode 502, a select layer 600, an intermediate electrode 503, a barrier layer 300, an adhesion layer 200, a phase change material layer 100, an adhesion layer 200, a barrier layer 300, and a top electrode 501, which are stacked in sequence from bottom to top. The adjacent memory sub-units 001 are isolated by an insulating layer. Compared with Example (1), an adhesion layer 200 is added in the memory sub-unit 001, and the arrangement of other layers is the same. Exemplarily, the thickness of the adhesion layer 200 can be 2 nm, and the material of the adhesion layer 200 can be WN or InGeSbTe. Among them, WN can be W2N, WN, WN2, or any component satisfying the following general formula: W x N 1-x , where x is the atomic percentage, and 0 < x < 1. The InGeSbTe compound can be, for example, In3%-Ge2Sb2Te5, that is, the atomic percentage of In is 3%, and in the GeSbTe phase change base material, the ratio of the atomic percentage contents of Ge, Sb, and Te is 2:2:5.

[0253] The preparation process of the phase change memory chip involved in this type of Example (2) can refer to the above Example (1), except that when forming the memory sub-unit 001, the adhesion layer 200 is formed at a specific position.

[0254] The phase-change memory chip in this example (2) improves the phase-change material by modifying the phase-change material and by adding an adhesion layer 200 between the phase-change material layer 100 and the barrier layer 300, thereby effectively enhancing the bonding force between them. Furthermore, since the total thickness of the two adhesion layers 200 is only 4 nm, which is only one-tenth the thickness of the phase-change material layer 100, it has a relatively small impact on the performance of the phase-change material layer 100.

[0255] As an example (3), a type 1S1R phase-change memory chip is provided. Its structure and fabrication process are described in Example (1). The difference between this chip and the phase-change memory chip in Example (1) is: see [link to example (3)] Figure 12 The barrier layer 300 in Example 1 is directly replaced with the adhesion layer 200. That is, an adhesion layer 200 is directly provided between the phase change material layer 100 and the top electrode 501, and between the phase change material layer 100 and the intermediate electrode 503.

[0256] The phase change memory chip involved in this type of example (3) improves the phase change material on the one hand, and increases the bonding force between the phase change material layer 100 and the electrode layer by adding an adhesion layer 200 between the phase change material layer 100 and the electrode layer on the other hand.

[0257] As an example (4), a type 1S1R phase change memory chip is provided. Its structure and fabrication process can be referred to in example (1). The difference between the phase change memory chip in example (1) is that the doping elements in the phase change material used in the phase change material layer 100 are limited to Hf and In elements.

[0258] As an example (5), a type 1S1R phase change memory chip is provided. Its structure and fabrication process can be referred to in example (1). The difference between the phase change memory chip in example (1) and the phase change material layer 100 is that the phase change material can be the phase change material involved in the second embodiment above.

[0259] For the 1S1R type phase change memory chip involved in Example (5), the latency, lifetime, high and low resistance characteristics of those phase change memory chips in which the atomic percentage of each atom in the Ge-Sb-Te phase change substrate is Ge:Sb:Te = 1:4:7 (abbreviated as GST147) were tested. The test results are shown in Table 5. In Table 5, NA refers to data that has no meaning.

[0260] Table 5

[0261]

[0262] Experiments have shown that when the atomic percentage of Sb in the Ge-Sb-Te phase change substrate is greater than 35% and less than 45%, the latency of the phase change memory chip can reach below 100 ns. When the atomic percentage of Sb in the Ge-Sb-Te phase change substrate exceeds 45%, the lifetime of the phase change memory chip is reduced to some extent. When the atomic percentage of Ge is greater than 15%, the latency of the phase change memory chip slows down to some extent. When the atomic percentage of Ge is less than 6%, the adhesion of the phase change material layer is reduced.

[0263] As shown in Table 5, the sum of the atomic percentages of Hf and N elements is greater than 4%, which is essential for imparting long-lifetime characteristics to phase-change memory chips. When the atomic percentage of Hf is 6.5% and the atomic percentage of N is 5%, the low resistance increases abnormally and the chip becomes unstable during cycling because the sum of their atomic percentages is greater than 10%.

[0264] As shown in Table 5, when the atomic percentage of Hf is 8%, the high resistance of the phase-change memory chip decreases, but it becomes unstable during cycling. When the atomic percentage of N is 8%, the low resistance of the phase-change memory chip increases, but it becomes unstable during cycling.

[0265] The phase-change memory chip provided in this disclosure has the potential to replace solid-state drives (SSDs) based on its high speed, high density and non-volatile characteristics. If the operating speed is further improved, it has the potential to be applied to universal memory, combining the functions of memory and external storage.

[0266] In another aspect, this disclosure also provides a storage device, which includes a controller and any of the phase-change memory chips described above. The controller is used to store data to the phase-change memory chip, wherein the controller reads and writes the data stored in the storage device and interacts and communicates with an external interface.

[0267] This storage device (also known as a memory) can be configured to store various types of data, such as contact data, phone book data, messages, pictures, videos, and instruction data.

[0268] The storage devices involved in the embodiments of this disclosure can be configured as various types, such as, but not limited to, memory, hard disk, magnetic disk, optical disk, etc.

[0269] This disclosure also provides an electronic device, which includes a processor and the aforementioned storage device, wherein the processor is used to store data generated by the electronic device to the storage device.

[0270] In some examples, the electronic device includes, but is not limited to: computers, mobile phones, music playback devices, digital broadcasting devices, messaging devices, game control devices, medical devices, fitness equipment, personal digital assistants, etc.

[0271] The above description is only for the purpose of enabling those skilled in the art to understand the technical solutions disclosed herein, and is not intended to limit the scope of this disclosure. Any modifications, equivalent substitutions, improvements, etc., made within the spirit and principles of this disclosure should be included within the protection scope of this disclosure.

Claims

1. A phase change material, characterized in that, The phase change material includes: Ge-Sb-Te phase change substrate; First doping element; Second doping element; Wherein, the first doping element and the second doping element are doped in the Ge-Sb-Te phase change substrate; The first doping element includes Hf, accounting for 1.5%-6.5% of the atomic percentage of the phase change material; The second doping element includes at least one of N and C elements, or at least one of In and Ga elements, accounting for 1.0%-5% of the atomic percentage of the phase change material.

2. The phase change material according to claim 1, characterized in that, The phase change material further includes a third doping element, which includes at least one of the following elements: O, Si, B, Sn, Bi, Cd, Pb, Zr, Zn, Cr, Al, Sc, Y, Ta, Ti, Er, Lu, Ho, Tm, Dy, Tb, Ca, Nd, Pr, Yb, and Ce.

3. The phase change material according to any one of claims 1-2, characterized in that, The chemical general formula of the Ge-Sb-Te phase change substrate is as follows: (GeTe 1-a ) x (Sb2Te 3-b ) 1-x , where x is the atomic percentage and 0 < x < 1, a and b are parameters related to the atomic number ratio, 0 < a ≤ 1, 0 < b ≤ 3, and a = 1 and b = 3 do not exist simultaneously; Alternatively, (GeTe 1-c ) x (Sb y Te 1-d ) 1-x , where x is the atomic percentage and 0 < x < 1, y, c, and d are parameters related to the atomic number ratio, y ≥ 2, 0 < c ≤ 1, 0 < d ≤ 1, and c = 1 and d = 1 do not exist simultaneously.

4. A phase change material, characterized in that, The phase change material includes a Ge-Sb-Te phase change substrate, a first doping element and a second doping element doped in the Ge-Sb-Te phase change substrate; The first doping element includes Hf, and the first doping element accounts for 1.5%-7% of the atomic percentage of the phase change material; The second doping element includes at least one of N, C, In, and Ga, and the second doping element accounts for 1.0%-7% of the atomic percentage of the phase change material. The sum of the atomic percentages of the first dopant element and the second dopant element is greater than 4% and less than 10%.

5. The phase change material according to claim 4, characterized in that, The phase change material further includes a third doping element, which includes at least one of the following elements: O, Si, B, Sn, Bi, Cd, Pb, Zr, Zn, Cr, Al, Sc, Y, Ta, Ti, Er, Lu, Ho, Tm, Dy, Tb, Ca, Nd, Pr, Yb, and Ce.

6. The phase change material according to any one of claims 4-5, characterized in that, The chemical general formula of the Ge-Sb-Te phase change substrate is as follows: (GeTe 1-a ) x (Sb2Te 3-b ) 1-x , where x is the atomic percentage and 0 < x < 1, a and b are parameters related to the atomic number ratio, 0 < a ≤ 1, 0 < b ≤ 3, and a = 1 and b = 3 do not exist simultaneously; Alternatively, (GeTe 1-c ) x (Sb y Te 1-d ) 1-x , where x is the atomic percentage and 0 < x < 1, y, c, and d are parameters related to the atomic number ratio, y ≥ 2, 0 < c ≤ 1, 0 < d ≤ 1, and c = 1 and d = 1 do not exist simultaneously.

7. The phase change material according to claim 6, characterized in that, The chemical general formula of the Ge-Sb-Te phase change substrate is as follows: (GeTe 1-a ) x (Sb2Te 3-b ) 1-x , and 0.2 < x ≤ 0.4, or, (GeTe 1-c ) x (Sb y Te 1-d ) 1-x , and 0.2 < x ≤ 0.

4.

8. A phase-change memory chip, characterized in that, The phase change memory chip includes: a plurality of phase change memory cells, each phase change memory cell including a phase change material layer, the phase change material layer being prepared from the phase change material according to any one of claims 1-3, or the phase change material layer being prepared from the phase change material according to any one of claims 4-7.

9. The phase-change memory chip according to claim 8, characterized in that, The phase change storage unit further includes an adhesion layer, which is stacked on at least one surface of the phase change material layer and is used to increase the adhesion between the phase change material layer and adjacent functional layers.

10. The phase-change memory chip according to claim 9, characterized in that, The adhesive layer material used in the adhesive layer includes at least one of the nitride of the target element and the carbide of the target element; The target element is selected from at least one of the elements W, Ti, Ge, Ta, Hf, In, Ga, Al, Cu, Co, and Mo.

11. The phase-change memory chip according to claim 9, characterized in that, The adhesive layer material used includes a Ge-Sb-Te phase change material doped with a fourth doping element, and the adhesive layer material is different from the phase change material. The fourth doping element is selected from at least one of Hf, N, C, In, and Ga, and the fourth doping element accounts for 0.01%-20% of the atomic percentage of the adhesive layer material.

12. The phase-change memory chip according to claim 9, characterized in that, The phase change storage unit further includes a barrier layer, and the adhesion layer is located between the phase change material layer and the barrier layer to increase the adhesion between the phase change material layer and the barrier layer.

13. The phase-change memory chip according to claim 12, characterized in that, The barrier layer material used includes at least one of the following elements: W, Ti, Ge, Ta, Hf, In, Ga, Al, Cu, Co, and Mo, as well as their nitrides and carbides.

14. The phase-change memory chip according to claim 9, characterized in that, The phase change storage unit further includes an electrode layer, and the adhesion layer is located between the phase change material layer and the electrode layer to increase the adhesion between the phase change material layer and the electrode layer.

15. The phase-change memory chip according to any one of claims 8-14, characterized in that, The phase-change memory chip further includes: a plurality of gate transistor units, wherein the gate transistor units are arranged in series with the phase-change memory units; The gate tube unit includes a gate layer, and the gate tube material used in the gate layer includes at least one of S-based gate tube material, Se-based gate tube material, and Te-based gate tube material.

16. The phase-change memory chip according to claim 15, characterized in that, The gate material further includes a fifth doping element, which is selected from at least one of the following elements: B, Al, Ga, In, C, Si, Ge, Sn, N, P, As, Sb, Bi, O, Au, Hf, Pd, Cu, Co, Ag, Pt, Sc, Ti, and Ta.

17. A storage device, characterized in that, The storage device includes a controller and at least one phase-change memory chip as described in any one of claims 8-16, wherein the controller is used to store data to the phase-change memory chip.

18. An electronic device, characterized in that, The electronic device includes a processor and the storage device of claim 17, wherein the processor is used to store data generated by the electronic device to the storage device.

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