Testing methods, testing apparatus, host computer, chips and equipment for chips.

Abstract

This application provides a testing method, testing apparatus, host computer, chip, and device for chip testing. The method may include: obtaining a test circuit constructed according to the requirements of a hot-swap test bench, the test circuit including at least one battery module and at least one chip; connecting the at least one chip to the at least one battery module; and testing the functionality of the at least one chip.

Description

Technical Field

[0001] This application relates to the field of battery management technology, and in particular to a testing method, testing apparatus, host computer, chip and device for chips. Background Technology

[0002] Energy conservation and emission reduction are key to the sustainable development of the automotive industry, and electric vehicles, due to their energy-saving and environmentally friendly advantages, have become an important component of this sustainable development. For electric vehicles, battery technology is a crucial factor in their development.

[0003] In the field of battery management, various chips are often used to sample batteries and collect their various states. However, the chips used in battery management frequently face scenarios involving hot-swapping or hot-plugging, which poses a more severe challenge to their voltage withstand performance. Therefore, an effective solution for testing these chips is desired. Summary of the Invention

[0004] This application aims to address at least one of the technical problems existing in the prior art. Therefore, one objective of this application is to provide a testing method, testing apparatus, host computer, chip, and device for chips, so as to effectively test chip performance.

[0005] An embodiment of the first aspect of this application provides a testing method for a chip, comprising: determining a configuration mode of a test circuit, the test circuit including at least one chip and at least one battery module, the at least one chip being connectable to the at least one battery module according to the configuration mode; connecting the at least one chip to the at least one battery module based on at least one operating condition corresponding to the configuration mode; determining whether an operation termination condition is met; and testing the performance of the at least one chip in response to determining that the operation termination condition is met.

[0006] The technical solution of this application embodiment proposes a standard hot-swap test equipment solution, which standardizes hot-swap testing. In practical applications, it can reduce the differences in testing between different chip manufacturers and achieve standardized and regulated chip testing.

[0007] In some embodiments, the test circuit further includes a switch matrix located between the at least one chip and the at least one battery module, the switch matrix being capable of connecting the at least one chip to the at least one battery module according to the configuration mode, wherein connecting the at least one chip to the at least one battery module includes performing a closing operation for closing at least two switches in the switch matrix.

[0008] According to this embodiment, chip testing can be performed flexibly based on a switch matrix, avoiding complex manual insertion and removal processes, flexibly simulating required scenarios and operating conditions, and accurately, quickly, and more closely resembling real-world application conditions to test the hot-swap functionality of the AFE.

[0009] In some embodiments, at least one chip includes a first chip, at least one battery module includes a first battery module, and the hot-swap test bench requires to include a first configuration mode, the first configuration mode indicating that the first chip is configured to be connected to a corresponding switch of a switch matrix, such that when the corresponding switch is turned on, the sampling channel line of the first chip can be connected to the corresponding sampling lead of the first battery module respectively.

[0010] According to this embodiment, standardized usage scenario-based testing can be achieved. In particular, by making the circuit configuration for testing approximate the chip's usage scenario, common chip usage scenarios can be simulated, thus obtaining more reliable test results.

[0011] In some embodiments, in response to determining that the test circuit is constructed according to the first configuration mode, performing the closing operation includes: closing a pair of switches corresponding to a pair of sampling channel lines when none of the switches corresponding to the other sampling channel lines in the first chip, except for the pair of sampling channel lines associated with the maximum battery potential difference, are closed.

[0012] According to this embodiment, the operating conditions that may occur in the simulated usage scenario can be further tested. In particular, by making the test conditions correspond to the circuit configuration mode, that is, simulating common operating conditions corresponding to the current usage scenario of the chip, realistic and reliable test results can be obtained. According to this embodiment, the maximum voltage difference on the chip can be created by first closing the switch of a pair of sampling channel lines associated with the maximum battery potential difference. Therefore, according to this embodiment, simulating the worst operating conditions is more helpful for chip functional testing, and the chip obtained after such testing will have satisfactory reliability even when dealing with extreme operating conditions.

[0013] In some embodiments, in response to determining that the test circuit is constructed according to the first configuration mode, performing the closing operation further includes: after a pair of switches corresponding to a pair of sampling channel lines are closed, causing switches corresponding to the remaining sampling channel lines in the first chip to be closed randomly.

[0014] According to this embodiment, for the simulated usage scenario, further testing can be performed on the operating conditions that may occur in the application scenario. By simulating common operating conditions corresponding to the chip's usage scenario, realistic and reliable test results can be obtained. Specifically, by simulating the most severe operating condition where both ends are closed first, and then randomly closing the remaining switches, not only severe operating conditions can be covered, but also other common insertion and removal conditions. In addition, using random closing logic makes the simulation results more realistic and comprehensive.

[0015] In some embodiments, in response to determining that the test circuit is constructed according to the first configuration mode, performing the closing operation includes: causing the switch corresponding to the sampling channel line of the first chip to close randomly.

[0016] According to this embodiment, more common insertion and removal conditions can be simulated by randomly closing the switches corresponding to all sampling channel lines for the simulated usage scenario, thereby making the simulation results more realistic and comprehensive, and thus obtaining a reliable chip and reducing possible failures during chip use.

[0017] In some embodiments, at least one chip includes a first chip, and at least one battery module includes at least two battery modules connected in series. The hot-swap test bench requires a second configuration mode, which means that the first chip is configured to be connected to a corresponding switch in a switch matrix such that when the corresponding switch is turned on, the sampling channel line of the first chip can be connected to the corresponding sampling leads of the at least two battery modules respectively.

[0018] According to such an embodiment, standardized usage scenario-based testing can be achieved, covering scenarios where the number of sampling channel lines of the first chip is greater than the number of sampling leads of a single battery module or other scenarios where one chip can be used to sample two or more batteries, thereby achieving realistic and reliable simulation and testing of such common usage scenarios.

[0019] In some embodiments, in response to determining that the test circuit is in a second configuration mode, performing a closing operation includes: closing the switches corresponding to the sampling leads of the remaining battery modules (excluding the positive-side battery module) in the at least two battery modules when none of the switches corresponding to the sampling leads of the sampling leads of the remaining battery modules are closed; and closing the switch corresponding to the sampling lead of the positive-side battery module associated with the highest battery potential after a first time delay following the closure of the switches corresponding to the sampling leads of the remaining battery modules.

[0020] According to such an embodiment, the operating conditions that may occur in the simulated application scenario can be further tested. It is possible to simulate a relatively harsh operating condition for a scenario in which a chip is connected to two or more battery modules, thereby improving the reliability of the chip obtained through such testing method.

[0021] In some embodiments, performing the closing operation further includes: after the switch corresponding to the sampling lead associated with the highest battery potential is closed, causing the switches corresponding to the remaining sampling leads of the positive electrode side battery module, other than the sampling lead associated with the highest battery potential, to be closed randomly.

[0022] According to this embodiment, for the simulated usage scenario, further testing can be performed on the operating conditions that may occur in the application scenario, and by using random closed-loop logic, the simulation results can be made more realistic and comprehensive. Specifically, for the first simulated operating condition of the second example scenario, the risks that sampling channel lines other than the sampling channel line that will bear the maximum voltage difference can also be simulated, thereby enabling risk testing and evaluation of each sampling channel line of the chip and the corresponding circuit parts, and obtaining more reliable test results.

[0023] In some embodiments, in response to determining that the test circuit is in a second configuration mode, performing a closing operation includes: closing the switches corresponding to the sampling leads of the remaining battery modules (excluding the negative-side battery modules) in the at least two battery modules when none of the switches corresponding to the sampling leads of the sampling leads of the remaining battery modules are closed; and closing the switch corresponding to the sampling lead of the negative-side battery module associated with the lowest battery potential after a second time delay following the closure of the switches corresponding to the sampling leads of the remaining battery modules.

[0024] According to this embodiment, a different, relatively harsh operating condition can be simulated for a second scenario in which a chip is connected to two or more battery modules.

[0025] In some embodiments, performing the closing operation further includes: after the switch corresponding to the sampling lead associated with the lowest battery potential is closed, causing the switches corresponding to the remaining sampling leads of the negative electrode side battery module, other than the sampling lead associated with the lowest battery potential, to be closed randomly.

[0026] According to this embodiment, for the simulated usage scenario, further testing can be performed on the operating conditions that may occur in the application scenario, and by using random closed-loop logic, the simulation results can be made more realistic and comprehensive. Specifically, for the second simulated operating condition of the second example scenario, the risks that sampling channel lines other than the sampling channel line that will bear the maximum voltage difference can also be simulated to obtain more reliable test results.

[0027] In some embodiments, at least one chip includes a first chip and a second chip, at least one battery module includes a first battery module, and obtaining a test circuit built according to the requirements of a hot-swap test bench includes determining that the test circuit is built according to the third configuration mode, the third configuration mode indicating that the first chip and the second chip are configured to be connected to corresponding switches in a switch matrix, such that when the corresponding switches are turned on, the first chip and the second chip can be connected to the corresponding sampling leads of the first battery module.

[0028] According to such an embodiment, it is possible to cover scenarios where the number of sampling channel lines of the first chip is less than the number of sampling leads of a single battery module or where two or more other chips can be used to sample a single battery, thereby achieving a realistic and reliable simulation and test of such a common use case.

[0029] In some embodiments, the first sampling channel line of the first chip and the second sampling channel line of the second chip can be connected to adjacent first and second sampling leads of the first battery module, and the third sampling channel line of the first chip and the fourth sampling channel line of the second chip can be connected to the third and fourth sampling leads of the first battery module associated with the maximum battery potential difference. In response to determining that the test circuit is constructed according to the third configuration mode, the closing operation includes: closing the switches corresponding to the first and second sampling channel lines when none of the switches corresponding to the other sampling channel lines of the first and second chips (excluding the first and second sampling channel lines) are closed; and closing the switches corresponding to the third and fourth sampling channel lines after a third time delay following the closure of the switches corresponding to the first and second sampling channel lines.

[0030] According to this embodiment, by simulating harsh scenarios, the test results and the reliability of the tested chips can be improved, and the chips obtained after such testing will have satisfactory reliability even when dealing with extreme operating conditions.

[0031] In some embodiments, performing the closing operation further includes: after the switch corresponding to the third sampling channel line and the switch corresponding to the fourth sampling channel line are closed, causing the switches corresponding to the remaining sampling channel lines of the first chip and the second chip, excluding the first sampling channel line, the second sampling channel line, the third sampling channel line and the fourth sampling channel line, to be closed randomly.

[0032] According to this embodiment, the simulated usage scenarios can be further tested for the operating conditions that may occur in the application scenario; using random closed-loop logic makes the simulation results more realistic and comprehensive. In other words, for the first simulated operating condition of the third example scenario, the risks that sampling channel lines other than the sampling channel line that will bear the maximum voltage difference can also be simulated to comprehensively test the chip's withstand capability.

[0033] In some embodiments, in response to determining that the test circuit is constructed according to the third configuration mode, performing a closing operation includes: causing the switches corresponding to the sampling channel lines of the first chip and the second chip to close randomly.

[0034] According to this embodiment, in addition to the worst-case scenario provided, other more common operating conditions in practice can be simulated during testing. This embodiment can cover other common plug-in / plug-out conditions. Furthermore, using randomized closed-loop logic makes the simulation results more realistic, thereby obtaining reliable and comprehensive test results.

[0035] In some embodiments, the first sampling channel line of the first chip and the second sampling channel line of the second chip can be connected to adjacent first and second sampling leads of the first battery module, the third sampling channel line of the first chip and the fourth sampling channel line of the second chip can be connected to the third and fourth sampling leads of the first battery module associated with the maximum battery potential difference, and the third configuration mode further indicates that the first sampling channel line and the second sampling channel line are electrically connected.

[0036] According to this embodiment, it is possible to further consider example scenarios in which the chip is pre-shorted, thereby more comprehensively covering the scenarios that the chip may face, and thus obtaining reliable test results.

[0037] In some embodiments, in response to determining that the test circuit is constructed according to the third configuration mode, performing a closing operation includes: closing the switch corresponding to the sampling channel line of the second chip when none of the switches corresponding to the sampling channel line of the first chip are closed; and closing the switch corresponding to the third sampling channel line after a third time delay following the closing of the switch corresponding to the sampling channel line of the second chip.

[0038] According to this embodiment, it is possible to simulate the harsh operating conditions that the chip can withstand during hot-plugging with the chip shorted, thereby obtaining reliable test results.

[0039] In some embodiments, performing the closing operation further includes: after the switch corresponding to the third sampling channel line is closed, causing the switches corresponding to the other sampling channel lines of the first chip, excluding the third sampling channel line, to be closed randomly.

[0040] According to this embodiment, other common insertion and removal conditions and various sampling channel lines can be covered, thereby enabling risk testing and evaluation of each sampling channel line of the chip and the corresponding circuit parts, and obtaining more reliable test results.

[0041] In some embodiments, the operation termination condition includes at least one of the following: the number of times a closing operation is executed for at least one chip reaches a first threshold, or the number of times a closing operation is executed based on a specific configuration mode reaches a second threshold for a specific configuration mode.

[0042] According to this embodiment, by defining the termination conditions, the testing of chips can be further standardized.

[0043] In some embodiments, the testing method further includes, in response to determining that an operation termination condition has not been met: performing a power-off operation on the at least one chip; discharging a capacitor in the at least one chip; and repeatedly performing a closing operation for closing at least two switches in the switch matrix and testing the functionality of the at least one chip, wherein the operation termination condition includes at least one of the following: the number of times the closing operation for the at least one chip is performed reaches a first threshold, or the number of times the operation is performed for each of the at least one operating conditions reaches a second threshold for that operating condition.

[0044] According to this embodiment, the influence of capacitor charge can be reduced, resulting in more realistic test results.

[0045] In some embodiments, the testing method further includes: in response to the step of determining that the at least one chip is connected to the at least one battery module being performed for the first time, adjusting the individual cell voltage of the battery in the at least one battery module to a specified value before testing the function of the at least one chip. According to such an embodiment, the stability of the test can be ensured.

[0046] In some embodiments, the testing method further includes testing the functionality of the at least one chip by performing a power supply voltage range test on the at least one chip.

[0047] An embodiment of the second aspect of this application provides a testing apparatus for a chip, comprising: at least one battery module; a switch matrix; and a host computer, the host computer being capable of controlling the operation of at least one switch in the switch matrix, wherein the switch matrix is ​​configured to connect at least one chip to at least one battery module, and the host computer is configured to perform a method according to an embodiment of this application.

[0048] In some embodiments, the testing apparatus further includes at least one discharge unit, which, when turned on, is capable of discharging a corresponding capacitor in at least one chip.

[0049] According to this embodiment, the influence of capacitor charge can be reduced, resulting in more realistic test results.

[0050] An embodiment of the third aspect of this application provides a host computer capable of controlling the operation of at least one switch in a switch matrix, the switch matrix being configured to connect at least one chip to at least one battery module, wherein the host computer is configured to perform a method according to an embodiment of this application.

[0051] An embodiment of the fourth aspect of this application provides a chip for a battery, the chip being tested according to the method of the embodiments of this application.

[0052] An embodiment of the fifth aspect of this application provides an electronic device, including: at least one processor; and a memory communicatively connected to the at least one processor; wherein the memory stores instructions executable by the at least one processor, the instructions being executed by the at least one processor to enable the at least one processor to perform the method of the embodiment of this application.

[0053] An embodiment of the sixth aspect of this application provides a non-transitory computer-readable storage medium storing computer instructions, wherein the computer instructions are used to cause a computer to perform a method according to an embodiment of this application.

[0054] The above description is only an overview of the technical solution of this application. In order to better understand the technical means of this application and to implement it in accordance with the contents of the specification, and to make the above and other objects, features and advantages of this application more obvious and understandable, the following are specific embodiments of this application. Attached Figure Description

[0055] In the accompanying drawings, unless otherwise specified, the same reference numerals throughout the various drawings denote the same or similar parts or elements. These drawings are not necessarily drawn to scale. It should be understood that these drawings depict only some embodiments disclosed in this application and should not be construed as limiting the scope of this application.

[0056] Figure 1 This is a schematic diagram of the vehicle structure according to some embodiments of this application;

[0057] Figure 2 This is an exploded structural diagram of a battery according to some embodiments of this application;

[0058] Figure 3 This is an exploded structural diagram of a battery cell according to some embodiments of this application;

[0059] Figure 4 This is a schematic flowchart illustrating a chip testing method according to some embodiments of this application;

[0060] Figure 5 This is a schematic diagram of the test circuit for some embodiments of this application;

[0061] Figure 6 This is a schematic diagram of the test circuit for some other embodiments of this application;

[0062] Figure 7 This is a schematic diagram of the test circuit for some other embodiments of this application;

[0063] Figure 8 This is a schematic diagram of a test circuit for some other embodiments of this application;

[0064] Figure 9 This is a schematic diagram of a test apparatus according to some embodiments of this application;

[0065] Figure 10 This is a schematic diagram of a computer device according to some embodiments of this application;

[0066] Figure 11 This is a schematic diagram of the test circuit for some other embodiments of this application;

[0067] Figure 12 This is a schematic diagram of the test circuit for some other embodiments of this application;

[0068] Figure 13 This is a schematic diagram of a test circuit for some other embodiments of this application;

[0069] Figure 14 This is a schematic diagram of a test circuit for yet another embodiment of this application.

[0070] Explanation of reference numerals in the attached figures:

[0071] 1000 vehicles;

[0072] Battery 100, controller 200, motor 300;

[0073] Box 10, Part 11, Part 2 12;

[0074] Battery cell 20, end cap 21, electrode terminal 21a, housing 22, cell assembly 23, tab 23a;

[0075] Test circuit 500, first battery module 510, switch matrix 520, first chip 530, sampling leads 510-1, 510-2, 510-3...510-N, switches 520-1, 520-2, 520-3...520-N, sampling channel lines 530-1, 530-2, 530-3...530-N;

[0076] The test circuit 600 includes a first battery module 611, a second battery module 612, a switch matrix 620, a first chip 630, sampling leads 610-1, 610-n, 610-(n+1)……610-N, switches 620-1, 620-n, 620-(n+1)……620-N, and sampling channel lines 630-1, 630-n, 630-(n+1)……630-N.

[0077] Test circuit 700, first battery module 710, switch matrix 720, first chip 731, second chip 732, sampling leads 710-1, 710-n, 710-(n+1)……710-N, switches 720-1, 720-n, 720-(n+1)……720-N, sampling channel lines 730-1, 730-n, 730-(n+1)……730-N;

[0078] Test circuit 800, first battery module 810, switch matrix 820, first chip 831, second chip 832, sampling leads 810-1, 810-n, 810-(n+1)……810-N, switches 820-1, 820-n, 820-(n+1)……820-N, sampling channel lines 830-1, 830-n, 830-(n+1)……830-N;

[0079] Test circuit 900, first battery module 910, switch matrix 920, first chip 930, host computer 940, sampling leads 910-1, 910-2, 910-3...910-N, switches 920-1, 920-2, 920-3...920-N, sampling channel lines 930-1, 930-2, 930-3...930-N;

[0080] 1000 electronic devices;

[0081] Test circuit 1100, at least one battery module 1110, switch matrix 1120, at least one chip 1130, host computer 1140, discharge unit 1150, chips 1131 and 1132, battery modules 1111 and 1112;

[0082] The test circuit 1200 includes at least one battery module 1210, a switch matrix 1220, at least one chip 1230, a host computer 1240, a discharge unit 1250, a chip 1231, and battery modules 1211 and 1212.

[0083] The test circuit 1300 includes at least one battery module 1210, a switch matrix 1320, at least one chip 1330, a host computer 1340, a discharge unit 1350, chips 1331 and 1332, and a battery module 1311.

[0084] The test circuit 1400 includes at least one battery module 1210, a switch matrix 1420, at least one chip 1430, a host computer 1440, a discharge unit 1450, chips 1431 and 1432, and a battery module 1411. Detailed Implementation

[0085] The embodiments of the technical solution of this application will now be described in detail with reference to the accompanying drawings. These embodiments are only used to more clearly illustrate the technical solution of this application and are therefore merely examples, and should not be used to limit the scope of protection of this application.

[0086] Unless otherwise defined, all technical and scientific terms used herein have the same meaning as commonly understood by one of ordinary skill in the art to which this application pertains; the terminology used herein is for the purpose of describing particular embodiments only and is not intended to limit the application; the terms “comprising” and “having”, and any variations thereof, in the specification, claims, and foregoing description of the drawings are intended to cover non-exclusive inclusion.

[0087] In the description of the embodiments of this application, technical terms such as "first" and "second" are used only to distinguish different objects and should not be construed as indicating or implying relative importance or implicitly specifying the number, specific order, or primary and secondary relationship of the indicated technical features. Throughout the different embodiments of this application, the objects described by "first," "second," etc., should not always be considered the same object. For example, a "first chip" described in one embodiment of this application may correspond to a "second chip" in another embodiment; a "first battery module" described in one embodiment of this application may correspond to a "second battery module" or a "third battery module" in another embodiment, and so on. In the description of the embodiments of this application, "multiple" means two or more, unless otherwise explicitly specified.

[0088] In this document, the term "embodiment" means that a particular feature, structure, or characteristic described in connection with an embodiment may be included in at least one embodiment of this application. The appearance of this phrase in various places throughout the specification does not necessarily refer to the same embodiment, nor is it a separate or alternative embodiment mutually exclusive with other embodiments. It will be explicitly and implicitly understood by those skilled in the art that the embodiments described herein can be combined with other embodiments.

[0089] In the description of the embodiments in this application, the term "and / or" is merely a description of the relationship between related objects, indicating that three relationships can exist. For example, A and / or B can represent: A existing alone, A and B existing simultaneously, and B existing alone. Additionally, the character " / " in this document generally indicates that the preceding and following related objects have an "or" relationship.

[0090] In the description of the embodiments of this application, the term "multiple" refers to two or more (including two), similarly, "multiple sets" refers to two or more (including two sets), and "multiple pieces" refers to two or more (including two pieces).

[0091] In the description of the embodiments of this application, the technical terms "center", "longitudinal", "lateral", "length", "width", "thickness", "upper", "lower", "front", "rear", "left", "right", "vertical", "horizontal", "top", "bottom", "inner", "outer", "clockwise", "counterclockwise", "axial", "radial", "circumferential", etc., indicate the orientation or positional relationship based on the orientation or positional relationship shown in the accompanying drawings. They are only for the convenience of describing the embodiments of this application and simplifying the description, and do not indicate or imply that the device or element referred to must have a specific orientation, or be constructed and operated in a specific orientation. Therefore, they should not be construed as limitations on the embodiments of this application.

[0092] In the description of the embodiments of this application, unless otherwise expressly specified and limited, the technical terms such as "installation," "connection," "joining," and "fixing" should be interpreted broadly. For example, they can refer to a fixed connection, a detachable connection, or an integral part; they can refer to a mechanical connection or an electrical connection; they can refer to a direct connection or an indirect connection through an intermediate medium; they can refer to the internal communication of two components or the interaction between two components. For those skilled in the art, the specific meaning of the above terms in the embodiments of this application can be understood according to the specific circumstances.

[0093] Currently, judging from market trends, the application of power batteries is becoming increasingly widespread. Power batteries are not only used in energy storage systems such as hydropower, thermal power, wind power, and solar power plants, but also extensively used in electric vehicles such as electric bicycles, electric motorcycles, and electric cars, as well as in military equipment and aerospace. With the continuous expansion of power battery applications, market demand is also constantly increasing.

[0094] In the field of battery management, various chips, including but not limited to analog front-end chips, are often used to manage and sample batteries. For example, chips can be used to collect information such as battery cell voltage and temperature, or to support battery balancing functions, and so on. Therefore, stable chips are very important.

[0095] However, the applicant notes that chips used in battery management often face hot-swapping scenarios. This is especially true because the chip itself needs to be connected to the battery, and as a power source, there are often voltage differences between the different pins of the battery. Therefore, this poses a more severe challenge to the chip's functionality.

[0096] The applicant also notes that currently, in the field of battery management systems, there is no effective solution for hot-plug testing of analog front-end chips used for sampling. The lack of an effective testing solution may lead to malfunctions in end-use applications. Furthermore, the applicant notes that existing, incomplete testing solutions often simulate operating conditions by manually pressing to turn the device on and off, requiring significant human intervention and lacking flexibility and comprehensiveness.

[0097] To this end, the applicant discovered that a test method for hot-plugging conditions in various application scenarios can be designed to achieve flexible chip testing.

[0098] Based on the above considerations, in order to fully verify the hot-swap performance of a chip at the chip design stage, a chip testing method is proposed, comprising: determining a configuration mode of a test circuit, the test circuit including at least one chip, at least one battery module, and a switch matrix, the switch matrix being located between the at least one chip and the at least one battery module, the switch matrix being capable of connecting the at least one chip to the at least one battery module according to the configuration mode; performing a closing operation for closing at least two switches in the switch matrix based on the configuration mode; determining whether an operation termination condition is met; and testing the performance of the at least one chip in response to determining that the operation termination condition is met.

[0099] According to this testing scheme, standardized hot-plug testing can be obtained, and the hot-plug performance of the chip can be fully verified before the chip is put into use (e.g., at the chip design stage), thereby reducing the occurrence of chip anomalies in applications and thus mitigating losses in end applications.

[0100] In this embodiment, the battery cell used for the chip can be, but is not limited to, used in electrical devices such as vehicles, ships, or aircraft. Electrical devices using batteries as a power source can be, but are not limited to, mobile phones, tablets, laptops, electric toys, power tools, electric vehicles, electric cars, ships, spacecraft, etc. Electric toys can include stationary or mobile electric toys, such as game consoles, electric car toys, electric ship toys, and electric airplane toys, etc. Spacecraft can include airplanes, rockets, space shuttles, and spacecraft, etc.

[0101] For ease of explanation, the following embodiments will be described using a vehicle 1000 as an example of an electrical device according to an embodiment of this application.

[0102] Please refer to Figure 1 , Figure 1 This is a schematic diagram of the structure of a vehicle 1000 provided in some embodiments of this application. The vehicle 1000 can be a gasoline-powered vehicle, a natural gas-powered vehicle, or a new energy vehicle. New energy vehicles can be pure electric vehicles, hybrid electric vehicles, or range-extended electric vehicles, etc. A battery 100 is disposed inside the vehicle 1000, and the battery 100 can be located at the bottom, front, or rear of the vehicle 1000. The battery 100 can be used to power the vehicle 1000; for example, the battery 100 can serve as the operating power source for the vehicle 1000. The vehicle 1000 may also include a controller 200 and a motor 300. The controller 200 is used to control the battery 100 to supply power to the motor 300, for example, to meet the power needs of the vehicle 1000 during startup, navigation, and driving.

[0103] In some embodiments of this application, the battery 100 can not only serve as the operating power source for the vehicle 1000, but also as the driving power source for the vehicle 1000, replacing or partially replacing fuel or natural gas to provide driving power for the vehicle 1000.

[0104] Please refer to Figure 2 , Figure 2This is an exploded view of a battery 100 provided in some embodiments of this application. The battery 100 includes a housing 10 and a battery cell 20, with the battery cell 20 housed within the housing 10. The housing 10 provides a space for the battery cell 20 and can have various structures. In some embodiments, the housing 10 may include a first portion 11 and a second portion 12, which overlap each other, jointly defining a space for accommodating the battery cell 20. The second portion 12 may be a hollow structure with one open end, and the first portion 11 may be a plate-like structure, covering the open side of the second portion 12 so that the first portion 11 and the second portion 12 jointly define the space; alternatively, the first portion 11 and the second portion 12 may both be hollow structures with one open side, with the open side of the first portion 11 covering the open side of the second portion 12. Of course, the housing 10 formed by the first portion 11 and the second portion 12 can have various shapes, such as a cylinder, a cuboid, etc.

[0105] In battery 100, there can be multiple battery cells 20, which can be connected in series, parallel, or in a mixed manner. A mixed connection means that multiple battery cells 20 are connected in both series and parallel configurations. Multiple battery cells 20 can be directly connected in series, parallel, or in a mixed manner, and then the entire assembly of the multiple battery cells 20 is housed within the housing 10. Alternatively, battery 100 can also be composed of multiple battery cells 20 first connected in series, parallel, or in a mixed manner to form a battery module, and then multiple battery modules are connected in series, parallel, or in a mixed manner to form a whole, which is also housed within the housing 10. Battery 100 may also include other structures; for example, it may include a busbar component for electrical connection between the multiple battery cells 20.

[0106] Each battery cell 20 can be a secondary battery or a primary battery; it can also be a lithium-sulfur battery, a sodium-ion battery, or a magnesium-ion battery, but is not limited to these. The battery cell 20 can be cylindrical, flat, cuboid, or other shapes.

[0107] Please refer to Figure 3 , Figure 3 This is an exploded structural diagram of a battery cell 20 provided in some embodiments of this application. The battery cell 20 refers to the smallest unit that makes up a battery. Figure 3 The battery cell 20 includes an end cap 21, a housing 22, a cell assembly 23, and other functional components.

[0108] End cap 21 refers to a component that covers the opening of housing 22 to isolate the internal environment of battery cell 20 from the external environment. The shape of end cap 21 can be adapted to the shape of housing 22 to fit it. According to some embodiments, end cap 21 can be made of a material with certain hardness and strength (such as aluminum alloy), so that end cap 21 is not easily deformed under pressure and impact, enabling battery cell 20 to have higher structural strength and improved safety. Functional components such as electrode terminals 21a can be provided on end cap 21. Electrode terminals 21a can be used for electrical connection with cell assembly 23 to output or input electrical energy to battery cell 20. In some embodiments, end cap 21 can also be provided with a pressure relief mechanism for releasing internal pressure when the internal pressure or temperature of battery cell 20 reaches a threshold. The material of end cap 21 can also be various, such as copper, iron, aluminum, stainless steel, aluminum alloy, plastic, etc., and this application embodiment does not impose any special limitations on this. In some embodiments, an insulating element may be provided on the inner side of the end cap 21. The insulating element can be used to isolate the electrical connection components within the housing 22 from the end cap 21 to reduce the risk of short circuits. For example, the insulating element may be made of plastic, rubber, etc.

[0109] The housing 22 is a component used to cooperate with the end cap 21 to form the internal environment of the battery cell 20. This internal environment can accommodate the cell assembly 23, electrolyte, and other components. The housing 22 and the end cap 21 can be independent components. An opening can be provided on the housing 22, and the end cap 21 can be used to close the opening to form the internal environment of the battery cell 20. Alternatively, the end cap 21 and the housing 22 can be integrated. Specifically, the end cap 21 and the housing 22 can form a common connecting surface before other components are inserted into the housing. When it is necessary to encapsulate the interior of the housing 22, the end cap 21 closes the housing 22. The housing 22 can be of various shapes and sizes, such as cuboid, cylindrical, hexagonal prism, etc. Specifically, the shape of the housing 22 can be determined according to the specific shape and size of the cell assembly 23. The material of the housing 22 can be various, such as copper, iron, aluminum, stainless steel, aluminum alloy, plastic, etc. This application embodiment does not impose any special limitations on this.

[0110] The cell assembly 23 is the component in the battery cell 100 where the electrochemical reaction occurs. The casing 22 may contain one or more cell assemblies 23. The cell assembly 23 is mainly formed by winding or stacking positive and negative electrode plates, and typically a separator is provided between the positive and negative electrode plates. The portions of the positive and negative electrode plates containing active material constitute the main body of the cell assembly, while the portions of the positive and negative electrode plates without active material each constitute a tab 23a. The positive and negative tabs may be located together at one end of the main body or separately at both ends of the main body. During the charging and discharging process of the battery, the positive and negative active materials react with the electrolyte, and the tabs 23a connect to the electrode terminals to form a current loop.

[0111] The following is for reference. Figure 4 A testing method 400 for a chip according to an embodiment of this application is described. For example... Figure 4 As shown, method 400 may include:

[0112] In step S401, a configuration mode for a test circuit is determined, the test circuit comprising at least one chip and at least one battery module, the at least one chip being able to be connected to the at least one battery module according to the configuration mode.

[0113] In step S402, the at least one chip is connected to the at least one battery module based on at least one operating condition corresponding to the configuration mode.

[0114] Furthermore, it is understandable that configuration patterns can be used to represent the simulated test scenarios. A specific configuration pattern for the circuit can be implemented, for example, by artificially setting up a test bench or through other means. As an example, the configuration pattern can be selected from a predetermined set of test patterns. As another example, the configuration pattern can be selected based on actual conditions, such as the number of sampling channel lines of the chip, the number of cells in the battery module, the characteristics of the specific application scenario in which the chip will be installed, and so on.

[0115] According to embodiments of this application, a standard hot-swap testing equipment scheme is proposed, which standardizes hot-swap testing. In practical applications, it can reduce the differences in testing between different chip manufacturers, and achieve standardized and regulated chip testing.

[0116] In particular, according to embodiments of this application, the hot-swap functionality of a chip can be fully verified before the chip is put into use (e.g., at the chip design stage), thereby reducing the occurrence of chip anomalies in applications and mitigating losses in end applications.

[0117] The embodiments of this application can be applied to the field of battery management systems, and are particularly suitable for hot-plug testing of analog front-end (AFE) chips, such as AFE chips used for sampling and managing batteries in new energy vehicles. Therefore, the methods according to the embodiments of this application can also accelerate the design, implementation, and application of terminals, and further, promote the healthy development of the new energy vehicle industry.

[0118] In some embodiments, the method further includes testing the performance of the at least one chip. In some embodiments, the method further includes: determining whether an operation termination condition is met before testing the performance of the at least one chip; and testing the performance of the at least one chip in response to determining that the operation termination condition is met.

[0119] It is understood that, in some exemplary embodiments, electrical data can be acquired for testing and verification after the operation condition ends and the switch connection process is completed. In some additional or optional exemplary embodiments, electrical data can also be acquired for testing and verification during the switch connection process of each operation condition.

[0120] For example, the method may further include steps S403-S404. In step S403, it is determined whether the operation termination condition is met.

[0121] At step S404, in response to determining that the operation termination condition is met, the performance of the at least one chip is tested.

[0122] The completion of the operation condition means that the simulation of the chip's operating conditions (e.g., applying pressure or powering on) has ended, and the chip can be used for performance testing. As a specific and non-limiting example of an operation completion condition, it is considered satisfied when the closing operation is completed, that is, when at least two switches that need to be closed based on the current configuration mode have been closed (or have been closed and a certain time delay has elapsed). Other non-limiting examples of operation completion conditions will be described in more detail below.

[0123] The process of testing the performance of the at least one chip may include various functional and performance testing of the chip as can be understood by those skilled in the art, such as, but not limited to, one or more tests performed under specific temperature, air pressure, or other conditions.

[0124] According to some embodiments, the method may include obtaining a test circuit constructed according to hot-swap test bench requirements, the test circuit including at least one battery module and at least one chip; connecting the at least one chip to the at least one battery module; and testing the functionality of the at least one chip. The test circuit constructed according to the hot-swap test bench requirements may be a test circuit constructed according to a desired circuit design, which can be used to simulate one or more desired scenarios or operating conditions. The test circuit constructed according to the hot-swap test bench requirements can be used to connect at least one battery module and at least one chip; however, it is understood that the battery module and chip may have been unconnected before the step of obtaining the test circuit, for example, never connected, previously connected but disconnected, previously connected but disconnected and fully discharged, etc.

[0125] Understandably, the chip here can be an analog front-end (AFE) chip, which can process analog signals from a signal source and digitize them, and includes modules such as an ADC, multiplexer, and state machine. More specifically, the chip here can be an analog front-end chip used in electric vehicles.

[0126] At least one chip can be combined to form a Cell Monitor Unit (CMU). A CMU can refer to a circuit module obtained by manufacturing analog front-end chips according to typical recommended circuit designs.

[0127] Hot-plugging can refer to plugging or unplugging a module into or out of the system while the system power is on.

[0128] According to some embodiments, the test circuit further includes a switch matrix located between the at least one chip and the at least one battery module, the switch matrix being capable of connecting the at least one chip to the at least one battery module according to the configuration mode, and wherein energizing the at least one chip includes: performing a closing operation for closing at least two switches in the switch matrix based on at least one operating condition corresponding to the test circuit.

[0129] It is understood that the statement that the switch matrix can "connect" the at least one chip to the at least one battery module according to at least one operating condition corresponding to the test circuit (or, as described below, according to the configuration mode) does not require that the corresponding switches of the switch matrix be closed, nor does it require that the chip be electrically connected to the corresponding battery module when the configuration mode of the test circuit is determined. Instead, the statement that the switch matrix can connect the at least one chip to the at least one battery module according to the configuration mode means that the first end of the corresponding switch of the switch matrix is ​​connected to the corresponding connection point of the at least one chip (e.g., the corresponding sampling channel line), and the second end of the corresponding switch is connected to the corresponding connection point of the at least one chip in the at least one battery module (e.g., the corresponding sampling lead), so that when the corresponding switch is turned on, the chip can form a connection with the battery module according to the desired configuration mode. By closing at least two switches in the switch matrix, an electrical connection is created between the chip and the battery module, enabling the formation of a path between the chip and the battery module, thereby simulating a hot-plugging scenario.

[0130] Furthermore, it is understood that although a switch matrix is ​​described herein, this disclosure is not limited thereto, and other techniques that can be understood by those skilled in the art to connect the chip to the battery module can be used to achieve hot-plug testing according to this disclosure.

[0131] According to embodiments of this application, a standardized chip testing scheme can be achieved by closing a switch based on the configuration mode of the test circuit and the corresponding operating conditions.

[0132] According to embodiments of this application, by introducing a switch matrix into the configuration circuit, the complex manual plugging and unplugging process can be avoided, the required scenarios and operating conditions can be flexibly simulated, and the hot-plugging function of the AFE can be tested accurately, quickly, and more closely to real application conditions.

[0133] According to some embodiments, performing a closing operation for closing at least two switches in the switch matrix includes closing the switches in the switch matrix based on at least one of the following strategies: a first strategy, which prioritizes closing two switches that form a closed circuit with the largest potential difference; or a second strategy, which prioritizes closing a switch that can form a path between the at least one battery module.

[0134] According to some embodiments, the at least one chip may include a first chip, and the at least one battery module may include a first battery module. In such an embodiment, determining the configuration mode of the test circuit may include determining that the test circuit is in a first configuration mode, the first configuration mode indicating that the first chip is configured to be connected to a corresponding switch of the switch matrix, such that when the corresponding switch is turned on, the sampling channel lines of the first chip can be respectively connected to the corresponding sampling leads of the first battery module.

[0135] Understandably, configuration patterns can be used to represent simulated test scenarios. A specific configuration pattern for a circuit can be implemented, for example, by artificially setting up a test bench or through other means. As an example, the configuration pattern can be selected from a predetermined set of test patterns. As another example, the configuration pattern can be selected based on actual conditions, such as the number of sampling channel lines of the chip, the number of cells in the battery module, the characteristics of the specific application scenario in which the chip will be installed, and so on.

[0136] Based on this example, a common use case where a chip is fully connected to a battery module can be simulated using a first configuration mode, referred to here as the first example scenario for ease of description. As a specific example, the number of sampling channel lines of the first chip can be equal to the number of sampling leads of the first battery module. Figure 5 A test circuit example diagram for the first configuration mode of the first example scenario is shown. Figure 5 As shown, in the test circuit 500, the first chip 530 is configured to be connected to the corresponding switches 520-1, 520-2, 520-3...520-N of the switch matrix 520, such that when the corresponding switches 520-1, 520-2, 520-3...520-N are turned on, the sampling channel lines 530-1, 530-2, 530-3...530-N of the first chip 530 can be connected to the corresponding sampling leads 510-1, 510-2, 510-3...510-N of the first battery module 510, respectively.

[0137] Understandably, although Figure 5 The diagram shows a one-to-one correspondence between the sampling channel lines of the first chip and the sampling leads of the first battery module; however, it is understood that this application is not limited thereto. As another non-limiting example, in such an embodiment, the number of sampling channels of the first chip may also be less than the number of sampling leads of the battery module. For example, only some sampling leads of the battery module may be sampled, and so on.

[0138] Furthermore, it is understandable that, although Figure 5The diagram shows N switches for connecting N sampling channel lines to N sampling leads, but the number of N is not limited here, as long as N is greater than or equal to 2 so that a voltage difference can be formed on the chip when the corresponding switches are connected.

[0139] According to this embodiment, standardized usage scenario-based testing can be achieved. In particular, by making the circuit configuration for testing approximate the chip's usage scenario, common chip usage scenarios can be simulated, thus obtaining more reliable test results.

[0140] According to some embodiments, in response to determining that the test circuit is in a first configuration mode, performing the closing operation includes: closing a pair of switches corresponding to the pair of sampling channel lines when none of the switches corresponding to the other sampling channel lines in the first chip, except for the pair of sampling channel lines associated with the maximum battery potential difference, are closed.

[0141] Therefore, for the first configuration mode, i.e., the first example scenario to be simulated, a relatively harsh operating condition is provided, under which the chip will withstand the maximum possible voltage difference. For ease of description, this is referred to here as the first simulated operating condition for the first example scenario. It is understood that the battery potential difference "associated" to a pair of sampling channel lines refers to the potential difference between the pair of sampling leads to which the pair of sampling channel lines will be connected after the corresponding switch is closed. Furthermore, it is understood that "associated to the maximum battery potential difference" means that among all the battery potential differences that can be associated with all pairs of sampling channel lines of the first chip, the battery potential difference associated with this pair of sampling channel lines will be the largest. (Continue to refer to...) Figure 5 As a specific example, in an embodiment where the number of sampling channel lines in the first chip is the same as the number of sampling leads in the first battery and they correspond one-to-one, the pair of sampling channel lines associated with the maximum battery potential difference will be the two sampling channel lines to be connected to the sampling lead 510-1 closest to the positive electrode side and the sampling lead 510-N closest to the negative electrode side of the first battery, respectively. That is, as shown... Figure 5 The 530-1 and 530-N are shown, and in such an example, switches 520-1 and 520-N can be closed first, before the rest of the switches.

[0142] It is understood that throughout this text, the use of phrases such as "closing a pair of switches while all other switches are closed," "closing two switches while all other switches are closed," "closing two switches first," or "closing a pair of switches first," etc., describing the closing order of a particular pair of switches relative to the remaining switches, is not intended to restrict the closing order between the "pair of switches" or "two switches," unless otherwise stated. Rather, such expressions can include, but are not limited to, scenarios such as: closing the two switches simultaneously, closing one of the two switches first and immediately closing the other, closing one of the two switches first and closing the other after a certain time delay or a random time delay, etc., as long as the closing time of the two switches satisfies a specific relationship with the described "remaining switches" (e.g., earlier than the closing of the "remaining switches").

[0143] It is also understood that closing the pair of switches when none of the switches corresponding to the other sampling channel lines are closed can mean closing this pair of switches first or preferentially compared to the other switches. It is understood that this statement does not require that all switches other than this pair of switches be closed in the subsequent closing operation, but only that this pair of switches be closed first. As a specific, non-limiting example, the closing operation can be considered complete only after closing the pair of switches corresponding to the largest potential difference.

[0144] According to this embodiment, it is possible to further test the operating conditions that may occur in the simulated application scenario. In particular, by making the test conditions correspond to the circuit configuration mode, that is, by simulating common operating conditions corresponding to the current use scenario of the chip, it is possible to obtain realistic and reliable test results.

[0145] According to this embodiment, the maximum voltage difference on the chip can be created by first closing the switches of a pair of sampling channel lines associated with the maximum battery potential difference. Therefore, according to this embodiment, simulating the worst operating conditions is more helpful for chip performance testing, and the chip obtained after such testing will have satisfactory reliability even when dealing with extreme conditions.

[0146] According to some embodiments, in response to determining that the test circuit is in a first configuration mode, performing the closing operation further includes: after the pair of switches corresponding to the pair of sampling channel lines are closed, causing the switches corresponding to the remaining sampling channel lines in the first chip to be closed randomly.

[0147] Therefore, the first simulation condition of the first example scenario can also simulate the closing of switches other than the sampling channel line subjected to the maximum voltage difference. It is understood that the expression "randomly closing" as used throughout this document can include any of the following: the closing order of the switches is random, the closing delay between any two sequentially closed switches is random, or other random closing parameters that can be understood by those skilled in the art. As a specific non-limiting example, the closing order can include any one or more of the following: sequential, reverse, randomized grouping (e.g., 2 groups, 3 groups, 4 groups), and randomized random numbering.

[0148] Continue to refer to Figure 5 As a specific, non-limiting example, after closing switches 520-1 and 520-N, switches 520-2, 520-3, and so on can be closed randomly.

[0149] According to such an embodiment, the operating conditions that may occur in the application scenario can be further tested for the simulated usage scenario. By simulating common operating conditions corresponding to the chip's usage scenario, real and reliable test results can be obtained.

[0150] Specifically, by simulating the worst-case scenario where both ends are closed first, and then randomly closing the remaining switches, we can cover not only the worst-case scenario but also other common plug-in / plug-out scenarios. Furthermore, using random closing logic makes the simulation results more realistic and comprehensive.

[0151] According to some embodiments, in response to determining that the test circuit is in a first configuration mode, performing the closing operation may include: causing the switch corresponding to the sampling channel line of the first chip to close randomly.

[0152] Therefore, for the first example scenario, in addition to the worst-case scenario provided, other more common scenarios in practice can also be simulated in the test. For ease of description, these are referred to here as the second simulated scenario for the first example scenario.

[0153] Continue to refer to Figure 5 As a specific, non-limiting example, according to the second simulation condition, switches 520-1 to 520-N can be closed randomly, or at least two of switches 520-1 to 520-N can be closed randomly.

[0154] It is understood that the closing operation according to this embodiment can be combined with closing operations according to other embodiments of this application. For example, for a first configuration mode, a closing operation of closing both switches can be performed once or multiple times for a first simulated operating condition, and for the same chip, a closing operation of randomly closing all switches can be performed once or multiple times for a second simulated operating condition, or vice versa. After each closing operation, the switches can be opened, and according to some embodiments, the chip can be discharged. Such exemplary embodiments will be further described below.

[0155] According to this embodiment, it is possible to further test the operating conditions that may occur in the simulated application scenario. In particular, by simulating common operating conditions corresponding to the chip's usage scenario, realistic and reliable test results can be obtained.

[0156] In particular, by randomly closing the switches corresponding to all sampling channel lines, more common insertion and removal conditions can be simulated, making the simulation results more realistic and comprehensive, and thus obtaining a reliable chip and reducing possible failures during chip use.

[0157] According to some embodiments, the at least one chip may include a first chip, the at least one battery module includes at least two battery modules connected in series, and determining the configuration mode of the test circuit includes determining that the test circuit is in a second configuration mode, the second configuration mode indicating that: the first chip is configured to be connected to a corresponding switch of the switch matrix, such that when the corresponding switch is turned on, the sampling channel line of the first chip can be connected to the corresponding sampling leads of the at least two battery modules respectively.

[0158] Based on this example, a common use case where a chip is connected to two or more battery modules can be simulated through a second configuration mode, referred to here as the second example scenario for ease of description. It is understood that the at least two battery modules connected in series can include the negative terminal of the first battery module connected to the positive terminal of the second battery module, the negative terminal of the second battery module connected to the positive terminal of the third battery module, and so on. The fact that the sampling channel lines of the first chip can be respectively connected to the corresponding sampling leads of the at least two battery modules means that the number of sampling channel lines of the first chip is greater than the number of sampling leads of a single battery module in the at least two battery modules. For example, the number of sampling channel lines of the first chip can be equal to the sum of the number of sampling leads of the at least two battery modules.

[0159] Figure 6 An example of the second configuration mode for the second example scenario is shown. For example... Figure 6As shown, in the test circuit 600, the first chip 630 is configured to be connected to the corresponding switches 620-1, ... 620-n, 620-(n+1), ... 620-N of the switch matrix 620, such that when the corresponding switches 620-1, ... 620-n, 620-(n+1), ... 620-N are turned on, the sampling channel lines 630-1, ... 630-n of the first chip 630 can be respectively connected to the corresponding sampling leads 610-1 ... 610-n of the first battery module 611 of the two battery modules 611 and 612 connected in series, and the sampling channel lines 630-(n+1), ... 630-N of the first chip 630 can be respectively connected to the corresponding sampling leads 610-(n+1) ... 610-N of the second battery module 612.

[0160] Understandably, although Figure 6 The diagram shows that the at least one battery module includes two battery modules connected in series, but it may also include more battery modules. Furthermore, although... Figure 6 The diagram shows a one-to-one correspondence between the sampling channel lines of the first chip and the sampling leads of the two battery modules; however, it is understood that this application is not limited thereto. As another non-limiting example, in such an embodiment, the number of sampling channels of the first chip may also be less than the sum of the number of sampling leads of the battery modules. For example, only some sampling leads of the battery modules may be sampled, and so on.

[0161] Furthermore, it is understandable that, although Figure 6 The diagram shows a first chip comprising N sampling channel lines, each capable of connecting to n sampling leads 610-1…610-n of a first battery module 611 and (Nn) sampling leads of a second battery module 612, but these values ​​are not limiting. As a specific example, the first battery module 611 and the second battery module 612 may have the same number of sampling leads, for example, N=2n. In other examples, the first battery module 611 and the second battery module 612 (and other battery modules connected in series according to some other embodiments) may have different numbers of sampling leads.

[0162] According to this embodiment, standardized usage scenario-based testing can be achieved. In particular, by making the circuit configuration for testing approximate the chip's usage scenario, common chip usage scenarios can be simulated, thus obtaining more reliable test results.

[0163] Specifically, such embodiments can cover scenarios where the number of sampling channel lines of the first chip is greater than the number of sampling leads of a single battery module, or where one chip can be used to sample two or more batteries, thereby achieving realistic and reliable simulation and testing of such common usage scenarios. It is understood that in this second example scenario, the maximum voltage that the chip can withstand may be greater than the voltage of a single battery module; therefore, covering such scenarios in testing would be highly advantageous.

[0164] According to some embodiments, in response to determining that the test circuit is in the second configuration mode, performing the closing operation may include: closing the switches corresponding to the sampling leads of the remaining battery modules other than the positive battery module in the at least two battery modules when none of the switches corresponding to the sampling leads of the positive battery module in the at least two battery modules are closed; and closing the switch corresponding to the sampling lead of the positive battery module associated with the highest battery potential after a first time delay following the closure of the switches corresponding to the sampling leads of the remaining battery modules.

[0165] According to this embodiment, it is possible to provide an operating condition for the second configuration mode, i.e., the second example scenario to be simulated, where, since the battery module on the negative side has been installed, the sampling channel line corresponding to the battery module on the positive side may have been placed at a relatively negative voltage potential. In this case, when the battery module on the positive side is installed, the chip may experience a large voltage difference momentarily. For ease of description, this is referred to here as the first simulated operating condition for the second example scenario.

[0166] As those skilled in the art will understand, the positive electrode side battery module can be the battery module closest to the positive electrode among at least two battery modules connected in series; in other words, the battery module with the highest battery potential. For example, continue to refer to Figure 6 For example, the positive-side battery module can be a first battery module 611, the "remaining battery modules" can be a second battery module 612, the sampling lead associated with the highest battery potential can be sampling lead 610-1, and the corresponding switch can be switch 620-1. In other words, switches 620-(n+1), ... 620-N can be closed before closing switches 620-1, ... 620-n, and the farthest switch 620-1 can be closed after a certain first time delay. The first time delay can be any time delay that can be selected by those skilled in the art as needed. For example, a longer first time delay can be selected so that the sampling channel lines 630-1 to 630-n that have not yet been connected to the corresponding sampling lead may have been placed at a relatively low voltage, or a shorter first time delay can be selected to increase test efficiency, or it can be an appropriate trade-off between the two. Alternatively, the first time delay can be randomly selected.

[0167] According to some embodiments, closing the switch corresponding to the sampling leads of the remaining battery modules in the at least two battery modules may further include: preferentially closing the switch corresponding to a pair of sampling leads of the remaining battery modules that are associated with the maximum battery potential difference, thereby simulating relatively harsh operating conditions locally; or, the switches corresponding to the sampling leads of the remaining battery modules may be closed randomly.

[0168] According to this embodiment, it is possible to further test the operating conditions that may occur in the simulated application scenario. In particular, by making the test conditions correspond to the circuit configuration mode, that is, by simulating common operating conditions corresponding to the current use scenario of the chip, it is possible to obtain realistic and reliable test results.

[0169] Specifically, the current embodiment can simulate a relatively harsh operating condition for a scenario where a chip is connected to two or more battery modules, thereby improving the reliability of the chip obtained through such a testing method.

[0170] According to some embodiments, performing the closing operation may further include: after the switch corresponding to the sampling lead associated with the highest battery potential is closed, causing the switches corresponding to the remaining sampling leads of the positive electrode side battery module, other than the sampling lead associated with the highest battery potential, to be closed randomly.

[0171] Continue to refer to Figure 6 For example, after closing the farthest switch 620-1, the second switch (not shown) to the nth switch (620-n) can be closed using a random strategy to perform a power-on test on the corresponding sampling channel line.

[0172] According to this embodiment, for the simulated usage scenario, further testing can be performed on the operating conditions that may occur in the application scenario, and by using random closed-loop logic, the simulation results can be made more realistic and comprehensive. Specifically, for the first simulated operating condition of the second example scenario, the risks that sampling channel lines other than the sampling channel line that will bear the maximum voltage difference can also be simulated, thereby enabling risk testing and evaluation of each sampling channel line of the chip and the corresponding circuit parts, and obtaining more reliable test results.

[0173] According to some embodiments, in response to determining that the test circuit is in the second configuration mode, performing the closing operation may include: closing the switches corresponding to the sampling leads of the remaining battery modules (excluding the negative-side battery module) in the at least two battery modules when none of the switches corresponding to the sampling leads of the sampling leads of the remaining battery modules are closed; and closing the switch corresponding to the sampling lead of the negative-side battery module associated with the lowest battery potential after a second time delay following the closure of the switches corresponding to the sampling leads of the remaining battery modules.

[0174] For the second example scenario, a symmetrical operating condition is provided corresponding to the first operating condition: Since the battery module on the positive side has already been installed, the sampling channel line corresponding to the battery module on the negative side may have been placed at a relatively positive voltage potential. At this time, when the battery module on the negative side is installed, the chip may experience a large voltage difference instantaneously. For ease of description, this is referred to here as the second simulated operating condition for the second example scenario.

[0175] Similarly, as those skilled in the art will understand, the negative electrode side battery module can be the battery module closest to the negative electrode among at least two battery modules connected in series; in other words, the battery module with the lowest battery potential. For example, continuing to refer to... Figure 6 For example, the negative battery module can be the second battery module 612, and the "other battery modules" can be the first battery module 611. In other words, switches 620-1, ..., 620-n can be closed before closing switches 620-(n+1), ..., 620-N, and the furthest switch 620-N can be closed after a certain second time delay. The second time delay can be similar to the first time delay, for example, it can be the same or similar value as the first time delay, or it can be selected following a similar strategy to the first time delay, and will not be elaborated further here.

[0176] According to some embodiments, closing the switches corresponding to the sampling leads of the remaining battery modules (excluding the negative electrode side battery module) of the at least two battery modules may include: preferentially closing the switches corresponding to a pair of sampling leads of the remaining battery modules associated with the maximum battery potential difference, thereby simulating relatively harsh operating conditions locally; or, the switches corresponding to the sampling leads of the remaining battery modules may be closed randomly.

[0177] According to this embodiment, it is possible to further test the operating conditions that may occur in the simulated application scenario. In particular, by making the test conditions correspond to the circuit configuration mode, that is, by simulating common operating conditions corresponding to the current use scenario of the chip, it is possible to obtain realistic and reliable test results.

[0178] Specifically, the current embodiment simulates another relatively harsh operating condition for a second scenario where a chip is connected to two or more battery modules.

[0179] It is understandable that, for this second scenario, according to some embodiments, the second operating condition here can be combined with the first operating condition mentioned above (for example, each tested once or multiple times), so as to more comprehensively cover the various application scenarios that the chip may undergo, making the test more standardized, comprehensive and reliable.

[0180] According to some embodiments, performing the closing operation may further include: after the switch corresponding to the sampling lead associated with the lowest battery potential is closed, causing the switches corresponding to the remaining sampling leads of the negative electrode side battery module, other than the sampling lead associated with the lowest battery potential, to be closed randomly.

[0181] Continue to refer to Figure 6 For example, after closing the furthest switch 620-N, the (n+1)th to (N-1)th switches (not shown) can be closed using a random strategy to power on the corresponding sampling channel line.

[0182] According to this embodiment, for the simulated usage scenario, further testing can be performed on the operating conditions that may occur in the application scenario, and by using random closed-loop logic, the simulation results can be made more realistic and comprehensive. Specifically, for the second simulated operating condition of the second example scenario, the risks that sampling channel lines other than the sampling channel line that will bear the maximum voltage difference can also be simulated to obtain more reliable test results.

[0183] According to some embodiments, the at least one chip includes a first chip and a second chip, the at least one battery module includes a first battery module, and determining the configuration mode of the test circuit includes determining that the test circuit is in a third configuration mode, the third configuration mode indicating that: the first chip and the second chip are configured to be connected to corresponding switches in the switch matrix, such that when the corresponding switches are turned on, the first chip and the second chip can be connected to corresponding sampling leads of the first battery module.

[0184] Based on this example, a scenario where two chips are connected to a battery module can be simulated using a third configuration mode, referred to here as the third example scenario for ease of description. For example, the number of sampling leads in the first battery module can be equal to the sum of the number of sampling channel lines of the first chip and the second chip. Alternatively, the third example scenario may only require the number of sampling leads in the first battery module to be equal to the number of sampling channel lines of the first chip, thus requiring more than one chip to sample the first battery module, without requiring the number of sampling leads in the first battery module to be strictly equal to the number of sampling channel lines of the first chip and the second chip.

[0185] Figure 7 An example of the third configuration mode for the third example scenario is shown. Figure 7 As shown, in the test circuit 700, the first chip 731 is configured to be connected to the corresponding switches 720-1, ... 720-n of the switch matrix 720, and the second chip 732 is configured to be connected to the corresponding switches 720-(n+1), ... 720-N of the switch matrix 720, such that when the corresponding switches 720-1, ... 720-n, 720-(n+1), ... 720-N are turned on, the sampling channel lines 730-1, ... 730-N of the first chip 731 and the second chip 732 can be connected to the corresponding sampling leads 710-1, ... 710-n, 710-(n+1), ... 710-N of the battery module 710, respectively.

[0186] Understandably, although Figure 7 The first chip 731 and the second chip 732 are shown, but this application is not limited to these. For example, there may be three or more chips sampling the same battery module. Furthermore, although... Figure 7 The diagram shows a one-to-one correspondence between the sampling channel lines of the first chip 731 and the second chip 732 and the sampling leads of the battery module 710. However, it is understood that this application is not limited to this; for example, sampling may be performed only on certain sampling leads of the battery module, etc. Furthermore, it is understood that the first chip 731 and the second chip 732 may have the same number of sampling channel lines, for example, N=2n, and the first chip 731 and the second chip 732 may also have different numbers of sampling leads; this application is not limited to this.

[0187] According to this embodiment, standardized usage scenario-based testing can be achieved. In particular, by making the circuit configuration for testing approximate the chip's usage scenario, common chip usage scenarios can be simulated, thus obtaining more reliable test results.

[0188] Specifically, such embodiments can cover scenarios where the number of sampling channel lines of the first chip is less than the number of sampling leads of a single battery module, or where two or more other chips can be used to sample a single battery, thereby achieving realistic and reliable simulation and testing of such common usage scenarios.

[0189] According to some embodiments, the first sampling channel line of the first chip and the second sampling channel line of the second chip can be connected to adjacent first and second sampling leads of the first battery module, and the third sampling channel line of the first chip and the fourth sampling channel line of the second chip can be connected to the third and fourth sampling leads of the first battery module associated with the maximum battery potential difference. In response to determining that the test circuit is in a third configuration mode, performing the closing operation may include: closing the switch corresponding to the first and second sampling channel lines when none of the switches corresponding to the other sampling channel lines of the first and second chips (excluding the first and second sampling channel lines) are closed; and closing the switch corresponding to the third sampling channel line and the switch corresponding to the fourth sampling channel line after a third time delay following the closure of the switches corresponding to the first and second sampling channel lines.

[0190] According to this embodiment, it is possible to provide a working condition for the third configuration mode, i.e., the third example scenario to be simulated, in which the switches corresponding to the adjacent sampling channel lines of the two chips are first closed. For ease of description, this is referred to herein as the first simulation working condition for the third example scenario.

[0191] Continue to refer to Figure 7 In this exemplary scenario, the adjacent first and second sampling leads of the first battery module are sampling leads 710-n and 710-(n+1), and the corresponding first sampling channel line of the first chip is sampling channel line 730-n, and the second sampling channel line of the second chip is sampling channel line 730-(n+1). The third and fourth sampling leads associated with the maximum battery potential difference are sampling leads 710-1 and 710-N, respectively. Therefore, the third sampling channel line of the first chip can be sampling channel line 730-1, and the fourth sampling channel line of the second chip can be sampling channel line 730-N.

[0192] like Figure 7As shown, it is understandable that, for the third example scenario, the first simulated operating condition envisioned here is a worst-case scenario, because in this scenario, the two adjacent sampling channel lines 730-n and 730-(n+1) of the two chips are connected to the adjacent sampling leads in the battery module through corresponding switches. At this time, the two chips can be approximated as one large chip in the circuit. Therefore, if the switches 720-1 and 720-N corresponding to the two sampling channel lines 730-1 and 730-N at the farthest end of the chip are turned on, the chip will withstand the voltage of the entire battery module 710.

[0193] Furthermore, it is understood that, as described above, the term "closing the switches corresponding to the first sampling channel line and the second sampling channel line" as used herein may include, but is not limited to, the following operational logic: closing switches 720-n and 720-(n+1) simultaneously or almost simultaneously within an allowable error range; closing one of switches 720-n and 720-(n+1) first, and immediately closing the other switch; closing one of switches 720-n and 720-(n+1) first, and closing the other switch after a certain time delay or a random time delay, etc., as long as it is ensured that the two switches corresponding to the first sampling channel line and the second sampling channel line are closed before the other switches are closed so that the two chips can be electrically connected.

[0194] Similarly, it can be understood that “closing the switch corresponding to the third sampling channel line and the switch corresponding to the fourth sampling channel line” may include, but is not limited to, the following operational logic: closing switches 720-1 and 720-N simultaneously or almost simultaneously within an allowable error range; closing one of switches 720-1 and 720-N first, and immediately closing the other switch; closing one of switches 720-1 and 720-N first, and closing the other switch after a certain time delay or a random time delay, etc.

[0195] According to this embodiment, it is possible to further test the operating conditions that may occur in the simulated application scenario. In particular, by making the test conditions correspond to the circuit configuration mode, that is, by simulating common operating conditions corresponding to the current use scenario of the chip, it is possible to obtain realistic and reliable test results.

[0196] Specifically, through the current embodiment, the test results and the reliability of the tested chips can be improved by simulating harsh scenarios, and the chips obtained after such testing will have satisfactory reliability even when dealing with extreme operating conditions.

[0197] According to some embodiments, performing the closing operation may further include: after the switch corresponding to the third sampling channel line and the switch corresponding to the fourth sampling channel line are closed, the switches corresponding to the remaining sampling channel lines of the first chip and the second chip other than the first sampling channel line, the second sampling channel line, the third sampling channel line and the fourth sampling channel line are randomly closed.

[0198] Continue to refer to Figure 7 For example, after first closing adjacent switches 720-n and 720-(n+1), and then closing the furthest switches 720-1 and 720-N, the remaining switches (not shown) can be closed in a random strategy to power on the corresponding sampling channel line.

[0199] According to this embodiment, the simulated usage scenarios can be further tested for the operating conditions that may occur in the application scenario; using random closed-loop logic makes the simulation results more realistic and comprehensive. In other words, for the first simulated operating condition of the third example scenario, the risks that sampling channel lines other than the sampling channel line that will bear the maximum voltage difference can also be simulated to comprehensively test the chip's withstand capability.

[0200] According to some embodiments, in response to determining that the test circuit is in a third configuration mode, performing the closing operation may include: causing the switches corresponding to the sampling channel lines of the first chip and the second chip to close randomly.

[0201] Continue to refer to Figure 7 For ease of description, this operating condition will be referred to here as the second simulated operating condition for the third example scenario. For the second simulated operating condition for the third example scenario, any two or more of the switches 720-1, ..., 720-n, 720-(n+1), ..., 720-N can be closed, and such closure can follow a random order, and / or there can be a random time delay between two switches closed in sequence.

[0202] Therefore, for the third example scenario, in addition to the worst-case scenario provided, other more common operating conditions in practice can be simulated in the test. According to this embodiment, other common plug-in / plug-out conditions can be covered. Furthermore, using randomized closed-loop logic makes the simulation results more realistic, thereby obtaining reliable and comprehensive test results.

[0203] According to some embodiments, the first sampling channel line of the first chip and the second sampling channel line of the second chip can be connected to adjacent first and second sampling leads of the first battery module, the third sampling channel line of the first chip and the fourth sampling channel line of the second chip can be connected to the third and fourth sampling leads of the first battery module associated with the maximum battery potential difference, and the third configuration mode can also indicate that the first sampling channel line and the second sampling channel line are electrically connected.

[0204] Based on this example, in the third example scenario described above, the two chips are further shorted. For ease of description, this scenario can be referred to as the fourth example scenario. The fourth example scenario can be used to cover practical applications where, when the number of sampling channel lines of a single chip is less than the number of sampling leads of a single battery to be sampled, two or more chips can be shorted or connected in series in advance.

[0205] refer to Figure 8 As an example. With Figure 7 Similarly, in Figure 8 In the test circuit 800, the first chip 831 is configured to be connected to the corresponding switches 820-1, ... 820-n of the switch matrix 820, and the second chip 832 is configured to be connected to the corresponding switches 820-(n+1), ... 820-N of the switch matrix 820, such that when the corresponding switches 820-1, ... 820-n, 820-(n+1), ... 820-N are turned on, the sampling channel lines 830-1, ... 830-N of the first chip 831 and the second chip 832 can be connected to the corresponding sampling leads 810-1, ... 810-n, 810-(n+1), ... 810-N of the battery module 810, respectively. It is also understood that the number of channels, chips, etc., shown in the figure are merely examples, and this application is not limited thereto.

[0206] like Figure 8 As shown, the first chip 831 and the second chip 832 are electrically connected through a jumper wire 8301.

[0207] According to this embodiment, standardized usage scenario-based testing can be achieved. In particular, by making the circuit configuration for testing approximate the chip's usage scenario, common chip usage scenarios can be simulated, thus obtaining more reliable test results.

[0208] Specifically, this embodiment, based on the third scenario, further considers a fourth example scenario in which the chip is pre-shorted, thereby more comprehensively covering the scenarios that the chip may face and thus obtaining reliable test results.

[0209] According to some embodiments, in response to determining that the test circuit is in a third configuration mode, performing the closing operation may include: closing the switch corresponding to the sampling channel line of the second chip when none of the switches corresponding to the sampling channel line of the first chip are closed; and closing the switch corresponding to the third sampling channel line after a third time delay following the closing of the switch corresponding to the sampling channel line of the second chip.

[0210] Continue to refer to Figure 8 As an example, in this exemplary scenario, the adjacent first and second sampling leads of the first battery module are sampling leads 810-n and 810-(n+1), and the corresponding first sampling channel line of the first chip is sampling channel line 830-n, and the second sampling channel line of the second chip is sampling channel line 830-(n+1). The third and fourth sampling leads associated with the maximum battery potential difference are sampling leads 810-1 and 810-N, respectively. Therefore, the third sampling channel line of the first chip can be sampling channel line 830-1, and the fourth sampling channel line of the second chip can be sampling channel line 830-N. In other words, switches 820-(n+1) to 820-N can be closed first, and after a third time delay, switch 820-1 can be closed. For ease of description, this operating condition can be referred to as the first operating condition for the fourth example scenario.

[0211] According to some embodiments, in response to determining that the test circuit is in a third configuration mode, performing the closing operation may include: closing the switch corresponding to the sampling channel line of the first chip when none of the switches corresponding to the sampling channel lines of the second chip are closed; and closing the switch corresponding to the fourth sampling channel line after a fourth time delay following the closure of the switch corresponding to the sampling channel line of the first chip. It is understood that this operating condition is symmetrical to the first operating condition described above, and for ease of distinction, it can be referred to as the second operating condition.

[0212] It is understandable that the third and / or fourth delays can be similar to the first and second delays. For example, they can be the same or similar values ​​as the first or second delays, or they can be selected following a similar strategy to the first or second delays, and will not be elaborated further here.

[0213] According to this embodiment, it is possible to further test the operating conditions that may occur in the simulated application scenario. In particular, by making the test conditions correspond to the circuit configuration mode, that is, by simulating common operating conditions corresponding to the current use scenario of the chip, it is possible to obtain realistic and reliable test results.

[0214] Specifically, through the current embodiment, by first closing one chip and then delaying the closing of the furthest switch in the other chip, it is possible to simulate the harsh operating conditions that can be withstood when hot-plugging the chip with a short circuit, thereby obtaining reliable test results.

[0215] According to some embodiments, performing the closing operation may further include: after the switch corresponding to the third sampling channel line is closed, causing the switches corresponding to the other sampling channel lines of the first chip, excluding the third sampling channel line, to be closed randomly.

[0216] Continue to refer to Figure 8 As an example, for the first working condition of the fourth example scenario, after switch 820-1 is closed, switches (e.g., 820-n) corresponding to the remaining sampling channel lines (e.g., 830-n) of the first chip 831 can be randomly closed.

[0217] It is understandable that, for the aforementioned pairing condition, that is, for the second condition of the fourth example scenario, there can also be subsequent random operations. For example, after the switch corresponding to the sampling channel line of the first chip is closed for a fourth time delay and the switch corresponding to the fourth sampling channel line is closed, the switches corresponding to the remaining sampling channel lines of the second chip can be randomly closed.

[0218] According to this embodiment, for the simulated usage scenario, further testing can be performed on the operating conditions that may occur in the application scenario, and by using random closed-loop logic, the simulation results can be made more realistic and comprehensive. Specifically, for the fourth example scenario, other common insertion and removal conditions and various sampling channel lines can be covered, thereby enabling risk testing and evaluation of each sampling channel line of the chip and the corresponding circuit parts, and obtaining more reliable test results.

[0219] According to some embodiments, the operation termination condition may include at least one of the following: the number of times a closing operation is executed for the at least one chip reaches a first threshold, or the number of times a closing operation based on a specific configuration mode is executed reaches a second threshold for the specific configuration mode.

[0220] According to this embodiment, after a certain number of tests are completed, the operation termination condition can be determined, thereby testing the chip performance, such as a five-point test. It is understood that the first and second thresholds can also be 1, meaning that scenarios requiring only one test can also be covered.

[0221] According to some embodiments, the operation termination condition may also include, for a specific configuration mode, the implementation of a closed operation under one or more specific operating conditions. As a specific non-limiting example, the operation termination condition may include, for a first configuration mode (first example scenario), the implementation of a first predetermined number of closed operations under a first operating condition, and the implementation of a second predetermined number of closed operations under a second operating condition, and so on. As a more specific non-limiting example, the hot-plug count under each operating condition may be specified to be not less than 30 times, but it is understood that this application is not limited thereto.

[0222] Therefore, by defining the termination conditions, the testing of chips can be further standardized.

[0223] Specifically, when the first or second threshold in the operation termination condition is set to a value greater than 1, reliability can be further tested by increasing the number of repeated tests under the same operating conditions. For example, if the same first or second threshold is specified across different chip manufacturers or testing locations, chip testing can be further standardized and normalized, reducing differences in test results, and resulting in more stable and compliant chips.

[0224] According to some embodiments, the testing method may further include, in response to determining that an operation termination condition has not been met: performing a power-off operation on the at least one chip; discharging the capacitor in the at least one chip; and repeatedly performing the closing operation for closing at least two switches in the switch matrix and testing the function of the at least one chip, wherein the operation termination condition includes at least one of the following: the number of times the closing operation for the at least one chip is executed reaches a first threshold, or the number of times the operation is executed for each of the at least one operating conditions reaches a second threshold for that operating condition.

[0225] According to such an embodiment, the switch can be turned off, the configuration mode determined, and the test can be repeated if the termination condition is not met (e.g., insufficient number of tests or no test for a specific configuration mode). This further standardizes and automates the test plan, avoids manual plugging and unplugging, and improves test efficiency.

[0226] According to this embodiment, after a certain number of tests are completed, the operation termination condition can be determined, thereby testing the chip's functionality, such as, but not limited to, various sample function tests described below. It is understood that the first and second thresholds can also be 1, meaning that scenarios requiring only one test can also be covered.

[0227] According to some embodiments, the operation termination condition may also include, for a specific configuration mode, the implementation of a closed operation under one or more specific operating conditions. As a specific non-limiting example, the operation termination condition may include, for a first configuration mode (first example scenario), the implementation of a first predetermined number of closed operations under a first operating condition, and the implementation of a second predetermined number of closed operations under a second operating condition, and so on. As a more specific non-limiting example, the hot-plug count under each operating condition may be specified to be not less than 30 times, but it is understood that this application is not limited thereto.

[0228] Therefore, by defining the termination conditions, the testing of chips can be further standardized.

[0229] Specifically, when the first or second threshold in the operation termination condition is set to a value greater than 1, reliability can be further tested by increasing the number of repeated tests under the same operating conditions. For example, if the same first or second threshold is specified across different chip manufacturers or testing locations, chip testing can be further standardized and normalized, reducing differences in test results, and resulting in more stable and compliant chips.

[0230] Furthermore, according to this embodiment, a discharge operation is performed before each repeated closing operation to ensure that the repeated operations are performed under conditions where the capacitor is not charged. This reduces the impact of the capacitor being charged in the previous operation, thereby making the test conditions more severe and thus ensuring the chip functionality obtained from the test is more reliable. Specifically, if a discharge unit is lacking, the AFE chip may be partially charged after the first hot-plug (closing operation), and the stress of subsequent hot-plugs will become weaker and weaker. Conversely, by designing and adding a discharge unit, each hot-plug is made closer to real-world conditions, thereby obtaining more realistic test results and making it more conducive to repeated testing to improve reliability.

[0231] It is understood that the discharge operation can be achieved through grounding or other operations that can be understood by those skilled in the art. For example, the discharge process can be considered complete after the discharge circuit has been connected for a certain period of time. Such a period can be determined by those skilled in the art based on experience, experimentation, or other methods, and can be fixed in hot-plug testing or modified according to other environmental conditions, circuit conditions, or sample conditions. The discharge operation can also be a discharge operation for a test bench.

[0232] According to one or more embodiments of this application, it is possible to simulate various possible hot-swap scenarios and operating conditions in practical applications, with wide applicability and considerable standardization and consistency.

[0233] According to some embodiments, the testing method may further include: in response to determining that the step of energizing the at least one chip is being performed for the first time for the at least one chip, adjusting the individual cell voltage of the battery in the at least one battery module to a specified value before testing the function of the at least one chip.

[0234] According to this embodiment, the stability of the test can be ensured. As a non-limiting example, the specified value of the single cell voltage can be 4.25V. For example, the specified value of the single cell voltage can be substantially equal to the cell voltage to be used in the corresponding scenario or operating condition, or it can be higher than the cell voltage to be used in the corresponding scenario or operating condition to obtain more reliable test results. Other examples will be described in detail below with reference to specific embodiments.

[0235] According to some embodiments, testing the performance of the at least one chip includes performing a supply voltage range test on the at least one chip.

[0236] The supply voltage range test can be a five-point test, that is, the chip is tested five times under five predetermined combinations of ambient temperature, voltage, etc. The supply voltage range test can also be other tests, inspections, checks, or verifications of the chip's voltage performance that can be understood by those skilled in the art.

[0237] Alternatively or additionally, testing the functionality of the at least one chip may also include performing at least one of the following on the at least one chip: supply current range testing, cell voltage sampling accuracy testing, cell temperature sampling accuracy testing, and leakage current diagnostic threshold testing. It is also understood that these tests can be tests, inspections, checks, or verifications of the chip's corresponding performance that would be understandable to someone skilled in the art.

[0238] Some non-limiting examples of chip testing are given below, and will not be elaborated further here.

[0239] According to this embodiment, the performance of the chip can be ensured, thereby making the test results more reliable.

[0240] According to one or more aspects of this application, a testing apparatus for a chip is also disclosed, comprising: a switch matrix; and a control device, the control device being capable of controlling the operation of at least one switch in the switch matrix to power on at least one chip according to a configuration mode, and wherein the control device is configured to connect the at least one chip to the at least one battery module based on at least one operating condition corresponding to the configuration mode.

[0241] According to some exemplary embodiments, the testing apparatus may further include at least one battery module, wherein powering on at least one chip in a configuration mode includes connecting at least one chip to the at least one battery module.

[0242] According to some exemplary embodiments, connecting the at least one chip to the at least one battery module includes performing a closing operation for closing at least two switches in the switch matrix.

[0243] According to some exemplary embodiments, performing a closing operation for closing at least two switches in the switch matrix includes closing the switches in the switch matrix based on at least one of the following strategies: a first strategy, which prioritizes closing two switches that form a power-carrying loop with the largest potential difference; or a second strategy, which prioritizes closing a switch that can form a path between the at least one battery module.

[0244] According to some exemplary embodiments, the test apparatus includes an interface for connecting to the at least one chip, such as an interface for connecting the chip under test, such as an AFE or a CSC.

[0245] According to some exemplary embodiments, the control device includes a host computer.

[0246] According to one or more aspects of this application, a testing apparatus for a chip is also disclosed, comprising: at least one battery module; a switch matrix; and a host computer capable of controlling the operation of at least one switch in the switch matrix, wherein the switch matrix is ​​capable of connecting at least one chip to the at least one battery module, and the host computer is configured to perform the method described according to one or more embodiments of this application.

[0247] refer to Figure 9 The testing device 900 may include at least one battery module 910, a switch matrix 920, and a host computer 940. At least one chip 930 may be configured to be connected to corresponding switches 920-1, 920-2, 920-3...920-N of the switch matrix 920, such that when the corresponding switches 920-1, 920-2, 920-3...920-N are turned on, the sampling channel lines 930-1, 930-2, 930-3...930-N of the at least one chip 930 can be respectively connected to the corresponding sampling leads 910-1, 910-2, 910-3...910-N of the at least one battery module 910.

[0248] As those skilled in the art will understand, the ability of a host computer to control the operation of at least one switch in a switch matrix can mean that the host computer is electrically connected, signal connected, or otherwise operably connected to the switch matrix to control the opening or closing of one or more switches in the switch matrix.

[0249] According to some embodiments, the testing apparatus may further include at least one discharge unit, which, when turned on, is capable of discharging a corresponding capacitor in the at least one chip.

[0250] For example, refer to Figure 9 The test apparatus 900 may also include a discharge unit 950. Specifically, the discharge unit 950 may include a grounding switch and a resistor. Alternatively, the discharge unit may employ other circuit arrangements capable of discharging the capacitor, and this application is not limited thereto.

[0251] According to this embodiment, by setting a grounding switch, the chip can be discharged. This allows for a closing operation while the capacitor is discharged, reducing the impact of potential capacitor charge within the chip and thus enabling more reliable testing.

[0252] According to one or more aspects of this application, a host computer is also disclosed, which is capable of controlling the operation of at least one switch in a switch matrix, the switch matrix being configured to connect at least one chip to at least one battery module, wherein the host computer is configured to perform the method described according to one or more embodiments of this application.

[0253] According to one or more aspects of this application, a chip for a battery is also disclosed, said chip being tested according to the method described in one or more embodiments of this application.

[0254] According to one or more aspects of this application, an electronic device is also disclosed, comprising: at least one processor; and a memory communicatively connected to the at least one processor; wherein the memory stores instructions executable by the at least one processor to enable the at least one processor to perform the method described according to one or more embodiments of this application.

[0255] According to one or more aspects of this application, a non-transitory computer-readable storage medium storing computer instructions is also disclosed, wherein the computer instructions are configured to cause the computer to perform the methods described according to one or more embodiments of this application.

[0256] In the following text, combined with Figure 10 Illustrative examples of computer devices, non-transitory computer-readable storage media, and computer program products according to this application are described.

[0257] Figure 10 An example configuration of a computer device 1000 that can be used to implement the methods described herein is shown. The computer device 1000 can be a variety of different types of devices, such as a service provider's server, a device associated with a client (e.g., a client device), a system-on-a-chip, and / or any other suitable computer device or computing system. Examples of the computer device 1000 include, but are not limited to: desktop computers, server computers, laptop or netbook computers, mobile devices (e.g., tablets, cellular or other wireless phones (e.g., smartphones), notebook computers, mobile stations), wearable devices (e.g., glasses, watches), or other display devices, automotive computers, and so on. Therefore, the range of the computer device 1000 can be from a full-resource device (e.g., a personal computer) with abundant memory and processor resources to a low-resource device with limited memory and / or processing resources.

[0258] Computer device 1000 may include at least one processor 1002, memory 1004, multiple communication interfaces 1006, display device 1008, other input / output (I / O) devices 1010, and one or more mass storage devices 1012 capable of communicating with each other, such as via system bus 1014 or other suitable connections.

[0259] Processor 1002 may be a single processing unit or multiple processing units, and all processing units may include single or multiple computing units or multiple cores. Processor 1002 may be implemented as one or more microprocessors, microcomputers, microcontrollers, digital signal processors, central processing units, state machines, logic circuits, and / or any device that manipulates signals based on operating instructions. Among other capabilities, processor 1002 may be configured to acquire and execute computer-readable instructions stored in memory 1004, mass storage device 1012, or other computer-readable media, such as program code of operating system 1016, program code of application program 1018, program code of other program 1020, etc.

[0260] Memory 1004 and mass storage device 1012 are examples of computer-readable storage media for storing instructions executed by processor 1002 to perform the various functions described above. For example, memory 1004 may generally include both volatile and non-volatile memory (e.g., RAM, ROM, etc.). Furthermore, mass storage device 1012 may generally include hard disk drives, solid-state drives, removable media, including external and removable drives, memory cards, flash memory, floppy disks, optical disks (e.g., CDs, DVDs), storage arrays, network-attached storage, storage area networks, etc. Both memory 1004 and mass storage device 1012 may be collectively referred to herein as memory or computer-readable storage media, and may be non-transitory media capable of storing computer-readable, processor-executable program instructions as computer program code, which may be executed by processor 1002 as a specific machine configured to perform the operations and functions described in the examples herein.

[0261] Multiple program modules may be stored on mass storage device 1012. These programs include operating system 1016, one or more applications 1018, other programs 1020, and program data 1022, and they may be loaded into memory 1004 for execution. Examples of such applications or program modules may include, for example, computer program logic (e.g., computer program code or instructions) for implementing methods according to one or more embodiments of this application.

[0262] Although Figure 10 The modules 1016, 1018, 1020, and 1022, or portions thereof, are illustrated as being stored in memory 1004 of computer device 1000. However, modules 1016, 1018, 1020, and 1022 may be implemented using any form of computer-readable medium accessible by computer device 1000. As used herein, “computer-readable medium” includes at least two types of computer-readable media: computer storage media and communication media.

[0263] Computer storage media includes volatile and non-volatile, removable and non-removable media implemented by any method or technology for storing information such as computer-readable instructions, data structures, program modules, or other data. Computer storage media includes, but is not limited to, RAM, ROM, EEPROM, flash memory or other memory technologies, CD-ROM, DVD, or other optical storage devices, magnetic cassettes, magnetic tapes, disk storage devices or other magnetic storage devices, or any other non-transfer medium that can be used to store information for access by computer equipment.

[0264] In contrast, communication media can embody computer-readable instructions, data structures, program modules, or other data within modulated data signals such as carrier waves or other transmission mechanisms. Computer storage media as defined herein do not include communication media.

[0265] Computer device 1000 may also include one or more communication interfaces 1006 for exchanging data with other devices, such as via a network, direct connection, etc., as discussed above. Such communication interfaces can be one or more of the following: any type of network interface (e.g., a network interface card (NIC)), wired or wireless (such as IEEE 802.10 Wireless LAN (WLAN)) wireless interface, Wi-MAX interface, Ethernet interface, Universal Serial Bus (USB) interface, cellular network interface, Bluetooth. TM Interfaces, near field communication (NFC) interfaces, etc. Communication interface 1006 can facilitate communication across various network and protocol types, including wired networks (e.g., LAN, cable, etc.) and wireless networks (e.g., WLAN, cellular, satellite, etc.), the Internet, etc. Communication interface 1006 can also provide communication with external storage devices (not shown) such as storage arrays, network-attached storage, storage area networks, etc.

[0266] In some examples, a display device 1008, such as a monitor, may be included for displaying information and images to the user. Other I / O devices 1010 may be devices that receive various inputs from the user and provide various outputs to the user, and may include touch input devices, gesture input devices, cameras, keyboards, remote controls, mice, printers, audio input / output devices, and so on.

[0267] The following will refer to the appendix. Figure 11-14 Describe specific, non-limiting examples according to this application.

[0268] like Figure 11 As shown, the exemplary test circuit 1100 may include at least one battery module 1110, a switch matrix 1120, at least one chip 1130, and a host computer 1140.

[0269] according to Figure 11 A specific example illustrates two analog front-end (AFE) chips, 1131 and 1132. These two AFE chips can be designed using typical recommended circuitry to form a cell monitor circuit (CMC) or a cell monitor unit (CMU). In some embodiments, the CMC requires at least two AFE chips.

[0270] At least one battery module 1110 may include battery modules 1111 and 1112. The number of battery cells in a battery module can vary in practical applications. Real battery cells or a cell simulator can be used.

[0271] The switch matrix 1120 can include switches for connecting and disconnecting modules and discharge circuits for discharging the CMC. Closing the switch is equivalent to connector insertion, and opening the switch is equivalent to connector removal. By using the closing and closing of switches (relays, semiconductor switches, etc.), the connection and disconnection of connectors in actual applications can be simulated, providing greater flexibility. Furthermore, when the switch matrix is ​​used in conjunction with a host computer, it can flexibly simulate each insertion and removal sequence.

[0272] The host computer 1140 can be used to control the opening and closing logic and timing of the switch matrix, simulating hot-plugging conditions with different access sequences. Furthermore, the host computer 1140 can be used to receive and read information from the CMC (Cyclic Module Control) to confirm whether the circuit function of the CMC is normal after hot-plugging. The host computer 1140 can be used to execute the methods described according to one or more embodiments of this application. It is understood that this application is not limited thereto, and the methods described according to one or more embodiments of this application can be implemented using other devices, apparatuses, units, code logic, etc.

[0273] Continue to refer to Figure 11 The example diagram illustrates a test circuit configuration for a first example scenario. As a specific, non-limiting example, the number of cells in the first battery 1111 is the same as the number of sampling channels in the first chip 1131, and all sampling leads of the first battery 1111 are concentrated on connector F1, while all sampling channel lines of the first chip 1131 are concentrated on J1. As a more specific, non-limiting example, the number of cells in the first battery 1111 and the number of sampling channels in the first chip 1131 can both be 16.

[0274] Given this circuit configuration, as an example of the first operating condition for the first example scenario as described in this article, for the first chip 1131, the worst operating condition could be that the switches K1 and Km at both ends are closed first.

[0275] According to some embodiments, Figure 11A second chip 1132 is also shown, whose configuration can be the same as that of the first chip 1131. It is understood that although two chips 1131 and 1132 are shown configured to connect to the corresponding two batteries 1111 and 1112, this application is not limited thereto. For example, the test circuit may include only one chip and one battery module. Alternatively, the test circuit may include more chips and more battery modules. In such an example, for the second chip 1132, the example of the first operating condition for the first example scenario, i.e., the worst-case operating condition, is that the switches Km+1 and K2m close first.

[0276] For example, the host computer 1140 (or other possible units, devices, etc.) can be configured to perform a closing operation on the first chip and the second chip independently or simultaneously to close the switches on both sides. Alternatively, the host computer 1140 can be configured to perform a closing operation on the first chip and the second chip respectively to test two or more chips in sequence, and so on, and this application is not limited thereto.

[0277] For the first chip 1131, after the switches K1 and Km at both ends are closed first, the other pins can be closed in a random order and / or with a random delay. According to some embodiments and similarly, for the second chip 1132, after the switches Km+1 and K2m at both ends are closed first, the other pins can be closed in a random order and / or with a random delay.

[0278] As another example, as a second working condition for the first example scenario, in order to simulate the situation as close to reality as possible, switches K1~Km and switches Km+1~K2m can be randomly closed, including, for example, random time delays and random closing order.

[0279] According to one or more embodiments of this application, the discharge unit 1150 can be configured according to some embodiments. For example, after each hot-plug simulation power-down, all discharge switches in the discharge unit 1150 can be closed to discharge the circuit to restore the initial state and ensure the consistency of the initial state of each hot-plug.

[0280] The following is combined Figure 12 This describes an example test circuit configuration for the second example scenario. For example... Figure 12As shown, the test circuit 1200 may include at least one battery module 1210, a switch matrix 1220, at least one chip 1230, and a host computer 1240. More specifically, at least one battery module 1210 includes battery modules 1211 and 1212, and at least one chip includes an AFE chip 1231, wherein the sum of the number of battery cells in battery modules 1211 and 1212 is consistent with the number of sampling channels of AFE chip 1231. Battery modules 1211 and 1212 have independent sampling leads F1 and F2, and all sampling channel lines of AFE chip 1231 are concentrated on J1. More specifically, the number of battery cells in battery module 1211 may be M1=8, the number of battery cells in battery module 1212 may be M2=8, M1+M2=16, and the number of sampling channels of AFE chip 1231 may be 16. According to some embodiments, a second AFE chip may also be included, the configuration of which may be the same as the first AFE chip (not shown).

[0281] As the first simulated operating condition for the second example scenario, the switches K1~Km of the AFE chip 1231 can be closed first, and then Km+1~K2m can be closed after a certain delay. During the closing process of switches Km+1~K2m, K2m can be closed first, and then Km+1~K2m-1 can be closed randomly.

[0282] As a second simulated operating condition for the second example scenario, the switches Km+1 to K2m of the AFE chip 1231 can be closed first, and then K1 to Km can be closed after a certain delay. During the closing process of switches K1 to Km, K1 can be closed first, and then K2 to Km can be closed randomly.

[0283] According to one or more embodiments of this application, the discharge unit 1250 can be configured according to some embodiments. For example, after each hot-plug simulation power-down, all discharge switches in the discharge unit 1250 can be closed to discharge the circuit to restore the initial state and ensure the consistency of the initial state of each hot-plug.

[0284] The following is combined Figure 13 This describes an example test circuit configuration for the third example scenario. Figure 13 As shown, the test circuit 1300 may include at least one battery module 1310, a switch matrix 1320, at least one chip 1330, and a host computer 1340. More specifically, the at least one battery module 1310 includes a battery module 1311, and the at least one chip includes an AFE chip 1331 and an AFE chip 1332, wherein the number of battery cells in the battery module 1311 is the same as the sum of the number of sampling channels in the AFE chip 1331 and the AFE chip 1332.

[0285] Battery module 1311 can be led out from a single connector F1. Alternatively, battery module 1311 can also be divided into two connectors F1 and F2 (not shown). All sampling channel lines of AFE chip 1331 and AFE chip 1332 are concentrated at J1. As a more specific example, the number of cells in battery module 1311 is M1=32, and the number of sampling channels of AFE chip 1331 and AFE chip 1332 is 16+16.

[0286] As the first simulated operating condition for the third example scenario, switches Km and Km+1 can be closed first, followed by the closure of K1 and K2m after a delay, with the remaining switches closed randomly.

[0287] As a second simulated operating condition for the third example scenario, all switches K1~K2m can be closed with random delays.

[0288] According to one or more embodiments of this application, the discharge unit 1350 can be configured exemplarily. For example, after each simulated power-down hot-plugging operation, all discharge switches in the discharge unit 1350 can be closed to discharge the circuit, restoring the initial state and ensuring the consistency of the initial state for each hot-plugging operation.

[0289] The following is combined Figure 14 This describes an example test circuit configuration for the fourth example scenario. The fourth example scenario can be a scenario where there is a short node between the two AFE chips, building upon the third example scenario.

[0290] like Figure 14 As shown, the test circuit 1400 may include at least one battery module 1410, a switch matrix 1420, at least one chip 1430, and a host computer 1440. More specifically, the at least one battery module 1410 includes battery module 1411, and the at least one chip includes AFE chip 1431 and AFE chip 1432, wherein the number of battery cells in battery module 1411 is the same as the sum of the number of sampling channels in AFE chip 1431 and AFE chip 1432. AFE chip 1431 and AFE chip 1432 can be shorted together using jumper wire 14301.

[0291] Battery module 1411 can be led out from a single connector F1. Alternatively, battery module 1411 can also be divided into two connectors F1 and F2 (not shown). All sampling channel lines of AFE chip 1431 and AFE chip 1432 are concentrated at J1. As a more specific example, the number of cells in battery module 1411 is M1=32, and the number of sampling channels of AFE chip 1431 and AFE chip 1432 is 16+16.

[0292] Understandably, in such an example, switches Km and Km+1 can correspond to the first and second sampling leads as described above, respectively, and switches K1 and K2m can correspond to the third and fourth sampling channel lines.

[0293] As the first simulated working condition for the fourth example scenario, it could be to first close switches Km+1~K2m, then close switch K1 after a delay, and finally close switches K2~Km randomly.

[0294] As a second simulated operating condition for the fourth example scenario, it could be to first close switches K1~Km, then close switch K2m after a delay, and finally randomly close switches Km+1~K2m-1.

[0295] According to one or more embodiments of this application, the discharge unit 1450 can be configured, for example. For example, after each hot-plug simulation power-down, all discharge switches in the discharge unit 1450 can be closed to discharge the circuit to restore the initial state and ensure the consistency of the initial state for each hot-plug.

[0296] According to one or more embodiments of this application, the sample state may be specified as follows:

[0297] —Number of samples: 6, from 3 different batches;

[0298] —Sample string configuration: The chip sampling channels need to be fully configured;

[0299] —Number of hot-swap cycles under each operating condition: not less than 30 times;

[0300] —Cell voltage: not less than 4.25V;

[0301] —Sample status: No abnormalities were found after five-point functional verification;

[0302] As a specific, non-limiting example, the experiment may include the following steps:

[0303] a) Construct a simulated test bench according to the requirements of the hot-swappable test bench;

[0304] b) Power on the test sample, adjust the voltage of the individual battery cells to the specified value, and check whether the function of the test sample meets the specified requirements;

[0305] c) Disconnect the power to the test sample and discharge any residual charge.

[0306] d) Simulate hot-swapping scenarios and corresponding operating conditions, and connect the corresponding cell channels in sequence. After all channels are connected, check whether the sample functions normally.

[0307] e) Repeat steps c to d to complete the required number of hot-plug tests under this operating condition;

[0308] f) Repeat steps c to e to complete the test requirements for the remaining hot-swap conditions;

[0309] g) For example, steps b through f can be repeated to complete the test requirements for the remaining hot-swap conditions of the samples.

[0310] It is understood that the aforementioned “scenario” and “operating condition” may correspond to various “example scenarios” and “simulated operating conditions” described in this application.

[0311] The following are exemplary test sample parameters:

[0312] —The number of samples is 6, or it could be any other number of samples;

[0313] —The number of strings S in the sample configuration can be selected according to specific hot-swap test bench requirements, typical circuit configuration, battery modules, the number of cells in each battery module, CMU configuration requirements, etc.

[0314] —Sample status: After testing, the functional status meets the required level requirements.

[0315] —The voltage value of a single cell is, for example, 4.25V. This can be determined through negotiation between the manufacturer and the application party. As an example, if there are deviations in the voltage value of a single cell, the differences can be required to be described in the test report.

[0316] Hot-swap cycles: no less than 30 times.

[0317] It is understood that, throughout the text, unless otherwise stated or clearly indicated from the context, the terms test sample, chip, device under test, test sample, test chip, etc., may be used interchangeably to refer to a chip to be tested, being tested, or having undergone hot-plug testing; and the terms test, verification, functional check, etc., may be used interchangeably to refer to the verification of the performance of the chip or test sample or the checking of its function, and this disclosure is not limited thereto.

[0318] Examples of environmental conditions and supply voltages are given below.

[0319] Exemplary environmental conditions may include:

[0320] —Ambient temperature: 23℃±5℃;

[0321] —Relative humidity: 20%RH~80%RH;

[0322] —Atmospheric pressure: 86 kPa~106 kPa;

[0323] —Altitude: Not exceeding 1000m. As an example, if it exceeds 1000m, the results should be corrected, and by way of example, the results should be corrected according to the relevant provisions of GB / T 18488.1-2015.

[0324] Example supply voltage conditions may include:

[0325] —Single cell voltage: 3.65V;

[0326] Total power supply voltage: (3.65*L)V

[0327] Where L represents the number of cells in the battery module, which can be 8, 12, 16, 18, etc., and can be changed according to specific hot-swap test bench requirements, typical circuit configurations, battery modules, the number of cells in each battery module, CMU configuration requirements, etc.

[0328] The following are some specific, non-limiting examples of exemplary functional parameter testing methods.

[0329] For example, the supply voltage range test may include verifying the supply voltage range of the AFE chip according to the following test method.

[0330] a) Place the test sample in the incubator and then adjust the incubator temperature to the specified temperature value;

[0331] b) Power on the test sample, adjust the voltage of the individual battery cells to the specified value, and check whether the function of the test sample meets the specified requirements;

[0332] c) Once the temperature of the test sample has stabilized, maintain the specified running time under these conditions;

[0333] d) During operation, monitor the working status of the test samples in real time to ensure they meet the specified requirements.

[0334] —Number of samples: 6

[0335] —Running time: 24 hours

[0336] —The combination of ambient temperature and power supply voltage can be shown in Table 1.

[0337] Table 1 Combination of Ambient Temperature and Power Supply Voltage

[0338]

[0339] Where L represents the number of battery cells, which can be 8, 12, 16, 18, etc., and can be changed according to specific hot-swap test bench requirements, typical circuit configurations, battery modules, the number of battery cells in each battery module, CMU configuration requirements, etc. The number of battery cells L can be selected in conjunction with the number of samples and the sampling channels of each sample chip, or vice versa.

[0340] It is understood that the ambient temperature and supply voltage shown in Table 1 can be referred to as a five-point test. Furthermore, it is understood that the temperature and voltage values ​​above are merely examples and can be adjusted as needed. In other cases, more combinations of ambient temperature and supply voltage can be selected, for example, performing more than five-point tests.

[0341] For example, the supply current range of the chip can be tested. The supply current range of the AFE chip can be verified according to the following test method.

[0342] a) Place the test sample in the incubator and then adjust the incubator temperature to the specified temperature value;

[0343] b) Power on the test sample, adjust the voltage of the individual battery cells to the specified value, and check whether the function of the test sample meets the specified requirements;

[0344] c) Once the temperature of the test sample reaches a stable state, set the test sample to enter the off state;

[0345] d) Maintain the specified operating time under these conditions;

[0346] e) During operation, monitor and record the operating current of the test sample in real time;

[0347] f) Repeat process a to e to complete the sleep state and run state current test.

[0348] —Number of samples: 6

[0349] —Running time: 15min

[0350] —The combination of ambient temperature and power supply voltage can be referenced in Table 1, for example.

[0351] For example, the cell voltage sampling accuracy of the chip can be tested. The cell voltage sampling accuracy of the AFE chip can be verified by the following test method.

[0352] g) Place the test sample in the incubator and then adjust the incubator temperature to the specified temperature value;

[0353] h) Power on the test sample, adjust the voltage of the individual battery cells to the specified value, and check whether the function of the test sample meets the specified requirements;

[0354] i) Once the temperature of the test sample has stabilized, begin reading the individual cell voltage values ​​collected from the test sample;

[0355] j) Compare the voltage value collected from the test sample with the value from the detection device, and record it;

[0356] k) Repeat steps a to d to complete the voltage sampling accuracy test at all set temperatures.

[0357] —Number of samples: 32

[0358] —The number of sample configuration strings can be S. S can be the number selected according to the actual scenario and typical working conditions.

[0359] —Sample condition: Sample aged for 1000 hours at +125°C. Aging conditions can be those understood by those skilled in the art, such as aging conditions set with reference to relevant standards.

[0360] —Running time: 1 minute

[0361] —For example, see Table 2 for combinations of ambient temperature and power supply voltage.

[0362] Table 2 Combination of Ambient Temperature and Individual Cell Voltage

[0363]

[0364] For example, the cell temperature sampling accuracy of the chip can be tested. The cell voltage sampling accuracy of the AFE chip can be verified by the following test method.

[0365] l) Place the test sample in the incubator and then adjust the incubator temperature to the specified temperature value;

[0366] m) Power on the test sample, adjust the voltage of the individual cell to the specified value, and check whether the function of the test sample meets the specified requirements;

[0367] n) Once the temperature of the test sample has stabilized, begin reading the temperature sampling line voltage value collected by the test sample;

[0368] o) Compare the voltage value collected from the test sample with the value from the detection device, and record it;

[0369] p) Repeat process a to d to complete the accuracy test of the temperature sampling line voltage value at all set temperatures.

[0370] —Number of samples: 32;

[0371] —The number of sample configuration strings can be S. S can be the number selected according to the actual scenario and typical working conditions.

[0372] —Sample condition: Sample aged for 1000 hours at +125°C. Aging conditions can be those understood by those skilled in the art, such as aging conditions set with reference to relevant standards.

[0373] —Running time: 1 minute;

[0374] —For example, see Table 3 for combinations of ambient temperature and power supply voltage.

[0375] Table 3 Combination of Ambient Temperature and Temperature Sampling Line Input Voltage

[0376]

[0377] For example, a leakage current diagnostic threshold test can be performed on the chip. The AFE chip can be subjected to a leakage current diagnostic threshold test according to the following test method.

[0378] q) Construct a simulated test bench for the test samples according to the requirements of the leakage current diagnostic threshold test;

[0379] r) Power on the test sample, adjust the voltage of the individual battery cells to the specified value, and check whether the function of the test sample meets the specified requirements;

[0380] s) Use a waveform generator to produce specific waveform interference and apply it to the corresponding diagnostic channel;

[0381] t) Observe and record the changes in the diagnostic channel thresholds via the host computer;

[0382] u) Repeat steps c to d to complete the test requirements for the remaining channels;

[0383] —Number of samples: 6;

[0384] —The number of sample configuration strings can be S. S can be the number selected according to the actual scenario and typical working conditions.

[0385] —Sample status: After testing and verification of the power supply voltage range, the functional status meets the level requirements;

[0386] —Interference waveform parameters: frequency 1kHz~20kHz, amplitude ±300mV;

[0387] Interference duration: 5 minutes.

[0388] For example, a classification of functional states is given. The classification is defined based on the functional state of the device under test (DUT) during and after exposure to electromagnetic interference.

[0389] --Status A: During and after the test, all functions and parameters of the DUT meet the design specifications.

[0390] --Status B: During the test, all functions of the DUT are normal, but one or more parameters exceed the specifications. After the test, all parameters automatically return to the specified requirements.

[0391] --Status C: During the test, one or more functions of the DUT fail to execute normally. After the test, all functions automatically return to the specified requirements.

[0392] --Status D: During the test, one or more functions of the DUT cannot be executed normally, and cannot be automatically restored to the specified requirements after the test. Simple operations or reactivation of the DUT are required.

[0393] --Status E: During the test, one or more functions of the DUT cannot be executed normally, and cannot be automatically restored to the specified requirements after the test. The DUT needs to be repaired or replaced.

[0394] For example, the functional state A level of the test for non-power-on / off state / sleep state is determined by powering on after the test.

[0395] As an example, the terms "meets required level requirements" and "meets level requirements" mentioned in the chip functional testing section of this document may refer to the sample conforming to level A, but it is understood that this disclosure is not limited thereto.

[0396] According to this application, the following examples are also provided:

[0397] Example 1 is a testing method for chips, including:

[0398] Determine the configuration mode of a test circuit, the test circuit including at least one chip and at least one battery module, the at least one chip being connectable to the at least one battery module according to the configuration mode; and

[0399] Based on at least one operating condition corresponding to the configuration mode, the at least one chip is connected to the at least one battery module.

[0400] Example 2 is the method according to Example 1, further comprising testing the performance of the at least one chip.

[0401] Example 3 is the method according to Example 2, further comprising: determining whether an operation termination condition is met before testing the performance of the at least one chip; and

[0402] In response to determining that the operation termination condition is met, the performance of the at least one chip is tested.

[0403] Example 4 is a method according to any one of Examples 1-3, wherein the test circuit further includes a switch matrix located between the at least one chip and the at least one battery module, the switch matrix being capable of connecting the at least one chip to the at least one battery module according to the configuration mode, and

[0404] Connecting the at least one chip to the at least one battery module includes performing a closing operation to close at least two switches in the switch matrix.

[0405] Example 5 is the method according to Example 4, wherein performing a closing operation for closing at least two switches in the switch matrix includes closing the switches in the switch matrix based on at least one of the following strategies: a first strategy, the first strategy being used to preferentially close two switches that form a power-carrying loop with the largest potential difference; or a second strategy, the second strategy being used to preferentially close a switch that can form a path between the at least one battery module.

[0406] Example 6 is the method according to Example 4, wherein the at least one chip includes a first chip, the at least one battery module includes a first battery module, and determining the configuration mode of the test circuit includes determining that the test circuit is in a first configuration mode, the first configuration mode indicating that the first chip is configured to be connected to a corresponding switch of the switch matrix, such that when the corresponding switch is turned on, the sampling channel line of the first chip can be connected to the corresponding sampling lead of the first battery module respectively.

[0407] Example 7 is the method according to Example 6, wherein performing the closure operation in response to determining that the test circuit is in a first configuration mode includes:

[0408] If none of the switches corresponding to the other sampling channel lines in the first chip, except for the pair of sampling channel lines associated with the maximum battery potential difference, are closed, close the pair of switches corresponding to the pair of sampling channel lines.

[0409] Example 8 is the method according to Example 7, wherein performing the closing operation in response to determining that the test circuit is in a first configuration mode further includes:

[0410] After the pair of switches corresponding to the pair of sampling channel lines are closed, the switches corresponding to the remaining sampling channel lines in the first chip are closed randomly.

[0411] Example 9 is a method according to any one of Examples 6-8, wherein, in response to determining that the test circuit is in a first configuration mode, performing the closing operation includes: causing a switch corresponding to a sampling channel line of the first chip to close randomly.

[0412] Example 10 is the method according to Example 4, wherein the at least one chip includes a first chip, the at least one battery module includes at least two battery modules connected in series, and determining the configuration mode of the test circuit includes determining that the test circuit is in a second configuration mode, the second configuration mode indicating that: the first chip is configured to be connected to a corresponding switch of the switch matrix such that when the corresponding switch is turned on, the sampling channel line of the first chip can be connected to the corresponding sampling leads of the at least two battery modules respectively.

[0413] Example 11 is the method according to Example 10, wherein performing the closure operation in response to determining that the test circuit is in the second configuration mode includes:

[0414] If none of the switches corresponding to the sampling leads of the positive-side battery modules in the at least two battery modules are closed, close the switches corresponding to the sampling leads of the remaining battery modules in the at least two battery modules, excluding the positive-side battery module; and

[0415] After a first time delay following the closing of the switch corresponding to the sampling lead of the other battery modules, the switch corresponding to the sampling lead of the positive electrode battery module associated with the highest battery potential is closed.

[0416] Example 12 is the method according to Example 11, wherein performing the closure operation further includes:

[0417] After the switch corresponding to the sampling lead associated with the highest battery potential is closed, the switches corresponding to the other sampling leads of the positive electrode side battery module, excluding the sampling lead associated with the highest battery potential, are randomly closed.

[0418] Example 13 is a method according to any one of Examples 10-12, wherein performing the closure operation in response to determining that the test circuit is in the second configuration mode includes:

[0419] If none of the switches corresponding to the sampling leads of the negative electrode side battery module in the at least two battery modules are closed, close the switches corresponding to the sampling leads of the remaining battery modules in the at least two battery modules, excluding the negative electrode side battery module; and

[0420] After a second time delay following the closing of the switch corresponding to the sampling lead of the other battery modules, the switch corresponding to the sampling lead of the negative electrode battery module associated with the lowest battery potential is closed.

[0421] Example 14 is the method according to Example 13, wherein performing the closure operation further includes:

[0422] After the switch corresponding to the sampling lead associated with the lowest battery potential is closed, the switches corresponding to the other sampling leads of the negative electrode side battery module, excluding the sampling lead associated with the lowest battery potential, are randomly closed.

[0423] Example 15 is the method according to Example 4, wherein the at least one chip includes a first chip and a second chip, the at least one battery module includes a first battery module, and determining the configuration mode of the test circuit includes determining that the test circuit is in a third configuration mode, the third configuration mode indicating that: the first chip and the second chip are configured to be connected to corresponding switches in the switch matrix, such that when the corresponding switches are turned on, the first chip and the second chip can be connected to corresponding sampling leads of the first battery module.

[0424] Example 16 is the method according to Example 14, wherein the first sampling channel line of the first chip and the second sampling channel line of the second chip can be connected to adjacent first and second sampling leads of the first battery module, the third sampling channel line of the first chip and the fourth sampling channel line of the second chip can be connected to the third and fourth sampling leads of the first battery module associated with the maximum battery potential difference, and the closing operation is performed in response to determining that the test circuit is in a third configuration mode.

[0425] If none of the switches corresponding to the sampling channel lines of the first chip and the second chip, other than the first sampling channel line and the second sampling channel line, are closed, close the switches corresponding to the first sampling channel line and the second sampling channel line; and

[0426] After a third time delay following the closing of the switches corresponding to the first and second sampling channel lines, the switches corresponding to the third and fourth sampling channel lines are closed.

[0427] Example 17 is the method according to Example 16, wherein performing the closure operation further includes:

[0428] After the switch corresponding to the third sampling channel line and the switch corresponding to the fourth sampling channel line are closed, the switches corresponding to the remaining sampling channel lines of the first chip and the second chip other than the first sampling channel line, the second sampling channel line, the third sampling channel line and the fourth sampling channel line are randomly closed.

[0429] Example 18 is a method according to any one of Examples 15-17, wherein, in response to determining that the test circuit is in a third configuration mode, performing the closing operation includes: causing the switches corresponding to the sampling channel lines of the first chip and the second chip to close randomly.

[0430] Example 19 is the method according to Example 15, wherein the first sampling channel line of the first chip and the second sampling channel line of the second chip can be connected to adjacent first and second sampling leads of the first battery module, the third sampling channel line of the first chip and the fourth sampling channel line of the second chip can be connected to the third and fourth sampling leads of the first battery module associated with the maximum battery potential difference, and the third configuration mode further indicates that the first sampling channel line and the second sampling channel line are electrically connected.

[0431] Example 20 is the method according to Example 19, wherein performing the closure operation in response to determining that the test circuit is in a third configuration mode includes:

[0432] If none of the switches corresponding to the sampling channel lines of the first chip are closed, close the switch corresponding to the sampling channel lines of the second chip; and

[0433] After a third time delay, the switch corresponding to the sampling channel line of the second chip is closed, and then the switch corresponding to the third sampling channel line is closed.

[0434] Example 21 is the method according to Example 20, wherein performing the closure operation further includes:

[0435] After the switch corresponding to the third sampling channel line is closed, the switches corresponding to the other sampling channel lines of the first chip, excluding the third sampling channel line, are randomly closed.

[0436] Example 22 is a test method according to any one of Examples 3-21, wherein the operation termination condition includes at least one of the following: the number of times a closing operation is executed for the at least one chip reaches a first threshold, or the number of times a closing operation based on a specific configuration mode is executed reaches a second threshold for the specific configuration mode.

[0437] Example 23 is a test method according to any one of Examples 1-22, further comprising:

[0438] Disconnect at least two switches;

[0439] Determine the current configuration mode between the first chip and the at least one battery module; and

[0440] Perform the closure operation again based on the current configuration mode.

[0441] Example 24 is a test method according to Example 23, further comprising: performing a discharge operation before performing the closing operation again based on the current configuration mode.

[0442] Example 25 is a method according to any one of Examples 1-24, further comprising responding to determining that a second operation termination condition has not been met:

[0443] Power off at least one chip;

[0444] Discharging the capacitor in at least one chip; and

[0445] Repeat the steps of closing at least two switches in the switch matrix and testing the functionality of the at least one chip.

[0446] The second operation termination condition includes at least one of the following: the number of times the closing operation is executed for the at least one chip reaches a first threshold, or the number of times the operation is executed for each of the at least one operating conditions reaches a second threshold for that operating condition.

[0447] Example 26 is a method according to any one of Examples 1-25, further comprising: in response to the step of determining that the at least one chip is connected to the at least one battery module being performed for the first time, adjusting the individual cell voltage of the battery in the at least one battery module to a specified value before testing the functionality of the at least one chip.

[0448] Example 27 is a method according to any one of Examples 1-26, wherein testing the performance of the at least one chip includes performing a supply voltage range test on the at least one chip.

[0449] Example 28 is a test apparatus for a chip, comprising:

[0450] Switch matrix; and

[0451] A control device capable of controlling the operation of at least one switch in the switch matrix to power on at least one chip according to a configuration mode, and

[0452] The control device is configured to connect the at least one chip to the at least one battery module based on at least one operating condition corresponding to the configuration mode.

[0453] Example 29 is a test apparatus according to Example 28, further comprising at least one battery module, wherein powering on at least one chip in a configuration mode includes connecting at least one chip to the at least one battery module.

[0454] Example 30 is a test apparatus according to Example 29, wherein connecting the at least one chip to the at least one battery module includes performing a closing operation for closing at least two switches in the switch matrix.

[0455] Example 31 is a test apparatus according to Example 30, wherein performing a closing operation for closing at least two switches in the switch matrix includes closing the switches in the switch matrix based on at least one of the following strategies: a first strategy for preferentially closing two switches that form a circuit with the largest potential difference; or a second strategy for preferentially closing a switch that can form a path between the at least one battery module.

[0456] Example 32 is a test apparatus according to any one of Examples 28-31, wherein the test apparatus includes an interface for connecting to the at least one chip.

[0457] Example 33 is a test apparatus according to any one of Examples 28-31, wherein the control device includes a host computer.

[0458] Example 34 is a test apparatus according to any one of Examples 28-31, further comprising at least one discharge unit capable of discharging a corresponding capacitor in the at least one chip when turned on.

[0459] Example 35 is a host computer capable of controlling the operation of at least one switch in a switch matrix configured to connect at least one chip to at least one battery module, wherein the host computer is configured to perform the method according to any one of Examples 1-27.

[0460] Example 36 is a chip for a battery, which is tested according to any one of Examples 1-27.

[0461] Example 37 is an electronic device comprising: at least one processor; and

[0462] A memory communicatively connected to the at least one processor; wherein

[0463] The memory stores instructions that can be executed by the at least one processor to enable the at least one processor to perform the method described in any one of Examples 1-27.

[0464] Example 38 is a non-transitory computer-readable storage medium storing computer instructions, wherein the computer instructions are used to cause the computer to perform the method according to any one of Examples 1-27.

[0465] Finally, it should be noted that the above embodiments are only used to illustrate the technical solutions of this application, and not to limit them. Although this application has been described in detail with reference to the foregoing embodiments, those skilled in the art should understand that modifications can still be made to the technical solutions described in the foregoing embodiments, or equivalent substitutions can be made to some or all of the technical features therein. These modifications or substitutions do not cause the essence of the corresponding technical solutions to deviate from the scope of the technical solutions of the embodiments of this application, and they should all be covered within the scope of the claims and specification of this application. In particular, as long as there is no structural conflict, the various technical features mentioned in the embodiments can be combined in any way. This application is not limited to the specific embodiments disclosed herein, but includes all technical solutions falling within the scope of the claims.

Claims

1. A method for testing a chip, comprising: determining a configuration mode of a test circuit, the test circuit comprising at least one chip and at least one battery module, the at least one chip being connectable to the at least one battery module in the configuration mode; the test circuit further comprising a switch matrix interposed between the at least one chip and the at least one battery module, the switch matrix being capable of connecting the at least one chip to the at least one battery module in the configuration mode; and connecting the at least one chip to the at least one battery module based on at least one operating condition corresponding to the configuration mode, comprising: performing a closing operation for closing at least two switches in the switch matrix; the closing operation comprising closing the switches in the switch matrix based on at least one of the following strategies: a first strategy for preferentially closing two switches of an energized loop that forms a maximum potential difference; or a second strategy for preferentially closing a switch capable of forming a path between the at least one battery module.

2. The method of claim 1, further comprising testing a performance of the at least one chip.

3. The method of claim 2, further comprising: determining whether an operation end condition is satisfied before testing the performance of the at least one chip; and in response to determining that the operation end condition is satisfied, testing the performance of the at least one chip. the at least one chip comprising a first chip, the at least one battery module comprising a first battery module, and determining a configuration mode of a test circuit comprising determining that the test circuit is in a first configuration mode, the first configuration mode indicating that the first chip is configured to be connected to respective switches of the switch matrix such that, when the respective switches are turned on, sampling channel lines of the first chip are respectively connectable to respective sampling leads of the first battery module.

4. The method of claim 1, wherein, in response to determining that the test circuit is in the first configuration mode, performing the closing operation comprising:

5. The method of claim 4, wherein, closing a pair of switches corresponding to a pair of sampling channel lines in the first chip other than a pair of sampling channel lines associated with a maximum battery potential difference, in a case where no switch corresponding to the remaining sampling channel lines in the first chip is closed. in response to determining that the test circuit is in the first configuration mode, performing the closing operation further comprising:

6. The method of claim 5, wherein, after the pair of switches corresponding to the pair of sampling channel lines are closed, causing switches corresponding to the remaining sampling channel lines in the first chip to be closed randomly. in response to determining that the test circuit is in the first configuration mode, performing the closing operation comprising: causing switches corresponding to sampling channel lines of the first chip to be closed randomly.

7. The method of claim 4, wherein, ​ 8. The method of claim 1, wherein, The at least one chip includes a first chip, the at least one battery module includes at least two battery modules connected in series, determining the configuration mode of the test circuit includes determining that the test circuit is in a second configuration mode, the second configuration mode indicating that the first chip is configured to be connected to a corresponding switch of the switch matrix, so that when the corresponding switch is turned on, a sampling channel line of the first chip can be connected to a corresponding sampling lead of the at least two battery modules respectively.

9. The method of claim 8, wherein, In response to determining that the test circuit is in the second configuration mode, performing the closing operation includes: In the case that none of the switches corresponding to the sampling leads of the positive electrode side battery module in the at least two battery modules is closed, closing the switches corresponding to the sampling leads of the remaining battery modules except the positive electrode side battery module in the at least two battery modules; and After the switches corresponding to the sampling leads of the remaining battery modules are closed for a first time delay, closing the switch corresponding to the sampling lead associated with the highest battery potential of the positive electrode side battery module.

10. The method of claim 9, wherein, Performing the closing operation further includes: After the switch corresponding to the sampling lead associated with the highest battery potential is closed, causing the switches corresponding to the remaining sampling leads of the positive electrode side battery module except the sampling lead associated with the highest battery potential to be closed randomly.

11. The method of claim 8, wherein, In response to determining that the test circuit is in the second configuration mode, performing the closing operation includes: In the case that none of the switches corresponding to the sampling leads of the negative electrode side battery module in the at least two battery modules is closed, closing the switches corresponding to the sampling leads of the remaining battery modules except the negative electrode side battery module in the at least two battery modules; and After the switches corresponding to the sampling leads of the remaining battery modules are closed for a second time delay, closing the switch corresponding to the sampling lead associated with the lowest battery potential of the negative electrode side battery module.

12. The method of claim 11, wherein, Performing the closing operation further includes: After the switch corresponding to the sampling lead associated with the lowest battery potential is closed, causing the switches corresponding to the remaining sampling leads of the negative electrode side battery module except the sampling lead associated with the lowest battery potential to be closed randomly.

13. The method of claim 1, wherein, The at least one chip includes a first chip and a second chip, the at least one battery module includes a first battery module, determining the configuration mode of the test circuit includes determining that the test circuit is in a third configuration mode, the third configuration mode indicating that the first chip and the second chip are configured to be connected to corresponding switches in the switch matrix, so that when the corresponding switches are turned on, the first chip and the second chip can be connected to corresponding sampling leads of the first battery module.

14. The method of claim 13, wherein, The first sampling channel line of the first chip and the second sampling channel line of the second chip can be connected to adjacent first and second sampling leads of the first battery module, the third sampling channel line of the first chip and the fourth sampling channel line of the second chip can be connected to third and fourth sampling leads of the first battery module associated with a maximum battery potential difference, and in response to determining that the test circuit is in a third configuration mode, performing the closing operation includes: closing switches corresponding to the first and second sampling channel lines of the first and second chips without closing switches corresponding to remaining sampling channel lines of the first and second chips other than the first and second sampling channel lines; and after the switches corresponding to the first and second sampling channel lines are closed for a third time delay, closing switches corresponding to the third and fourth sampling channel lines.

15. The method of claim 14, wherein, Performing the closing operation further includes: after the switches corresponding to the third and fourth sampling channel lines are closed, causing switches corresponding to remaining sampling channel lines of the first and second chips other than the first, second, third, and fourth sampling channel lines to be closed randomly.

16. The method of claim 13, wherein, In response to determining that the test circuit is in a third configuration mode, performing the closing operation includes causing switches corresponding to sampling channel lines of the first and second chips to be closed randomly.

17. The method of claim 13, wherein, The first sampling channel line of the first chip and the second sampling channel line of the second chip can be connected to adjacent first and second sampling leads of the first battery module, the third sampling channel line of the first chip and the fourth sampling channel line of the second chip can be connected to third and fourth sampling leads of the first battery module associated with a maximum battery potential difference, and the third configuration mode further indicates that the first and second sampling channel lines are electrically connected.

18. The method of claim 17, wherein, In response to determining that the test circuit is in a third configuration mode, performing the closing operation includes: closing switches corresponding to sampling channel lines of the second chip without closing switches corresponding to sampling channel lines of the first chip; and after the switches corresponding to the sampling channel lines of the second chip are closed for a third time delay, closing switches corresponding to the third sampling channel line.

19. The method of claim 18, wherein, Performing the closing operation further includes: after the switch corresponding to the third sampling channel line is closed, causing switches corresponding to remaining sampling channel lines of the first chip other than the third sampling channel line to be closed randomly.

20. The test method of claim 3, the operation end condition including at least one of a number of times the closing operation is performed for the at least one chip reaching a first threshold or a number of times the closing operation is performed based on configuration modes reaching a second threshold for the configuration modes.

21. The testing method of any one of claims 4-19, further comprising: opening the at least two switches; determining a current configuration mode between the first chip and the at least one battery module; and performing a closing operation again based on the current configuration mode.

22. The test method of claim 21, further comprising: The discharging operation is performed before the closing operation again based on the current configuration mode.

23. The method of any one of claims 1-20, further comprising, in response to determining that a second operation end condition is not met: performing a power-off operation on the at least one chip; discharging a capacitance in the at least one chip; and repeating the steps of performing a closing operation for closing at least two switches in the switch matrix and testing a function of the at least one chip, wherein the second operation end condition comprises at least one of a number of times of performing the closing operation for the at least one chip reaching a first threshold, or a number of times of performing for each of the at least one operating condition reaching a second threshold for the operating condition. In response to determining that the step of connecting the at least one chip to the at least one battery module is performed for the first time, adjusting a cell voltage of a battery cell in the at least one battery module to a specified value before testing the function of the at least one chip.

24. The method of any one of claims 1-20, further comprising: The testing of the performance of the at least one chip comprises performing a supply voltage range test on the at least one chip.

25. The method of any one of claims 1-20, wherein, 26. A testing apparatus for a chip, comprising: a switch matrix; and a control device capable of controlling an operation of at least one switch in the switch matrix to perform a power-on operation on at least one chip in a configuration mode, and wherein the control device is configured to connect the at least one chip to the at least one battery module based on at least one operating condition corresponding to the configuration mode; wherein the connecting of the at least one chip to the at least one battery module comprises performing a closing operation for closing at least two switches in the switch matrix, the closing operation comprising closing the switches in the switch matrix based on at least one of a first strategy for preferentially closing two switches of a power-on loop forming a maximum potential difference, or a second strategy for preferentially closing a switch capable of forming a path between the at least one battery module. The testing apparatus comprises an interface for connecting to the at least one chip. The control device comprises a host computer.

27. The test device of claim 26, wherein, 29. The testing apparatus of claim 26 or 27, further comprising at least one discharging unit capable of discharging a corresponding capacitance in the at least one chip when switched on.

28. The test device of claim 26 or 27, wherein, The host computer is configured to perform the method of any one of claims 1-25.

31. A chip for a battery, the chip being tested according to the method of any one of claims 1-25.

30. A host computer capable of controlling operation of at least one switch in a switch matrix, the switch matrix configured to enable connection of at least one chip to at least one battery module, wherein, at least one processor; and 32. An electronic device, comprising: a memory in communication connection with the at least one processor; wherein ​ ​ The memory stores instructions executable by the at least one processor, the instructions being executed by the at least one processor to enable the at least one processor to perform the method of any one of claims 1-25.

33. A non-transitory computer readable storage medium having stored thereon computer instructions, wherein, The computer instructions are for causing the computer to perform the method of any one of claims 1-25.

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