Mode resistance detection circuit and mode resistance detection method of display panel

Abstract

A mode resistance detection circuit according to one aspect of the present invention includes: a current source generator that generates a reference current and applies the reference current to a mode resistance; a reference voltage generator that generates a reference voltage using the plurality of resistors and the plurality of switches; a comparator that compares a magnitude of a detection voltage detected according to a reference current applied to the mode resistor with a magnitude of the reference voltage, and outputs a voltage comparison result; and a circuit controller outputting a reference voltage control signal for controlling the plurality of switches according to the voltage comparison result.

Description

Technical Field

[0001] The invention relates to a mode resistance detection circuit and a mode resistance detection method of a display panel. Background Art

[0002] With the development of information society, the demand for display devices that display images in various forms has increased, and recently, various display devices such as LCD (Liquid Crystal Display), OLED (Organic Light Emitting Display), etc. are being used.

[0003] In the display device, a malfunction may occur due to an increase or decrease in resistance of the display panel due to damage to an internal circuit of the display panel or generation of cracks in the display panel. Summary of the invention

[0004] Technical issues

[0005] In order to solve the above problems, an object of the present invention is to provide a pattern resistance detection circuit capable of detecting the resistance of a display panel and a pattern resistance detection method of a display panel.

[0006] In addition, another technical objective of the present invention is to provide a mode resistance detection circuit and a mode resistance detection method for a display panel that can improve resistance detection accuracy.

[0007] Technical Solution

[0008] In order to achieve the above-mentioned purpose, according to one aspect of the present invention, a mode resistance detection circuit includes: a current source generator, which is configured to generate a reference current and apply the reference current to the mode resistance; a reference voltage generator, which is configured to generate a reference voltage using multiple resistors and multiple switches; a comparator, which is configured to compare the amplitude of the detection voltage detected according to the reference current applied to the mode resistance with the amplitude of the reference voltage, and output a voltage comparison result; and a circuit controller, which is configured to output a reference voltage control signal for controlling multiple switches according to the voltage comparison result.

[0009] In order to achieve the above-mentioned purpose, according to one aspect of the present invention, a mode resistance detection method of a display panel includes: generating a reference current and applying the reference current to the mode resistance of the display panel; comparing the amplitude of a detection voltage detected according to the reference current applied to the mode resistance with the amplitude of a reference voltage; when the number of comparisons between the reference voltage and the detection voltage is less than a predetermined value, changing the reference voltage based on a voltage comparison result between the detection voltage and the reference voltage, and comparing the changed reference voltage with the detection voltage; and when the number of comparisons between the reference voltage and the detection voltage is greater than or equal to a predetermined value, completing the detection of the mode resistance.

[0010] Effects of the Invention

[0011] According to the present invention, by using reference current instead of variable resistance value, internal resistors and variable switches which occupy a large area can be omitted. Therefore, the present invention can reduce the circuit area.

[0012] In addition, since the present invention can use a reference current and a reference voltage that vary very little with temperature, high detection accuracy can be maintained even when the temperature varies.

[0013] In addition, the present invention can prevent current distortion caused by channel length modulation, thereby improving detection accuracy. BRIEF DESCRIPTION OF THE DRAWINGS

[0014] Figure 1 is a block diagram showing a display device according to an embodiment of the present invention.

[0015] Figure 2 is a schematic diagram showing a connection relationship between a display panel and a mode resistance detection circuit according to an embodiment of the present invention.

[0016] Figure 3 is a block diagram showing a configuration of a mode resistance detection circuit according to one embodiment of the present invention.

[0017] Figure 4 It is shown Figure 3 A circuit diagram of the configuration of the current source generator is shown.

[0018] Figure 5 It is a schematic diagram used to describe the channel length modulation phenomenon.

[0019] Figure 6 It is schematically shown Figure 3 A block diagram of the configuration of the reference voltage generator is shown.

[0020] Figure 7 is a circuit diagram showing an example of a digital-to-analog converter.

[0021] Figure 8 is a flow chart illustrating a method for detecting a mode resistance of a display panel according to an embodiment of the present invention.

[0022] Fig. 9 is a schematic diagram illustrating an exemplary process of detecting a mode resistance using a mode resistance detection circuit. DETAILED DESCRIPTION

[0023] Throughout the specification, the same reference numerals represent substantially the same components. In the following description, if structures and features known in the art are irrelevant to the core structure of the present invention, their detailed description may be omitted. The terms used in this specification should be understood as follows.

[0024] According to the embodiments described in detail below in conjunction with the accompanying drawings, the advantages and features of the present invention and the implementation methods thereof will become apparent. However, the present invention is not limited to the following embodiments, but can be implemented in various different forms; on the contrary, these embodiments are provided to make the description of the present invention complete and allow those skilled in the art to fully understand the scope of the present invention, and the present invention is only limited to the scope of the appended claims.

[0025] Throughout the specification, the same reference numerals may denote the same components. In addition, when describing the present invention, a detailed description of known related art may be omitted if it is deemed that it would unnecessarily obscure the gist of the present invention.

[0026] As used herein, terms such as "including," "having," "comprising," etc. are generally intended to allow for the addition of other components unless these terms are used with the term "only." References to components of a singular noun also include the plural of that noun unless expressly stated otherwise.

[0027] When describing a temporal context, for example "after", "after", "immediately following" or "before", non-sequential situations may also be included unless "immediately" or "directly" is used.

[0028] First, second, etc. are used to describe various components, but these components are not limited by these terms. These terms are only used to distinguish one component from another component. Therefore, within the technical concept of the present invention, the first component mentioned herein may also be the second component.

[0029] It should be understood that the term "at least one" includes any combination that can be presented according to one or more related items. For example, the meaning of "at least one of the first item, the second item, and the third item" can represent each of the first item, the second item, and the third item, as well as any combination items that can be presented according to two or more of the first item, the second item, and the third item.

[0030] Each feature in the various embodiments of the present invention may be coupled or combined with each other in whole or in part, and may be technically interlocked and operated in various ways, and each embodiment may be performed independently or in combination with each other.

[0031] Hereinafter, embodiments of the present invention will be described in detail with reference to the accompanying drawings.

[0032] Figure 1 is a block diagram showing a display device according to an embodiment of the present invention, Figure 2 is a schematic diagram showing a connection relationship between a display panel and a mode resistance detection circuit according to an embodiment of the present invention.

[0033] The display device 100 according to one embodiment of the present invention may perform a display function and may be implemented as a flat panel display device, such as a liquid crystal display (LCD) device or an organic light emitting diode (OLED) device.

[0034] Reference Figure 1 , the display device 100 according to the present invention includes a display panel 110 and a display driver for driving the display panel 110 .

[0035] The display panel 110 includes a display area, which is an area where a plurality of pixels P are arranged to display an image. The display panel 110 includes a plurality of data lines D1 to Dn, a plurality of gate lines G1 to Gm, and a plurality of pixels P, where n is a positive integer greater than 2 and m is a positive integer greater than 2.

[0036] Each of the plurality of data lines D1 to Dn receives a data signal. Each of the plurality of gate lines G1 to Gm receives a gate signal. The plurality of data lines D1 to Dn and the plurality of gate lines G1 to Gm are arranged to intersect each other on a substrate to define a plurality of pixels P. Each of the plurality of pixels P may be connected to any one of the plurality of data lines D1 to Dn and any one of the plurality of gate lines G1 to Gm. Each of the plurality of pixels P may include a driving transistor, a scanning transistor turned on by a gate signal on the gate line to provide a data voltage from the data line to the gate of the driving transistor, an organic light emitting diode that emits light in response to a drain-source current of the driving transistor, and a capacitor for storing a gate voltage of the driving transistor. Therefore, each of the plurality of pixels P may emit light according to the current provided to the organic light emitting diode.

[0037] According to an embodiment of the present invention, the display panel 110 may include a mode resistor circuit. Figure 2 As shown in , the mode resistance circuit may include a first pad P1, a mode resistor R_Panel, a resistance line RL, and a second pad P2.

[0038] The first pad P1 may be located at one end of the display panel 110 and may be connected to the mode resistance detection circuit 210 of the data driver 112. The second pad P2 may be located at the other end of the display panel 110 and may be connected to the mode resistance detection circuit 210 of the data driver 112. Figure 2 , the first pad P1 and the second pad P2 are shown to be located at different corners, but are not limited thereto. The first pad P1 and the second pad P2 may be disposed to be spaced apart from one corner of the display panel 110 .

[0039] The resistance line RL may be disposed along the edge of the display panel 110 and may electrically connect the mode resistor R_Panel to the first pad P1 and the second pad P2. Specifically, the resistance line RL may include a first resistance line RL1 electrically connecting the mode resistor R_Panel and the first pad P1 and a second resistance line RL2 electrically connecting the mode resistor R_Panel and the second pad P2.

[0040] The mode resistor R_Panel may be connected to the mode resistor detection circuit 210 via the resistance line RL and the first and second pads P1 and P2. The magnitude of the mode resistor R_Panel may be detected by the mode resistor detection circuit 210.

[0041] The display driver ensures that data signals are provided to a plurality of pixels P included in the display panel 110 to display an image on the display panel 110. To this end, the display driver may include a data driver 112, a gate driver 114, and a timing controller 116.

[0042] The timing controller 116 receives digital video data VDATA and a timing signal TSS from the host system. The timing signal TSS may include a reference clock signal (e.g., dot clock), a vertical synchronization signal, a horizontal synchronization signal, a data enable signal, etc. The vertical synchronization signal is a signal that defines a frame period. The horizontal synchronization signal is a signal that defines a horizontal period required to provide a data signal to a pixel P on a horizontal line of the display panel 110. The data enable signal is a signal that defines a time period for inputting valid data. The dot clock is a signal that repeats in a predetermined short period.

[0043] The timing controller 116 may include a data processor (not shown) that generates pixel data PDATA, a data control signal DCS, and a gate control signal GCS using the digital video data VDATA and the timing signal TSS.

[0044] To control operation timings of the data driver 112 and the gate driver 114 , the data processor of the timing controller 116 may generate a data control signal DCS for controlling operation timing of the data driver 112 and a gate control signal GCS for controlling operation timing of the gate driver 114 based on the timing signal TSS.

[0045] In addition, the data processor of the timing controller 116 can calibrate the digital video data VDATA to match the pixel structure formed on the display panel 105, and convert the calibrated digital video data VDATA into pixel data PDATA. For example, the data processor can convert and calibrate the digital video data VDATA of three colors of red, green and blue into pixel data PDATA of four colors of white, red, green and blue using a predetermined conversion method. In addition, the data processor can correct the pixel data PDATA through various image processing such as image quality compensation, external compensation and degradation compensation.

[0046] The gate driver 114 receives a gate control signal GCS from the timing controller 116. The gate driver 114 provides gate signals to the plurality of gate lines G1 to Gm according to the gate control signal GCS.

[0047] Specifically, the gate driver 114 generates a gate signal (or a scan signal) synchronized with the data signal under the control of the timing controller 116, and sequentially provides the generated gate signal to the gate lines G1 to Gm while shifting the generated gate signal. To this end, the gate driver 114 may include a plurality of gate drive ICs (not shown). The gate drive IC may sequentially provide the gate signal synchronized with the data signal to the plurality of gate lines G1 to Gm under the control of the timing controller 116 to select the data line to which the data signal is written. The gate signal may swing between a gate high voltage and a gate low voltage.

[0048] The data driver 112 receives the pixel data PDATA and the data control signal DCS from the timing controller 116. Figure 2 As shown, the data driver 112 according to one embodiment of the present invention is characterized in that it includes a mode resistance detection circuit 210 and a data signal generation circuit 220 .

[0049] The data signal generating circuit 220 converts the pixel data PDATA in digital form into analog positive / negative data signals according to the data control signal DCS, and provides the analog positive / negative data signals to the pixels P through the plurality of data lines D1 to Dn.

[0050] The mode resistance detection circuit 210 is connected to the mode resistance circuit of the specific device to detect the mode resistance R_Panel of the mode resistance circuit. The specific device may refer to a device including the mode resistance circuit. Hereinafter, the specific device is described as the display panel 110, but is not limited thereto.

[0051] In the following, reference will be made to Figures 3 to 7 The mode resistance detection circuit 210 is described in detail.

[0052] Figure 3is a block diagram showing a configuration of a mode resistance detection circuit according to one embodiment of the present invention, Figure 4 It is shown Figure 3 The circuit diagram of the configuration of the current source generator is shown in, Figure 5 It is a schematic diagram used to describe the channel length modulation phenomenon. Figure 6 It is schematically shown Figure 3 The block diagram of the configuration of the reference voltage generator shown in, Figure 7 is a circuit diagram showing an example of a digital-to-analog converter.

[0053] The mode resistance detection circuit 210 detects the magnitude of the detected resistance. The mode resistance detection circuit 210 according to one embodiment of the present invention may be connected to the mode resistance circuit of the display panel 110 to detect the magnitude of the mode resistance R_Panel of the mode resistance circuit. According to one embodiment of the present invention, the magnitude of the mode resistance R_Panel detected by the mode resistance detection circuit 210 may be used to determine whether the display panel 110 is faulty.

[0054] Reference Figure 3 The mode resistance detection circuit 210 includes a current source generator 310 , a reference voltage generator 320 , a comparator 330 , and a circuit controller 350 . In one embodiment, the mode resistance detection circuit 210 may further include a level shifter 340 .

[0055] The current source generator 310 generates a reference current and applies the generated reference current to the mode resistor R_Panel via the first pad P1 of the display panel 110. Figure 4 As shown in , the current source generator 310 may include a reference current generating circuit 410 to generate a reference current.

[0056] The reference current generating circuit 410 may include a current source I_REF, a first transistor TR1, and a second transistor TR2. In one embodiment, the first transistor TR1 and the second transistor TR2 may be MOS transistors.

[0057] The current source I_REF may be connected to the first power source VSS. The first transistor TR1 may be connected to the current source I_REF and the second power source VDD to allow a first reference current to flow. Here, the first power source VSS may be a low potential voltage or a ground voltage, and the second power source VDD may be a high potential voltage.

[0058] Specifically, the first transistor TR1 may include a first gate, a first drain, and a first source. The first drain of the first transistor TR1 is connected to the current source I_REF, and the first source of the first transistor TR1 is connected to the second power supply VDD, so that the first reference current can flow between the first drain and the first source. The first drain of the first transistor TR1 may be connected to the first gate of the first transistor TR1, and therefore, the first drain voltage and the first gate voltage may be the same.

[0059] The second transistor TR2 may be connected to the first transistor TR1 so that a second reference current obtained by replicating the first reference current flowing through the first transistor TR1 may flow.

[0060] Specifically, the second transistor TR2 may include a second gate, a second drain, and a second source. The second drain of the second transistor TR2 may be connected to the mode resistor R_Panel of the display panel 110, and the second source of the second transistor TR2 may be connected to the second power supply VDD. The second gate of the second transistor TR2 may be connected to the first gate of the first transistor TR1. Therefore, the first reference current flowing through the first transistor TR1 may be copied, so the second reference current may flow between the second drain and the second source of the second transistor TR2.

[0061] The first pad P1 of the display panel 110 may be connected to the reference current generating circuit 410, in particular, the second transistor TR2, and the second pad P2 of the display panel 110 may be connected to the first power source VSS. Therefore, the second reference current flowing through the second transistor TR2 may be applied to the mode resistor R_Panel via the first pad P1 of the display panel 110.

[0062] In one embodiment, a first switch SW_R may be provided between the current source generator 310 and the first pad P1 of the display panel 110. In this case, when the first switch SW_R is turned on by the mode resistance detection operation signal, the current source generator 310 is connected to the first pad P1 of the display panel 110, and a reference current may be applied to the mode resistance R_Panel via the first pad P1 of the display panel 110.

[0063] In one embodiment, a second switch SW_L may be further provided between the second pad P2 of the display panel 110 and the first power source VSS. The second switch SW_L may be turned on together with the first switch SW_R by the mode resistance detection operation signal.

[0064] In one embodiment, the reference current generating circuit 410 may further include a bias transistor VBP. The bias transistor VBP is disposed between the current source I_REF and the first transistor TR1 to provide a constant bias current to the first transistor TR1.

[0065] Meanwhile, in the current source generator 310, even if the magnitude of the current source I_REF is fixed, the second reference current flowing through the second transistor TR2 may also change due to the change of the mode resistor R_Panel. Figure 5 To explain in detail, the mode resistor R_Panel does not have a fixed value and can be changed to various values. As the mode resistor R_Panel changes, the detection voltage V_Panel detected by the mode resistor R_Panel also changes. Therefore, the second drain voltage of the second transistor TR2 may change, and the second reference current flowing through the second transistor TR2 may be different from the first reference current flowing through the first transistor TR1.

[0066] Therefore, although the second source voltage and the second gate voltage of the second transistor TR2 are fixed, the amplitude of the second reference current flowing through the second transistor TR2 increases or decreases due to the increase or decrease of the second drain voltage. This phenomenon is called channel length modulation. When the second reference current applied from the second transistor TR2 to the mode resistor R_Panel increases or decreases due to the channel length modulation, the actual detected detection voltage V_Panel is different from the detection voltage V_Panel. Figure 5 The expected values ​​shown are different, which may lead to reduced detection accuracy.

[0067] The current source generator 310 may further include a channel length modulation prevention circuit 420 to prevent current distortion due to channel length modulation. The channel length modulation prevention circuit 420 may include a differential amplifier 425 and a third transistor TR3. In one embodiment, the third transistor TR3 may be a MOS transistor.

[0068] The differential amplifier 425 may amplify the difference between the first drain voltage Va of the first transistor TR1 and the second drain voltage Vb of the second transistor TR2. The differential amplifier 425 may include a non-inverting input terminal (+) connected to the first drain of the first transistor TR1, an inverting input terminal (-) connected to the second drain of the second transistor TR2, and an output terminal connected to the third gate of the third transistor TR3.

[0069] The third transistor TR3 may include a third drain connected to the mode resistor R_Panel, a third gate connected to the differential amplifier 425, and a third source connected to the second drain of the second transistor TR2.

[0070] The channel length modulation prevention circuit 420 can use the differential amplifier 425 and the third transistor TR3 to ensure that the second drain voltage Vb of the second transistor TR2 is fixed to the first drain voltage Va of the first transistor TR1 without being affected by the change of the mode resistance R_Panel. Therefore, the mode resistance detection circuit 210 according to one embodiment of the present invention can prevent current distortion caused by channel length modulation.

[0071] The comparator 330 compares the magnitude of the detection voltage V_Panel detected according to the reference current applied to the mode resistor R_Panel with the magnitude of the reference voltage VR_SEL. The comparator 330 may include a non-inverting input terminal (+) to which the detection voltage V_Panel detected according to the reference current applied to the mode resistor R_Panel is input, an inverting input terminal (-) to which the reference voltage VR_SEL output from the reference voltage generator 320 is input, and an output terminal for outputting a voltage comparison result between the detection voltage V_Panel and the reference voltage VR_SEL.

[0072] When the detection voltage V_Panel is greater than the reference voltage VR_SEL, the comparator 330 may output a high level signal as a voltage comparison result between the detection voltage V_Panel and the reference voltage VR_SEL. On the other hand, when the detection voltage V_Panel is less than the reference voltage VR_SEL, the comparator 330 may output a low level signal as a voltage comparison result between the detection voltage V_Panel and the reference voltage VR_SEL.

[0073] In one embodiment, the comparator 330 may compare the magnitudes of the detection voltage V_Panel and the reference voltage VR_SEL based on the clock signal CLK. The clock signal CLK may be input from the timing controller 116.

[0074] The level shifter 340 may adjust the level of the voltage comparison result output from the comparator 330 and transmit it to the circuit controller 350 .

[0075] The circuit controller 350 generates a reference voltage control signal based on the voltage comparison result, and outputs the reference voltage control signal to the reference voltage generator 320. Specifically, the circuit controller 350 may select one of the multiple voltages as a new reference voltage based on the voltage comparison result. The circuit controller 350 may generate a reference voltage control signal for generating the reference voltage to be selected, and output the reference voltage control signal to the reference voltage generator 320.

[0076] In one embodiment, the circuit controller 350 may generate an N-bit reference voltage control signal SEL[(N-1):0] to generate 2 N One of the voltages is used as the reference voltage.

[0077] Specifically, the circuit controller 350 may select 2 based on the voltage comparison result. N One of the voltages is used as a new reference voltage. When the voltage comparison result is a high level, the circuit controller 350 can select from 2 N The circuit controller 350 can select a voltage greater than the current reference voltage from the two voltages as the new reference voltage VR_SEL. That is, when the detection voltage V_Panel is greater than the reference voltage VR_SEL, the circuit controller 350 can select a voltage greater than the current reference voltage from the two voltages as the new reference voltage VR_SEL. N A voltage greater than the current reference voltage is selected from the voltages as the new reference voltage.

[0078] In one embodiment, when the voltage comparison result is a high level, the circuit controller 350 may change the minimum voltage within the expected range to the current reference voltage, and N The circuit controller 350 can select a voltage between the maximum voltage in the expected range and the minimum voltage in the expected range as the new reference voltage. For example, the circuit controller 350 can select an intermediate voltage from the voltages between the maximum voltage and the minimum voltage in the expected range as the new reference voltage.

[0079] On the other hand, when the voltage comparison result is a low level, the circuit controller 350 may select 2 N In other words, when the detection voltage V_Panel is less than the reference voltage VR_SEL, the circuit controller 350 can select a voltage from 2 N A voltage smaller than the current reference voltage is selected from the voltages as the new reference voltage.

[0080] In one embodiment, when the voltage comparison result is a low level, the circuit controller 350 may change the maximum voltage within the expected range to the current reference voltage, and N The circuit controller 350 can select a voltage between the maximum voltage in the expected range and the minimum voltage in the expected range as the new reference voltage. For example, the circuit controller 350 can select an intermediate voltage from the voltages between the maximum voltage and the minimum voltage in the expected range as the new reference voltage.

[0081] In addition, the circuit controller 350 may generate an N-bit reference voltage control signal SEL[(N−1):0] for generating the selected reference voltage, and output the generated N-bit reference voltage control signal SEL[(N−1):0] to the reference voltage generator 320 .

[0082] The N-bit reference voltage control signal SEL[(N-1):0] may contain two N A reference voltage control signal. N The reference voltage control signals can correspond to 2 N voltage, and 2 N The voltages can correspond to 2 N The amplitude of the pattern resistor R_Panel.

[0083] For example, the circuit controller 350 may generate a 4-bit reference voltage control signal (SEL[3:0]). In this case, the 4-bit reference voltage control signal SEL[3:0] may correspond to 2 N The voltage corresponds to 2 N The amplitude of each mode resistor R_Panel is shown in Table 1 below.

[0084] [Table 1]

[0085] SEL[3:0] R_Panel[kΩ] SEL[3:0] R_Panel[kΩ] SEL[3:0] R_Panel[kΩ] 0000 1 0110 7 1100 13 0001 2 0111 8 1101 14 0010 3 1000 9 1110 15 0011 4 1001 10 1111 16 0100 5 1010 11 0101 6 1011 12

[0086] Referring to Table 1, for example, the circuit controller 350 can be selected from 2 4 The voltage corresponding to the mode resistor R_Panel with an amplitude of "9" is selected as the reference voltage from the voltages. The circuit controller 350 may generate "1000" as the reference voltage control signal SEL[3:0] to generate the selected reference voltage. The circuit controller 350 may output the reference voltage control signal SEL[3:0] "1000" to the reference voltage generator 320. The reference voltage generator 320 may generate a reference voltage VR_SEL corresponding to the mode resistor R_Panel with an amplitude of "9" according to the reference voltage control signal SEL[3:0] "1000", and output the generated reference voltage VR_SEL to the comparator 330.

[0087] When the detection voltage V_Panel is greater than the reference voltage VR_SEL, the circuit controller 350 can 4 The circuit controller unit 350 can select a voltage greater than the current reference voltage from the two voltages as a new reference voltage. 4The voltage corresponding to the mode resistor R_Panel with an amplitude of "13" is selected as a new reference voltage from the voltages. The circuit controller 350 can generate "1100" as the reference voltage control signal SEL[3:0] to generate the selected reference voltage. The circuit controller 350 can output the reference voltage control signal SEL[3:0] "1100" to the reference voltage generator 320. The reference voltage generator 320 can generate a reference voltage VR_SEL corresponding to the mode resistor R_Panel with an amplitude of "13" according to the reference voltage control signal SEL[3:0] "1100", and output the generated reference voltage VR_SEL to the comparator 330.

[0088] In one embodiment, the circuit controller 350 may change some bit values ​​of the N bits based on the voltage comparison result, thereby generating an N-bit reference voltage control signal SEL[(N-1):0].

[0089] Specifically, when the detection voltage V_Panel is greater than the reference voltage VR_SEL, the circuit controller 350 may maintain the bit value of the (i-1)th bit after the most significant bit and change the bit value of the (i)th bit from 0 to 1, thereby generating a reference voltage control signal SEL[(N-1):0], wherein i is the number of comparisons between the detection voltage V_Panel and the reference voltage VR_SEL.

[0090] For example, when the comparison number is 1 and the detection voltage V_Panel is greater than the reference voltage VR_SEL generated according to the reference voltage control signal SEL[3:0] “1000”, the circuit controller 350 may generate the reference voltage control signal SEL[3:0] “1100”.

[0091] When the detection voltage V_Panel is less than the reference voltage VR_SEL, the circuit controller 350 may change the bit value of the (i-1)th bit after the most significant bit to 0 and change the bit value of the (i)th bit from 0 to 1, thereby generating a reference voltage control signal SEL[(N-1):0].

[0092] For example, when the comparison number is 1 and the detection voltage V_Panel is less than the reference voltage VR_SEL generated according to the reference voltage control signal SEL[3:0] “1000”, the circuit controller 350 may generate the reference voltage control signal SEL[3:0] “0100”.

[0093] Meanwhile, when the number of comparisons between the detection voltage V_Panel and the reference voltage VR_SEL is greater than a preset value, the circuit controller 350 may stop the detection operation of the mode resistor R_Panel. The user may determine the mode resistor R_Panel of the display panel 110 based on the final selected reference voltage or the final reference voltage control signal SEL[(N-1):0]. Referring to Table 1, for example, when the reference voltage control signal SEL[(N-1):0] is "1011", the user may determine that the magnitude of the mode resistor R_Panel of the display panel 110 is 12.

[0094] In addition, the circuit controller 350 may determine a fault in the display panel 110 based on the final selected reference voltage or the final reference voltage control signal SEL[(N-1):0]. For example, when the reference voltage control signal SEL[(N-1):0] is "0000" or "1111", the circuit controller 350 may determine that there is a fault in the display panel 110.

[0095] The reference voltage generator 320 generates a reference voltage VR_SEL under the control of the circuit controller 350 , and outputs the generated reference voltage VR_SEL to the comparator 330 .

[0096] refer to Figure 6 and Figure 7 The reference voltage generator 320 may include a digital to analog converter DAC (Digital to Analog Converter) 610, and the digital to analog converter DAC includes a plurality of resistors R0, R1, . . . , R N-1 and R N and a plurality of switches SW.

[0097] A plurality of resistors R0, R1, ..., R N-1 and R N The first voltage VR_bottom and the second voltage VR_top may be connected in series. Here, the first voltage VR_bottom may correspond to the lowest voltage, and the second voltage VR_top may correspond to the highest voltage.

[0098] The first voltage VR_bottom and the second voltage VR_top may be determined based on the reference current and the range of the mode resistor R_Panel. The range of the mode resistor R_Panel may vary for each device. In one embodiment, the first voltage VR_bottom may be equivalent to the value obtained by multiplying the reference current by the minimum value of the mode resistor R_Panel. The second voltage VR_top may be equivalent to the value obtained by multiplying the reference current by the maximum value of the mode resistor R_Panel.

[0099] In one embodiment, a plurality of resistors R0, R1, ..., R N-1 and R N can have the same magnitude.

[0100] DAC 610 receives a plurality of resistors R0, R1, . . . , R N-1 and R N The nodes between receive multiple reference voltages VR[0], VR[1], ..., VR[2 N -2] and VR[2 N -1], and outputs a plurality of reference voltages VR[0], VR[1], ..., VR[2 N -2] and VR[2 N -1] selects a reference voltage VR_SEL.

[0101] To this end, the DAC 610 may include a plurality of resistors R0, R1, . . . , R N-1 and R N In response to the reference voltage control signal SEL[(N-1):0] input from the circuit controller 350, the multiple switches SW can be turned on or off, so that multiple reference voltages VR[0], VR[1], ..., VR[2 N -2] and VR[2 N- 1] is a reference voltage VR_SEL.

[0102] In one embodiment, the DAC 610 can be configured to receive a plurality of resistors R0, R1, . . . , R N-1 and R N The nodes between receive 2 N There are three reference voltages VR[0], VR[1], ..., VR[2 N -2] and VR[2 N -1]. When the N-bit reference voltage control signal SEL[(N-1):0] is input from the circuit controller 350, the DAC 610 may control the plurality of switches SW according to the N-bit reference voltage control signal SEL[(N-1):0] to output the voltage from 2 N There are three reference voltages VR[0], VR[1], ..., VR[2 N -2] and VR[2 N -1] as the reference voltage VR_SEL.

[0103] The reference voltage generator 320 may control the plurality of switches SW of the DAC 610 by using an inverted control signal SELB[(N-1):0] of the reference voltage control signal SEL[(N-1):0] in addition to the N-bit reference voltage control signal SEL[(N-1):0] input from the circuit controller 350. In this case, when the N-bit reference voltage control signal SEL[(N-1):0] is input from the circuit controller 350, the reference voltage generator 320 may generate an inverted control signal SELB[(N-1):0] inverted to the reference voltage control signal SEL[(N-1):0]. For example, when the reference voltage control signal SEL[(N-1):0] "1000" is input from the circuit controller 350, the reference voltage generator 320 may generate an inverted control signal SELB[(N-1):0] "0111" inverted to the reference voltage control signal SEL[(N-1):0].

[0104] In the DAC 610, the operation of the plurality of switches SW may be controlled according to the reference voltage control signal SEL[(N-1):0] and the inversion control signal SELB[(N-1):0]. The plurality of switches SW may include a first switch SW1, the operation of which is controlled by the reference voltage control signal SEL[(N-1):0], and a second switch SW2, the operation of which is controlled by the inversion control signal SELB[(N-1):0].

[0105] The mode resistance detection circuit 210 according to one embodiment of the present invention is characterized in that it detects the voltage V_Panel by applying a reference current to the mode resistance R_Panel, and compares the detected voltage V_Panel with the reference voltage VR_SEL. Compared with the mode resistance detection circuit 210 according to one embodiment of the present invention, the method of comparing the mode resistance value and the variable resistance value has the following problems: a large area needs to be allocated to the resistor to reduce the deviation of the resistance value, and a large area also needs to be allocated to the switch to reduce the resistance value of the variable switch. In addition, the method of comparing the mode resistance value and the variable resistance value has another problem: due to temperature changes, the change in the resistance value of the internal resistor and the resistance value of the variable switch exceeds 20%, so the detection accuracy is reduced.

[0106] The mode resistance detection circuit 210 according to an embodiment of the present invention can use the reference current IREF instead of the variable resistance value, thereby removing the internal resistor and the variable switch SW that occupy a large area. Therefore, the mode resistance detection circuit 210 according to an embodiment of the present invention can reduce the area.

[0107] Furthermore, the mode resistance detection circuit 210 according to one embodiment of the present invention can use a reference current and a reference voltage that vary very little with temperature, thereby maintaining high detection accuracy even when the temperature varies.

[0108] Figure 8 is a flow chart illustrating a method for detecting a mode resistance of a display panel according to an embodiment of the present invention.

[0109] refer to Figure 8 , first, the mode resistance detection circuit 210 generates a reference current and applies the reference current to the mode resistance R_Panel ( S801 ).

[0110] For example, when the enable control signal becomes a high level, the mode resistance detection circuit 210 may start mode resistance detection when the first switch SW_R connected to the first pad P1 of the display panel 110 and the second switch SW_L connected to the second pad P2 of the display panel 110 are turned on. The mode resistance detection circuit 210 may generate a reference current and apply the generated reference current to the mode resistance R_Panel via the first pad P1 of the display panel 110.

[0111] Next, the mode resistance detection circuit 210 generates an initial reference voltage VR_SEL (S802). The mode resistance detection circuit 210 may select one of the multiple voltages as the initial reference voltage VR_SEL. The mode resistance detection circuit 210 may generate a reference voltage control signal for generating the initial reference voltage VR_SEL. The mode resistance detection circuit 210 may generate the initial reference voltage VR_SEL selected according to the reference voltage control signal.

[0112] In one embodiment, the mode resistance detection circuit 210 may select an intermediate voltage from voltages between the maximum voltage and the minimum voltage as the initial reference voltage VR_SEL.

[0113] In another embodiment, the mode resistance detection circuit 210 may select a maximum voltage as the initial reference voltage VR_SEL.

[0114] In another embodiment, the mode resistance detection circuit 210 may select a minimum voltage as the initial reference voltage VR_SEL.

[0115] Afterwards, when the number of comparisons between the detection voltage V_Panel and the reference voltage VR_SEL is greater than or equal to a preset value, the mode resistance detection circuit 210 completes the detection of the mode resistance ( S803 and S805 ).

[0116] When the number of comparisons between the detection voltage V_Panel and the reference voltage VR_SEL is equal to or greater than a preset value, the mode resistance detection circuit 210 may stop the detection operation of the mode resistance R_Panel and provide the user with a finally selected reference voltage or a finally selected reference voltage control signal. The user may determine the mode resistance R_Panel of the display panel 110 based on the finally selected reference voltage or the finally selected reference voltage control signal.

[0117] In addition, the mode resistance detection circuit 210 may determine a failure of the display panel 110 based on the final selected reference voltage or the final reference voltage control signal.

[0118] Next, the mode resistance detection circuit 210 compares the magnitudes of the detection voltage V_Panel and the reference voltage VR_SEL ( S804 ).

[0119] In the mode resistance detection circuit 210, the detection voltage V_Panel and the reference voltage VR_SEL are both input to the comparator 330, and an output value is obtained from the comparator 330 as a voltage comparison result. When the detection voltage V_Panel is greater than the reference voltage VR_SEL, the comparator 330 may output a high level signal as a voltage comparison result between the detection voltage V_Panel and the reference voltage VR_SEL. On the other hand, when the detection voltage V_Panel is less than the reference voltage VR_SEL, the comparator 330 may output a low level signal as a voltage comparison result between the detection voltage V_Panel and the reference voltage VR_SEL.

[0120] In one embodiment, the comparator 330 may compare the magnitudes of the detection voltage V_Panel and the reference voltage VR_SEL based on the clock signal CLK. The clock signal CLK may be input from the timing controller 116.

[0121] Next, when the detection voltage V_Panel is greater than the reference voltage VR_SEL, the mode resistance detection circuit 210 selects a new reference voltage between the maximum voltage and the reference voltage ( S806 ).

[0122] The mode resistance detection circuit 210 may select a voltage between a minimum voltage and a maximum voltage within a desired range as a new reference voltage VR_SEL.

[0123] In one embodiment, the mode resistance detection circuit 210 can select 2 N When the detection voltage V_Panel is greater than the reference voltage VR_SEL, the mode resistance detection circuit 210 can change the minimum voltage in the expected range to the current reference voltage. NSelect a voltage between the maximum voltage and the minimum voltage in the expected range as the new reference voltage VR_SEL. In other words, when the detection voltage V_Panel is greater than the reference voltage VR_SEL, the mode resistance detection circuit 210 can select a voltage between the maximum voltage and the minimum voltage in the expected range as the new reference voltage VR_SEL. N A voltage greater than the current reference voltage is selected from the voltages as the new reference voltage.

[0124] In one embodiment, when the detection voltage V_Panel is greater than the reference voltage VR_SEL, the mode resistance detection circuit 210 may change the minimum voltage within the expected range to the current reference voltage, and N The middle voltage is selected as the new reference voltage from the voltages between the maximum voltage and the minimum voltage within the expected range among the voltages.

[0125] Next, when the detection voltage V_Panel is less than the reference voltage VR_SEL, the mode resistance detection circuit 210 selects a new reference voltage between the minimum voltage and the reference voltage ( S807 ).

[0126] The mode resistance detection circuit 210 may select a voltage between a minimum voltage and a maximum voltage within a desired range as a new reference voltage VR_SEL.

[0127] In one embodiment, the mode resistance detection circuit 210 can select 2 N When the detection voltage V_Panel is less than the reference voltage VR_SEL, the mode resistance detection circuit 210 can change the maximum voltage within the expected range to the current reference voltage. Then, the mode resistance detection circuit 210 can select one of the two voltages as the reference voltage. N In other words, when the detection voltage V_Panel is less than the reference voltage VR_SEL, the mode resistance detection circuit 210 can select a voltage between the minimum voltage in the expected range and the current reference voltage as the new reference voltage VR_SEL. N A voltage smaller than the current reference voltage is selected from the voltages as the new reference voltage.

[0128] In one embodiment, when the detection voltage V_Panel is less than the reference voltage VR_SEL, the mode resistance detection circuit 210 may change the maximum voltage within the expected range to the current reference voltage, and N The middle voltage is selected as the new reference voltage from the voltages between the minimum voltage and the maximum voltage within the expected range among the voltages.

[0129] Next, the mode resistance detection circuit 210 generates a reference voltage control signal ( S808 ).

[0130] In one embodiment, the mode resistance detection circuit 210 can generate an N-bit reference voltage control signal for generating a selected reference voltage. In this case, the N-bit reference voltage control signal can include 2 N A reference voltage control signal. N The reference voltage control signals can correspond to 2 N voltage, and 2 N The voltages can correspond to 2 N The amplitude of the pattern resistor R_Panel.

[0131] In one embodiment, the mode resistance detection circuit 210 may change some bit values ​​of the N bits based on the voltage comparison result to generate an N-bit reference voltage control signal.

[0132] Specifically, when the detection voltage V_Panel is greater than the reference voltage VR_SEL, the mode resistance detection circuit 210 may maintain the bit value of the (i-1)th bit after the most significant bit and change the bit value of the (i)th bit from 0 to 1 to generate a reference voltage control signal, where i is the number of comparisons between the detection voltage V_Panel and the reference voltage VR_SEL.

[0133] On the other hand, when the detection voltage V_Panel is less than the reference voltage VR_SEL, the mode resistance detection circuit 210 may change the bit value of the (i-1)th bit after the most significant bit to 0 and the bit value of the (i)th bit from 0 to 1 to generate a reference voltage control signal.

[0134] Next, the mode resistance detection circuit 210 generates the selected reference voltage VR_SEL ( S809 ).

[0135] The mode resistance detection circuit 210 can generate the selected reference voltage VR_SEL using a plurality of resistors connected in series and a plurality of switches connected to nodes between the plurality of resistors. Specifically, the mode resistance detection circuit 210 can control the plurality of switches according to the reference voltage control signal so that the selected reference voltage VR_SEL is N A reference voltage VR_SEL selected from among the reference voltages is input to the comparator 330 .

[0136] The mode resistance detection circuit 210 may repeat S803 to S809 until the mode resistance detection is completed.

[0137] Fig. 9 is a diagram illustrating an exemplary process of detecting a mode resistance using a mode resistance detection circuit.

[0138] exist Fig. 9In other words, the mode resistance detection circuit 210 assumes that the 4-bit reference voltage control signal SEL[3:0] generates 2 4 One of the voltages is used as the reference voltage VR_SEL.

[0139] The mode resistance detection circuit 210 may start mode resistance detection using an enable control signal (EN control). For example, when the enable control signal becomes a high level, the mode resistance detection circuit 210 may start mode resistance detection when a first switch SW_R connected to a first pad P1 of the display panel 110 and a second switch SW_L connected to a second pad P2 of the display panel 110 are turned on. The mode resistance detection circuit 210 may generate a reference current and apply the generated reference current to the mode resistance R_Panel via the first pad P1 of the display panel 110.

[0140] The mode resistance detection circuit 210 may initialize the reference voltage control signal SEL[3:0] to “0000” and initialize the number of comparisons COUNT[2:0] between the detection voltage V_Panel and the reference voltage VR_SEL to “000”.

[0141] Since the comparison number COUNT[2:0] is less than the preset value 4, the mode resistance detection circuit 210 changes the comparison number COUNT[2:0] between the detection voltage V_Panel and the reference voltage VR_SEL to “001” and performs comparison between the detection voltage V_Panel and the reference voltage VR_SEL.

[0142] The mode resistance detection circuit 210 may change the reference voltage control signal SEL[3:0] to "1000", thereby generating the reference voltage VR_SEL according to the reference voltage control signal SEL[3:0] "1000". For example, when the reference voltage control signal SEL[3:0] and the mode resistance R_Panel have a relationship as shown in Table 1, the mode resistance detection circuit 210 may generate the reference voltage VR_SEL corresponding to the mode resistance R_Panel having an amplitude of "9" according to the reference voltage control signal SEL[3:0] "1000".

[0143] The mode resistance detection circuit 210 may compare the magnitudes of the detection voltage V_Panel detected according to the reference current applied to the mode resistance R_Panel and the reference voltage VR_SEL using the comparator 330 according to the clock signal CLK.

[0144] like Fig. 9As shown in , since the detection voltage V_Panel is greater than the reference voltage VR_SEL, the comparator 330 of the mode resistance detection circuit 210 can output a high level signal as a voltage comparison result between the detection voltage V_Panel and the reference voltage VR_SEL during the first clock cycle Phase-0.

[0145] Then, since the comparison number COUNT[2:0] is less than the preset value 4, the mode resistance detection circuit 210 changes the comparison number COUNT[2:0] between the detection voltage V_Panel and the reference voltage VR_SEL to '010' and performs comparison between the detection voltage V_Panel and the reference voltage VR_SEL.

[0146] The mode resistance detection circuit 210 can maintain the bit value of the most significant bit as 1 and change the bit value of the first bit after the most significant bit from 0 to 1, thereby generating a reference voltage control signal SEL[3:0]. As a result, the mode resistance detection circuit 210 can generate a reference voltage control signal SEL[3:0] "1100", and can change the reference voltage VR_SEL according to the reference voltage control signal SEL[3:0] "1100". For example, the mode resistance detection circuit 210 can generate a reference voltage VR_SEL corresponding to the mode resistance R_Panel having an amplitude of "13" according to the reference voltage control signal SEL[3:0] "1100".

[0147] The mode resistance detection circuit 210 may compare the magnitudes of the detection voltage V_Panel detected according to the reference current applied to the mode resistance R_Panel and the reference voltage VR_SEL using the comparator 330 according to the clock signal CLK.

[0148] Since the detection voltage V_Panel is lower than the reference voltage VR_SEL, the comparator 330 of the mode resistance detection circuit 210 may output a low level signal as a voltage comparison result between the detection voltage V_Panel and the reference voltage VR_SEL during the second clock cycle Phase- 1 .

[0149] Then, since the comparison number COUNT[2:0] is less than the preset value 4, the mode resistance detection circuit 210 changes the comparison number COUNT[2:0] between the detection voltage V_Panel and the reference voltage VR_SEL to '011' and performs comparison between the detection voltage V_Panel and the reference voltage VR_SEL.

[0150] The mode resistance detection circuit 210 may change the bit value of the first bit after the most significant bit to 0 and change the bit value of the second bit after the most significant bit from 0 to 1, thereby generating a reference voltage control signal SEL[3:0]. As a result, the mode resistance detection circuit 210 may generate a reference voltage control signal SEL[3:0] "1010", and may change the reference voltage VR_SEL according to the reference voltage control signal SEL[3:0] "1010". For example, the mode resistance detection circuit 210 may generate a reference voltage VR_SEL corresponding to the mode resistance R_Panel having an amplitude of "11" according to the reference voltage control signal SEL[3:0] "1010".

[0151] The mode resistance detection circuit 210 may compare the magnitudes of the detection voltage V_Panel detected according to the reference current applied to the mode resistance R_Panel and the reference voltage VR_SEL using the comparator 330 according to the clock signal CLK.

[0152] Since the detection voltage V_Panel is greater than the reference voltage VR_SEL, the comparator 330 of the mode resistance detection circuit 210 may output a high level signal as a voltage comparison result between the detection voltage V_Panel and the reference voltage VR_SEL during the third clock cycle Phase-2.

[0153] Then, since the comparison number COUNT[2:0] is less than the preset value 4, the mode resistance detection circuit 210 changes the comparison number COUNT[2:0] between the detection voltage V_Panel and the reference voltage VR_SEL to '100' and performs comparison between the detection voltage V_Panel and the reference voltage VR_SEL.

[0154] The mode resistance detection circuit 210 can maintain the bit value of the second bit after the most significant bit as 1 and change the bit value of the third bit after the most significant bit from 0 to 1, thereby generating a reference voltage control signal SEL[3:0]. As a result, the mode resistance detection circuit 210 can generate a reference voltage control signal SEL[3:0] "1011", and can change the reference voltage VR_SEL according to the reference voltage control signal SEL[3:0] "1011". For example, the mode resistance detection circuit 210 can generate a reference voltage VR_SEL corresponding to the mode resistance R_Panel having an amplitude of "12" according to the reference voltage control signal SEL[3:0] "1011".

[0155] The mode resistance detection circuit 210 may compare the magnitudes of the detection voltage V_Panel detected according to the reference current applied to the mode resistance R_Panel and the reference voltage VR_SEL using the comparator 330 according to the clock signal CLK.

[0156] Since the detection voltage V_Panel is greater than the reference voltage VR_SEL, the comparator 330 of the mode resistance detection circuit 210 may output a high level signal as a voltage comparison result between the detection voltage V_Panel and the reference voltage VR_SEL during the fourth clock cycle Phase-3.

[0157] Then, since the comparison number COUNT[2:0] is equal to the preset value 4, the mode resistance detection circuit 210 changes the comparison number COUNT[2:0] between the detection voltage V_Panel and the reference voltage VR_SEL to “101”, and completes the detection of the mode resistance.

[0158] The mode resistance detection circuit 210 may provide the final reference voltage control signal to the user. The user may determine that the mode resistance R_Panel of the display panel 110 is 12 kΩ based on the final reference voltage control signal “1011”.

[0159] Those skilled in the art to which the present invention pertains will appreciate that the present invention described above may also be implemented in other specific forms without changing its technical concept or basic features.

[0160] In addition, the methods described herein may be implemented at least in part using one or more computer programs or components. The component may be provided as a set of computer instructions on a computer-readable medium, the computer-readable medium including volatile and non-volatile memory or machine-readable medium. The above instructions may be provided as software or firmware, and may be implemented in whole or in part in a hardware structure such as an ASIC, FPGA, DSP or other similar device. The above instructions may be configured to be executed by one or more processors or other hardware structures, and when executing the above computer instruction set, the one or more processors or other hardware structures perform all or part of the methods and processes disclosed herein.

[0161] The present specification described above is not limited to the aforementioned embodiments and drawings, and it is obvious to those skilled in the art that various substitutions, modifications and changes can be made within the scope without departing from the technical spirit of the present specification. Therefore, the scope of the present specification is represented by the attached claims, and should be interpreted as all changes or modifications derived from the meaning and scope of the claims and their equivalent concepts are included in the scope of the present specification.

[0162] Modes for carrying out the invention

[0163] Various ways for practicing the invention have been described in the foregoing subheading "Detailed Description of the Invention".

[0164] Industrial Applicability

[0165] The present invention is applicable to any type of display device (eg, LCD, LED, OLED, etc.), and thus can be implemented industrially.

Claims

1. A mode resistance detection circuit, comprising: a current source generator configured to generate a reference current and apply the reference current to a mode resistor; a reference voltage generator configured to generate a reference voltage; a comparator configured to compare a magnitude of a detection voltage detected according to the reference current applied to the mode resistor with a magnitude of the reference voltage and output a voltage comparison result; as well as A circuit controller is configured to output a reference voltage control signal for controlling the reference voltage generator according to the voltage comparison result.

2. The mode resistance detection circuit according to claim 1, wherein: The current source generator comprises: a current source connected to a first power source; a first transistor including a first drain connected to the current source, a first gate connected to the first drain, and a first source connected to a second power source; and The second transistor includes a second drain connected to the mode resistor, a second gate connected to the first gate of the first transistor, and a second source connected to the second power source.

3. The mode resistance detection circuit according to claim 2, wherein: A first reference current flows through the first transistor, and a second reference current copied from the first reference current flows through the second transistor.

4. The mode resistance detection circuit according to claim 2, wherein: The first power source is a low potential voltage, and the second power source is a high potential voltage.

5. The mode resistance detection circuit according to claim 2, wherein: A second drain of the second transistor is connected to the first power source via the mode resistor.

6. The mode resistance detection circuit according to claim 2, wherein: The current source generator further comprises: A bias transistor is configured to provide a constant bias current to the first transistor.

7. The mode resistance detection circuit according to claim 2, wherein: The current source generator further comprises: A channel length modulation prevention circuit is configured to copy a first drain voltage of the first transistor to a second drain voltage of the second transistor.

8. The mode resistance detection circuit according to claim 7, wherein: The channel length modulation prevention circuit comprises: a differential amplifier configured to amplify a difference between the first drain voltage of the first transistor and the second drain voltage of the second transistor; and The third transistor includes a third drain connected to the mode resistor, a third gate connected to the differential amplifier, and a third source connected to the second drain of the second transistor.

9. The mode resistance detection circuit of claim 1, wherein the circuit controller is configured to: Based on the voltage comparison result, select 2 N One of the voltages is used as the reference voltage; generating an N-bit reference voltage control signal for generating a selected reference voltage; as well as The N-bit reference voltage control signal is output to the reference voltage generator.

10. The mode resistance detection circuit according to claim 9, wherein: The circuit controller is configured to: When the reference voltage is greater than the detection voltage, the N Select a voltage smaller than the current reference voltage from among the voltages as a new reference voltage; as well as When the reference voltage is less than the detection voltage, the N Select a voltage greater than the current reference voltage from the voltages as the new reference voltage.

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