Crack detection device, crack detection method, and data driving device

Abstract

The crack detection apparatus may include a signal providing unit, a resistance adjusting unit, a path control unit, and a detection unit. The path control unit may select a first path and a second path. The detection signal may pass through the at least one resistor through the first path. The detection signal may pass through a crack detection target of the plurality of crack detection targets through a second path. When the first path is selected, the at least one resistor may be connected to the signal providing unit. When the second path is selected, the crack detection target may be connected to the signal providing unit. The detection unit may detect a crack in the one crack detection target based on a first detection signal obtained from the output signal on the first path and a second detection signal obtained from the output signal on the second path.

Description

Technical Field

[0001] The embodiments relate to a crack detection device, a crack detection method, and a data driven device. Background Art

[0002] As display technology advances, flexible displays, transparent displays, etc. are being developed. A flexible display may be a display that can be bent, folded, or rolled up.

[0003] Flexible displays are not only thin and light, but also impact-resistant. Since flexible displays have bending properties, they have the advantage of being able to be manufactured in various shapes. In particular, flexible displays can be applied in industrial fields where the application of existing glass substrate-based displays is limited or impossible.

[0004] In a flexible display, a panel, various components, and circuits are manufactured based on plastic to have a bending property. However, a problem with the flexible display is that defects such as cracks occur during manufacturing or use due to its bending property. Summary of the invention

[0005] [Technical issues]

[0006] Embodiments are directed to solving the above-referenced and other problems.

[0007] Another object of an embodiment is to provide a crack detection device, a crack detection method, and a data driving device capable of detecting defects such as cracks.

[0008] The technical problems of the embodiments are not limited to the technical problems described in this item but include technical problems that can be understood through the description of the invention.

[0009] [Technical solution]

[0010] In order to achieve the above or other purposes, according to a first aspect of an embodiment, a crack detection device includes: a signal providing unit, which is configured to provide a detection signal; a resistance adjusting unit, which is configured to use a plurality of resistors to adjust a reference resistance value to correspond to resistance values ​​of a plurality of crack detection targets; a path control unit, which is configured to select a first path and a second path, wherein the detection signal passes through at least one resistor through the first path, and the detection signal passes through one crack detection target among the plurality of crack detection targets through the second path; and a detection unit, which is configured to detect a crack in the one crack detection target based on a first detection signal obtained from an output signal on the first path and a second detection signal obtained from an output signal on the second path, wherein when the first path is selected, the at least one resistor is connected to the signal providing unit, and when the second path is selected, the crack detection target is connected to the signal providing unit.

[0011] One cycle may include a first interval and a second interval. In this case, the detection unit may obtain the first detection signal during the first interval, and obtain the second detection signal during the second interval.

[0012] The plurality of resistors may be connected in parallel to each other. In this case, the resistance adjustment unit may include a plurality of first switches configured to be respectively connected in series to the plurality of resistors.

[0013] The resistance adjustment unit may adjust the reference resistance value to correspond to the resistance value of the one crack detection target by switching the plurality of first switches.

[0014] The resistance adjusting unit may include a second switch connected in parallel with the resistor.

[0015] The path control unit may select a third path through which the detection signal passes through the second switch. The detection unit may detect cracks in the one crack detection target based on the first detection signal, the second detection signal, and the third detection signal. The third detection signal may be obtained on the selected third path.

[0016] One cycle may include a third interval. In this case, the detection unit may obtain the third detection signal during the third interval.

[0017] According to a second aspect of an embodiment for achieving the above or other purposes, a crack detection method includes: a detection signal is provided by a signal providing unit; a reference resistance value is adjusted by a resistance adjustment unit to correspond to the resistance values ​​of multiple crack detection targets using multiple resistors; a first path and a second path are selected by a path control unit, wherein the detection signal passes through at least one resistor through the first path, and the detection signal passes through one crack detection target among the multiple crack detection targets through the second path; and a detection unit detects a crack in the one crack detection target based on a first detection signal obtained from an output signal on the first path and a second detection signal obtained from an output signal on the second path, wherein when the first path is selected, the at least one resistor is configured to be connected to the signal providing unit, and when the second path is selected, the crack detection target is configured to be connected to the signal providing unit.

[0018] The crack detection method may include selecting a third path through which the detection signal passes through a second switch connected in parallel with the resistor. In this case, the detection of the crack may include detecting the crack in the one crack detection target based on the first detection signal, the second detection signal, and the third detection signal. The third detection signal may be obtained on the selected third path.

[0019] According to a third aspect of an embodiment for achieving the above or other purposes, a data driving device configured to provide a data signal to a panel includes a plurality of source driving circuits, each source driving circuit including a crack detection device, wherein the crack detection device includes: a signal providing unit, the signal providing unit being configured to provide a detection signal; a first resistance adjusting unit, the first resistance adjusting unit being configured to adjust a reference resistance value to correspond to resistance values ​​of a plurality of crack detection targets using a plurality of first resistors; a path control unit, the path control unit being configured to select a first path and a second path, wherein the detection signal passes through at least one resistor through the first path, and the detection signal passes through one crack detection target among the plurality of crack detection targets through the second path; and a detection unit, the detection unit being configured to detect a crack in the one crack detection target based on a first detection signal obtained from an output signal on the first path and a second detection signal obtained from an output signal on the second path, wherein when the first path is selected, the at least one resistor is connected to the signal providing unit, and when the second path is selected, the crack detection target is connected to the signal providing unit.

[0020] One of the plurality of source driving circuits may be designated as a main source driving circuit, and the remaining source driving circuits may be designated as slave source driving circuits. In this case, in the main source driving circuit, the detection unit may cause the detection signal to pass through the panel and the plurality of slave source driving circuits to obtain the first detection signal from the panel as the one crack detection target.

[0021] In the master source driving circuit, the crack detection device may include a second resistance adjusting unit configured to offset resistance values ​​of the plurality of slave source driving circuits using a plurality of second resistors.

[0022] One of the plurality of source driving circuits may be designated as a main source driving circuit, and the remaining source driving circuits may be designated as slave source driving circuits. In this case, in the main source driving circuit, the detection unit may cause the detection signal to pass through the main source driving circuit to obtain the first detection signal from the main source driving circuit as the one crack detection target.

[0023] One of the plurality of source driving circuits may be designated as a master source driving circuit, and the remaining source driving circuits may be designated as slave source driving circuits. In this case, in one of the plurality of designated slave source driving circuits, the detection unit may cause the detection signal to pass through the one slave source driving circuit to obtain the first detection signal from the one slave source driving circuit as the one crack detection target.

[0024] The plurality of first resistors may be connected in parallel to each other. The first resistance adjusting unit may include a plurality of first switches respectively connected in series to the plurality of first resistors.

[0025] The first resistance adjusting unit may adjust the reference resistance value to correspond to the resistance value of the one crack detection target by switching the plurality of first switches.

[0026] The first resistance adjusting unit may include a second switch connected in parallel with the first resistor.

[0027] The path control unit may select a third path through which the detection signal passes through the second switch. The detection unit may detect cracks in the one crack detection target based on the first detection signal, the second detection signal, and the third detection signal. The third detection signal may be obtained on the selected third path.

[0028] [Beneficial Effects]

[0029] Effects of the crack detection device, the crack detection method, and the data driving device according to the embodiment are described as follows.

[0030] According to at least one embodiment, for each of a plurality of crack detection targets, cracks may be accurately and quickly detected.

[0031] According to at least one embodiment, cracks may be detected by taking into account resistance values ​​present in a signal providing unit, a multiplexer, a detection unit, etc., so that the accuracy of crack detection may be significantly improved.

[0032] According to at least one embodiment, since the internal resistance values ​​of multiple third switches of the second resistance adjustment unit are reflected in the first detection signal obtained on the first path, the internal resistance value of each switch used to connect multiple slave source driving circuits reflected in the second detection signal obtained on the second path through the panel is offset, thereby preventing errors in crack detection of the panel. BRIEF DESCRIPTION OF THE DRAWINGS

[0033] Figure 1 is a block diagram of a display device according to a first embodiment.

[0034] Figure 2 A crack detection device according to a first embodiment is shown.

[0035] Figure 3 Shows Figure 2 detection unit.

[0036] Figure 4 is a circuit diagram of a resistance adjusting unit according to the first embodiment.

[0037] Figure 5 is an operation waveform diagram of the crack detection device according to the first embodiment.

[0038] Figure 6a is Figure 2 An operation waveform diagram of detecting the first crack detection target in the detection unit.

[0039] Figure 6b is Figure 2 An operation waveform diagram of detecting a second crack detection target in a detection unit.

[0040] Figure 7 A state in which the path control unit operates to obtain a first detection signal on a first path is shown.

[0041] Figure 8 A state in which the path control unit operates to obtain a second detection signal on the second path is shown.

[0042] Fig. 9The detection pads provided on the panel are shown.

[0043] Fig.10 is a circuit diagram of a resistance adjusting unit according to a second embodiment.

[0044] Fig.11 is another operation waveform diagram of the crack detection device according to the first embodiment.

[0045] Fig.12 A state in which the path control unit operates to obtain a third detection signal on the third path is shown.

[0046] Fig.13 is a block diagram of a display device according to a second embodiment.

[0047] Fig.14 A crack detection device according to a second embodiment is shown.

[0048] Fig.15 yes Fig.14 A circuit diagram of a first resistance adjusting unit and a second resistance adjusting unit.

[0049] Fig.16 The crack detection device according to the second embodiment is shown detecting a crack on a panel.

[0050] Fig.17 It shows the state in which the detection signal passes through the first resistance adjustment unit and the second resistance adjustment unit when a crack on the panel is detected.

[0051] The size, shape, dimensions, etc. of the elements shown in the drawings may be different from the actual elements. In addition, although the same elements are shown in different sizes, shapes, dimensions, etc. between the drawings, this is only an example on the drawings, and the same elements have the same size, shape, dimensions, etc. between the drawings. DETAILED DESCRIPTION

[0052] Hereinafter, the embodiments disclosed in this specification will be described in detail with reference to the accompanying drawings, but regardless of the figure numerals, the same or similar elements are given the same figure numerals, and their redundant descriptions will be omitted. Considering the ease of writing the specification, the suffixes "module" and "unit" of the elements used in the following description can be given or used interchangeably, and they themselves do not have different meanings or functions from each other. In addition, the accompanying drawings are for easy understanding of the embodiments disclosed in this specification, and the technical concepts disclosed in this specification are not limited to the accompanying drawings. In addition, when an element such as a layer, a region, or a substrate is referred to as being "on" another element, this means that it can be directly on another element or there are other intermediate elements between them.

[0053] In the following, "~module", "~unit", etc. may be configured as a "~circuit". "~module", "~unit", etc. may be configured as an integrated circuit. In the following, reference numerals missing from the corresponding drawings may be replaced by reference numerals of components having the same function or value in other drawings.

[0054] [Display Device According to First Embodiment]

[0055] Figure 1 is a block diagram of a display device according to a first embodiment.

[0056] refer to Figure 1 , the display device 100 according to the embodiment may include a panel 110 and a display driving device 120 .

[0057] The display device 100 may include a flexible display device having a bending characteristic. The embodiment may also be applied to a rigid display device without a bending characteristic. Examples of the flexible display device 100 include an organic light emitting element (OLED) display device 100, a liquid crystal display device 100, a field emission display device 100, an electrophoretic display device 100, and the like.

[0058] The panel 110 may include a plurality of gate lines GL1 to GLm, a plurality of data lines DL1 to DLn, and a plurality of pixels P. The plurality of pixels P may be connected to the plurality of gate lines GL1 to GLm and the plurality of data lines DL1 to DLn.

[0059] The panel 110 may receive a data signal in units of frames and display an image corresponding to the data signal.

[0060] Meanwhile, the display driving device 120 may provide a data signal to the panel 110 in units of frames and display an image on the panel 110. The display driving device 120 may include a data processing device 130, a gate driving device 150, and a data driving device 140.

[0061] At least one or more of the data processing device 130, the gate driving device 150, and the data driving device 140 may be configured as an integrated circuit. The data processing device 130 may include a timing controller. The data processing device 130 may be referred to as a processor, a microprocessor, a microcontroller unit (MCU), a control device, a control circuit, a control IC, etc.

[0062] The data processing device 130 may generate control signals GCS and DCS for driving the gate driving device 150 and the data driving device 140 by using various timing signals including a vertical synchronization signal Vsync, a horizontal synchronization signal Hsync, a data enable signal DE (Data Enable), a clock signal CLK, etc. from an external system (not shown).

[0063] The gate driving device 150 may shift the scan pulse based on the gate control signal GCS provided from the data processing device 130 and sequentially provide the scan pulse to the gate lines GL1 to GLm.

[0064] Meanwhile, the data driving device 140 may convert the digital data RGB′ into analog data signals according to the data control signal DCS from the data processing device 130 , and provide the analog data signals to the panel 110 for each line.

[0065] Meanwhile, in the display device 100 according to the embodiment, the panel 110 or the display driving device 120 has a bending characteristic of a flexible display, and thus there is a problem of cracks occurring during manufacturing or product use.

[0066] Hereinafter, various embodiments in which defects such as cracks can be detected will be described.

[0067] Figure 2 A crack detection device according to a first embodiment is shown. Figure 3 Shows Figure 2 detection unit.

[0068] refer to Figure 2 and Figure 3 The crack detection device 200 according to the first embodiment may include a signal providing unit 210 , a resistance adjusting unit 220 , a path control unit 230 , and a detection unit 240 .

[0069] The signal providing unit 210 may provide a detection signal RMCP. The detection signal RMCP may be a DC voltage having a high level, but is not limited thereto. The signal providing unit 210 may adjust the high level of the DC voltage. The detection signal RMCP may be provided to the path control unit 230. The signal providing unit 210 may provide a reference signal REFTOP. The reference signal REFTOP may be provided to the comparator 242 of the detection unit 240.

[0070] The resistance adjusting unit 220 may adjust the resistance values ​​Rref11 to Rref1k to respectively correspond to the resistance values ​​R1 and R2 of the plurality of crack detection targets 201 and 202. The crack detection targets 201 and 202 may represent targets on which crack detection is to be performed. Figure 1 The panel 110 or the driving device shown may be the crack detection targets 201 and 202. For example, the data processing device 130, the data driving device 140, the gate driving device 150, etc. may be the crack detection targets 201 and 202. When the data driving device 140 includes a plurality of source driving circuits 140-1 to 140-L, each of the plurality of source driving circuits 140-1 to 140-L may be the crack detection targets 201 and 202.

[0071] like Figure 4 As shown, the resistance adjustment unit 220 may include a plurality of resistors 220-1 to 220-k. The plurality of resistors 220-1 to 220-k may be connected in parallel to each other. The plurality of resistors 220-1 to 220-k may respectively have a plurality of resistance values ​​Rref11 to Rref1k different from each other. For example, the resistance value Rref11 of the first resistor 220-1 may be the smallest, and the resistance value Rref1k of the Kth resistor 220-k may be the largest.

[0072] The resistance adjusting unit 220 may include a plurality of switches SW11 to SW1k. The plurality of switches SW11 to SW1k may be connected in series to the plurality of resistors 220-1 to 220-k, respectively.

[0073] The resistance adjusting unit 220 may adjust the reference resistance value to correspond to the resistance values ​​R1 and R2 of the plurality of crack detection targets 201 and 202 , respectively, by switching the plurality of switches SW11 to SW1 k.

[0074] As an example, the resistance values ​​R1 and R2 of the plurality of crack detection targets 201 and 202 may be respectively the same as the resistance values ​​Rref11 to Rref1k of the plurality of resistors 220-1 to 220-k. For example, the resistance value Rref1k of the resistor 220-k may be the same as the resistance value R1 of the first crack detection target 201. In this case, when crack detection is performed on the first crack detection target 201, the resistance adjustment unit 220 may turn on the switch SW1k to adjust the reference resistance value using the resistance value Rref1k of the resistor 220-k. For example, the resistance value Rref12 of the resistor 220-2 may be the same as the resistance value of the second crack detection target 202. In this case, when crack detection is performed on the second crack detection target 202, the resistance adjustment unit 220 may turn on the switch SW12 to adjust the resistance value Rref12 of the resistor 220-2 to the reference resistance value. Therefore, when the resistance values ​​R1 and R2 of the plurality of crack detection targets 201 and 202 are respectively equal to the resistance values ​​Rref11 to Rref1k of the plurality of resistors 220 - 1 to 220 - k, the resistance adjustment unit 220 may switch one switch when detecting a crack.

[0075] As another example, the resistance values ​​R1 and R2 of the plurality of crack detection targets 201 and 202 may be respectively different from the resistance values ​​Rref11 to Rref1k of the plurality of resistors 220-1 to 220-k. For example, the resistance value R1 of the first crack detection target 201 may be equal to the total resistance value of the resistance value Rref1(k-1) of the resistor 220-(k-1) and the resistance value Rref1k of the resistor 220-k. In this case, when crack detection is performed on the first crack detection target 201, the resistance adjustment unit 220 may turn on the switches SW1(k-1) and SW1k to make the reference resistance value equal to the resistance value R1 of the first crack detection target 201. Therefore, when the resistance values ​​R1 and R2 of the plurality of crack detection targets 201 and 202 are respectively different from the resistance values ​​Rref11 to Rref1k of the plurality of resistors 220-1 to 220-k, the resistance adjustment unit 220 may switch at least one or more switches when detecting a crack.

[0076] At the same time, the path control unit 230 can select multiple paths ( Figure 7 310 and Figure 8 320). For example, the path control unit 230 may include a multiplexer, but is not limited thereto. The path may include a first path 310 and a second path 320. The first path 310 may be a path for obtaining a first detection signal DOUT1 using a reference resistance value adjusted by the resistance adjustment unit 220. The second path 320 may be a path for obtaining a second detection signal DOUT2 using a resistance value of one crack detection target among the plurality of crack detection targets 201 and 202. Since the second detection signal DOUT2 may be obtained for each of the plurality of crack detection targets 201 and 202, the second path 320 may be configured in plurality.

[0077] For each of the plurality of crack detection targets 201 and 202, the path control unit 230 may select the first path 310 to obtain the first detection signal DOUT1 using the first path 310, or select the second path 320 to obtain the second detection signal DOUT2 using the second path 320. The path control unit 230 may select the first path 310 so that the plurality of crack detection targets 201 and 202 are connected to the signal providing unit 210 and the detection unit 240. The path control unit 230 may select the second path 320 so that the resistance adjusting unit 220 is connected to the signal providing unit 210 and the detection unit 240.

[0078] When the first path 310 is selected, the detection unit 240 can obtain the first detection signal DOUT1 ( Figure 7When the first path 310 is selected, the detection signal RMCP can pass through at least one resistor 220-1 to 220-k for adjusting the reference resistance value to obtain the first detection signal DOUT1. When the second path 320 is selected, the detection unit 240 can obtain the second detection signal DOUT2 on the second path 320 ( Figure 8 ). When the second path 320 is selected, the detection signal RMCP may pass through one of the plurality of crack detection targets 201 and 202 to obtain the second detection signal DOUT2.

[0079] Meanwhile, the detection unit 240 may detect a crack of each of the plurality of crack detection targets 201 and 202 based on the first detection signal DOUT1 obtained on the first path 310 and the second detection signal DOUT2 obtained on the second path 320 .

[0080] For example, the first output signal RMCN of the resistance adjustment unit 220 passing through the first path 310 may be provided to the detection unit 240. The detection unit 240 may obtain the first detection signal DOUT1 by performing a calculation process on the first output signal RMCN. For example, the second output signal INT_OUT of the specific crack detection targets 201 and 202 passing through the second path 320 may be provided to the detection unit 240. The detection unit 240 may obtain the second detection signal DOUT2 by performing a calculation process on the second output signal INT_OUT. The detection unit 240 may detect cracks in the specific crack detection targets 201 and 202 based on the first detection signal DOUT1 and the second detection signal DOUT2. The first detection signal DOUT1 and the second detection signal DOUT2 may each have a code value consisting of a binary number.

[0081] refer to Figure 3 , the detection unit 240 may include an integrator 241 , a comparator 242 , and a code generator 244 .

[0082] The integrator 241 may perform an integral calculation on the first output signal RMCN output on the first path 310 or the second path 320, and output a second output signal INT_OUT. The second output signal INT_OUT may have a slope to increase over time because it performs an integral operation on the first output signal RMCN. The slope may vary according to the resistance values ​​R1 and R2 of the plurality of crack detection targets 201 and 202, respectively, or the reference resistance value adjusted by the resistance adjustment unit 220. For example, the slope may decrease as the resistance values ​​R1 and R2 increase.

[0083] The comparator 242 may compare the second output signal INT_OUT with the reference signal REFTOP and output a third output signal D_CMP_O. The reference signal REFTOP may be generated by the signal providing unit 210, but is not limited thereto. The reference signal REFTOP may be constant regardless of the respective resistance values ​​R1 and R2 of the plurality of crack detection targets 201 and 202, but is not limited thereto. However, as described above, the slope of the second output signal INT_OUT may be different according to the resistance values ​​R1 and R2 of the plurality of crack detection targets 201 and 202, respectively.

[0084] In this case, when detecting a crack of each of the multiple crack detection targets 201 and 202, the time point at which the second output signal INT_OUT intersects with the reference signal REFTOP may be different. For example, the smaller the corresponding resistance values ​​R1 and R2 of the multiple crack detection targets 201 and 202, the greater the slope of the second output signal INT_OUT, so that the time point at which the second output signal INT_OUT intersects with the reference signal REFTOP may be shortened. Therefore, the operation intervals of the integrator 241 and the comparator 242 may be different according to the resistance values ​​R1 and R2 of the multiple crack detection targets 201 and 202, respectively. Each operation interval of the integrator 241 and the comparator 242 may be controlled by the control signal AD_START ( Figure 5 , Figure 6a and Figure 6b )Decide.

[0085] For example, the start time of each operation interval of the integrator 241 and the comparator 242 may be the same regardless of the respective resistance values ​​R1 and R2 of the plurality of crack detection targets 201 and 202. However, the end time of each operation interval of the integrator 241 and the comparator 242 may vary according to the respective resistance values ​​R1 and R2 of the plurality of crack detection targets 201 and 202. As the respective resistance values ​​R1 and R2 of the plurality of crack detection targets 201 and 202 increase, the end time of each operation interval of the integrator 241 and the comparator 242 may move further away from the start time.

[0086] Meanwhile, the third output signal D_CMP_O may include a pulse signal. The rising time of the pulse signal may be the time when the second output signal INT_OUT intersects the reference signal REFTOP. The falling time of the pulse signal may be consistent with the end time of each operation interval of the integrator 241 and the comparator 242.

[0087] Meanwhile, the detection unit 240 may include a level shifter 243. The level shifter 243 may be connected between the comparator 242 and the code generator 244. The third output signal D_CMP_O of the comparator 242 may be provided to the level shifter 243. The level shifter 243 may output a fourth output signal having a level lower than that of the third output signal D_CMP_O. The fourth output signal may be provided to the code generator 244. The level shifter 243 may be an analog-to-digital converter that converts an analog signal into a DC signal, but is not limited thereto. The code generator 244 may generate a code value using the fourth output signal converted into a digital signal by the level shifter 243. Therefore, the code value may be generated by counting using a frequency modulated by a clock dividing option in a digital counter (rather than an analog counter), thereby preventing overflow. In the case of clock division, operation may be performed at a speed of up to 154 MHz divided by 2, 4, or 8. Overflow may mean that when the second output signal INT_OUT does not intersect the reference signal REFTOP within a set time period, the third output signal D_CMP_O is not generated, resulting in an error in which the count is not completed and the detection signal is not obtained. However, according to an embodiment, since the code generator 244 counts using a frequency modulated by a clock division option in a digital counter, the desired count can be performed within a set time period, so that overflow can be prevented, and an accurate code value can be generated, thereby improving the accuracy of crack detection.

[0088] When the code generator 244 uses an analog counter for counting, the level shifter 243 may be omitted. That is, the third output signal D_CMP_O output by the comparator 242 may be provided to the code generator 244 without passing through the level shifter 243.

[0089] Reference again Figure 3 , the code generator 244 may generate a code value based on the third output signal D_CMP_O or the fourth output signal.

[0090] For example, the code value may be generated by counting the rising time of the third output signal D_CMP_O or the fourth output signal. As the rising time of the third output signal D_CMP_O or the fourth output signal becomes later in time, the number of counts may increase. As the number of counts increases, a larger code value may be generated, but is not limited thereto.

[0091] For example, based on the predetermined detection interval ( Figure 6a D11 and D12 and Figure 6bThe code value is generated by counting the number of times counted during the detection intervals (D11, D12, D21, and D22). The detection intervals (D11, D12, D21, and D22) may be intervals between the rising time of the control signal AD_START and the rising time of the third output signal D_CMP_O or the fourth output signal.

[0092] The code value may constitute the detection signal DOUT, but is not limited thereto. That is, the detection signal DOUT may include the code value. Therefore, the code generator 244 may generate the detection signal DOUT including different code values ​​according to the resistance values ​​R1 and R2 of the plurality of crack detection targets 201 and 202, respectively, or the reference resistance value adjusted by the resistance adjustment unit 220.

[0093] At the same time, if Fig. 9 As shown, a detection pad 112 may be provided on the panel 110. The detection pad 112 may be formed of a conductive material. For example, the detection pad 112 may be made of a metal or a conductive oxide film (e.g., ITO), but is not limited thereto. The detection pad 112 may have a predetermined resistance value. The resistance value of the detection pad 112 may be the resistance value R1 of the panel 110 as the crack detection target 201 and 202. Therefore, the resistance value R1 of the panel 110 and the resistance value of the detection pad 112 may be mixed.

[0094] For example, when the second detection signal DOUT2 is obtained via the detection pad 112 of the panel 110, the second detection signal DOUT2 may include a code value corresponding to the resistance value R1 of the detection pad 112 provided on the panel 110. When detecting a crack in the panel 110, the resistance adjustment unit 220 may adjust the reference resistance value to the resistance value R1 of the detection pad 112 provided on the panel 110. In this case, when the first detection signal DOUT1 is obtained via the resistance adjustment unit 220, the first detection signal DOUT1 may include a code value corresponding to the adjusted reference resistance value.

[0095] [Crack detection operation method]

[0096] Reference below Figures 5 to 8 Explain how to operate crack detection. Figures 1 to 4 Can be used in Figures 5 to 8 Figure numerals omitted in the description. Figures 5 to 8 The operation method of crack detection of the first crack detection target is shown, but it can also be Figures 5 to 8 The illustrated drawings make it easy to understand the operation method of crack detection of other crack detection targets.

[0097] Figure 5 is an operation waveform diagram of the crack detection device according to the first embodiment. Figure 6a is Figure 2An operation waveform diagram of detecting the first crack detection target in the detection unit. Figure 7 A state in which the path control unit operates to obtain a first detection signal on a first path is shown. Figure 8 A state in which the path control unit operates to obtain a second detection signal on the second path is shown.

[0098] In an embodiment, the detection signal DOUT for the crack detection targets 201 and 202 can be obtained in one cycle. The periodic operation of the crack detection device 200 according to the embodiment can be controlled by the enable signal PCD_EN. The crack detection device 200 according to the embodiment can operate in each cycle in response to the high level of the enable signal PCD_EN to obtain the detection signal DOUT for the crack detection targets 201 and 202.

[0099] One cycle may include a first interval T11 and a second interval T12. In this case, the first detection signal DOUT1 may be obtained in the first interval T11, and the second detection signal DOUT2 may be obtained in the second interval T12. The first detection signal DOUT1 may be obtained on the first path 310, and the second detection signal DOUT2 may be obtained on the second path 320. To this end, the path control unit 230 may select the first path 310 or the second path 320.

[0100] The path control unit 230 may receive a control signal PCD_CTL, a first enable signal RREF_SEN, and a second enable signal RPANEL_SEN. The control signal PCD_CTL may be a signal for controlling the selection of each of the plurality of crack detection targets 201 and 202. The width of the high level of the control signal PCD_CTL may be the same as the width of the high level of the enable signal PCD_EN, but is not limited thereto. The first enable signal RREF_SEN may be a signal for controlling the selection of the first path 310 passing through the resistance adjustment unit 220, the reference resistance value of the resistance adjustment unit 220 being adjusted to the resistance values ​​R1 and R2 of the selected crack detection targets 201 and 202. The second enable signal RPANEL_SEN may be a signal for controlling the selection of the second path 320 passing through the selected crack detection targets 201 and 202.

[0101] The control signal PCD_CTL and the first enable signal RREF_SEN may be provided to the path control unit 230 at the same time, and the second enable signal RPANEL_SEN may be provided to the path control unit 230 at a later time than the first enable signal RREF_SEN, but is not limited thereto. The control signal PCD_CTL may be consistent with one cycle, but is not limited thereto. The first enable signal RREF_SEN may be consistent with the first interval T11 of one cycle, and the second enable signal RPANEL_SEN may be consistent with the second interval T12 of one cycle, but is not limited thereto. The rising time of the control signal PCD_CTL may be the same as the rising time of the first enable signal RREF_SEN, and the rising time of the control signal PCD_CTL may be the same as the falling time of the second enable signal RPANEL_SEN. The rising time of the second enable signal RPANEL_SEN may be the same as the falling time of the first enable signal RREF_SEN or later than the falling time of the first enable signal RREF_SEN.

[0102] <Operation in First Section T11>

[0103] like Figure 7 As shown, during the first interval T11 , the path control unit 230 may select the first path 310 to connect the resistance adjustment unit 220 to the signal providing unit 210 and the detection unit 240 .

[0104] First, the path control unit 230 may perform path control of the first crack detection target 201 in response to the control signal PCD_CTL.

[0105] The path control unit 230 may select the first path 310 in response to the first enable signal RREF_SEN, so that the resistance adjustment unit 220 may be connected to the signal providing unit 210 and the detection unit 240. At this time, the reference resistance value in the resistance adjustment unit 220 may be adjusted to the resistance value R1 of the first crack detection target 201. The detection signal RMCP of the signal providing unit 210 may be output to the detection unit 240 via the path control unit 230 and the resistance adjustment unit 220. Therefore, the first output signal RMCN generated by the detection signal RMCP via the resistance adjustment unit 220 may be output to the detection unit 240. The first output signal RMCN may be a voltage or a current.

[0106] The detection unit 240 can obtain the first detection signal DOUT1 based on the first output signal RMCN. Figure 3 , Figure 5 and Figure 6a As shown, the integrator 241 and the comparator 242 may operate in response to the control signal AD_START.

[0107] The rising time of the control signal AD_START may be later than the rising time of the first enable signal RREF_SEN or the second enable signal RPANEL_SEN. That is, the interval between the rising time of the first enable signal RREF_SEN or the second enable signal RPANEL_SEN and the rising time of the control signal AD_START may be defined as an initialization interval ( Figure 6a INT11 and INT12 as well as Figure 6b For example, the integrator 241 or the comparator 242 may be initialized during the initialization intervals INT11, INT12, INT21, and INT22, but is not limited thereto. The initialization interval may be omitted. That is, the rising time of the control signal AD_START may be consistent with the rising time of the first enable signal RREF_SEN or the second enable signal RPANEL_SEN.

[0108] The integrator 241 may perform an integration operation on the first output signal RMCN in response to the control signal AD_START to generate a second output signal INT_OUT that increases with time. The generated second output signal INT_OUT may be provided to the comparator 242 .

[0109] The comparator 242 may compare the second output signal INT_OUT with the reference signal REFTOP to generate a third output signal D_CMP_O. The reference signal REFTOP has a constant high level, and the second output signal INT_OUT increases over time, so that the second output signal INT_OUT may intersect the high level of the reference signal REFTOP.

[0110] The time point at which the second output signal INT_OUT intersects the high level of the reference signal REFTOP may coincide with the rising time of the third output signal D_CMP_O. That is, at the time point at which the second output signal INT_OUT intersects the high level of the reference signal REFTOP, a pulse of the third output signal D_CMP_O may be generated. At the same time, the falling time of the third output signal D_CMP_O may be synchronized with the falling time of the control signal AD_START provided to the comparator 242 and the integrator 241. Therefore, the third output signal D_CMP_O as a pulse signal may be provided to the code generator 244 via the level shifter 243.

[0111] The code generator 244 may count using the clock signal P_CLK based on the start time, i.e., the rise time, of the control signal AD_START provided to the comparator 242 and the integrator 241. The code generator 244 may end counting in synchronization with the rise time of the third output signal D_CMP_O. Therefore, the code generator 244 may generate a first detection signal DOUT1 including a code value based on the number of times counted during an interval between the rise time of the control signal AD_START and the rise time of the third output signal D_CMP_O. The first detection signal DOUT1 may be a signal reflecting a reference resistance value adjusted by the resistance adjustment unit 220. The reference resistance value adjusted in the resistance adjustment unit 220 may be the same as the resistance value R1 of the first crack detection target 201.

[0112] <Operation in Second Section T12>

[0113] like Figure 8 As shown, during the second interval T12 , the path control unit 230 may select the second path 320 to connect the first crack detection target 201 to the signal providing unit 210 and the detection unit 240 .

[0114] The path control unit 230 may select the second path 320 in response to the second enable signal RPANEL_SEN so that the first crack detection target 201 may be connected to the signal providing unit 210 and the detection unit 240. The detection signal RMCP of the signal providing unit 210 may be output to the detection unit 240 via the path control unit 230 and the first crack detection target 201. Therefore, the first output signal RMCN generated by the detection signal RMCP via the first crack detection target 201 may be output to the detection unit 240. The first output signal RMCN may be a voltage or a current.

[0115] The detection unit 240 may obtain a second detection signal DOUT2 based on the first output signal RMCN.

[0116] Specifically, Figure 3 , Figure 5 and Figure 6a As shown, the integrator 241 and the comparator 242 can operate in response to the control signal AD_START. The integrator 241 can perform an integration operation on the first output signal RMCN in response to the control signal AD_START to generate a second output signal INT_OUT that increases over time. The generated second output signal INT_OUT can be provided to the comparator 242.

[0117] The comparator 242 may compare the second output signal INT_OUT with the reference signal REFTOP to generate a third output signal D_CMP_O. The reference signal REFTOP has a constant high level, and the second output signal INT_OUT increases over time, so that the second output signal INT_OUT may intersect the high level of the reference signal REFTOP.

[0118] The time point at which the second output signal INT_OUT intersects the high level of the reference signal REFTOP may coincide with the rising time of the third output signal D_CMP_O. That is, at the time point at which the second output signal INT_OUT intersects the high level of the reference signal REFTOP, a pulse of the third output signal D_CMP_O may be generated. At the same time, the falling time of the third output signal D_CMP_O may be synchronized with the falling time of the control signal AD_START provided to the comparator 242 and the integrator 241.

[0119] Therefore, the third output signal D_CMP_O as a pulse signal may be provided to the code generator 244 via the level shifter 243 .

[0120] The code generator 244 may count using the clock signal P_CLK based on the start time, i.e., the rise time, of the control signal AD_START provided to the comparator 242 and the integrator 241. The code generator 244 may end the counting in synchronization with the rise time of the third output signal D_CMP_O. Therefore, the code generator 244 may generate a second detection signal DOUT2 including a code value based on the number of times counted during the interval between the rise time of the control signal AD_START and the rise time of the third output signal D_CMP_O. The second detection signal DOUT2 may be a signal reflecting the resistance value R1 of the first crack detection target 201.

[0121] The crack detection apparatus 200 according to the embodiment may detect a crack of the first crack detection target 201 based on the first detection signal DOUT1 and the second detection signal DOUT2 .

[0122] That is, the crack of the first crack detection target 201 may be detected using the following mathematical formula 1. Mathematical formula 1 may be an estimated resistance value obtained by the crack detection device 200 according to the first embodiment for the first crack detection target 201 (ie, the panel 110), but the estimated resistance values ​​for the other crack detection targets 201 and 202 may also be obtained using mathematical formula 1.

[0123] [Mathematical formula 1]

[0124] R PANEL = R ref ㆍ(T PANEL[code] / T REF [code])

[0125] R PANEL is the estimated resistance value of the panel 110 obtained by the crack detection device 200 according to the embodiment, R ref It can be the reference resistance value adjusted by the resistance adjustment unit 220. REF [code] may be a code value of the first detection signal DOUT1 obtained on the first path 310 via the resistance adjustment unit 220, T PANEL [code] may be a code value of the second detection signal DOUT2 obtained on the second path 320 via the first crack detection target 201 .

[0126] R PANEL , R ref 、T REF [code] and T PANEL [code] can have a binary value, but is not limited to this.

[0127] Using Mathematical Formula 1, when the reference resistance value in the resistance adjusting unit 220 is adjusted to the same resistance value as the actual resistance value of the first crack detection target 201, the code value of the first detection signal DOUT1 obtained on the first path 310 and the code value of the second detection signal DOUT2 obtained on the second path 320 may be the same. In this case, the estimated resistance value of the panel 110 may be the same as the reference resistance value adjusted by the resistance adjusting unit 220.

[0128] The crack detection device 200 according to the embodiment can detect cracks by comparing the estimated resistance value of the panel 110 with the actual resistance value of the panel 110. When the estimated resistance value of the panel 110 is the same as the actual resistance value of the panel 110, no crack is detected, and the first crack detection target 201 can be determined as a good product. When the estimated resistance value of the panel 110 is different from the actual resistance value of the panel 110, a crack can be detected, and the first crack detection target 201 can be determined as a defective product. Fig. 9 As shown, the actual resistance value of the panel 110 may be a resistance value measured with respect to the detection pad 112 disposed at the edge of the panel 110 , but is not limited thereto. Fig. 9 The detection pad 112 shown is merely an example and may be modified into various shapes or structures.

[0129] Meanwhile, even if the estimated resistance value of the panel 110 is different from the actual resistance value of the panel 110 , when the difference is within a certain range, the first crack detection target 201 may be determined as a good product.

[0130] At the same time, if Figure 5 , Figure 6a , Figure 7 and Figure 8 As shown, the crack detection operation for the second crack detection target 202 may also be the same as the above-mentioned crack detection operation for the first crack detection target 201, and therefore, a detailed description thereof will be omitted.

[0131] like Figure 6a and Figure 6b As shown, when crack detection is performed on each of the first crack detection target 201 and the second crack detection target 202, the reference signal REFTOP input to the comparator 242 may be the same. Since the resistance value R2 of the second crack detection target 202 is smaller than the resistance value R1 of the first crack detection target 201, the slope of the second output signal INT_OUT generated from the second crack detection target 202 may be greater than the slope of the second output signal INT_OUT generated from the first crack detection target 201. Therefore, since the rise time of the third output signal D_CMP_O generated from the second crack detection target 202 is earlier than the rise time of the third output signal D_CMP_O generated from the first crack detection target 201, the code value may be obtained with a smaller number of counts. Therefore, different code values ​​may be obtained according to the resistance values ​​R1 and R2 of the plurality of crack detection targets 201 and 202, respectively, and the detection signal DOUT including these code values ​​may also be different.

[0132] As described above, the first detection signal DOUT1 may include a code value reflecting the reference resistance value adjusted by the resistance adjustment unit 220 , and the second detection signal DOUT2 may include a code value reflecting the resistance value R1 of the first crack detection target 201 .

[0133] Meanwhile, various resistance values ​​may exist on the first path 310 for obtaining the first detection signal DOUT1 or the second path 320 for obtaining the second detection signal DOUT2. For example, various resistance values ​​may exist in the signal providing unit 210, the path control unit 230, and the detection unit 240. In addition, resistance values ​​may exist in the integrator 241, the comparator 242, the level shifter 243, the code generator 244, etc. included in the detection unit 240.

[0134] Since these various resistance values ​​are reflected in the code value of the first detection signal DOUT1 or the code value of the second detection signal DOUT2, the estimated resistance value R shown in Mathematical Formula 1 is PANEL may not be accurate. When estimating the resistance value R PANEL When it is inaccurate, even if the first crack detection target 201 is a good product, an error may occur in which the first crack detection target 201 is determined to be a defective product.

[0135] Fig.10is a circuit diagram of a resistance adjusting unit according to a second embodiment.

[0136] like Fig.10 As shown, the resistance adjusting unit 220 may include a plurality of resistors 220 - 1 to 220 - k , a plurality of first switches SW11 to SW1 k , and a second switch SW00 .

[0137] The plurality of resistors 220-1 to 220-k may be connected in parallel to each other. The plurality of first switches SW11 to SW1k may be connected in series to the plurality of resistors 220-1 to 220-k, respectively. Through the selective switching control of the plurality of first switches SW11 to SW1k, at least one or more resistors among the plurality of resistors 220-1 to 220-k may be selected, so that the resistance value of the selected at least one or more resistors may be used to adjust the reference resistance value.

[0138] Meanwhile, the second switch SW00 may be connected in parallel with the resistors 220-1 to 220-k. For example, the other side of the resistors 220-1 to 220-k may be connected to one side of the first switches SW11 to SW1k. In this case, one side of the second switch SW00 may be connected to one side of the resistors 220-1 to 220-k, and the other side of the second switch SW00 may be connected to the other side of the first switches SW11 to SW1k.

[0139] The second switch SW00 can be used to obtain a third detection signal DOUT3, and the third detection signal DOUT3 reflects the resistance values ​​existing in the signal providing unit 210, the path control unit 230, the detection unit 240, etc. Figure 2 As shown, the path control unit 230 may select the third path, and the resistance adjustment unit 220 may turn on the second switch SW00. Therefore, the detection signal RMCP of the signal providing unit 210 may be provided to the detection unit 240 through the second switch SW00 of the resistance adjustment unit 220.

[0140] like Fig.11 As shown, the third interval T13 can be included in one cycle. Fig.11 In the embodiment, the third interval T13 may be located before the first interval T11 in time, but it may also be located between the first interval T11 and the second interval T12 or after the third interval T13.

[0141] like Fig.12As shown, the third path may be selected by the path control unit 230 during the third interval T13, so that the second switch SW00 of the resistance adjustment unit 220 may be connected to the signal providing unit 210 and the detection unit 240. At this time, the second switch SW00 may be turned on. In this case, the detection signal RMCP of the signal providing unit 210 may be provided to the detection unit 240 as the first output signal RMCN via the second switch SW00 of the resistance adjustment unit 220. The detection unit 240 may obtain the third detection signal DOUT3 based on the first output signal RMCN, but since this has been described above, its detailed description will be omitted.

[0142] The third detection signal DOUT3 may be a signal reflecting a resistance value existing in the signal providing unit 210 , the path control unit 230 , the detection unit 240 , and the like.

[0143] The crack detection device 200 according to the embodiment may detect a crack in one (eg, the first crack detection target 201 ) of a plurality of crack detection targets 201 and 202 based on the first detection signal DOUT1 , the second detection signal DOUT2 , and the third detection signal DOUT3 .

[0144] That is, the crack in the first crack detection target 201 can be detected using Mathematical Formula 2. Mathematical Formula 2 may be an estimated resistance value obtained by the crack detection device 200 according to the first embodiment for the first crack detection target 201 (i.e., the panel 110), but Mathematical Formula 2 may also be used to obtain estimated resistance values ​​for other crack detection targets 201 and 202.

[0145] [Mathematical formula 2]

[0146] R PANEL = R ref ㆍ[(T PANEL [code]-Tref0k[code]) / (T REF [code]-Tref0k[code])]

[0147] R PANEL is the estimated resistance value of the panel 110 obtained by the crack detection device 200 according to the embodiment, R ref It can be the reference resistance value adjusted by the resistance adjustment unit 220. REF [code] may be a code value of the first detection signal DOUT1 obtained on the first path 310 via the resistance adjustment unit 220, T PANEL[code] may be a code value of the second detection signal DOUT2 obtained on the second path 320 via the first crack detection target 201. Tref0k[code] may be a code value of the third detection signal DOUT3 obtained via the second switch SW00 of the resistance adjustment unit 220.

[0148] R PANEL , R ref 、T REF [code]、T PANEL [code] and Tref0k[code] can have binary values, but are not limited to this.

[0149] As shown in Mathematical Formula 2, since the code value of the third detection signal DOUT3 is subtracted from the code value of the second detection signal DOUT2, and the code value of the third detection signal DOUT3 is subtracted from the code value of the first detection signal DOUT1, the resistance values ​​existing in the signal providing unit 210, the path control unit 230, and the detection unit 240 can be removed from the estimated resistance value of the panel 110. Therefore, the accuracy of the estimated resistance value of the panel 110 can be significantly improved, and errors in crack detection can be prevented.

[0150] [Display Device According to Second Embodiment]

[0151] Fig.13 is a block diagram of a display device according to a second embodiment. Figures 1 to 12 Can be used in Fig.13 Reference numerals omitted in FIG.

[0152] refer to Fig.13 The display device 101 according to the second embodiment may include a panel 110 and a data driving device 140. Although not shown, the display device 101 according to the second embodiment may include a data processing device 130, a gate driving device 150, and the like.

[0153] The data driving device 140 may include a plurality of source driving circuits 140-1 to 140-L. The source driving circuit may be configured as an integrated circuit.

[0154] The plurality of source driving circuits 140 - 1 to 140 -L may be connected in series in an electrically arranged communication manner. The plurality of source driving circuits 140 - 1 to 140 -L may be connected to the data processing device 130 in an electrically arranged communication manner.

[0155] One of the plurality of source driver circuits 140-1 to 140-L may be designated as a master source driver circuit, and the remaining source driver circuits may be designated as slave source driver circuits. Fig.13As shown, the first source driver circuit 140-1 can be designated as a master source driver circuit, and the remaining source driver circuits 140-2 to 140-L can be designated as slave source driver circuits. At the same time, a slave source driver circuit can be changed to a master source driver circuit, and a master source driver circuit can be changed to a slave source driver circuit.

[0156] In the following, it is assumed that the first source driver circuit 140-1 is designated as the main source driver circuit, and the remaining source driver circuits 140-2 to 140-1 are designated as slave source driver circuits. Therefore, in the following description, the main source driver circuit can adopt the reference numeral "140-1" of the first source driver circuit, and the slave source driver circuit can adopt the reference numerals "140-2 to 140-L" of the remaining source driver circuits.

[0157] At least one of the plurality of source driving circuits 140-1 to 140-L may include the crack detection device 200. In this case, one source driving circuit may detect cracks of the plurality of crack detection targets 201 and 202 using the crack detection device 200.

[0158] The plurality of source driving circuits 140-1 to 140-L may each include a crack detection device 200. In this case, the plurality of source driving circuits 140-1 to 140-L may respectively detect cracks of the source driving circuits themselves using the crack detection device 200.

[0159] Meanwhile, when detecting cracks of the crack detection targets 201 and 202 located outside instead of the source driving circuit itself, some of the source driving circuits 140-1 to 140-L may detect cracks of two or more crack detection targets 201 and 202 located outside. For example, the main source driving circuit may detect cracks of two or more crack detection targets 201 and 202 located outside using the crack detection device 200.

[0160] For example, the first detection pad 112 may be disposed along the edge of the panel 110. For example, the second detection pads 142-1 to 142-L may be disposed along the edges of the plurality of source driver circuits 140-1 to 140-L. Both ends of each of the first detection pad 112 and the second detection pads 142-1 to 142-L may be connected to the path control unit 230 of the crack detection device 200.

[0161] The first detection pad 112 on the panel 110 may be connected to the crack detection device 200 via a plurality of source driving circuits 140 - 1 to 140 -L.

[0162] For example, when the first crack detection device 200-1 of the first source driving circuit 140-1 detects a crack on the panel 110, the first detection pad 112 on the panel 110 can be connected to the path control unit 230 of the first crack detection device 200-1 of the first source driving circuit 140-1 via the second source driving circuit 140-2 to the Lth source driving circuit 140-L.

[0163] Each of the second source driver circuit 140-2 to the Lth source driver circuit 140-L may include a connection switch SW22 to SW2P. The connection switches SW22 to SW2P of the second source driver circuit 140-2 to the Lth source driver circuit 140-L may be connected to each other. When the connection switches SW22 to SW2P of the second source driver circuit 140-2 to the Lth source driver circuit 140-L are turned on, the first detection pad 112 on the panel 110 may pass through the second source driver circuit 140-2 to the Lth source driver circuit 140-L. When the connection switches SW22 to SW2P of the second source driver circuit 140-2 to the Lth source driver circuit 140-L are turned off, the connection between the first detection pad 112 on the panel 110 and the path control unit 230 of the first crack detection device 200-1 of the first source driver circuit 140-1 may be blocked.

[0164] Although not shown, the first source driver circuit 140-1 may also include a connection switch. The connection switch of the first source driver circuit 140-1 may be turned off. When the crack detection device 200 of one of the second source driver circuits 140-2 to the L-th source driver circuit 140-L detects a crack on the panel 110, the connection switch of the first source driver circuit 140-1 may be turned on. At this time, the connection switch of one source driver circuit may be turned off.

[0165] As an example, Figure 2 and Figure 3 As shown, as the first crack detection target 201, a crack on the panel 110 can be detected. When the path control unit 230 selects the first path 310, the detection signal RMCP of the signal providing unit 210 can be provided to the detection unit 240 as the first output signal RMCN via the resistance adjusting unit 220, and the reference resistance value of the resistance adjusting unit 220 is adjusted to the resistance value R1 of the panel 110. The detection unit 240 can obtain a first detection signal DOUT1 based on the first output signal RMCN, which includes a code value corresponding to the reference resistance value adjusted by the resistance adjusting unit 220.

[0166] When the path control unit 230 selects the second path 320, the detection signal RMCP of the signal providing unit 210 may be provided as the first output signal RMCN to the detection unit 240 via the first detection pad 112 provided on the panel 110. The detection unit 240 may obtain the second detection signal DOUT2 including the code value corresponding to the resistance value R1 of the first detection pad on the panel 110 based on the first output signal RMCN.

[0167] When the path control unit 230 selects the second path 320, the connection switch (not shown) of the first source driving circuit 140-1 may be turned off, and the connection switches SW22 to SW2P of the second to Lth source driving circuits 140-2 to 140-L may be turned on.

[0168] like Fig.10 As shown, when the path control unit 230 selects the third path, the detection signal RMCP of the signal providing unit 210 can be provided as the first output signal RMCN to the detection unit 240 via the second switch SW00 of the resistance adjusting unit 220. The detection unit 240 can obtain the third detection signal DOUT3 based on the first output signal RMCN, which includes a code value corresponding to the resistance value present in the signal providing unit 210, the path control unit 230, the detection unit 240, etc.

[0169] Based on the first, second and third detection signals DOUT1, DOUT2 and DOUT3, an estimated resistance value of the panel 110 may be obtained using Formula 2. The estimated resistance value of the panel 110 may be compared with an actual resistance value of the first detection pad 112 on the panel 110 to detect cracks in the panel 110.

[0170] Similarly, if Figure 2 and Figure 3 As shown, as the second crack detection target 202, cracks in the plurality of source driver circuits 140-1 to 140-L themselves can be detected. For example, in the second crack detection device 200-2 of the second source driver circuit 140-2, when the path control unit 230 selects the first path 310, the detection signal RMCP of the signal providing unit 210 can be provided to the detection unit 240 as the first output signal RMCN via the resistance adjustment unit 220, and the resistance adjustment unit 220 is adjusted to the resistance value R2 of the second detection pads 142-1 to 142-L of the second source driver circuit 140-2. The detection unit 240 can obtain the first detection signal DOUT1 based on the first output signal RMCN, which includes a code value corresponding to the reference resistance value adjusted by the resistance adjustment unit 220.

[0171] When the path control unit 230 selects the second path 320, the detection signal RMCP of the signal providing unit 210 may be provided as the first output signal RMCN to the detection unit 240 via the second detection pads 142-1 to 142-L of the second source driving circuit 140-2. The detection unit 240 may obtain the second detection signal DOUT2 including the code value corresponding to the resistance value R2 of the second detection pads 142-1 to 142-L of the second source driving circuit 140-2 based on the first output signal RMCN.

[0172] like Fig.10 As shown, when the path control unit 230 selects the third path, the detection signal RMCP of the signal providing unit 210 can be provided as the first output signal RMCN to the detection unit 240 via the second switch SW00 of the resistance adjusting unit 220. The detection unit 240 can obtain the third detection signal DOUT3 based on the first output signal RMCN, which includes a code value corresponding to the resistance value present in the signal providing unit 210, the path control unit 230, the detection unit 240, etc.

[0173] Based on the first detection signal DOUT1, the second detection signal DOUT2, and the third detection signal DOUT3, the estimated resistance values ​​of the second detection pads 142-1 to 142-L of the second source driver circuit 140-2 can be obtained using Math 2. The estimated resistance values ​​of the second detection pads 142-1 to 142-L of the second source driver circuit 140-2 can be compared with the actual resistance values ​​R2 of the second detection pads 142-1 to 142-L of the second source driver circuit 140-2, and thus cracks in the second source driver circuit 140-2 can be detected.

[0174] Meanwhile, as described above, the plurality of source driving circuits 140 - 1 to 140 -L may include a plurality of connection switches SW22 to SW2P. The plurality of connection switches SW22 to SW2P may have an internal resistance value.

[0175] When the first path 310, the second path 320, and the third path are selected to detect cracks in the panel 110, the plurality of connection switches SW22 to SW2P may be turned on, and the first detection signal DOUT1, the second detection signal DOUT2, and the third detection signal DOUT3 may be obtained via each of the plurality of connection switches SW22 to SW2P. In this case, the first detection signal DOUT1, the second detection signal DOUT2, and the third detection signal DOUT3 may respectively reflect the internal resistance values ​​of the plurality of connection switches SW22 to SW2P, resulting in that the accuracy of the estimated resistance value of the panel 110 represented by Mathematical Formula 2 may be reduced.

[0176] Reference below Figures 14 to 17A method of improving the accuracy of the estimated resistance value of the panel 110 by canceling the internal resistance value of each of the plurality of connection switches SW22 to SW2P is described.

[0177] Fig.14 A crack detection device according to a second embodiment is shown. Fig.15 yes Fig.14 A circuit diagram of a first resistance adjusting unit and a second resistance adjusting unit.

[0178] refer to Fig.14 and Fig.15 The crack detection device 200 according to the second embodiment may include a signal providing unit 210, a resistance adjusting unit, a path control unit 230, and a detection unit 240. Since the signal providing unit 210, the path control unit 230, and the detection unit 240 have been described above, their detailed description will be omitted.

[0179] The resistance adjusting unit may include a first resistance adjusting unit 220 and a second resistance adjusting unit 250. The first resistance adjusting unit 220 has been described above, and thus a detailed description thereof will be omitted.

[0180] exist Fig.15 In the embodiment, the second switch ( Fig.10 SW00), but it may include a second switch SW00.

[0181] The second resistance adjusting unit 250 may be connected in series with the first resistance adjusting unit 220 .

[0182] The second resistance adjusting unit 250 may include a plurality of third switches SW31 to SW3Q connected in series with each other. The second resistance adjusting unit 250 may include a plurality of fourth switches SW41 to SW4Q connected in parallel with the plurality of third switches SW31 to SW3Q.

[0183] When the third switches SW31 to SW3Q are turned on, the detection signal RMCP of the signal supply unit 210 may pass through the third switches SW31 to SW3Q. The fourth switches SW41 to SW4Q may be bypass switches. That is, the fourth switches SW41 to SW4Q may prevent the detection signal RMCP from passing through the third switches SW31 to SW3Q.

[0184] For example, the third switches SW31 to SW3Q and the fourth switches SW41 to SW4Q may be switched complementarily. When the third switches SW31 to SW3Q are turned on, the fourth switches SW41 to SW4Q may be turned off.

[0185] The number of third switches to be turned on among the plurality of third switches SW31 to SW3Q may be determined in consideration of the number of the plurality of slave source driving circuits. For example, when the internal resistance values ​​of the plurality of third switches SW31 to SW3Q are respectively the same as the internal resistance values ​​of the connection switches SW22 to SW2P of the plurality of slave source driving circuits, the number of third switches to be turned on among the plurality of third switches SW31 to SW3Q may be the same as the number of the connection switches SW22 to SW2P. That is, when the number of the connection switches SW22 to SW2P is 2, the number of third switches to be turned on among the plurality of third switches SW31 to SW3Q may also be 2. In this case, among the plurality of fourth switches SW41 to SW4Q, two fourth switches connected in parallel with the turned-on third switches may be turned off, and the remaining fourth switches may be turned on.

[0186] For example, the path control unit 230 may select the first path 310 to detect a crack in the panel 110. In this case, the detection signal RMCP of the signal providing unit 210 may be provided to the detection unit 240 as the first output signal RMCN via the first resistance adjusting unit 220 and the second resistance adjusting unit 250. At this time, the first resistance adjusting unit 220 may adjust the reference resistance value to the resistance value R1 of the panel 110. The second resistance adjusting unit 250 may select as many third switches SW31 to SW3Q as the number of the slave source driving circuits. For example, Fig.17 As shown, the detection signal RMCP can be provided as the first output signal RMCN to the detection unit 240 via the resistor 220-3 having the adjusted reference resistance value and the two third switches SW31 and SW32. Therefore, as many internal resistance values ​​as the number of the selected third switches SW31 and SW32 can be reflected in the first detection signal DOUT1 obtained from the first output signal RMCN by the detection unit 240. At the same time, the internal resistance value of each of the fourth switches SW41 to SW4Q can be 0 or close to 0.

[0187] Afterwards, if Fig.16 As shown, when the path control unit 230 selects the second path 320, the detection signal RMCP of the signal providing unit 210 can be provided as the first output signal RMCN to the detection unit 240 via the panel 110 and the plurality of slave source driving circuits. In this case, the internal resistance values ​​of the connection switches of the plurality of slave source driving circuits can be reflected in the second detection signal DOUT2 obtained by the detection unit 240 from the first output signal RMCN.

[0188] When the estimated resistance value of the panel 110 is obtained using Math 1 or Math 2, the internal resistance values ​​of the plurality of selected third switches SW31 to SW3Q reflected in the first detection signal DOUT1 can offset the internal resistance values ​​of the connection switches of the plurality of slave source driving circuits. Therefore, the accuracy of the estimated resistance value of the panel 110 can be improved by the internal resistance values ​​of the connection switches of the plurality of slave source driving circuits, thereby preventing errors in crack detection.

[0189] The above specific embodiments should not be interpreted as being restrictive in all aspects, but should be considered as illustrative. The scope of the embodiments should be determined by reasonable interpretation of the appended claims, and all changes within the equivalent scope of the embodiments are included in the scope of the embodiments.

Claims

1. Crack detection device, comprising: a signal providing unit, wherein the signal providing unit is configured to provide a detection signal; a resistance adjusting unit configured to adjust a reference resistance value to correspond to resistance values ​​of a plurality of crack detection targets using a plurality of resistors; a path control unit configured to select a first path through which the detection signal passes through at least one resistor and a second path through which the detection signal passes through one crack detection target among the plurality of crack detection targets; and a detection unit configured to detect a crack in the one crack detection target based on a first detection signal obtained from the output signal on the first path and a second detection signal obtained from the output signal on the second path, Wherein, when the first path is selected, the at least one resistor is connected to the signal providing unit, and when the second path is selected, the crack detection target is connected to the signal providing unit.

2. The crack detection device according to claim 1, wherein: One cycle includes a first interval and a second interval. Wherein, the detection unit is configured as: obtaining the first detection signal during the first interval, The second detection signal is obtained during the second interval.

3. The crack detection device according to claim 1, wherein: The plurality of resistors are connected in parallel with each other, The resistance adjustment unit includes a plurality of first switches configured to be respectively connected in series to the plurality of resistors.

4. The crack detection device according to claim 3, wherein: The resistance adjustment unit is configured as follows: By switching the plurality of first switches, the reference resistance value is adjusted to correspond to the resistance value of the one crack detection target.

5. The crack detection device according to claim 1, wherein: The resistance adjusting unit includes a second switch connected in parallel with the resistor.

6. The crack detection device according to claim 5, wherein: The path control unit is configured to select a third path, and the detection signal passes through the second switch through the third path. wherein the detection unit is configured to detect cracks in the one crack detection target based on the first detection signal, the second detection signal and the third detection signal, The third detection signal is configured to be obtained on the selected third path.

7. The crack detection device according to claim 6, wherein: The one cycle includes a third interval, The detection unit is configured to obtain the third detection signal during the third interval.

8. Crack detection methods, including: The signal providing unit provides a detection signal; adjusting, by a resistance adjusting unit, a reference resistance value to correspond to resistance values ​​of a plurality of crack detection targets using a plurality of resistors; selecting, by a path control unit, a first path and a second path, wherein the detection signal passes through at least one resistor through the first path, and the detection signal passes through one crack detection target among the plurality of crack detection targets through the second path; and detecting, by a detection unit, a crack in the one crack detection target based on a first detection signal obtained from an output signal on the first path and a second detection signal obtained from an output signal on the second path, Wherein, when the first path is selected, the at least one resistor is configured to be connected to the signal providing unit, and when the second path is selected, the crack detection target is configured to be connected to the signal providing unit.

9. The crack detection method according to claim 8, comprising: selecting a third path through which the detection signal passes through a second switch connected in parallel with the resistor, Among them, crack detection includes: detecting a crack in the one crack detection target based on the first detection signal, the second detection signal, and the third detection signal, The third detection signal is configured to be obtained on the selected third path.

10. A data driving device, configured to provide a data signal to the panel, the data driving device comprising: A plurality of source driving circuits, each source driving circuit comprising a crack detection device, Wherein, the crack detection device comprises: a signal providing unit, wherein the signal providing unit is configured to provide a detection signal; a first resistance adjusting unit configured to adjust a reference resistance value to correspond to resistance values ​​of a plurality of crack detection targets using a plurality of first resistors; a path control unit configured to select a first path through which the detection signal passes through at least one resistor and a second path through which the detection signal passes through one crack detection target among the plurality of crack detection targets; and a detection unit configured to detect a crack in the one crack detection target based on a first detection signal obtained from the output signal on the first path and a second detection signal obtained from the output signal on the second path, Wherein, when the first path is selected, the at least one resistor is connected to the signal providing unit, and when the second path is selected, the crack detection target is connected to the signal providing unit.

11. The data driving device according to claim 10, wherein: One of the plurality of source driver circuits is designated as a master source driver circuit, and the remaining source driver circuits are designated as slave source driver circuits, Among them, in the main source driving circuit, the detection unit is configured to make the detection signal pass through the panel and the plurality of slave source driving circuits to obtain the first detection signal from the panel as the one crack detection target.

12. The data driving device according to claim 11, wherein: In the main source driving circuit, the crack detection device comprises: A second resistance adjusting unit is configured to use a plurality of second resistors to offset resistance values ​​of the plurality of slave source driving circuits.

13. The data driving device according to claim 10, wherein: One of the plurality of source driver circuits is designated as a master source driver circuit, and the remaining source driver circuits are designated as slave source driver circuits, Among them, in the main source driving circuit, the detection unit is configured to make the detection signal pass through the main source driving circuit to obtain the first detection signal from the main source driving circuit as the one crack detection target.

14. The data driving device according to claim 10, wherein: One of the plurality of source driver circuits is designated as a master source driver circuit, and the remaining source driver circuits are designated as slave source driver circuits, Among them, in one of the specified multiple slave source driving circuits, the detection unit is configured to enable the detection signal to pass through the one slave source driving circuit to obtain the first detection signal from the one slave source driving circuit that is the one crack detection target.

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