Sliced graphics processing unit (GPU) architecture in processor-based device

Abstract

A sliced graphics processing unit (GPU) architecture in a processor-based device is disclosed. In some aspects, a GPU based on a slicing GPU architecture includes a plurality of hardware slices. The GPU also includes command processor (CP) circuitry and a non-slice primitive controller (PCUS). Upon receiving a graphics instruction from a central processing unit (CPU), the CP circuitry determines a graphics workload and sends the graphics workload to the PCUS. The PCUS then divides the graphics workload into a plurality of sub-batches, and distributes each sub-batch to the PCS of the hardware slice for processing.

Description

[0001] Priority claim

[0002] This application claims priority to U.S. Provisional Patent Application Serial No. 63 / 374,286, filed on September 1, 2022, and entitled “SLICED GRAPHICS PROCESSING UNIT (GPU) ARCHITECTURE IN PROCESSOR-BASED DEVICES,” the contents of which are incorporated herein by reference in their entirety.

[0003] This application also claims the benefit of U.S. patent application serial number 18 / 067,837, filed on December 19, 2022, and entitled “SLICED GRAPHICS PROCESSING UNIT (GPU) ARCHITECTURE IN PROCESSOR-BASED DEVICES,” the contents of which are incorporated herein by reference in their entirety. Technical Field

[0004] Generally speaking, the techniques of this disclosure relate to graphics processing unit (GPU) architectures in processor-based devices. Background Art

[0005] Modern processor-based devices include a dedicated processing unit called a graphics processing unit (GPU) to accelerate the rendering of graphics and video data for display. The GPU can be implemented as an integrated component of a general-purpose central processing unit (CPU), or as a discrete hardware component separated from the CPU. Due to its highly parallel architecture and structure, the GPU can perform algorithms that process large data blocks in parallel more efficiently than a general-purpose CPU. For example, the GPU can render a three-dimensional (3D) graphic image using a mode called "tile rendering" or "bin-based rendering". The GPU subdivides an image that can be decomposed into triangles into multiple smaller tiles. Then, the GPU determines which triangles that make up the image are visible in each tile, and uses the fast on-chip memory in the GPU to save the portion of the image inside the tile, thereby rendering each tile in turn. Once the tile has been rendered, the on-chip memory is copied to its correct location in the system memory for output to the display, and the next tile is rendered.

[0006] The process of rendering tiles by the GPU can be further subdivided into multiple operations, which can be performed concurrently in separate processor cores or graphics hardware pipelines. For example, tile rendering can involve a tile visibility thread executed on a first processor core, a rendering thread executed on a second processor core, and a parsing thread executed on a third processor core. The purpose of the tile visibility thread is to determine which triangles contribute fragments to each tile in the tile, where the result is a visibility stream that contains a bit for each triangle checked and indicates whether the triangle is visible in a given tile. The visibility stream is compressed and written to the system memory. The GPU also executes a rendering thread to draw the portion of the image located inside each tile, and performs pixel rasterization and shading. Triangles that are not eliminated by the visibility stream check are rendered by this thread. Finally, the GPU can also execute a parsing thread to copy the portion of the image contained in each tile to the system memory. After the rendering of the tile is completed, the color content of the rendered tile is parsed into the system memory before proceeding to the next tile.

[0007] In response to market pressure to produce GPUs with the ability to perform at higher performance levels, GPU manufacturers have begun to expand the physical size of GPUs. However, implementing traditional GPU architectures with larger physical sizes does not necessarily lead to performance improvements, and may even cause problems that smaller GPUs do not encounter. For example, in the case of smaller GPUs, increasing the voltage leads to a corresponding increase in the maximum frequency, reflecting a roughly linear relationship between voltage and frequency. However, since wire delays also play a large role in determining the maximum frequency, increasing the voltage in a larger GPU beyond a certain point will not increase the maximum frequency in a linear manner. In addition, since GPUs are configured to operate as single instruction multiple data (SIMD) processors, they are most efficient when operating on large amounts of data. Since larger GPUs need to distribute workloads as smaller data chunks, they may not be able to fully fill each processing pipeline to mask latency issues caused by memory fetches. In addition, differences in workloads and execution speeds within different pipelines within the GPU and different execution bottlenecks (i.e., double data rate (DDR) memory bottlenecks and internal GPU bottlenecks) may also cause larger GPU sizes to not translate into GPU performance gains. Summary of the invention

[0008] Various aspects disclosed in the specific implementation include a sliced ​​graphics processing unit (GPU) architecture in a processor-based device. Related devices and methods are also disclosed. In this regard, in some exemplary aspects disclosed herein, a GPU based on a sliced ​​GPU architecture includes: multiple hardware slices, each hardware slice includes a slice primitive controller (PC_S) and multiple slice hardware units. The slice hardware unit of each hardware slice includes a geometry pipeline controller (GPC), a vertex shader (VS), a graphics rasterizer (GRAS), a low-resolution Z buffer (LRZ), a rendering backend (RB), a cache and compression unit (CCU), a graphics memory (GMEM), a high-level sequencer (HLSQ), a fragment shader / texture pipeline (FS / TP), and a cluster cache (CCHE). In addition, the GPU also includes a command processor (CP) circuit and a non-slice primitive controller (PC_US). When a graphics instruction is received from a central processing unit (CPU), the CP circuit determines a graphics workload based on the graphics instruction, and sends the graphics workload to PC_US. PC_US then divides the graphics workload into multiple sub-batches, and distributes each sub-batch to the PC_S of the hardware slice for processing (e.g., based on a polling slice selection mechanism, and / or based on the current processing utilization of each hardware slice). By applying a sliced ​​GPU architecture, a large GPU can be implemented as multiple hardware slices, where the graphics workload is more efficiently subdivided between multiple hardware slices. In this way, the above-mentioned issues regarding physical design, clock frequency, design scalability, and workload imbalance can be effectively addressed.

[0009] Some aspects may also provide that each CCHE of each hardware slice may receive data from one or more clients (i.e., one or more slice hardware units of a plurality of slice hardware units) and may synchronize the one or more clients. In such aspects, a unified cache (UCHE) coupled to the CCHE also synchronizes the plurality of hardware slices. In some aspects, each LRZ of each hardware slice is configured to store cache lines corresponding only to pixel tiles assigned to the corresponding hardware slice. This may be achieved by first mapping screen coordinates into a slice space that is continuous in coordinates and stores only blocks for the hardware slice, and then addressing tiles based on the coordinates in the slice space.

[0010] According to some aspects, the hardware slices of the GPU perform additional operations to determine triangle visibility and assign triangle vertices to corresponding hardware slices. In such aspects, the GPU also includes a non-slice vertex parameter cache (VPC_US), and each hardware slice in the hardware slices also includes a corresponding slice triangle setup engine front end (TSEFE_S), a slice vertex parameter cache front end (VPCFE_S), a slice vertex parameter cache back end (VPCBE_S) and a triangle setup engine (TSE). Each VPCFE_S of each hardware slice can receive primitive attributes and position outputs generated by the VS from the corresponding VS of the hardware slice, and can write the primitive attributes and position outputs to the GMEM of the hardware slice. Each TSEFE_S of each corresponding hardware slice then determines the triangle visibility for one or more hardware slices based on the primitive attributes and position outputs. Then, each TSEFE_S sends one or more indications of triangle visibility for each hardware slice in one or more hardware slices to the VPC_US, and the VPC_US assigns triangles visible to each hardware slice of the one or more hardware slices to the corresponding hardware slice based on the one or more indications of triangle visibility. Each VPCBE_S of each hardware slice identifies vertices for triangles visible to the corresponding hardware slice based on the triangles designated by the VPC_US, and then sends the vertices to the TSE of the corresponding hardware slice.

[0011] In another aspect, a processor-based device is provided. The processor-based device includes a GPU, which includes: multiple hardware slices; a CP circuit; and a PC_US. Each of the multiple hardware slices includes a PC_S and multiple slice hardware units. The multiple slice hardware units include GPC, VS, GRAS, LRZ, RB, CCU, GMEM, HLSQ, FS / TP, and CCHE. The CP circuit is configured to receive graphics instructions from the CPU. The CP circuit is also configured to determine a graphics workload based on the graphics instructions. The CP circuit is also configured to send a graphics workload to the PC_US. The PC_US is configured to receive a graphics workload from the CP circuit. The PC_US is also configured to divide the graphics workload into multiple sub-batches. The PC_US is configured to distribute each of the multiple sub-batches to the PC_S of the hardware slices in the multiple hardware slices for processing.

[0012] On the other hand, a processor-based device is provided. The processor-based device includes a unit for receiving graphics instructions from a CPU. The processor-based device also includes a unit for determining a graphics workload based on the graphics instructions. The processor-based device also includes a unit for dividing the graphics workload into a plurality of sub-batches. The processor-based device further includes a unit for distributing each of the plurality of sub-batches to a hardware slice in a plurality of hardware slices of a GPU for processing. Each of the plurality of hardware slices includes a plurality of slice hardware units, and the plurality of slice hardware units include GPC, VS, GRAS, LRZ, RB, CCU, GMEM, HLSQ, FS / TP, and CCHE.

[0013] In another aspect, a method for operating a sliced ​​GPU architecture is provided. The method includes receiving a graphics instruction from a CPU by a CP circuit of a GPU. The method also includes determining a graphics workload based on the graphics instruction. The method also includes sending a graphics workload to a PC_US of a GPU. The method further includes receiving a graphics workload from a CP circuit by a PC_US. The method also includes dividing the graphics workload into a plurality of sub-batches. The method also includes distributing each of the plurality of sub-batches to a PC_S of a hardware slice in a plurality of hardware slices of a GPU for processing. Each of the plurality of hardware slices includes a plurality of slice hardware units, and the plurality of slice hardware units include GPC, VS, GRAS, LRZ, RB, CCU, GMEM, HLSQ, FS / TP, and CCHE.

[0014] In another aspect, a non-transitory computer-readable medium having computer-executable instructions stored thereon is disclosed, the computer-executable instructions causing the processor to receive graphics instructions when executed by a processor. The computer-executable instructions also cause the processor to determine a graphics workload. The computer-executable instructions also cause the processor to divide the graphics workload into a plurality of sub-batches. The computer-executable instructions further cause the processor to distribute each of the plurality of sub-batches to a slice primitive controller (PC_S) of a hardware slice in a plurality of hardware slices for processing, wherein each of the plurality of hardware slices includes a plurality of slice hardware units, and the plurality of slice hardware units include GPC, VS, GRAS, LRZ, RB, CCU, GMEM, HLSQ, FS / TP, and CCHE. BRIEF DESCRIPTION OF THE DRAWINGS

[0015] Figure 1 is a block diagram of an exemplary processor-based device including a GPU based on a sliced ​​graphics processing unit (GPU) architecture;

[0016] Figure 2A and 2Bare block diagrams illustrating the arrangement of contents of a low-resolution Z-buffer (LRZ) for caching pixel tiles in a conventional LRZ and in some aspects described herein, respectively;

[0017] Figures 3A-3C It is shown that according to some aspects Figure 1 A flowchart of exemplary operations of a processor-based device and a GPU for receiving a graphics workload and subdividing it among hardware slices;

[0018] Figure 4A and 4B is to show that according to some aspects Figure 1 A flowchart of exemplary operations of a hardware slice of a GPU for determining triangle visibility and assigning triangle vertices to corresponding hardware slices; and

[0019] Figure 5 is a block diagram of an exemplary processor-based device including, but not limited to Figure 1 processor-based devices. DETAILED DESCRIPTION

[0020] Several exemplary aspects of the present disclosure are now described with reference to the accompanying drawings. The word "exemplary" is used herein to mean "serving as an example, instance, or illustration." Any aspect described herein as "exemplary" is not necessarily to be construed as preferred or advantageous over other aspects.

[0021] Aspects disclosed in the detailed description include a sliced ​​graphics processing unit (GPU) architecture in a processor-based device. Related devices and methods are also disclosed. In this regard, in some exemplary aspects disclosed herein, a GPU based on a sliced ​​GPU architecture includes multiple hardware slices, each of which includes a slice primitive controller (PC_S) and multiple slice hardware units. The slice hardware unit of each hardware slice includes a geometry pipeline controller (GPC), a vertex shader (VS), a graphics rasterizer (GRAS), a low-resolution Z buffer (LRZ), a rendering backend (RB), a cache and compression unit (CCU), a graphics memory (GMEM), a high-level sequencer (HLSQ), a fragment shader / texture pipeline (FS / TP) and a cluster cache (CCHE). In addition, the GPU also includes a command processor (CP) circuit and a non-slice primitive controller (PC_US). When a graphics instruction is received from a central processing unit (CPU), the CP circuit determines the graphics workload based on the graphics instruction and sends the graphics workload to the PC_US. PC_US then divides the graphics workload into multiple sub-batches, and distributes each sub-batch to the PC_S of the hardware slice for processing (e.g., based on a polling slice selection mechanism, and / or based on the current processing utilization of each hardware slice). By applying a sliced ​​GPU architecture, a large GPU can be implemented as multiple hardware slices, where the graphics workload is more efficiently subdivided between multiple hardware slices. In this way, the above-mentioned issues regarding physical design, clock frequency, design scalability, and workload imbalance can be effectively solved.

[0022] Some aspects may also provide that each CCHE of each hardware slice may receive data from one or more clients (i.e., one or more of a plurality of slice hardware units) and may synchronize the one or more clients. In such aspects a unified cache (UCHE) coupled to the CCHE also synchronizes the plurality of hardware slices. In some aspects, each LRZ of each hardware slice is configured to store cache lines corresponding only to pixel tiles assigned to the corresponding hardware slice. This may be achieved by first mapping screen coordinates into a slice space that is continuous in coordinates and stores only blocks for the hardware slice, and then addressing tiles based on the coordinates in the slice space.

[0023] According to some aspects, the hardware slices of the GPU perform additional operations to determine triangle visibility and assign triangle vertices to corresponding hardware slices. In such aspects, the GPU also includes a non-slice vertex parameter cache (VPC_US), and each hardware slice in the hardware slices also includes a corresponding slice triangle setup engine front end (TSEFE_S), a slice vertex parameter cache front end (VPCFE_S), a slice vertex parameter cache back end (VPCBE_S) and a triangle setup engine (TSE). Each VPCFE_S of each hardware slice can receive primitive attributes and position outputs generated by the VS from the corresponding VS of the hardware slice, and can write the primitive attributes and position outputs to the GMEM of the hardware slice. Each TSEFE_S of each corresponding hardware slice then determines the triangle visibility for one or more hardware slices based on the primitive attributes and position outputs. Then, each TSEFE_S sends one or more indications of triangle visibility for each hardware slice in one or more hardware slices to the VPC_US, and the VPC_US assigns triangles visible to each hardware slice in one or more hardware slices to the corresponding hardware slice based on the one or more indications of triangle visibility. Each VPCBE_S of each hardware slice identifies vertices for triangles visible to the corresponding hardware slice based on the triangles designated by the VPC_US, and then sends the vertices to the TSE of the corresponding hardware slice.

[0024] At this point, Figure 1 is a block diagram of an exemplary processor-based device 100. The processor-based device includes a CPU 102, which may also be referred to herein as a "processor core" or "CPU core", which may be an in-order or out-of-order processor (OoP), and / or may be one of a plurality of CPUs 102 provided by the processor-based device 100. Examples of CPU 102 may include, but are not limited to, a digital signal processor (DSP), a general-purpose microprocessor, an application-specific integrated circuit (ASIC), a field-programmable logic array (FPGA), or other equivalent integrated or discrete logic circuits. Figure 1 As shown in FIG. 1 , CPU 102 includes a graphics processing unit (in Figure 1 The GPU 104 may include one or more dedicated processors for performing graphics operations. As a non-limiting example, the GPU 104 may include dedicated hardware units with fixed functions and programmable components for rendering graphics and executing GPU applications. The GPU 104 may also include a DSP, a general-purpose microprocessor, an ASIC, an FPGA, or other equivalent integrated or discrete logic circuits. It should be noted that although the Figure 1In the example of FIG. 1 , CPU 102 and GPU 104 are shown as separate units, but in some examples, CPU 102 and GPU 104 may be integrated into a single unit. Figure 1 Not shown, but it will be understood that Figure 1 The CPU 102 may execute a software application or application programming interface (API) that submits graphics instructions to the CPU, from which a graphics workload (including, for example, a number of primitives) for processing by the GPU 104 may be determined.

[0025] Figure 1 The processor-based device 100 may include any of known digital logic elements, semiconductor circuits, processing cores, and / or memory structures, as well as other elements or combinations thereof. The aspects described herein are not limited to any particular arrangement of elements, and the disclosed techniques may be readily extended to various structures and layouts on a semiconductor die or package. It will be understood that some aspects of the processor-based device 100 may include, in addition to the Figure 1 Elements other than those shown in the drawings and / or may be included in the drawings Figure 1 For example, the processor-based device 100 may also include additional CPUs 102, processor cores, caches, controllers, communication buses, and / or persistent storage devices, which are not shown for clarity. Figure 1 These items are omitted.

[0026] To address issues regarding physical design, clock frequency, design scalability, and workload imbalance that may arise when increasing the physical size of GPU 104, Figure 1 The GPU 104 in the example implements a sliced ​​GPU architecture. Accordingly, the GPU 104 is configured to include a plurality of hardware slices 106 (0)-106 (H), each of which provides a corresponding slice primitive controller (in Figure 1 108(0)-108(H) and a plurality of slice hardware units. As used herein, the phrase “slice hardware unit” refers to the elements of each hardware slice that provide functionality corresponding to conventional elements of a graphics pipeline of a GPU, and includes GPCs 110(0)-110(H), VSs 112(0)-112(H), GRAS 114(0)-114(H), LRZs 116(0)-116(H), RBs 118(0)-118(H), CCUs 120(0)-120(H), GMEMs 122(0)-122(H), HLSQs 124(0)-124(H), FS / TPs 126(0)-126(H), and CCHEs 128(0)-128(H). GPU 104 also includes CP circuitry (in Figure 1 The text described in the figure is "CP")130 and PC_US132.

[0027] Each of the GPCs 110(0)-110(H) manages the way vertices form the geometry of the image to be rendered, and is responsible for fetching vertices from memory and handling vertex data caches and vertex transformations. VS112(0)-112(H) performs vertex transformation calculations, while each of the GRAS114(0)-114(H) uses information received from the GPCs 110(0)-110(H) to select vertices and construct the triangles that make up the graphics image. Each of the GRAS114(0)-114(H) also converts triangles to viewport coordinates, removes triangles that are outside the viewport (i.e., "back-facing" triangles), and rasterizes each triangle to select pixels inside the triangle for later processing. LRZ 116(0)-116(H) provides a mechanism for detecting whether a block of pixels is completely hidden by other primitives, which is faster but more conservative than calculating a detailed Z value for each pixel.

[0028] The RBs 118(0)-118(H) each perform detailed Z-value checks and reject pixels that are hidden by other pixels, and also take the output from the pixel shader and perform final processing (e.g., blending, format conversion, etc., as non-limiting examples) before sending the data to the color buffer. The CCUs 120(0)-120(H) provide a cache for depth and color data, and compress the data before sending it to system memory to save bandwidth. The GMEMs 122(0)-122(H) are used to buffer color and depth data in binning mode, and essentially serve as random access memory (RAM) for the corresponding CCU 120(0)-120(H). Each HLSQ 124(0)-124(H) operates as a controller for the corresponding FS / TP 126(0)-126(H), and each FS / TP 126(0)-126(H) performs fragment shading (i.e., pixel shading) operations. The CCHE 128 ( 0 )- 128 (H) provides a first level cache between each FS / TP 126 ( 0 )- 126 (H) and the UCHE 140 .

[0029] In an exemplary operation, CPU 102 sends graphics instructions 134 to CP circuit 130 of GPU 104. Graphics instructions 134 represent high-level instructions from an executing application or API that request GPU 104 to perform corresponding graphics operations to generate an image or video. Graphics instructions 134 are received by CP circuit 130 of GPU 104 and used to determine the graphics workload (in Figure 1The graphics workload 136 includes a series of graphics primitives (not shown), each of which represents a basic operation for generating and / or rendering an image. The CP circuit 130 sends the graphics workload 136 to the PC_US 132, and the PC_US 132 divides the graphics workload 136 into multiple sub-batches 138 (0)-138 (S). The PC_US 132 then distributes each of the sub-batches 138 (0)-138 (S) to the hardware slices 106 (0)-106 (H) for parallel processing. Some aspects may provide that the size of each of the sub-batches 138 (0)-138 (S) (i.e., the number of primitives contained therein) is configurable. In some aspects, each of the sub-batches 138 (0)-138 (S) may include 256 primitives (not shown).

[0030] In some aspects, PC_US132 may employ a round-robin slice selection mechanism to assign sub-batches 138(0)-138(S) to hardware slices 106(0)-106(H). Some aspects may provide that PC_US132 may determine a current processing utilization of each of the hardware slices 106(0)-106(H), wherein each processing utilization indicates how much of the available processing resources of the corresponding hardware slice 106(0)-106(H) are currently in use. In such aspects, PC_US132 may then assign sub-batches 138(0)-138(S) to hardware slices 106(0)-106(H) based on the current processing utilization of the hardware slices 106(0)-106(H). For example, PC_US132 may assign sub-batches only to hardware slices that have lower current processing utilizations and therefore more available processing resources.

[0031] In accordance with Figure 1 In an aspect of the present invention, each CCHE 128(0)-128(H) of a hardware slice 106(0)-106(H) caches data for a workload processed by the slice hardware unit of the corresponding hardware slice 106(0)-106(H) in a manner similar to the level 1 (L1) cache of a CPU. Figure 1In the example of , GPU 104 also provides a UCHE 140 similar to the CPU's Level 2 (L2) cache. UCHE 140 is communicatively coupled to CCHE 128(0)-128(H) via a crossbar switch (not shown) and caches data for all hardware slices 106(0)-106(H). Accordingly, in some aspects, each CCHE 128(0)-128(H) can receive data (not shown) from one or more clients (i.e., one or more of the slice hardware units corresponding to hardware slices 106(0)-106(H)) and can synchronize one or more clients. In such aspects, UCHE 140 also synchronizes multiple hardware slices 106(0)-106(H).

[0032] In some aspects, Figure 1The hardware slices 106(0)-106(H) of the GPU 104 are configured to perform additional exemplary operations for determining triangle visibility and assigning triangle vertices to corresponding hardware slices. In such an aspect, the GPU 104 also includes a VPC_US 142, and each of the hardware slices 106(0)-106(H) also includes a corresponding TSEFE_S 144(0)-144(H), a VPCFE_S 146(0)-146(H), a VPCBE_S 148(0)-148(H), and a TSE 150(0)-150(H). Each VPCFE_S 146(0)-146(H) receives primitive attributes and position outputs (not shown) generated by the corresponding VS 112(0)-112(H). Each VPCFE_S 146 (0) -146 (H) writes the primitive attributes and position outputs to the GMEM 122 (0) -122 (H) of the corresponding hardware slice 106 (0) -106 (H). The primitive attributes and position outputs are then used by each TSEFE_S 144 (0) -144 (H) of the corresponding hardware slice 106 (0) -106 (H) to determine triangle visibility for each of one or more hardware slices in the hardware slices 106 (0) -106 (H). Each TSEFE_S 144 (0) -144 (H) then sends corresponding one or more indications of triangle visibility for each of the one or more hardware slices to the VPC_US 142. The VPC_US 142 uses the one or more indications of triangle visibility to assign triangles visible to each of the one or more hardware slices to the corresponding hardware slice. Each VPCBE_S 148(0)-148(H) of each hardware slice of the plurality of hardware slices 106(0)-106(H) identifies vertices for triangles visible to the corresponding hardware slice based on the triangles assigned by the VPC_US 142 of the corresponding hardware slice. Each VPCBE_S 148(0)-148(H) then sends the vertices to the TSE 150(0)-150(H) of the corresponding hardware slice.

[0033] As described above, the hardware slices 106(0)-106(H) of GPU 104 provide corresponding LRZs 116(0)-116(H). In some aspects, LRZs 116(0)-116(H) may be configured to store cache lines more efficiently than conventional LRZs. In this regard, Figure 2A and 2B Cache line storage in the conventional LRZ of GPU 104 and in LRZs 116(0)-116(H) are shown respectively. Figure 2AAs seen in FIG. 2 , a pixel array 200 representing pixels to be processed for display is subdivided into pixel tiles, such as, as indicated by pattern 202, 32x32 pixel tiles assigned to a first pixel slice 0; as indicated by pattern 204, 32x32 pixel tiles assigned to a second pixel slice 1; and, as indicated by pattern 206, 32x32 pixel tiles assigned to a third pixel slice 2. As used herein, a "pixel slice" refers to the functional element of each hardware slice 106(0)-106(H) responsible for pixel processing. A conventional LRZ provides a conventional LRZ cache line 208, which in this example covers 128x128 pixels, which stores pixel slices assigned to pixel slice 0, pixel slice 1, and pixel slice 2. This results in wasted area due to not using cache space for each slice and consistency issues caused by the LRZ fast clear flag bit (not shown), which covers a 64x64 screen area and can be read and / or written by multiple pixel slices.

[0034] Accordingly, in some aspects, each LRZ 116(0)-116(H) of each hardware slice 106(0)-106(H) of the GPU 104 is configured to store only cache lines corresponding to the corresponding hardware slice 106(0)-106(H). This may be accomplished by first mapping screen coordinates into a slice space that is contiguous in coordinates and stores only blocks for the hardware slice, and then addressing tiles based on the coordinates in the slice space. Figure 2B LRZ cache lines are shown in both screen space view 210 and slice space view 212 according to some aspects. As seen in screen space view 210, the LRZ cache line covers 384x128 pixels of pixel array 200, but only includes pixel tiles assigned to pixel slice 2, such as pixel tile 214. Thus, as seen in slice space view 212, the LRZ cache line covers 128x128 pixels of the pixel tiles assigned to pixel slice 2, thereby reducing space waste and coherency issues associated with traditional LRZ.

[0035] In some aspects, screen coordinates represented by integers x and y may be mapped into a slice space that is continuous in coordinates using the exemplary code shown in Table 1 below:

[0036] Table 1

[0037]

[0038] Inside each LRZ cache block, the hardware is configured to address pixel tiles using the traditional formula, but based on coordinates in tile space, as shown by the example code in Table 2 below:

[0039] Table 2

[0040]

[0041]

[0042] Finally, when accessing the external LRZ buffer, each pixel slice adds a slice pitch based on the total number of hardware slices 106(0)-106(H) in GPU 104 so that the system memory address can accommodate the LRZ 116(0)-116(H) for all hardware slices 106(0)-106(H), as shown by the exemplary code in Table 3 below:

[0043] Table 3

[0044]

[0045] In some aspects, the slice spacing may be implemented as a new hardware register.Some aspects may provide that the graphics driver may allocate more LRZ buffer space to account for the alignment requirements for the slice spacing.

[0046] To further describe Figure 1 The processor-based device 100 and the GPU 104 in the embodiment of the present invention are configured to receive a graphics workload and to subdivide the graphics workload among hardware slices. Figures 3A-3C A flow chart is provided showing process 300. For clarity, in describing Figures 3A-3C Cited Figure 1 , 2A and 2B. It will be appreciated that some aspects may provide that: Figures 3A-3C Some operations shown in the may be performed in an order different from that shown herein and / or may be omitted. Figure 3A In the example, the operation starts with the following operations: the CP circuit of the GPU (e.g., Figure 1 CP circuit 130 of GPU 104) from CPU (e.g., Figure 1 The CPU 102 receives graphics instructions (e.g., Figure 1 CP circuit 130 determines a graphics workload (e.g., Figure 1 The CP circuit 130 then sends a graphics workload 136 to the GPU 104 (e.g., Figure 1The PC_US 132 sends the graphics workload 136 to the CP circuit 130 (block 306). The PC_US 132 receives the graphics workload 136 from the CP circuit 130 (block 308). The PC_US 132 then divides the graphics workload 136 into a plurality of sub-batches (e.g., Figure 1 Then, the operation is performed at Figure 3B Continue at block 312 of .

[0047] Reference now Figure 3B , PC_US 132 then distributes each of the plurality of sub-batches 138 ( 0 )- 138 (S) to a plurality of hardware slices of the GPU (e.g., Figure 1 The PC_S of the hardware slices in the hardware slices 106(0)-106(H)) (e.g., Figure 1 PC_S108(0)-108(H)) for processing, wherein each of the plurality of hardware slices 106(0)-106(H) further comprises a plurality of slice hardware units (e.g., Figure 1 Slice hardware unit) (block 312). Figure 1 As seen in FIG. 1 , in some aspects, the plurality of slice hardware units may include GPCs 110(0)-110(H), VSs 112(0)-112(H), GRASs 114(0)-114(H), LRZs 116(0)-116(H), RBs 118(0)-118(H), CCUs 120(0)-120(H), GMEMs 122(0)-122(H), HLSQs 124(0)-124(H), FS / TPs 126(0)-126(H), and CCHEs 128(0)-128(H). In some aspects, the operation of block 312 for distributing each of the plurality of sub-batches 138(0)-138(S) may be based on a round-robin slice selection mechanism (block 314). Some aspects may provide that the operations of block 312 for distributing each of the plurality of sub-batches 138(0)-138(S) may include the PC_US 132 first determining a corresponding plurality of current processing utilizations for the plurality of hardware slices 106(0)-106(H) (block 316). The PC_US 132 may then distribute each of the plurality of sub-batches 138(0)-138(S) based on the plurality of current processing utilizations (block 318). The operations in some aspects may include Figure 3C Continue at block 320 of .

[0048] Now go to Figure 3CIn some aspects, each CCHE 128(0)-128(H) of each hardware slice of the plurality of hardware slices 106(0)-106(H) receives data from one or more clients, the one or more clients comprising one or more slice hardware units of the plurality of slice hardware units of the hardware slice (block 320). Each CCHE synchronizes the one or more clients (block 322). The UCHE of the GPU 104 (e.g., Figure 1 The UCHE 140 also synchronizes the plurality of hardware slices 106(0)-106(H) (block 324).

[0049] Some aspects may provide that each LRZ 116(0)-116(H) of each hardware slice in the plurality of hardware slices 106(0)-106(H) stores only pixel tiles (e.g., Figure 2B 214) (block 326). In accordance with some aspects, the operation of block 326 for storing cache lines corresponding to only pixel tiles assigned to a corresponding hardware slice of the plurality of hardware slices 106(0)-106(H) may include first mapping the screen coordinates into a slice space that is contiguous in coordinates and saving only the tiles for that hardware slice (block 328). Each LRZ 116(0)-116(H) then addresses the tile based on the coordinates in the slice space (block 330).

[0050] Figure 4A and 4B Provided are diagrams showing the Figure 1 104 of the GPU 104 for determining triangle visibility and assigning triangle vertices to corresponding hardware slices. Figure 4A and 4B Cited Figure 1 It will be understood that in some aspects, Figure 4A and 4B Some of the operations shown in the drawings may be performed in an order different from that shown herein, or may be omitted.

[0051] Figure 4A The operations in start with the following operations: Figure 1Each VPCFE_S 146(0)-146(H) in the plurality of hardware slices 106(0)-106(H) receives primitive attributes and position outputs generated by the VS 112(0)-112(H) from a corresponding VS, such as the VS 112(0)-112(H) of a corresponding hardware slice in the plurality of hardware slices 106(0)-106(H) (block 402). Each VPCFE_S 146(0)-146(H) writes the primitive attributes and position outputs to the GMEM 122(0)-122(H) of the corresponding hardware slice (block 404). Each TSEFE_S 144(0)-144(H) of the corresponding hardware slice in the plurality of hardware slices 106(0)-106(H) then determines triangle visibility for each hardware slice in one or more hardware slices in the plurality of hardware slices 106(0)-106(H) based on the primitive attributes and position outputs (block 406). Each TSEFE_S 144(0)-144(H) then sends a request to VPC_US (such as Figure 1 The VPC_US 142 of the processor 400 sends corresponding one or more indications of triangle visibility for each of the one or more hardware slices (block 408).

[0052] VPC_US 142 receives one or more indications of triangle visibility (block 410). VPC_US 142 then assigns triangles visible to each hardware slice of one or more hardware slices to the corresponding hardware slice based on the one or more indications of triangle visibility (block 412). Then, the operation Figure 4B Continue at block 414 of .

[0053] Reference now Figure 4B , each VPCBE_S 148(0)-148(H) of each hardware slice of the plurality of hardware slices 106(0)-106(H) identifies vertices for triangles visible to the corresponding hardware slice based on the triangles assigned by the VPC_US 142 of the corresponding hardware slice (block 414). Each VPCBE_S 148(0)-148(H) then sends the vertices to the TSE 150(0)-150(H) of the corresponding hardware slice (block 416).

[0054] A GPU implemented according to a sliced ​​GPU architecture as disclosed in the various aspects described herein may be provided in or integrated into any processor-based device. Non-limiting examples include a set-top box, an entertainment unit, a navigation device, a communication device, a fixed location data unit, a mobile location data unit, a global positioning system (GPS) device, a mobile phone, a cellular phone, a smart phone, a session initiation protocol (SIP) phone, a tablet device, a tablet phone, a server, a computer, a portable computer, a mobile computing device, a laptop computer, a wearable computing device (e.g., a smart watch, a health or fitness tracker, glasses, etc.), a desktop computer, a personal digital assistant (PDA), a monitor, a computer monitor, a television, a tuner, a radio unit, a satellite radio unit, a music player, a digital music player, a portable music player, a digital video player, a video player, a digital video disc (DVD) player, a portable digital video player, an automobile, a vehicle component, an avionics system, a drone, and a multirotor helicopter.

[0055] At this point, Figure 5 An example of a processor-based device 500 is shown, which may include a processor-based device 500. Figure 1 1. The processor-based device 100 shown in FIG. In this example, the processor-based device 500 includes a processor 502, which includes one or more central processing units (CPUs). Figure 5 The central processing unit 504 may include Figure 1 The CPU 102 of the embodiment of the present invention may also be referred to as a CPU core or a processor core. The processor 502 may have a cache memory 506 coupled to the processor 502 for quickly accessing temporarily stored data. The processor 502 is coupled to a system bus 508 and may couple the master devices and slave devices included in the processor-based device 500 to each other. As is well known, the processor 502 communicates with these other devices by exchanging address, control, and data information on the system bus 508. For example, as an example of a slave device, the processor 502 may transmit a bus transaction request to the memory controller 510. Although in Figure 5 Although not shown, multiple system buses 508 may be provided, wherein each system bus 508 constitutes a different structure.

[0056] Other master devices and slave devices may be connected to the system bus 508. Figure 5As shown in , as an example, these devices may include: a memory system 512, which includes a memory controller 510 and a memory array 514; one or more input devices 516; one or more output devices 518; one or more network interface devices 520; and one or more display controllers 522. Input device 516 may include any type of input device, including but not limited to input keys, switches, voice processors, etc. Output device 518 may include any kind of output device, including but not limited to audio, video, other visual indicators, etc. Network interface device 520 can be any device configured to allow the exchange of data to and from network 524. Network 524 can be any type of network, including but not limited to wired or wireless networks, private or public networks, local area networks (LANs), wireless local area networks (WLANs), wide area networks (WANs), Bluetooth TM Networks and the Internet. Network interface device 520 may be configured to support any type of communication protocol desired.

[0057] The processor 502 may also be configured to access a display controller 522 via the system bus 508 to control information sent to one or more displays 526. The display controller 522 sends information to the display 526 for display via one or more video processors 528, which process the information to be displayed into a format suitable for the display 526. The display controller 522 and / or the video processor 528 may include a GPU (such as a Figure 1 The display 526 may include any type of display, including but not limited to a cathode ray tube (CRT), a liquid crystal display (LCD), a plasma display, etc.

[0058] Figure 5 The processor-based device 500 may include an instruction set (in Figure 5 The instruction set 530 may be executed by the processor 502 for any application desired according to the instructions. The instructions 530 may be stored in the memory array 516, the processor 502, and / or the cache memory 508, each of which may include an example of a non-transitory computer-readable medium. The instructions 530 may also reside completely or at least partially within the memory array 516 and / or within the processor 502 during its execution. The instructions 530 may also be sent or received over the network 524, so that the network 524 may include an example of a computer-readable medium.

[0059] Although the computer-readable medium is described as a single medium in the exemplary embodiments herein, the term "computer-readable medium" should be taken to include a single medium or multiple media (e.g., a centralized or distributed database, and / or associated caches and servers) storing one or more instruction sets 530. The term "computer-readable medium" should also be taken to include any medium capable of storing, encoding, or carrying an instruction set for execution by a processing device and causing the processing device to perform any one or more of the methods of the embodiments disclosed herein. Accordingly, the term "computer-readable medium" should be taken to include, but is not limited to, solid-state memory, optical media, and magnetic media.

[0060] It will also be appreciated by those skilled in the art that the various illustrative logic blocks, modules, circuits and algorithms described in conjunction with the various aspects disclosed herein can be implemented as electronic hardware, stored in a memory or in another computer-readable medium and executed by a processor or other processing device, or a combination of the two. The memory disclosed herein can be a memory of any type and size, and can be configured to store any type of information desired. In order to clearly illustrate this interchangeability, various illustrative components, frames, modules, circuits and steps have been generally described above around their functions. How to implement such functions depends on specific applications, design choices and / or the design constraints imposed on the entire system. A skilled person can implement the described functions in a varying manner for each specific application, but such implementation decisions should not be interpreted as causing a departure from the scope of the present disclosure.

[0061] The various illustrative logical blocks, modules, and circuits described in conjunction with the various aspects disclosed herein may be implemented or performed using a processor, a digital signal processor (DSP), an application specific integrated circuit (ASIC), a field programmable gate array (FPGA) or other programmable logic device, discrete gate or transistor logic, discrete hardware components, or any combination thereof designed to perform the functions described herein. The processor may be a microprocessor, but in an alternative, the processor may be any conventional processor, controller, microcontroller, or state machine. The processor may also be implemented as a combination of computing devices (e.g., a combination of a DSP and a microprocessor, a plurality of microprocessors, a combination of one or more microprocessors and a DSP core, or any other such configuration).

[0062] The various aspects disclosed herein may be embodied in hardware and instructions stored in hardware, and may be located, for example, in a random access memory (RAM), flash memory, read-only memory (ROM), electrically programmable ROM (EPROM), electrically erasable programmable ROM (EEPROM), registers, hard disks, removable disks, CD-ROMs, or any other form of computer-readable medium known in the art. An exemplary storage medium is coupled to a processor so that the processor can read information from the storage medium and write information to the storage medium. In an alternative, the storage medium may be an integral part of the processor. The processor and storage medium may be located in an ASIC. The ASIC may be located in a remote station. In an alternative, the processor and storage medium may be located in a remote station, a base station, or a server as discrete components.

[0063] It should also be noted that the operation steps described in any exemplary aspect of the exemplary aspects of this article are described to provide examples and discussions. The described operation can be performed in many different orders except for the order shown. In addition, the operation described in a single operation step can actually be performed in a plurality of different steps. In addition, one or more operation steps discussed in the exemplary aspects can be combined. It should be understood that, as will be apparent to those skilled in the art, the operation steps shown in the flow chart can be subject to many different modifications. It will also be understood by those skilled in the art that information and signals can be represented using any of a variety of different techniques and methods. For example, the data, instructions, commands, information, signals, bits, symbols, and chips mentioned throughout the above description may be represented by voltage, current, electromagnetic waves, magnetic fields or particles, light fields or particles, or any combination thereof.

[0064] The foregoing description of the present disclosure is provided to enable any person skilled in the art to implement or use the present disclosure. Various modifications to the present disclosure will be apparent to those skilled in the art, and the overall principles defined herein may be applied to other variations. Therefore, the present disclosure is not intended to be limited to the examples and designs described herein, but is given the widest scope consistent with the principles and novel features disclosed herein.

[0065] Implementation examples are described in the following numbered clauses:

[0066] 1. A processor-based device comprising:

[0067] Graphics Processing Unit (GPU), including:

[0068] Multiple hardware slices;

[0069] command processor (CP) circuitry; and

[0070] Non-slicing primitive controller (PC_US);

[0071] The CP circuit is configured as:

[0072] receiving graphics instructions from a central processing unit (CPU);

[0073] determining a graphics workload based on the graphics instructions; and

[0074] sending the graphics workload to the PC_US; and

[0075] The PC_US is configured as:

[0076] receiving the graphics workload from the CP circuit;

[0077] dividing the graphics workload into a plurality of sub-batches; and

[0078] Each sub-batch of the plurality of sub-batches is distributed to a slice primitive controller (PC_S) of a hardware slice of the plurality of hardware slices for processing.

[0079] 2. A processor-based device according to claim 1, wherein each of the multiple hardware slices includes multiple slice hardware units, and the multiple slice hardware units include a geometry pipeline controller (GPC), a vertex shader (VS), a graphics rasterizer (GRAS), a low-resolution Z buffer (LRZ), a rendering back end (RB), a cache and compression unit (CCU), a graphics memory (GMEM), a high-level sequencer (HLSQ), a fragment shader / texture pipeline (FS / TP), and a cluster cache (CCHE).

[0080] 3. A processor-based device as described in clause 2, wherein:

[0081] The GPU also includes a unified cache (UCHE) communicatively coupled to each CCHE of each hardware slice of the plurality of hardware slices; and

[0082] Each CCHE of each hardware slice of the plurality of hardware slices and the UCHE are configured to operate as a hierarchical cache.

[0083] 4. A processor-based device according to clause 3, wherein:

[0084] Each CCHE of each hardware slice of the plurality of hardware slices is configured as:

[0085] receiving data from one or more clients of one or more slice hardware units of the plurality of slice hardware units comprising the hardware slice; and

[0086] synchronizing the one or more clients; and

[0087] The UCHE is configured to synchronize the plurality of hardware slices.

[0088] 5. A processor-based device according to any of clauses 1-3, wherein the PC_US is configured to distribute each sub-batch based on a polling slice selection mechanism.

[0089] 6. A processor-based device according to any of clauses 1 to 5, wherein the PC_US is configured to distribute each sub-batch by being configured to:

[0090] determining a corresponding plurality of current processing utilizations for the plurality of hardware slices; and

[0091] Each sub-batch of the plurality of sub-batches is distributed based on the plurality of current process utilizations.

[0092] 7. A processor-based device as described in any of clauses 1-6, wherein the size of each sub-batch of the plurality of sub-batches is configurable.

[0093] 8. A processor-based device as claimed in any of clauses 1 to 7, wherein each sub-batch comprises 256 primitives.

[0094] 9. A processor-based device according to any of clauses 2 to 8, wherein:

[0095] The GPU also includes a non-slice vertex parameter cache (VPC_US);

[0096] The plurality of slice hardware units of each hardware slice of the plurality of hardware slices further comprises:

[0097] Slice triangles to set up the engine front end (TSEFE_S);

[0098] Slice Vertex Parameter Cache Front End (VPCFE_S); and

[0099] Slice vertex parameter cache backend (VPCBE_S);

[0100] Each VPCFE_S is configured as:

[0101] receiving primitive attributes and position outputs generated by the VS from the VS corresponding to the hardware slice; and

[0102] Writing the primitive attributes and the position output to the GMEM of the corresponding hardware slice;

[0103] Each TSEFE_S is configured as:

[0104] determining triangle visibility for each hardware slice of one or more hardware slices of the plurality of hardware slices based on the primitive attributes and the position output; and

[0105] sending to the VPC_US corresponding one or more indications of triangle visibility for each of the one or more hardware slices;

[0106] The VPC_US is configured as:

[0107] receiving the one or more indications of triangle visibility; and

[0108] assigning triangles visible to each of the one or more hardware slices to the corresponding hardware slice based on the one or more indications of triangle visibility; and

[0109] Each VPCBE_S is configured as:

[0110] extracting vertices for the triangle visible to the corresponding hardware slice based on the triangle assigned by the VPC_US of the corresponding hardware slice; and

[0111] The vertices are sent to a triangle setup engine (TSE) of the corresponding hardware slice.

[0112] 10. A processor-based apparatus as recited in any of clauses 2-9, wherein each LRZ is configured to store cache lines corresponding only to pixel tiles assigned to a corresponding hardware slice of the plurality of hardware slices.

[0113] 11. The processor-based apparatus of clause 10, wherein each LRZ is configured to store cache lines corresponding only to pixel tiles assigned to the corresponding hardware slice of the plurality of hardware slices by being configured to:

[0114] Mapping screen coordinates into a slice space that is coordinately continuous and holds only the blocks for the hardware slice; and

[0115] Tiles are addressed based on coordinates in the slice space.

[0116] 12. A processor-based device comprising:

[0117] a unit for receiving graphics instructions from a central processing unit (CPU);

[0118] means for determining a graphics workload based on the graphics instructions;

[0119] means for dividing the graphics workload into a plurality of sub-batches; and

[0120] Means for distributing each of the plurality of sub-batches to a hardware slice of a plurality of hardware slices of a graphics processing unit (GPU) for processing.

[0121] 13. A method for operating a graphics processing unit (GPU) comprising a plurality of hardware slices, comprising:

[0122] A command processor (CP) circuit of a graphics processing unit (GPU) receives graphics instructions from a central processing unit (CPU);

[0123] determining a graphics workload based on the graphics instructions;

[0124] Sending the graphics workload to a non-slicing primitive controller (PC_US) of the GPU;

[0125] receiving, by the PC_US, the graphics workload from the CP circuit;

[0126] dividing the graphics workload into a plurality of sub-batches; and

[0127] Each sub-batch of the plurality of sub-batches is distributed to a slice primitive controller (PC_S) of a hardware slice of the plurality of hardware slices of the GPU for processing.

[0128] 14. A method according to clause 13, wherein each of the multiple hardware slices includes multiple slice hardware units, and the multiple slice hardware units include a geometry pipeline controller (GPC), a vertex shader (VS), a graphics rasterizer (GRAS), a low-resolution Z buffer (LRZ), a rendering back end (RB), a cache and compression unit (CCU), a graphics memory (GMEM), a high-level sequencer (HLSQ), a fragment shader / texture pipeline (FS / TP), and a cluster cache (CCHE).

[0129] 15. A method according to clause 14, wherein:

[0130] The GPU also includes a unified cache (UCHE) communicatively coupled to each CCHE of each hardware slice of the plurality of hardware slices;

[0131] Each CCHE of each hardware slice of the plurality of hardware slices and the UCHE are configured to operate as a hierarchical cache; and

[0132] The method further comprises:

[0133] receiving, by each CCHE of each hardware slice of the plurality of hardware slices, data from one or more clients of one or more slice hardware units of the plurality of slice hardware units comprising the hardware slice;

[0134] synchronizing, by each CCHE of each hardware slice of the plurality of hardware slices, the one or more clients;

[0135] as well as

[0136] The UCHE synchronizes the multiple hardware slices.

[0137] 16. A method according to any of clauses 13-15, wherein distributing each sub-batch is based on a round-robin slice selection mechanism.

[0138] 17. A method according to any of clauses 13 to 16, wherein distributing each sub-batch comprises:

[0139] determining a corresponding plurality of current processing utilizations for the plurality of hardware slices; and

[0140] Each sub-batch of the plurality of sub-batches is distributed based on the plurality of current process utilizations.

[0141] 18. A method according to any of clauses 13-17, wherein the size of each sub-batch of the plurality of sub-batches is configurable.

[0142] 19. A method according to any of clauses 13-18, wherein each sub-batch comprises 256 primitives.

[0143] 20. A method according to any of clauses 14 to 19, wherein:

[0144] The GPU also includes a non-slice vertex parameter cache (VPC_US);

[0145] The plurality of slice hardware units of each hardware slice of the plurality of hardware slices further comprises:

[0146] Slice triangles to set up the engine front end (TSEFE_S);

[0147] Slice Vertex Parameter Cache Front End (VPCFE_S); and

[0148] Slice Vertex Parameter Cache Backend (VPCBE_S); and

[0149] The method further comprises:

[0150] Receiving, by each VPCFE_S, primitive attributes and position outputs generated by the VS of the corresponding hardware slice;

[0151] Each VPCFE_S writes the primitive attributes and the position output into the GMEM of the corresponding hardware slice;

[0152] determining, by each TSEFE_S, triangle visibility for each hardware slice of one or more hardware slices of the plurality of hardware slices based on the primitive attributes and the position output;

[0153] sending, by each TSEFE_S, to the VPC_US corresponding one or more indications of triangle visibility for each of the one or more hardware slices;

[0154] receiving, by the VPC_US, the one or more indications of triangle visibility;

[0155] assigning, by the VPC_US, triangles visible to each of the one or more hardware slices to the corresponding hardware slice based on the one or more indications of triangle visibility;

[0156] extracting, by each VPCBE_S of each hardware slice of the plurality of hardware slices, vertices for the triangle visible to the corresponding hardware slice based on the triangle assigned by the VPC_US of the corresponding hardware slice; and

[0157] The vertices are sent to a triangle setup engine (TSE) of the corresponding hardware slice.

[0158] 21. The method of any of clauses 14-20, further comprising storing, by each LRZ of each hardware slice of the plurality of hardware slices, cache lines corresponding only to pixel tiles assigned to a corresponding hardware slice of the plurality of hardware slices.

[0159] 22. The method of clause 21, wherein storing cache lines corresponding only to pixel tiles assigned to the corresponding hardware slice of the plurality of hardware slices comprises:

[0160] Mapping screen coordinates into a slice space that is coordinately continuous and holds only the blocks for the hardware slice; and

[0161] Tiles are addressed based on coordinates in the slice space.

[0162] 23. A non-transitory computer readable medium having computer executable instructions stored thereon, the computer executable instructions, when executed by a processor, causing the processor to:

[0163] Receive graphics instructions;

[0164] determining a graphics workload based on the graphics instructions;

[0165] dividing the graphics workload into a plurality of sub-batches; and

[0166] Each sub-batch of the plurality of sub-batches is distributed to a slice primitive controller (PC_S) of a hardware slice of the plurality of hardware slices for processing.

[0167] 24. A non-transitory computer-readable medium according to clause 23, wherein each of the plurality of hardware slices comprises a plurality of slice hardware units, the plurality of slice hardware units comprising a geometry pipeline controller (GPC), a vertex shader (VS), a graphics rasterizer (GRAS), a low-resolution Z-buffer (LRZ), a rendering backend (RB), a cache and compression unit (CCU), a graphics memory (GMEM), a high-level sequencer (HLSQ), a fragment shader / texture pipeline (FS / TP), and a cluster cache (CCHE).

[0168] 25. The non-transitory computer-readable medium of any of clauses 23-24, wherein the computer-executable instructions further cause the processor to:

[0169] receiving data from one or more clients of one or more slice hardware units of the plurality of slice hardware units comprising the hardware slice;

[0170] synchronizing the one or more clients; and

[0171] The plurality of hardware slices are synchronized.

[0172] 26. The non-transitory computer-readable medium of any of clauses 23-25, wherein the computer-executable instructions cause the processor to perform the following operations: distribute each sub-batch based on a polling slice selection mechanism.

[0173] 27. The non-transitory computer-readable medium of any of clauses 23-26, wherein the computer-executable instructions cause the processor to distribute each sub-batch by causing the processor to:

[0174] determining a corresponding plurality of current processing utilizations for the plurality of hardware slices; and

[0175] Each sub-batch of the plurality of sub-batches is distributed based on the plurality of current process utilizations.

[0176] 28. The non-transitory computer-readable medium of any of clauses 23-27, wherein the size of each sub-batch of the plurality of sub-batches is configurable.

[0177] 29. The non-transitory computer-readable medium of any of clauses 23-28, wherein each sub-batch comprises 256 primitives.

[0178] 30. The non-transitory computer-readable medium of any one of clauses 24-29, wherein the computer-executable instructions further cause the processor to:

[0179] receiving primitive attributes and position outputs generated by the VS for each hardware slice;

[0180] writing the primitive attributes and the position output to the GMEM of the hardware slice;

[0181] determining triangle visibility for each hardware slice of one or more hardware slices of the plurality of hardware slices based on the primitive attributes and the position output;

[0182] assigning triangles visible to each of the one or more hardware slices to the corresponding hardware slice based on the corresponding one or more indications of triangle visibility;

[0183] extracting vertices for the triangle visible to the corresponding hardware slice; and

[0184] The vertices are sent to a triangle setup engine (TSE) of the corresponding hardware slice.

[0185] 31. The non-transitory computer-readable medium of any of clauses 23-30, wherein the computer-executable instructions further cause the processor to store cache lines corresponding only to pixel tiles assigned to corresponding hardware slices of the plurality of hardware slices.

[0186] 32. The non-transitory computer-readable medium of clause 31, wherein the computer-executable instructions cause the processor to store cache lines corresponding only to pixel tiles assigned to the corresponding hardware slice of the plurality of hardware slices by causing the processor to:

[0187] Mapping screen coordinates into a slice space that is coordinately continuous and holds only the blocks for the hardware slice; and

[0188] Tiles are addressed based on coordinates in the slice space.

Claims

1. A processor-based device comprising: A graphics processing unit (GPU), comprising: Multiple hardware slices; command processor (CP) circuit; and Non-slicing primitive controller (PC_US); The CP circuit is configured as: receiving graphics instructions from a central processing unit (CPU); determining a graphics workload based on the graphics instructions; and sending the graphics workload to the PC_US; and The PC_US is configured as: receiving the graphics workload from the CP circuit; dividing the graphics workload into a plurality of sub-batches; and Each sub-batch of the plurality of sub-batches is distributed to a slice primitive controller (PC_S) of a hardware slice of the plurality of hardware slices for processing.

2. The processor-based device of claim 1, wherein: Each of the multiple hardware slices includes multiple slice hardware units, and the multiple slice hardware units include a geometry pipeline controller (GPC), a vertex shader (VS), a graphics rasterizer (GRAS), a low-resolution Z buffer (LRZ), a rendering back end (RB), a cache and compression unit (CCU), a graphics memory (GMEM), a high-level sequencer (HLSQ), a fragment shader / texture pipeline (FS / TP), and a cluster cache (CCHE).

3. The processor-based device of claim 2, wherein: The GPU also includes a unified cache (UCHE) communicatively coupled to each CCHE of each hardware slice of the plurality of hardware slices; and Each CCHE of each hardware slice of the plurality of hardware slices and the UCHE are configured to operate as a hierarchical cache.

4. The processor-based device of claim 3, wherein: Each CCHE of each hardware slice of the plurality of hardware slices is configured as: receiving data from one or more clients of one or more slice hardware units of the plurality of slice hardware units comprising the hardware slice; as well as synchronizing the one or more clients; and The UCHE is configured to synchronize the plurality of hardware slices.

5. The processor-based device of claim 1 , wherein: The PC_US is configured to distribute each sub-batch based on a round-robin slice selection mechanism.

6. The processor-based device of claim 1, wherein: The PC_US is configured to distribute each sub-batch by being configured to: determining a corresponding plurality of current processing utilizations for the plurality of hardware slices; as well as Each sub-batch of the plurality of sub-batches is distributed based on the plurality of current process utilizations.

7. The processor-based device of claim 1, wherein: The size of each sub-batch of the plurality of sub-batches is configurable.

8. The processor-based device of claim 1, wherein: Each subbatch consists of 256 primitives.

9. The processor-based device of claim 2, wherein: The GPU also includes a non-slice vertex parameter cache (VPC_US); The plurality of slice hardware units of each hardware slice of the plurality of hardware slices further comprises: Slice triangles to set up the engine front end (TSEFE_S); Slice Vertex Parameter Cache Front End (VPCFE_S); and Slice vertex parameter cache backend (VPCBE_S); Each VPCFE_S is configured as: receiving primitive attributes and position outputs generated by the VS from the VS corresponding to the hardware slice; and Writing the primitive attributes and the position output to the GMEM of the corresponding hardware slice; Each TSEFE_S is configured as: determining triangle visibility for each hardware slice of one or more hardware slices of the plurality of hardware slices based on the primitive attributes and the position output; and sending to the VPC_US corresponding one or more indications of triangle visibility for each of the one or more hardware slices; The VPC_US is configured as: receiving the one or more indications of triangle visibility; and assigning triangles visible to each of the one or more hardware slices to the corresponding hardware slice based on the one or more indications of triangle visibility; and Each VPCBE_S is configured as: extracting vertices for the triangle visible to the corresponding hardware slice based on the triangle assigned by the VPC_US of the corresponding hardware slice; and The vertices are sent to a triangle setup engine (TSE) of the corresponding hardware slice.

10. The processor-based device of claim 2, wherein: Each LRZ is configured to store cache lines corresponding only to pixel tiles assigned to a corresponding hardware slice of the plurality of hardware slices.

11. The processor-based device of claim 10, wherein: Each LRZ is configured to store cache lines corresponding only to pixel tiles assigned to the corresponding hardware slice of the plurality of hardware slices by being configured to, for each hardware slice: Mapping screen coordinates into a slice space that is coordinately continuous and holds only the blocks for the hardware slice; and Tiles are addressed based on coordinates in the slice space.

12. A processor-based device comprising: a unit for receiving graphics instructions from a central processing unit (CPU); means for determining a graphics workload based on the graphics instructions; means for dividing said graphics workload into a plurality of sub-batches; as well as Means for distributing each of the plurality of sub-batches to a hardware slice of a plurality of hardware slices of a graphics processing unit (GPU) for processing.

13. A method for operating a graphics processing unit (GPU) comprising a plurality of hardware slices, comprising: A command processor (CP) circuit of a graphics processing unit (GPU) receives graphics instructions from a central processing unit (CPU); determining a graphics workload based on the graphics instructions; Sending the graphics workload to a non-slicing primitive controller (PC_US) of the GPU; receiving, by the PC_US, the graphics workload from the CP circuit; dividing the graphics workload into a plurality of sub-batches; as well as Each sub-batch of the plurality of sub-batches is distributed to a slice primitive controller (PC_S) of a hardware slice of the plurality of hardware slices of the GPU for processing.

14. The method according to claim 13, wherein: Each of the multiple hardware slices includes multiple slice hardware units, and the multiple slice hardware units include a geometry pipeline controller (GPC), a vertex shader (VS), a graphics rasterizer (GRAS), a low-resolution Z buffer (LRZ), a rendering back end (RB), a cache and compression unit (CCU), a graphics memory (GMEM), a high-level sequencer (HLSQ), a fragment shader / texture pipeline (FS / TP), and a cluster cache (CCHE).

15. The method according to claim 14, wherein: The GPU also includes a unified cache (UCHE) communicatively coupled to each CCHE of each hardware slice of the plurality of hardware slices; Each CCHE of each hardware slice of the plurality of hardware slices and the UCHE are configured to operate as a hierarchical cache; as well as The method further comprises: receiving, by each CCHE of each hardware slice of the plurality of hardware slices, data from one or more clients of one or more slice hardware units of the plurality of slice hardware units comprising the hardware slice; synchronizing, by each CCHE of each hardware slice of the plurality of hardware slices, the one or more clients; and The UCHE synchronizes the multiple hardware slices.

16. The method according to claim 13, wherein: Distributing each subbatch is based on a round-robin slice selection mechanism.

17. The method according to claim 13, wherein: Distributing each sub-batch includes: determining a corresponding plurality of current processing utilizations for the plurality of hardware slices; and Each sub-batch of the plurality of sub-batches is distributed based on the plurality of current process utilizations.

18. The method according to claim 13, wherein: The size of each sub-batch of the plurality of sub-batches is configurable.

19. The method according to claim 13, wherein: Each subbatch consists of 256 primitives.

20. The method of claim 14, wherein: The GPU also includes a non-slice vertex parameter cache (VPC_US); The plurality of slice hardware units of each hardware slice of the plurality of hardware slices further comprises: Slice triangles to set up the engine front end (TSEFE_S); Slice Vertex Parameter Cache Front End (VPCFE_S); and Slice Vertex Parameter Cache Backend (VPCBE_S); and The method further comprises: Each VPCFE_S receives primitive attributes and position outputs generated by the VS from the VS of the corresponding hardware slice; Each VPCFE_S writes the primitive attributes and the position output into the GMEM of the corresponding hardware slice; determining, by each TSEFE_S, triangle visibility for each hardware slice of one or more hardware slices of the plurality of hardware slices based on the primitive attributes and the position output; sending, by each TSEFE_S, to the VPC_US corresponding one or more indications of triangle visibility for each of the one or more hardware slices; receiving, by the VPC_US, the one or more indications of triangle visibility; assigning, by the VPC_US, triangles visible to each of the one or more hardware slices to the corresponding hardware slice based on the one or more indications of triangle visibility; extracting, by each VPCBE_S of each hardware slice of the plurality of hardware slices, vertices for the triangle visible to the corresponding hardware slice based on the triangle assigned by the VPC_US of the corresponding hardware slice; and The vertices are sent to a triangle setup engine (TSE) of the corresponding hardware slice.

21. The method of claim 14, further comprising: Each LRZ of each hardware slice of the plurality of hardware slices stores cache lines corresponding only to pixel tiles assigned to a corresponding hardware slice of the plurality of hardware slices.

22. The method according to claim 21, wherein: Storing cache lines corresponding only to pixel tiles assigned to the corresponding hardware slice of the plurality of hardware slices comprises: Mapping screen coordinates into a slice space that is coordinately continuous and holds only the blocks for the hardware slice; and Tiles are addressed based on coordinates in the slice space.

23. A non-transitory computer readable medium having stored thereon computer executable instructions, the computer executable instructions, when executed by a processor, causing the processor to: Receive graphics instructions; determining a graphics workload based on the graphics instructions; dividing the graphics workload into a plurality of sub-batches; and Each sub-batch of the plurality of sub-batches is distributed to a slice primitive controller (PC_S) of a hardware slice of the plurality of hardware slices for processing.

24. The non-transitory computer readable medium of claim 23, wherein: Each of the multiple hardware slices includes multiple slice hardware units, and the multiple slice hardware units include a geometry pipeline controller (GPC), a vertex shader (VS), a graphics rasterizer (GRAS), a low-resolution Z buffer (LRZ), a rendering back end (RB), a cache and compression unit (CCU), a graphics memory (GMEM), a high-level sequencer (HLSQ), a fragment shader / texture pipeline (FS / TP), and a cluster cache (CCHE).

25. The non-transitory computer readable medium of claim 24, wherein: The computer executable instructions further cause the processor to: receiving data from one or more clients of one or more slice hardware units of the plurality of slice hardware units comprising the hardware slice; synchronizing the one or more clients; as well as The plurality of hardware slices are synchronized.

26. The non-transitory computer readable medium of claim 23, wherein: The computer executable instructions cause the processor to distribute each sub-batch based on a round-robin slice selection mechanism.

27. The non-transitory computer readable medium of claim 23, wherein: The computer executable instructions cause the processor to distribute each sub-batch by causing the processor to: determining a corresponding plurality of current processing utilizations for the plurality of hardware slices; as well as Each sub-batch of the plurality of sub-batches is distributed based on the plurality of current process utilizations.

28. The non-transitory computer readable medium of claim 23, wherein: The size of each sub-batch of the plurality of sub-batches is configurable.

29. The non-transitory computer readable medium of claim 23, wherein: Each subbatch consists of 256 primitives.

30. The non-transitory computer readable medium of claim 24, wherein: The computer executable instructions further cause the processor to: receiving primitive attributes and position outputs generated by the VS for each hardware slice; writing the primitive attributes and the position output to the GMEM of the hardware slice; determining triangle visibility for each hardware slice of one or more hardware slices of the plurality of hardware slices based on the primitive attributes and the position output; assigning triangles visible to each of the one or more hardware slices to a corresponding hardware slice based on the corresponding one or more indications of triangle visibility; extracting vertices for the triangle visible to the corresponding hardware slice; as well as The vertices are sent to a triangle setup engine (TSE) of the corresponding hardware slice.

31. The non-transitory computer readable medium of claim 23, wherein: The computer-executable instructions further cause the processor to store cache lines corresponding only to pixel tiles assigned to corresponding hardware slices of the plurality of hardware slices.

32. The non-transitory computer readable medium of claim 31 , wherein: The computer executable instructions cause the processor to store cache lines corresponding only to pixel tiles assigned to the corresponding hardware slice of the plurality of hardware slices by causing the processor to: Mapping screen coordinates into a slice space that is coordinately continuous and holds only the blocks for the hardware slice; and Tiles are addressed based on coordinates in the slice space.

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