Chip structure, preparation method thereof and display device

Abstract

The invention discloses a chip structure, a preparation method thereof and a display device. The chip structure comprises a chip wafer unit and a color conversion unit arranged on the light emitting side of the chip wafer unit. The color conversion unit comprises a substrate, the substrate comprises a main body part and an edge part surrounding the main body part, the edge part comprises original layers and modified layers which are alternately arranged in the first direction, in the edge part, the layers located on the two outermost sides in the first direction are the original layers, and the modified layers are located on the other two outermost layers in the first direction. The first direction is perpendicular to the surface, far away from the chip wafer unit, of the substrate. The original layer and the modified layer have different light reflectance.

Description

Chip structure and manufacturing method thereof, and display device Technical Field

[0001] The present disclosure relates to the field of display technology, and in particular to a chip structure and a manufacturing method thereof, and a display device. Background Art

[0002] Micro-LED (micro light-emitting diode) display devices are a new generation of display technology with the advantages of high brightness, high luminous efficiency, low power consumption, and fast response speed.

[0003] Summary of the Invention

[0004] In one aspect, a chip structure is provided. The chip structure includes: a chip wafer unit and a color conversion unit disposed on the light-emitting side of the chip wafer unit. The color conversion unit includes a base substrate, the base substrate including a main portion and an edge portion surrounding the main portion. The edge portion includes original layers and modified layers alternately arranged along a first direction, and within the edge portion, the outermost layers in the first direction are both original layers. The original layer and the modified layer have different light reflectivities. The first direction is perpendicular to the surface of the base substrate away from the chip wafer unit.

[0005] In some embodiments, the main portion has the same light reflectivity as the original layer.

[0006] In some embodiments, the substrate includes a first surface and a second surface opposing each other along a first direction, and a plurality of side surfaces connecting the first surface and the second surface, wherein the second surface is closer to the chip wafer unit than the first surface. The edge portion includes a plurality of sub-portions corresponding to the plurality of side surfaces, wherein the plurality of sub-portions each include the same number of modified layers; alternatively, the plurality of sub-portions each include different numbers of modified layers.

[0007] In some embodiments, at least one of the multiple sub-sections of the edge portion includes N modified layers, where N is a positive integer and N ≥ 2. The modified layer farthest from the chip wafer unit is the first modified layer, and the modified layer closest to the chip wafer unit is the Nth modified layer. The distance between the first modified layer and the first surface is greater than or equal to the distance between any two adjacent modified layers; and / or the distance between the Nth modified layer and the second surface is greater than or equal to the distance between any two adjacent modified layers.

[0008] In some embodiments, the distance between the first modified layer and the first surface ranges from 15 μm to 35 μm; and / or the distance between the Nth modified layer and the second surface ranges from 15 μm to 35 μm.

[0009] In some embodiments, the distance between the first modified layer and the first surface is greater than or equal to 20 μm; and / or the distance between the Nth modified layer and the second surface is greater than or equal to 20 μm.

[0010] In some embodiments, the color conversion unit further comprises: a color filter layer, a defining dam layer, and a color conversion layer. The color filter layer is disposed on the side of the base substrate facing the chip wafer unit. The color filter layer includes a black matrix and multiple filter portions defined by the black matrix. In an orthographic projection onto the base substrate, the black matrix is ​​located within the area enclosed by the edge portion. The defining dam layer is disposed on the side of the color filter layer facing away from the base substrate. The defining dam layer includes multiple openings corresponding one-to-one to the multiple filter portions. The color conversion layer and the defining dam layer are disposed on the same layer.

[0011] In some embodiments, the plurality of opening regions defined within the dam layer include a first type of opening region and a second type of opening region. The color conversion layer includes a color conversion portion and a filling portion. The color conversion portion includes a quantum dot conversion portion or a fluorescent color conversion portion. The filling portion includes a scattering particle portion or a transparent adhesive. The color conversion portion is disposed within the first type of opening region, and the filling portion is disposed within the second type of opening region.

[0012] In some embodiments, the base substrate includes a functional area and a peripheral area surrounding the functional area. The orthographic projection of the chip wafer unit on the base substrate is located in the functional area, with the main body at least located within the functional area and the edge located within the peripheral area. The color conversion unit also includes an encapsulation layer covering the color filter layer. In an orthographic projection onto the base substrate, the portion of the encapsulation layer located in the peripheral area overlaps with the edge.

[0013] In some embodiments, the distance between the boundary of the black matrix and the side surface of the base substrate is e1, and the size of the modified layer in a direction parallel to the first surface of the base substrate and perpendicular to the side surface of the base substrate is e2, e2≤e1.

[0014] In some embodiments, a dimension e2 of the modified layer in a direction parallel to the first surface of the base substrate and perpendicular to the side surface of the base substrate ranges from 5 μm to 10 μm.

[0015] In some embodiments, a distance e1 between a boundary of the black matrix and a side surface of the base substrate ranges from 10 μm to 30 μm.

[0016] In another aspect, a display device is provided, comprising a driving substrate and a plurality of chip structures provided according to any one of the above embodiments, wherein the driving substrate is coupled to the plurality of chip structures respectively.

[0017] On the other hand, a method for preparing a chip structure is provided, comprising the following steps.

[0018] An initial wafer is formed; the initial wafer includes a plurality of chip wafer units.

[0019] A color conversion substrate is formed; the color conversion substrate includes a base substrate motherboard and a plurality of color conversion structures arranged on the base substrate motherboard, each color conversion structure and its corresponding base substrate motherboard constitute a color conversion unit.

[0020] The color conversion substrate is coupled to the initial wafer to obtain a coupling structure, wherein each chip wafer unit is opposite to a color conversion unit.

[0021] A laser is sequentially applied to multiple focal points within a substrate motherboard to perform cutting, thereby forming cutting lines within the substrate motherboard. The multiple focal points are sequentially arranged along a first direction, perpendicular to a surface of the substrate motherboard distal from the multiple color conversion structures. After cutting, the substrate motherboard forms multiple substrates, each of which includes a main body and an edge portion surrounding the main body. The edge portion includes original layers and modified layers alternately arranged along the first direction, with the outermost layers in the first direction being both original layers.

[0022] In some embodiments, in the step of sequentially applying laser light to multiple focal points inside the base substrate motherboard for cutting, the base substrate motherboard is cut from the color conversion substrate side of the self-coupling structure.

[0023] In some embodiments, the substrate motherboard includes a plurality of cutting streets, and the laser cuts along the cutting streets. When cutting each cutting street, the number of focal spots acted on by the laser is the same or different.

[0024] In some embodiments, in the step of applying the laser to multiple focal points inside the substrate motherboard for cutting in sequence, the number of focal points is N, N is a positive integer, and N≥2, the focal point farthest from the initial wafer is the first focal point, and the focal point closest to the initial wafer is the Nth focal point; the surface of the substrate motherboard far from the initial wafer is the first surface, and the surface of the substrate motherboard close to the initial wafer is the second surface.

[0025] The distance between the first focus and the first surface of the substrate motherboard is greater than or equal to the distance between any two adjacent focuses; and / or, the distance between the Nth focus and the second surface of the substrate motherboard is greater than or equal to the distance between any two adjacent focuses.

[0026] In some embodiments, the distance between the first focus and the first surface of the substrate motherboard is in the range of 15 μm to 35 μm; and / or the distance between the Nth focus and the second surface of the substrate motherboard is in the range of 15 μm to 35 μm.

[0027] In some embodiments, the distance between any two adjacent chip structures ranges from 30 μm to 50 μm. BRIEF DESCRIPTION OF THE DRAWINGS

[0028] To more clearly illustrate the technical solutions of the present disclosure, the following briefly introduces the drawings required for use in some embodiments of the present disclosure. Obviously, the drawings described below are only drawings of some embodiments of the present disclosure, and those skilled in the art can also derive other drawings based on these drawings. Furthermore, the drawings described below are schematic diagrams and are not intended to limit the actual dimensions of the products, actual processes of the methods, actual timing of signals, and the like involved in the embodiments of the present disclosure.

[0029] FIG1 is a planar structural diagram of a display device according to some embodiments;

[0030] FIG2 is a cross-sectional structural diagram according to the cross-sectional line GG in FIG1 ;

[0031] FIG3 is a flow chart of a method for preparing a chip structure according to some embodiments;

[0032] FIG4 is a top view of the structure corresponding to step S1 in the preparation method in FIG3 ;

[0033] FIG5 is a top view of the structure corresponding to step S2 in the preparation method in FIG3 ;

[0034] FIG6 is a top view of the structure corresponding to step S3 in the preparation method in FIG3 ;

[0035] FIG7 is a side structural diagram corresponding to step S4 in the preparation method in FIG3 ;

[0036] FIG8 is an enlarged structural diagram according to the cross-sectional line FF in FIG7;

[0037] FIG9 is an enlarged structural diagram of point E in FIG7 ;

[0038] FIG10 is a side structural diagram corresponding to steps S11 to S14 in the preparation method according to some embodiments;

[0039] FIG11 is a side structural diagram corresponding to step S15 in the preparation method according to some embodiments;

[0040] FIG12 is a side structural diagram corresponding to step S16 in the preparation method according to some embodiments;

[0041] FIG13 is a side structural diagram corresponding to step S21 in the preparation method according to some embodiments;

[0042] FIG14 is a side structural diagram corresponding to steps S22 and S23 in the preparation method according to some embodiments;

[0043] FIG15 is a side view of the structure corresponding to steps S24 and S31 in the preparation method according to some embodiments;

[0044] FIG16 is a side structural diagram corresponding to step S32 in the preparation method according to some embodiments;

[0045] FIG17 is a side structural diagram corresponding to step S33 in the preparation method according to some embodiments;

[0046] FIG18 is a side structural diagram corresponding to step S34 in the preparation method according to some embodiments;

[0047] FIG19 is a side structural diagram corresponding to step S35 in the preparation method according to some embodiments;

[0048] FIG. 20 is a top view of the structure corresponding to step S6 in the preparation method according to some embodiments. DETAILED DESCRIPTION

[0049] The following will be combined with the accompanying drawings to clearly and completely describe the technical solutions in some embodiments of the present disclosure. Obviously, the embodiments described are only some embodiments of the present disclosure, not all embodiments. Based on the embodiments provided by the present disclosure, all other embodiments obtained by ordinary technicians in this field are within the scope of protection of the present disclosure.

[0050] Unless the context requires otherwise, throughout the specification and claims, the term "comprise" and its other forms, such as the third person singular form "comprises" and the present participle form "comprising", are to be interpreted as open and inclusive, that is, "including, but not limited to". In the description of the specification, the terms "one embodiment", "some embodiments", "exemplary embodiments", "example", "specific example" or "some examples" are intended to indicate that the particular features, structures, materials or characteristics associated with the embodiment or example are included in at least one embodiment or example of the present disclosure. The schematic representation of the above terms does not necessarily refer to the same embodiment or example. In addition, the particular features, structures, materials or characteristics may be included in any one or more embodiments or examples in any appropriate manner.

[0051] In the following, the terms "first" and "second" are used for descriptive purposes only and should not be understood to indicate or imply relative importance or implicitly specify the number of the technical features indicated. Therefore, a feature defined as "first" or "second" may explicitly or implicitly include one or more of the features. In the description of the embodiments of the present disclosure, unless otherwise specified, "plurality" means two or more.

[0052] When describing some embodiments, the expressions "coupled" and "connected" and their derivatives may be used. The term "connected" should be understood in a broad sense. For example, "connection" can be a fixed connection, a detachable connection, or an integral connection; it can be directly connected or indirectly connected through an intermediate medium. The term "coupled" indicates, for example, that two or more components are in direct physical or electrical contact. The term "coupled" or "communicatively coupled" may also refer to two or more components that are not in direct contact with each other, but still cooperate or interact with each other. The embodiments disclosed herein are not necessarily limited to the contents of this document.

[0053] “At least one of A, B and C” has the same meaning as “at least one of A, B or C” and both include the following combinations of A, B and C: A only, B only, C only, the combination of A and B, the combination of A and C, the combination of B and C, and the combination of A, B and C.

[0054] “A and / or B” includes the following three combinations: A only, B only, and a combination of A and B.

[0055] The use of "adapted to" or "configured to" herein is intended to be open and inclusive language that does not exclude devices adapted or configured to perform additional tasks or steps.

[0056] Additionally, the use of “based on” is meant to be open and inclusive, as a process, step, calculation, or other action “based on” one or more stated conditions or values ​​may, in practice, be based on additional conditions or values ​​beyond those stated.

[0057] As used herein, "about," "substantially," or "approximately" includes the stated value and an average value that is within an acceptable range of deviation from the particular value as determined by one of ordinary skill in the art taking into account the measurements in question and the errors associated with the measurement of the particular quantity (i.e., the limitations of the measurement system).

[0058] As used herein, "parallel", "perpendicular", and "equal" include the situations described and situations similar to the situations described, and the range of the similar situations is within an acceptable deviation range, wherein the acceptable deviation range is as determined by a person of ordinary skill in the art taking into account the measurement in question and the errors associated with the measurement of the specific quantity (i.e., the limitations of the measurement system). For example, "parallel" includes absolute parallelism and approximate parallelism, wherein the acceptable deviation range of approximate parallelism can be, for example, a deviation within 5°; "perpendicular" includes absolute perpendicularity and approximate perpendicularity, wherein the acceptable deviation range of approximate perpendicularity can also be, for example, a deviation within 5°. "Equal" includes absolute equality and approximate equality, wherein the acceptable deviation range of approximate equality can be, for example, that the difference between the two equals is less than or equal to 5% of either one.

[0059] It will be understood that when a layer or element is referred to as being on another layer or substrate, it can be directly on the other layer or substrate, or intervening layers may be present therebetween.

[0060] Exemplary embodiments are described herein with reference to cross-sectional and / or plan views that are idealized exemplary drawings. In the drawings, the thickness of layers and the area of ​​regions are exaggerated for clarity. Therefore, variations in shape relative to the drawings due to, for example, manufacturing techniques and / or tolerances are contemplated. Therefore, the exemplary embodiments should not be construed as limited to the shapes of the regions shown herein, but rather include deviations in shape due to, for example, manufacturing. For example, an etched region shown as a rectangle will typically have curved features. Therefore, the regions shown in the drawings are schematic in nature, and their shapes are not intended to illustrate the actual shape of regions of the device and are not intended to limit the scope of the exemplary embodiments.

[0061] In some embodiments, as shown in FIG2 , the chip structure 10 includes a chip wafer unit 1 and a color conversion unit 2 disposed on the light-emitting side of the chip wafer unit 1. The chip wafer unit 1 is configured to emit at least one of a plurality of colors of light, and the color conversion unit 2 is configured to perform color conversion on the color of light emitted by the chip wafer unit 1.

[0062] Exemplarily, the chip wafer unit 1 includes multiple light-emitting layers 13, each configured to emit one of multiple colors. The color conversion unit 2 includes color conversion sections 241 and filling sections 242 corresponding to the light-emitting layers 13. Each color conversion section 241 is disposed opposite at least one light-emitting layer 13, and each filling section 242 is disposed opposite at least one light-emitting layer 13. Each light-emitting layer 13 is disposed corresponding to either a color conversion section 241 or a filling section 242.

[0063] In some examples, the colors of light emitted by each of the plurality of light emitting layers 13 are not exactly the same.

[0064] For example, some of the plurality of light emitting layers 13 emit blue light, some emit green light, and some emit red light.

[0065] In other examples, each of the plurality of light-emitting layers 13 emits light of the same color.

[0066] The following description will be made by taking an example where each light emitting layer 13 emits light of the same color.

[0067] The single color light emitted by the light emitting layer 13 is emitted while maintaining the same color after passing through the filling portion 242 , and is emitted while being converted into light of another color after passing through the color conversion portion 241 , thereby enabling the chip structure 10 to emit light of multiple colors.

[0068] Illustratively, the chip structure 10 includes a functional area AA and a peripheral area AN surrounding the functional area AA. Functional structures in the chip structure 10 , such as the light emitting layer 13 , the color conversion portion 241 and the filling portion 242 , are all located in the functional area AA.

[0069] Exemplarily, the functional structure of the chip structure 10 further includes an anode and a cathode located on opposite sides of the light-emitting layer 13 .

[0070] When preparing a chip structure, for example, multiple chip structures are first formed in a motherboard, and then the motherboard is cut to obtain multiple chip structures.

[0071] In some examples, a diamond knife is used to cut the motherboard; or a grinding wheel knife is used to saw the motherboard.

[0072] Using this method, the edge of the chip structure is prone to cutting debris and micro cracks, which can easily lead to low chip structure yield. At the same time, using this method to cut the motherboard has low cutting accuracy and low cutting efficiency.

[0073] In other examples, a laser surface cutting process is used to cut the motherboard, where a laser beam is irradiated onto one surface of the motherboard and cuts along the thickness direction of the motherboard.

[0074] To ensure complete separation of the multiple chip structures on the motherboard using this method, the laser beam must be directed from one surface of the motherboard to the other, opposite surface. The laser beam's energy must be able to penetrate the motherboard, and therefore, the laser beam's energy must be maintained within a relatively high range to effectively cut the motherboard. Laser cutting generates heat, and the higher the laser beam's energy, the larger the heat-affected zone (HAZ). This can potentially cause the HAZ to overlap the functional area of ​​the chip structure, affecting the light-emitting layer within that area and potentially preventing the chip structure from emitting light properly.

[0075] Based on this, some embodiments of the present disclosure provide a chip structure and a method for manufacturing the same, and a display device to overcome the above problems. The following introduces the chip structure 10 and a method for manufacturing the same, and the display device 100 provided in some embodiments of the present disclosure.

[0076] In the present disclosure, FIG1 is a planar structural diagram of the display device 100, and FIG2 is a cross-sectional structural diagram of the display device 100 according to FIG1 . FIG9 is an enlarged structural diagram of the alternating original layers 2121 and modified layers 2122 included in the edge portion 212. FIG6 is a top-down structural diagram of the coupling structure C, FIG7 is a cross-sectional structural diagram of the coupling structure C after being cut along a scribe line Q, and FIG8 is an enlarged structural diagram of the scribe line Q. FIG10, FIG11, and FIG12 are corresponding side-view structural diagrams of the chip wafer unit 1 during the preparation process, FIG13, FIG14, and FIG15 are corresponding side-view structural diagrams of the color conversion unit 2 during the preparation process, and FIG16, FIG17, FIG18, and FIG19 are corresponding cross-sectional structural diagrams of the respective steps in the process of thinning the substrate motherboard 21' after coupling the initial wafer A and the color conversion substrate B and before laser cutting the substrate motherboard 21'.

[0077] 8 and 20 show top views of the chip structure 10 during the preparation process in which the light emitting layer 13 and other structures in the chip wafer unit 1 are removed to obtain a chip structure 10 comprising only a substrate 21 and a pad layer (e.g., a first pad 15 and a second pad 16).

[0078] In some embodiments of the present disclosure, a display device 100 is provided. As shown in Figures 1 and 2, the display device 100 includes a driving substrate 20 and a plurality of chip structures 10 provided according to any of the above embodiments.

[0079] Exemplarily, the driving substrate 20 includes but is not limited to an FPC (Flexible Printed Circuit) and a PCB (Printed Circuit Board).

[0080] Exemplarily, a circuit structure is provided on a surface of the drive substrate 20 facing the chip structure 10. The chip structure 10 is electrically connected to the circuit structure on the drive substrate 20, for example, via a pad layer (e.g., the first pad 15 and the second pad 16 shown in FIG. 2 ). The drive substrate 20 is configured to drive the chip structure 10 to emit light.

[0081] In some embodiments, as shown in FIG2 , solder paste reflow is used to solder a pad layer (e.g., the first pad 15 and the second pad 16 shown in FIG2 ) to the circuit structure to achieve connection between the chip structure 10 and the drive substrate 20. The drive substrate 20 issues a light-emitting control signal, which is transmitted to the light-emitting layer 13 through the pad layer, thereby driving the light-emitting layer 13 to emit light.

[0082] Exemplarily, as shown in FIG1 , the display device 100 includes a plurality of chip structures 10 that are arranged in an array, for example.

[0083] Exemplarily, as shown in FIG1 , a display device 100 includes a plurality of pixels, each of which includes sub-pixels P (pixels) of at least three colors. The sub-pixels P of at least three colors include at least a first color sub-pixel, a second color sub-pixel, and a third color sub-pixel. The first color, the second color, and the third color are three primary colors, such as R (red), G (green), and B (blue).

[0084] Exemplarily, each chip structure 10 is configured to emit at least one of multiple colors of light.

[0085] In some examples, a single chip structure 10 can emit light of multiple colors. For example, a single chip structure 10 includes multiple light-emitting regions, each of which can emit light of a single color, and the colors of the light emitted by the multiple light-emitting regions are not completely the same.

[0086] When the chip structure 10 is applied to the display device 100, a single chip structure 10 can realize multi-color light emission. For example, a single chip structure 10 can realize R, G, and B three-color light emission, thereby enabling the display device 100 to realize multi-color display.

[0087] It is understood that, when the chip structures 10 have the same size, in some embodiments of the present disclosure, a single chip structure 10 can achieve multi-color light emission. Thus, the light-emitting area corresponding to each color of light is smaller than that of a single chip structure capable of emitting only monochromatic light. This allows the display device 100 to achieve higher pixel accuracy and better display effects. The specific structure of the chip structure 10 is described below.

[0088] Some embodiments of the present disclosure also provide a method for preparing the chip structure 10 .

[0089] As shown in FIG3 , the method for preparing the chip structure 10 includes steps S1 to S4 .

[0090] S1 . As shown in FIG4 , an initial wafer A is formed. The initial wafer A includes a plurality of chip wafer units 1 .

[0091] For example, as shown in FIG4 , each chip wafer unit 1 includes multiple light-emitting layers 13 . Each light-emitting layer 13 is configured to emit one of multiple colors of light. For example, the multiple light-emitting layers 13 emit light of the same color; or at least two of the multiple light-emitting layers 13 emit light of different colors.

[0092] The multiple colors of light include, but are not limited to, blue light, red light, and green light.

[0093] For example, the light emitting layer 13 is, for example, MQW (Multiple Quantum Well).

[0094] Exemplarily, the shape of the initial wafer A includes, but is not limited to, a circle.

[0095] Exemplarily, the shape of the chip wafer unit 1 includes but is not limited to a rectangle.

[0096] S2. As shown in FIG5 , a color conversion substrate B is formed. The color conversion substrate B includes a base substrate motherboard 21 ′ and a plurality of color conversion structures J disposed on the base substrate motherboard 21 ′. Each color conversion structure J and its corresponding base substrate motherboard 21 ′ constitute a color conversion unit 2 .

[0097] Exemplarily, the material of the substrate motherboard 21 ′ is a transparent material, including but not limited to any one of glass, sapphire, silicon carbide, silicon, gallium arsenide or aluminum nitride.

[0098] Exemplarily, the shape of the color conversion substrate B is the same as that of the initial wafer A.

[0099] Exemplarily, the shape of the substrate motherboard 21 ′ includes but is not limited to a circle.

[0100] Exemplarily, the shape of the color conversion unit 2 is the same as that of the chip wafer unit 1 .

[0101] It should be noted that the preparation order of step S1 and step S2 is not limited, and is only used here to illustrate a possible implementation method.

[0102] S3 . As shown in FIG6 , the color conversion substrate B is coupled to the initial wafer A to obtain a coupling structure C. Each chip wafer unit 1 is opposite to a color conversion unit 2 .

[0103] Exemplarily, as shown in FIG. 4 and FIG. 5 , the size of the initial wafer A is 4 inches or 6 inches, and the size of the color conversion substrate B is the same as that of the initial wafer A.

[0104] Exemplarily, as shown in FIG. 2 , the chip wafer unit 1 and the color conversion unit 2 are coupled via a connection layer 3 .

[0105] Exemplarily, the connection layer 3 includes but is not limited to an adhesive layer or a bonding layer.

[0106] In some examples, the color conversion substrate B is coupled to the initial wafer A using a bonding process.

[0107] In other examples, the color conversion substrate B is coupled to the initial wafer A using a bonding process.

[0108] This is merely an example of a possible implementation method and is not intended to limit the specific implementation methods disclosed herein.

[0109] S4. As shown in FIG. 7 , FIG. 8 and FIG. 9 , the laser is sequentially applied to a plurality of focal points D inside the substrate motherboard 21 ′ to perform cutting, so as to form cutting lines inside the substrate motherboard 21 ′.

[0110] The multiple focal points D are sequentially arranged along a first direction X, and the first direction X is perpendicular to a surface of the base substrate motherboard 21 ′ away from the multiple color conversion structures J.

[0111] After cutting, the base substrate motherboard 21' is formed into a plurality of base substrates 21. Each base substrate 21 includes a main portion 211 and an edge portion 212 surrounding the main portion 211. The edge portion 212 includes original layers 2121 and modified layers 2122 arranged alternately along the first direction X, and the layers on the outermost sides in the first direction X are both original layers 2121.

[0112] By applying the laser to multiple focal points D inside the substrate motherboard 21' for cutting, during the process of forming the chip structure 10, the energy of the laser is lower each time the laser cuts than when using surface cutting, thereby reducing the range of the heat-affected zone of the laser beam, avoiding the laser cutting from affecting the functional structures in the chip structure 10, such as the light-emitting layer 13, thereby avoiding the problem of poor light emission in the chip structure 10.

[0113] It should be noted that during the laser cutting process within the substrate motherboard 21', the area near the laser cut (the laser's heat-affected zone) is heated, and the structure within this area undergoes certain changes under the heat of the laser. For example, the substrate motherboard 21' is glass. When the laser cuts the substrate motherboard 21', when the laser cuts at any focal point D, the chemical bonds of the atoms within the glass within the laser's heat-affected zone, such as Si-O bonds (silicon-oxygen covalent bonds), are broken by the laser, resulting in a stress layer within the substrate motherboard 21'. The area between any two stress layers is not affected by the laser heat, and therefore, the atoms therein maintain their original structure and remain unchanged. Thus, in the chip structure 10, a unique structure is formed in which the edge portion 212 of the substrate 21 includes alternating original layers 2121 and modified layers 2122, wherein the modified layers 2122 are the stress layers generated during the laser cutting process.

[0114] The base substrate 21 is cut from the base substrate motherboard 21', and the side surface of the base substrate 21 is the cut surface of the base substrate motherboard 21' (the surface obtained by separating its interior after laser cutting); or, the side surface of the base substrate 21 is a part of the side surface of the base substrate motherboard 21'.

[0115] For example, as shown in FIG8 , in the coupling structure C, the spacing between the functional areas AA of any two chip structures 10 is a scribe line Q. The substrate motherboard 21 ′ includes multiple scribe lines Q, and the laser cuts along each scribe line Q. When the laser cuts along a scribe line Q, the laser sequentially acts on N focal points D within the substrate motherboard 21 ′, and these N focal points are all located within a scribe line Q, where N is a positive integer and N ≥ 2. When cutting each scribe line Q, the number of focal points D acted on by the laser may be the same or different.

[0116] The following description takes laser cutting in a cutting street Q as an example. The laser acts on N focal points D in the motherboard 21 ′ to perform cutting, which includes the following steps.

[0117] As shown in FIG9 , first, the energy focus point of the laser beam is aligned with the first focus D (1), and then the laser beam moves along the Y direction or Z direction shown in FIG8 within the cutting path Q, and the moving path of the laser beam is the laser cutting path; the laser cutting path is located in a plane parallel to the first surface 21 'a or the second surface 21 'b of the substrate motherboard 21 ' where the focus D is located, and the laser cutting path is parallel to the Y direction or Z direction shown in FIG8 .

[0118] The above steps are repeated until the energy focus of the laser beam is aligned with the Nth focus D(n), and the cutting of the base substrate motherboard 21 ′ is completed.

[0119] 9 , when the laser acts on any focal point D for cutting, the laser forms a modified layer 2122 in the substrate motherboard 21 ′. When the laser acts on N focal points D for cutting in sequence, N modified layers 2122 are formed accordingly.

[0120] The laser cutting path during each cutting operation is within a cutting path Q. For example, the laser uses three or four focal points for cutting. It should be noted that the use of three or four focal points for cutting described herein refers to the laser acting sequentially at three or four focal points within the substrate motherboard 21' to perform the cutting. The number of focal points used in laser cutting is merely an example of a possible implementation method and does not limit the specific implementation methods of the present disclosure.

[0121] During the preparation of the chip structure 10 , the laser cuts a total of M cutting lanes Q, where M is a positive integer. The laser cuts the first cutting lane Q( 1 ) to the mth cutting lane Q(m) in sequence.

[0122] In some examples, when the laser cuts the 1st to mth cutting streets Q, the number N of focal spots D used in each cutting is the same.

[0123] For example, when laser cutting the first cutting line Q(1) to the mth cutting line Q(m), three-focus cutting is adopted.

[0124] In other examples, when the laser cuts the 1st to mth cutting streets Q, the number N of focal spots D used in each cutting is not exactly the same.

[0125] For example, when laser cutting the first cutting line Q(1), 3-focus cutting is adopted; when laser cutting the second cutting line Q(2), 4-focus cutting is adopted; when laser cutting the third cutting line Q(3), 3-focus cutting is adopted; when laser cutting the mth cutting line Q(m), 5-focus cutting is adopted.

[0126] For another example, when laser cutting the 1st to mth cutting streets Q, the number N of focal spots D used in each cutting is different, for example.

[0127] Exemplarily, the chip structure 10 includes multiple side surfaces of the substrate substrate 21, all of which are cutting surfaces of the substrate substrate motherboard 21', and the multiple side surfaces are obtained after the laser cuts the multiple cutting lanes Q. It can be understood that when the laser cuts the multiple cutting lanes Q, the number of focal points D acting on the substrate substrate motherboard 21' each time is the same. At this time, the number of modified layers 2122 included in the multiple side surfaces of the substrate substrate 21 is the same; when the laser cuts the multiple cutting lanes Q, the number of focal points D acting on the substrate substrate motherboard 21' each time is not exactly the same. At this time, the number of modified layers 2122 included in the multiple side surfaces of the substrate substrate 21 is not exactly the same.

[0128] As embodied in the chip structure 10, as shown in FIG8 , the substrate 21 forms a special structure including a main portion 211 and an edge portion 212 surrounding the main portion 211. The edge portion 212 includes a plurality of sub-portions 212(k) corresponding one-to-one to the plurality of side surfaces of the substrate 21 (k is the number of side surfaces of the substrate 21, and k side surfaces correspond to k sub-portions of the edge portion 212). The plurality of sub-portions 212(k) of the edge portion 212 all include the same number of modified layers 2122; alternatively, the plurality of sub-portions of the edge portion 212 may include different numbers of modified layers 2122. The number of modified layers 2122 included in each sub-portion 212(k) of the edge portion 212 is the same as the number of focal points D when the laser cuts the portion.

[0129] As shown in FIG8 , the base substrate 21 is, for example, rectangular and includes four side surfaces. Accordingly, the edge portion 212 of the base substrate 21 includes four sub-portions, namely, a first sub-portion 212 (1), a second sub-portion 212 (2), a third sub-portion 212 (3) and a fourth sub-portion 212 (4). The first sub-portion 212 (1), the second sub-portion 212 (2), the third sub-portion 212 (3) and the fourth sub-portion 212 (4) each include, for example, four modified layers 21 22; or, the first sub-section 212(1) and the second sub-section 212(2) include 3 layers of modified layers 2122, and the third sub-section 212(3) and the fourth sub-section 212(4) include 4 layers of modified layers 2122; or, the first sub-section 212(1) includes 3 layers of modified layers 2122, the second sub-section 212(2) includes 4 layers of modified layers 2122, and the third sub-section 212(3) and the fourth sub-section 212(4) include 5 layers of modified layers 2122.

[0130] The laser beam acts on multiple focal points D inside the coupling structure C from one side of the conversion substrate B to perform cutting. As shown in FIG7 , when the laser cuts the coupling structure C, if the laser cuts the substrate motherboard 21' from the side of the initial wafer A, the distance between the position where the laser is emitted and the focal point D is farther than when the laser cuts the substrate motherboard 21' from the side of the conversion substrate B. It can be understood that the farther the distance between the position where the laser is emitted and the focal point D is, the more difficult it is to accurately locate the position of the focal point D. When the positioning of the focal point D is offset and exceeds the range corresponding to the cutting path Q, for example, when the focal point D is located in the functional area AA of the chip structure 10, the functional structure in the functional area AA may be damaged by the laser irradiation during laser cutting, thereby causing the chip structure 10 to have abnormal light emission problems.

[0131] The following description is made by taking an example where each sub-portion of the edge portion 212 includes the same number of modified layers 2122 .

[0132] In some embodiments, in step S4 , as shown in FIG. 7 , the base substrate motherboard 21 ′ is cut from the color conversion substrate B side of the coupling structure C.

[0133] In some examples, in the plurality of chip wafer units included in the initial wafer, a distance between any two adjacent chip structures ranges from 20 μm to 100 μm.

[0134] In some embodiments of the present disclosure, a multi-focus cutting method is used to cut the substrate motherboard 21', which can effectively narrow the width of the cutting street Q. As shown in Figure 8, among the multiple chip wafer units 1 included in the initial wafer A, the distance d4 between any two adjacent chip structures 10 ranges from 20μm to 50μm.

[0135] As shown in FIG7 , among the multiple chip structures 10 arranged in the coupling structure C, when the distance d4 between the functional areas AA of any two adjacent chip structures is relatively small, for example, when the distance d4 ranges from 20 μm to 50 μm, by adopting such a method, the distance between the laser emission position and the focus D is closer, which is more conducive to accurate positioning of the focus D, thereby avoiding the problem that the laser focus D is difficult to align due to the small size of the cutting path Q and deviates from the cutting path Q.

[0136] It is understood that to ensure that the resulting plurality of chip structures 10 are of the same or substantially the same size, the laser cutting path is collinear or substantially collinear with the axis of symmetry of the cutting lane Q. As shown in FIG8 , the cutting lane Q is, for example, rectangular, and a rectangle has two axes of symmetry. The axis of symmetry of the cutting lane Q described herein is the axis of symmetry that coincides with the direction in which the length of the cutting lane Q extends. For example, for the cutting lane Q shown in FIG8 , the laser cutting path is collinear or substantially collinear with the axis of symmetry of the cutting lane Q extending in the direction Z shown in the figure.

[0137] In some embodiments, in step S4, as shown in FIG9 , the laser sequentially acts on N focal points D inside the substrate motherboard 21 ′ for cutting, where N is a positive integer and N ≥ 2. The focal point D farthest from the initial wafer A is the first focal point D(1), and the focal point D closest to the initial wafer A is the Nth focal point D(n). The surface of the substrate motherboard 21 ′ away from the initial wafer A is the first surface 21 ′a, and the surface of the substrate motherboard 21 ′ close to the initial wafer A is the second surface b.

[0138] In some examples, as shown in FIG. 9 , the distance d1 between the first focus D( 1 ) and the first surface 21 ′ a is greater than or equal to the distance d2 between any two adjacent focuses D.

[0139] When the material of the substrate motherboard 21' is glass, when the laser acts on the focal point D in the substrate motherboard 21', cracks will be generated inside the substrate motherboard 21' near the focal point D, and the cracks will extend from the focal point D to a certain area. By controlling the distance d1 between the first focal point D(1) and the first surface 21'a, the cracks generated inside the substrate motherboard 21' when the laser acts on the substrate motherboard 21' are prevented from extending to the first surface 21'a of the substrate motherboard 21', thereby avoiding the problem of cracking and fragmentation of the first surface 21'a of the substrate motherboard 21'.

[0140] In some other examples, as shown in FIG. 9 , the distance d3 between the Nth focus D(n) and the second surface 21 ′ b is greater than or equal to the distance d2 between any two adjacent focuses D.

[0141] By controlling the distance d1 between the Nth focus D(n) and the second surface 21'b, cracks generated inside the substrate motherboard 21' when the laser acts on the inside of the substrate motherboard 21' are prevented from extending to the second surface 21'b of the substrate motherboard 21', thereby avoiding the second surface 21'b of the substrate motherboard 21' from cracking or fragmenting.

[0142] In some other examples, as shown in Figure 9, the distance d1 between the first focus D(1) and the first surface 21'a is greater than or equal to the distance d2 between any two adjacent focuses D, and the distance d3 between the Nth focus D(n) and the second surface 21'b is greater than or equal to the distance d2 between any two adjacent focuses D.

[0143] As described above, by controlling the distance d1 between the first focus D(1) and the first surface 21'a, and the distance d3 between the Nth focus D(n) and the second surface 21'b, when the laser acts on the substrate motherboard 21' for cutting, the cracks generated in the substrate motherboard 21' will not extend to the surface of the substrate motherboard 21', thereby avoiding the problem of cracking and fragmentation on the surface of the substrate motherboard 21'.

[0144] For example, the distance d2 between any two adjacent focal points D is in the range of 15 μm to 35 μm. d2 is, for example, 15 μm, 20 μm, or 35 μm.

[0145] For another example, the distance d1 between the first focus D(1) and the first surface 21'a of the substrate motherboard 21' is in the range of 15 μm to 35 μm. d1 is, for example, 15 μm, 20 μm, or 35 μm. Furthermore, the distance d1 between the first focus D(1) and the first surface 21'a of the substrate motherboard 21' is greater than or equal to 20 μm.

[0146] For another example, the distance d3 between the Nth focal point D(n) and the second surface 21 'b of the substrate motherboard 21 ' is in the range of 15 μm to 35 μm. d3 is, for example, 15 μm, 20 μm, or 35 μm. Furthermore, the distance d3 between the Nth focal point D(n) and the second surface 21 'b of the substrate motherboard 21 ' is greater than or equal to 20 μm.

[0147] By appropriately increasing the distance d1 between the first focus D(1) and the first surface 21'a of the substrate motherboard 21', and the distance d3 between the Nth focus D(n) and the second surface 21'b of the substrate motherboard 21', it is possible to effectively prevent the laser from acting on the focal position of the substrate motherboard 21' during the internal focal point cutting of the substrate motherboard 21'. The cracks generated in the substrate motherboard 21' when the laser acts on the focal position will not extend to the surface of the substrate motherboard 21', thereby avoiding the problem of cracking and fragmentation on the surface of the substrate motherboard 21'.

[0148] It should be noted that, while ensuring that d1 ≥ d2 and d3 ≥ d2, the value of d1 + k × d2 + d3 should also be equal to the thickness of the base substrate motherboard 21 ′ (e.g., the dimension along the direction Z shown in FIG9 ). k is the number of spacings d2 between the N focal points arranged along the first direction X, where k = N-1.

[0149] For example, the thickness of the substrate motherboard 21 ′ is 100 μm. The following description will be made by taking the substrate motherboard 21 ′ having a thickness of 100 μm as an example.

[0150] In some examples, three focal points are used for cutting, where N=3, and the laser sequentially acts on three focal points D inside the substrate motherboard 21 ′ for cutting, where d1+2×d2+d3=100 μm.

[0151] For example, the distance d2 between any two adjacent focal points D is 18 μm, and accordingly, d1+d3=100-18×2=64 μm, then d1=d3=32 μm; or, d1=29 μm, d3=35 μm; or, d1=35 μm, d3=29 μm; or, d1=31 μm, d3=33 μm.

[0152] For another example, the distance d2 between any two adjacent focal points D is 15 μm. Accordingly, d1 + d3 = 100 - 15 × 2 = 70 μm. In this case, d1 = d3 = 35 μm.

[0153] In other examples, four focal points are used for cutting, where N=4, and the laser sequentially acts on four focal points D inside the substrate motherboard 21 ′ for cutting, where d1+3×d2+d3=100 μm.

[0154] For example, the distance d2 between any two adjacent focal points D is 18 μm. Accordingly, d1+d3=100-18×3=46 μm, then d1=d3=23 μm; or, d1=18 μm, d3=28 μm; or, d1=28 μm, d3=18 μm; d1=20 μm, d3=23 μm.

[0155] For example, the distance d2 between any two adjacent focal points D is 15 μm. Accordingly, d1+d3=100-15×3=55 μm. In this case, d1=20 μm, d3=35 μm; or, d1=35 μm, d3=20 μm; or, d1=25 μm, d3=30 μm.

[0156] It should be noted that the above dimensions such as the thickness of the substrate motherboard 21', the distance d2 between any two adjacent focal points D, and the distance (d1 and d3) between the focal points D and the surface of the substrate motherboard 21' are merely examples of possible implementations and are not intended to limit the specific implementations of the present disclosure.

[0157] For example, as shown in FIG9 , the laser sequentially acts on N focal points D inside the substrate motherboard 21 ′ to cut, forming N modified layers 2122 sequentially arranged along the first direction X, and the spacing between any two adjacent modified layers 2122 along the first direction X is greater than 0.

[0158] In some embodiments of the present disclosure, a laser is applied to a substrate motherboard 21' to perform cutting, thereby obtaining multiple chip structures 10. It is understood that the opposing side surfaces of the substrate 21 included in any two adjacent chip structures 10 are cut surfaces, obtained by laser cutting within the substrate motherboard 21'. During the laser cutting process, the area near the laser cut (the laser's heat-affected zone) is heated, and the structure within this area undergoes certain changes under the influence of the laser's heat.

[0159] It should be noted that the stress of the portion of the substrate motherboard 21' close to the focus D and located within the laser heat affected zone is different from that of the remaining positions outside the laser heat affected zone; this is reflected in the chip structure 10 as the stresses of the original layer 2121 and the modified layer 2122 included in the edge portion 212 are different; at the same time, the main body 211 and the original layer 2121 are both portions that are not affected by laser heat, and therefore, the stresses of the main body 211 and the original layer 2121 are the same.

[0160] Under the action of the laser, cracks will form within the substrate motherboard 21', extending from the focal point D in a direction away from the focal point D. The cracks extend in a divergent and irregular direction. Therefore, the light reflectivity (for example, the reflectivity for light with a wavelength range of 380μm to 780μm) of the portion of the substrate motherboard 21' near the focal point D, within the laser heat-affected zone, is different from that of the rest of the substrate motherboard 21'. This is reflected in the chip structure 10 by the different light reflectivities of the original layer 2121 and the modified layer 2122, while the light reflectivities of the original layer 2121 and the main body 211 are the same.

[0161] By controlling the energy of the laser beam within a certain range, the laser beam acts on the focal point D with lower energy, resulting in a smaller heat-affected zone. Accordingly, when the laser acts on the focal point D, the extension range of the cracks generated is smaller. After sequentially cutting through multiple focal points D, the resulting multiple modified layers 2122 are spaced apart along the first direction X and are not connected. Furthermore, because the extension range of the cracks generated when the laser acts on the focal point D is smaller, in the resulting chip structure 10, the modified layer 2122 exists only within the peripheral area AN of the chip structure 10 and does not extend into the functional area AA. As a result, when light emitted from the chip wafer unit 1 passes through the color conversion unit 2 and is emitted, the portion of the substrate 21 located within the functional area AA has a higher light reflectivity, thereby ensuring the luminous effect of the chip structure 10.

[0162] The layers on the outermost sides of the edge portion 212 in the first direction X are both original layers 2121, and the original layers 2121 and the modified layers 2122 are arranged alternately. It can be understood that the original layer 2121 has one more layer than the modified layer 2122, and the number of original layers 2121 is P, P=N+1.

[0163] By adopting a multi-focus cutting method, the laser acts on N focal points D in the substrate motherboard 21' in sequence. When the substrate motherboard 21' of the same thickness is laser cut, the larger the number N of focal points D set, the smaller the energy value of the laser beam acting on a single focal point D can be, and the heat-affected zone during laser cutting is also smaller. In this way, when forming the coupling structure C, the distance d4 between any two adjacent chip structures 10 can also be smaller, so that more chip structures 10 can be set in the coupling structure C of the same size, thereby reducing the manufacturing cost of the chip structure 10.

[0164] Referring to the description of step S4 (the laser is sequentially applied to multiple focal points D inside the substrate motherboard 21' for cutting to form cutting lines inside the substrate motherboard 21') in the previous text, when the coupling structure C is laser cut, a multi-focus cutting method is adopted, and the laser is sequentially applied to multiple focal points D positions inside the substrate motherboard 21' for cutting. In this way, the energy of the laser beam at each action is smaller than that of the surface cutting method. Accordingly, the range of the heat-affected zone will be smaller, thereby making the spacing between the chip structures 10 arranged in the coupling structure C smaller, that is, the width of the cutting path Q is narrower, and more chip structures 10 can be cut from the coupling structure C of the same size. It can be understood that in this way, more chip structures 10 can be prepared with the same time and materials, reducing the preparation cost of the chip structure 10 and improving the preparation efficiency of the chip structure 10.

[0165] As shown in FIG8 , the area between the functional areas AA of any two adjacent chip structures 10 is a scribe line Q. When a laser is applied to a substrate motherboard 21′ for cutting, multiple focal points D are located within the same scribe line Q. The laser cuts along a cutting plane, which is a plane perpendicular to the first surface 21′a or the second surface 21′b of the substrate motherboard 21′ and where the focal points D are located. The scribe line Q is roughly divided into two equal parts (the two parts are of equal or substantially equal size).

[0166] For example, as shown in FIG7 , during the preparation process of the chip structure 10 , each time the substrate motherboard 21 ′ is cut using a laser, the wavelength of the laser is less than 2000 nm.

[0167] For example, each time the base substrate motherboard 21 ′ is cut using laser, the wavelength of the laser used is 1024 nm.

[0168] To clearly describe the method for preparing the chip structure 10, the following description uses the formation of one chip structure 10 as an example. It is understood that the method for preparing the chip structure 10 first forms a coupling structure C comprising a plurality of chip structures 10 arranged in an array, and then obtains a plurality of chip structures 10 by cutting the coupling structure C.

[0169] The following describes the specific implementation of each step in the method for preparing the chip structure 10. The chip structure 10 formed according to this embodiment is the chip structure 10 shown in FIG. 1 and FIG. 2 .

[0170] Exemplarily, step S1 (forming an initial wafer A, the initial wafer A including a plurality of chip wafer units 1 ) includes steps S11 to S16 .

[0171] S11 , as shown in FIG10 , a buffer layer 11 and an N-type gallium nitride layer 12 are stacked and formed on a first substrate W1 .

[0172] Exemplarily, as shown in FIG10 , the first substrate W1 is a silicon-based substrate or a sapphire substrate.

[0173] Exemplarily, as shown in FIG10 , the buffer layer 11 and the N-type gallium nitride layer 12 are formed by, for example, a metal sputtering process or a chemical deposition process.

[0174] S12 . As shown in FIG. 10 , a plurality of light-emitting layers 13 are formed on a side of the N-type gallium nitride layer 12 away from the first substrate W1 .

[0175] In some embodiments, each light emitting layer 13 in the plurality of light emitting layers 13 is configured to emit one of a plurality of colors of light, for example.

[0176] In some examples, the plurality of light emitting layers 13 emit light of the same color, for example.

[0177] Illustratively, the plurality of colors of light include, but are not limited to, blue light.

[0178] Exemplarily, as shown in FIG10 , the light emitting layer 13 includes, for example, a quantum well layer.

[0179] For example, the quantum well layer is a blue quantum well, and the light-emitting layer 13 including the blue quantum well emits blue light.

[0180] For another example, the quantum well layer is a red quantum well, and the light-emitting layer 13 including the red quantum well emits red light.

[0181] For another example, the quantum well layer is a green quantum well, and the light-emitting layer 13 including the green quantum well emits green light.

[0182] S13 , as shown in FIG10 , forming a cathode transfer electrode 14 on a side of the N-type gallium nitride layer 12 away from the first substrate W1 .

[0183] Exemplarily, the cathode switching electrode 14 and the plurality of light-emitting layers 13 are provided in the same layer.

[0184] 8 , the chip structure 10 includes a functional area AA, which includes a connection area A1 and multiple light-emitting areas A2, which are arranged in an array. A cathode transfer electrode 14 is provided in each connection area A1.

[0185] Each light-emitting area A2 is provided with at least one light-emitting layer 13. When each light-emitting area A2 includes multiple light-emitting layers 13, the multiple light-emitting layers 13 are connected to each other. For example, the multiple light-emitting layers 13 in each light-emitting area A2 are sequentially connected in series or in parallel.

[0186] Exemplarily, the cathode switching electrode 14 is made of a conductive material, including but not limited to at least one of gold, silver, lead, tin, copper, titanium, aluminum, molybdenum, nickel gold, and conductive silver paste.

[0187] S14 , as shown in FIG10 , forming a pad layer on a side of the plurality of light emitting layers 13 away from the first substrate W1 , the pad layer including a second pad 16 and a plurality of first pads 15 corresponding to the plurality of light emitting layers 13 one by one.

[0188] Exemplarily, the material of the pad layer is a conductive material.

[0189] The material of the pad layer includes but is not limited to at least one of gold, silver, copper, titanium, aluminum, molybdenum, niobium, nickel gold and conductive silver paste.

[0190] In some examples, the pad layer is a single-layer structure.

[0191] For example, the pad layer is a copper layer.

[0192] In other examples, the pad layer is a multi-layer structure.

[0193] For example, the pad layer has a stacked structure formed of MoNb / Cu / CuNi (molybdenum-niobium alloy / copper / copper-nickel alloy) stacked in sequence.

[0194] Exemplarily, the pad layer is configured to achieve connection between the chip structure 10 and other structures; the pad layer is also configured to transmit electrical signals.

[0195] In some examples, as shown in FIG1 and FIG2 , when the chip structure 10 is applied to a display device 100, multiple chip structures 10 are disposed on a driving substrate 20 (e.g., an FPC or a PCB), and each chip structure 10 is connected to the driving substrate 20 via a first solder pad 15 and a second solder pad 16 within a solder pad layer. For example, the first solder pad 15 and the second solder pad 16 are soldered to the circuit structure of the driving substrate 20 using solder paste reflow, thereby achieving the connection between the chip structure 10 and the driving substrate 20. The electrical signal emitted by the driving substrate 20 is transmitted to the chip structure 10 via the solder pad layer.

[0196] S15 . As shown in FIG11 , a second substrate W2 is formed on a side of the pad layer away from the first substrate W1 .

[0197] Illustratively, the second substrate W2 includes but is not limited to any one of glass, sapphire and PI film (Polyimide Film).

[0198] S16 , as shown in FIG12 , removing the first substrate W1 .

[0199] For example, referring to the previous description of step S3 (coupling the color conversion substrate B with the initial wafer A to obtain a coupling structure C), the side of the color conversion structure J away from the second substrate W2 is configured to be connected to the chip wafer unit 1, and the second substrate W2 serves as a temporary carrier to carry the color conversion structure J after removing the first substrate W1 and before the color conversion structure J is connected to the chip wafer unit 1.

[0200] In some embodiments, step S2 (forming the color conversion substrate B) includes steps S21 to S24.

[0201] S21 , as shown in FIG13 , forming a color filter layer 22 on a base substrate motherboard 21 ′, wherein the color filter layer 22 includes a black matrix 221 and a plurality of filter portions 222 defined by the black matrix 221 .

[0202] Exemplarily, the thickness of the substrate motherboard 21 ′ is h1.

[0203] Exemplarily, the color filter layer 22 is formed by coating, exposure, development, post-baking, and the like.

[0204] For example, the black matrix 221 and the plurality of filter portions 222 defined by the black matrix 221 are formed by coating, exposure, development, post-baking, and the like.

[0205] Exemplarily, each filter section 222 is disposed corresponding to at least one light-emitting layer 13. The plurality of filter sections 222 include, for example, a first filter section, a second filter section, and a third filter section. The first filter section, the second filter section, and the third filter section are disposed opposite to at least one light-emitting layer 13, respectively.

[0206] When each light-emitting area A2 includes multiple light-emitting layers 13, the multiple light-emitting layers 13 in each light-emitting area A2 are, for example, all arranged corresponding to the same filter portion 222; or, the multiple light-emitting layers 13 in each light-emitting area A2 are respectively arranged corresponding to multiple filter portions 222.

[0207] Exemplarily, the substrate motherboard 21 ′ includes but is not limited to a glass substrate, a quartz substrate, a plastic substrate, a sapphire substrate or a silicon-based substrate.

[0208] In the chip structure 10, light emitted by the light emitting layer 13 is sequentially emitted after passing through the filter 222. By providing the filter 222, the color gamut of the light emitted by the light emitting layer 13 can be improved, thereby improving the color gamut of the light emitted by the chip structure 10.

[0209] S22 , as shown in FIG14 , forming a defining dam layer 23 , wherein the defining dam layer 23 is disposed on a side of the color filter layer 22 away from the base substrate motherboard 21 ′, and includes a plurality of openings 231 corresponding to the plurality of filter portions 222 .

[0210] Exemplarily, the definition dam layer 23 is formed by coating, exposure, development, post-baking, etc.

[0211] Illustratively, the plurality of opening areas 231 include a first type of opening area 2311 corresponding to the first filter portion and the second filter portion, and a second type of opening area 2312 corresponding to the third filter portion.

[0212] Each first type opening area 2311 corresponds to a first filter portion or a second filter portion.

[0213] S23 , as shown in FIG14 , forming a color conversion layer 24 , wherein the color conversion layer 24 includes a plurality of color conversion portions 241 and a filling portion 242 disposed in the opening area 231 .

[0214] Exemplarily, the color conversion layer 24 is formed in the opening area by coating, exposure, development, post-baking, or inkjet printing.

[0215] Exemplarily, a quantum dot conversion unit is formed in the first type opening area 2311. The light emitting layer 13 in the light emitting area A2 corresponding to the first type opening area 2311 emits a color light, which is converted into another color light after passing through the quantum dot conversion unit.

[0216] For example, the quantum dot conversion unit uses a red quantum dot luminescent material or a red fluorescent material.

[0217] For another example, the quantum dot conversion unit uses green quantum dot luminescent material or green fluorescent material.

[0218] It should be noted that the material of the quantum dot conversion part can be any material that can achieve the color conversion function. This is only used as an example of a possible implementation method and is not intended to limit the specific implementation methods of the present disclosure.

[0219] Illustratively, a scattering particle portion is formed in the second type opening region 2312. The scattering particle portion is, for example, made of scattering particles.

[0220] It should be noted that the scattering particle portion has good light transmittance. After the light emitted by the chip wafer unit 1 passes through the scattering particle portion, the intensity of the light does not change significantly and remains basically unchanged, thereby ensuring the light extraction effect of the chip structure 10.

[0221] The color light emitted by the light-emitting layer 13 in the light-emitting area A2 corresponding to the second-type opening area 2312 remains the same color after passing through the scattering particles. The scattering particles fill the second-type opening area 2312, thereby improving the thickness uniformity of the dam layer 23 and further improving the thickness uniformity of the chip structure 10.

[0222] S24 , as shown in FIG15 , forming an encapsulation layer 25 . The encapsulation layer 25 covers the color filter layer 22 , the definition dam layer 23 and the color conversion layer 24 .

[0223] For example, the material of the encapsulation layer 25 has good sealing and heat resistance, and includes but is not limited to any one of silicon nitride, silicon oxide, or silicon oxynitride.

[0224] Exemplarily, the encapsulation layer 25 is formed by deposition using a CVD (chemical vapor deposition) process.

[0225] The encapsulation layer 25 effectively prevents the color conversion layer 24 from long-term exposure to air, such as corrosion from water and oxygen, or mechanical damage, which could affect the color conversion effect of the color conversion layer 24. This improves the operational stability of the color conversion layer 24, and thus the operational stability of the chip structure 10. Furthermore, the color conversion layer 24 has better luminous efficiency and heat dissipation, thereby extending the service life of the color conversion layer 24 and, in turn, the chip structure 10.

[0226] In some embodiments, step S3 (coupling the color conversion substrate B to the initial wafer A to obtain a coupling structure C) includes steps S31 to S36, or includes steps S31 to S37.

[0227] S31 . As shown in FIG. 15 , a connection layer 3 is formed on a side of the packaging layer 25 away from the substrate motherboard 21 ′.

[0228] Exemplarily, the chip wafer unit 1 and the color conversion unit 2 are bonded together, for example, via a connecting layer 3 , and the bonding function of the connecting layer 3 may be an adhesive bonding function or a metal bonding function.

[0229] This is merely an example of a possible implementation method and is not intended to limit the specific implementation methods disclosed herein.

[0230] S32 , as shown in FIG16 , coupling the chip wafer unit 1 and the color conversion unit 2 through the connection layer 3 .

[0231] S33 , as shown in FIG17 , remove the second substrate W2 .

[0232] S34. As shown in FIG18 , a protective film 4 is applied to one side of the chip wafer unit 1. The protective film 4 covers the chip wafer unit 1 and the color conversion unit 2 except for the base substrate motherboard 21 ′. The protective film 4 also covers the second surface 21 ′b of the base substrate motherboard 21 ′ and portions of multiple side surfaces of the base substrate motherboard 21 ′ adjacent to the second surface 21 ′b.

[0233] Illustratively, the protective film 4 includes but is not limited to an acid-proof film.

[0234] S35, as shown in FIG17, thinning the base substrate motherboard 21'.

[0235] For example, as shown in Figures 17 and 18, the substrate motherboard 21' is, for example, a glass substrate. When thinning the substrate motherboard 21', the chip wafer unit 1, covered with the protective film 4, is placed in an etching solution (e.g., a potassium nitrate solution). The portion covered by the protective film 4 is protected from damage by the etching solution, while the exposed portion of the substrate motherboard 21' is etched and thinned by the etching solution. The thickness of the substrate motherboard 21' is reduced from h1 to h2.

[0236] S36: As shown in FIG19 , the protective film 4 is removed.

[0237] In some embodiments, after step S36, step S37 is further included.

[0238] S37 , as shown in FIG7 , attaching a third substrate W3 from one side of the chip wafer unit 1 .

[0239] Illustratively, the third substrate W3 has high temperature resistance and good ductility.

[0240] The third substrate W3 includes but is not limited to a blue film.

[0241] This is merely an example of a possible implementation method and is not intended to limit the specific implementation methods of the present disclosure.

[0242] Furthermore, after step S4 (acting the laser on multiple focal points D inside the base substrate motherboard 21 ′ in sequence to perform cutting), step S5 and step S6 are also included.

[0243] S5 . Apply pressure to the substrate motherboard 21 ′ from the side of the substrate motherboard 21 ′ away from the chip wafer unit 1 , so as to cut the substrate motherboard 21 ′ along the cutting surface.

[0244] Since the cracks caused by the laser in the substrate motherboard 21' during the laser cutting process do not extend to the surface of the substrate motherboard 21', it can be understood that at this time, the multiple chip structures 10 have not been completely separated. Therefore, it is necessary to press and split the coupling structure C after laser cutting so that the substrate motherboard 21' can be broken along the cutting surface, so that the multiple chip structures 10 are completely separated from each other.

[0245] S6. As shown in FIG. 20 , the third substrate W3 is extended along the second direction Y and the third direction Z, and the distance between any two adjacent chip structures 10 is greater than zero.

[0246] 20 , in step S6 , the distance k between any two adjacent chip structures 10 is changed from 0 in step S4 to k. For example, the range of k is 20 μm to 30 μm.

[0247] After extending the third substrate W3 through step S6, the plurality of chip structures 10 can be further separated from each other. For example, in step S5, the adjacent side surfaces of the substrates 21 of some adjacent chip structures 10 are not completely separated. Step S6 can further separate the adjacent substrates 21 that are not completely separated.

[0248] It should be noted that the size of k is related to the ductility of the third substrate W3 and is set according to actual conditions during the preparation of the chip structure 10. It is only used as an example of a possible implementation and is not intended to limit the specific implementation of the present disclosure.

[0249] S7 , removing the third substrate W3 .

[0250] Illustratively, after step S6, the substrate motherboard 21' is divided into multiple substrates 21 along the cutting surface, each substrate 21 corresponds to a chip structure 10, and multiple chip structures 10 located on the third substrate W3 are obtained. After the third substrate W3 is removed, multiple chip structures 10 are obtained.

[0251] In step S5, the separation of multiple substrate bases 21 is achieved, so that the multiple chip structures 10 are separated from each other; in step S6, when the third substrate W3 is extended and expanded, the distance between the multiple chip structures 10 is also increased. For example, the multiple chip structures 10 are respectively grabbed and removed from the third substrate W3 by a grabbing device. In this way, the grabbing space for the chip structure 10 is increased, which facilitates the separation of the multiple chip structures 10 from the third substrate W3.

[0252] It can be understood that in the aforementioned steps, the purpose of setting up the third substrate W3 is to enable multiple chip structures 10 to remain on one side surface of the third substrate W3 during step S5 (splitting) and step S6 (film expansion) to avoid damage caused by accidental falling of the chip structure 10.

[0253] It is understandable that in step S4, if the cut surface of the substrate motherboard 21' has been completely separated after laser cutting and the multiple chip structures 10 have become independent structures, then steps S5 and S6 are no longer necessary.

[0254] Some embodiments of the present disclosure provide a chip structure 10. The chip structure 10 is manufactured, for example, using the above-mentioned manufacturing method.

[0255] As shown in Figures 1 and 2, the chip structure 10 includes a chip wafer unit 1 and a color conversion unit 2 disposed on the light-emitting side of the chip wafer unit 1. The color conversion unit 2 includes a base substrate 21, which includes a main body 211 and an edge portion 212 surrounding the main body 211. The edge portion 212 includes original layers 2121 and modified layers 2122 alternately arranged along a first direction X. The original layers 2121 and the modified layers 2122 have different light reflectivities.

[0256] In the edge portion 212 , the layers located on the outermost sides in the first direction X are both original layers 2121 . The first direction X is perpendicular to the surface of the base substrate 21 away from the chip wafer unit 1 .

[0257] Illustratively, the light reflectivity mentioned here refers to the reflectivity of the original layer 2121 and the modified layer 2122 to light with a wavelength ranging from 380 μm to 780 μm.

[0258] For example, during the preparation of the chip structure 10, referring to the description of the chip structure preparation method in the previous text, the laser acts on N focal points inside the substrate motherboard 21' in sequence for cutting. The modified layer 2122 is the part of the substrate motherboard 21' close to the laser cutting surface that is affected by the laser and produces structural changes. The original layer 2121 is the part of the substrate motherboard 21' close to the laser cutting surface that is not affected by the laser and maintains the original structure.

[0259] It should be noted that the base substrate 21 is cut from the base substrate motherboard 21', and the side surface of the base substrate 21 is the cut surface of the base substrate motherboard 21'; alternatively, the side surface of the base substrate 21 is a portion of the side surface of the base substrate motherboard 21'. Both the original layer 2121 and the modified layer 2122 are produced by laser cutting within the base substrate motherboard 21'.

[0260] The structural changes described here include but are not limited to changes in the atomic structure of the material based on the substrate 21 (such as the chemical bonds of atoms in the glass within the laser heat affected zone, such as the Si-O bonds breaking under the action of the laser, resulting in changes in the atomic structure) and / or surface cracks visible to the naked eye.

[0261] 2 , the substrate 21 includes a functional area AA and a peripheral area AN surrounding the functional area AA. The orthographic projection of the chip wafer unit 1 on the substrate 21 is located in the functional area AA. The main body 211 is located at least in the functional area AA, and the edge portion 212 is located in the peripheral area AN.

[0262] Exemplarily, the base substrate 21 is made of a transparent material, including but not limited to glass.

[0263] For example, referring to the description of the preparation method of the chip structure 10 above, the multiple side surfaces of the substrate substrate 21 are the cut surfaces obtained by laser cutting the substrate substrate motherboard 21' when forming the chip structure 10. For example, when the material of the substrate substrate motherboard 21' is glass, cracks will be generated on the cut surface during laser cutting, causing the structure of the part to change, resulting in changes in the light reflectivity and stress of the part. However, the interior of the substrate substrate 21 is not affected by the laser and maintains the original structure of the material (the light reflectivity and stress do not change). This forms a special structure in which the substrate substrate 21 includes a main body 211 and an edge portion 212, and the edge portion 212 includes alternating original layers 2121 and modified layers 2122.

[0264] Referring to the above description of the method for preparing the chip structure 10, it can be understood that the substrate 21 is a unitary structure, and the main portion 211 and the edge portion 212 serve only as a demarcation of the portion of the substrate 21 that is affected by laser cutting during the preparation of the chip structure 10, rather than the substrate 21 being composed of two structural parts. The main portion 211 is the portion of the substrate 21 that is not affected by the laser and does not change during the preparation of the chip structure 10. The edge portion 212 is the portion of the substrate 21 that is close to the laser cutting path during the preparation of the chip structure 10. The modified layer 2122 is the portion of the substrate 21 that is affected by the laser and changes during the laser cutting process during the preparation of the chip structure 10.

[0265] For example, the modified layer 2122 of the substrate 21 has a lower light reflectivity than the main portion 211 and the original layer 2121, and accordingly, a lower light transmittance. Light with an illuminance of P, after passing through the main portion 211 and / or the original layer 2121, has an illuminance of, for example, 0.95P to P; while light with an illuminance of P, after passing through the modified layer 2122, has an illuminance of, for example, 0.8P. It is understood that if the modified layer 2122 extends into the functional area AA, it will affect the light extraction effect of the chip structure 10.

[0266] Exemplarily, the stress of the original layer 2121 and the modified layer 2122 are different.

[0267] It can be understood that the main body 211 of the base substrate 21 is the part inside the base substrate 21 that is not affected by the laser, the modified layer 2122 of the edge portion 212 is the part of the base substrate 21 close to the cutting surface that is affected by the laser and undergoes structural changes, and the original layer 2121 is also the part that is not affected by the laser during laser cutting.

[0268] Exemplarily, the main body portion 211 and the original layer 2121 have the same light reflectivity.

[0269] The light reflectivity mentioned here refers to the reflectivity of the main body 211 and the original layer 2121 to light with a wavelength ranging from 380 μm to 780 μm.

[0270] Exemplarily, the stress of the main body portion 211 is the same as that of the original layer 2121 .

[0271] In some embodiments, as shown in FIG2 , the base substrate 21 includes a first surface 21a and a second surface 21b that are opposite to each other, and a plurality of side surfaces connecting the first surface 21a and the second surface 21b, wherein the second surface 21b is closer to the chip wafer unit 1 than the first surface 21a. As shown in FIG8 , the edge portion 212 includes a plurality of sub-portions 212(k) disposed corresponding to the plurality of side surfaces of the base substrate 21.

[0272] In some examples, the plurality of sub-portions 212 ( k ) include the same number of modified layers 2122 .

[0273] In other examples, the sub-portions 212 ( k ) include different numbers of modified layers 2122 .

[0274] It should be noted that, referring to the above description of the method for preparing the chip structure 10, among the multiple sub-portions 212(k) included in the edge portion 212, the number of modified layers 2122 included in each sub-portion 212(k) is the same as the number of focal points D during laser cutting.

[0275] In some embodiments, referring to the description of the preparation method of the corresponding chip structure 10 above, as shown in FIG8 , the chip structure 10 includes a functional area AA, which includes multiple light-emitting areas A2. Each light-emitting area A2 is provided with at least one light-emitting layer 13. When each light-emitting area A2 includes multiple light-emitting layers 13, the multiple light-emitting layers 13 are connected to each other. The multiple light-emitting layers 13 in each light-emitting area A2 are connected in series or in parallel, for example.

[0276] For example, the plurality of light emitting areas A2 include a first color light emitting area, a second color light emitting area, and a third color light emitting area.

[0277] Exemplarily, the first color is red, the second color is green, and the third color is blue.

[0278] For example, the light-emitting layer 13 in the same light-emitting area A2 is configured to emit one of a plurality of colors of light, including but not limited to blue light.

[0279] In some examples, multiple light-emitting layers 13 are configured to emit blue light. As shown in FIG2 , the blue light emitted by the light-emitting layer 13 in each light-emitting area A2 remains blue light after passing through the color conversion layer 24 , or is converted into red or green light for emission.

[0280] In some examples, the light-emitting layers 13 in different light-emitting areas A2 are configured to emit light of the same color.

[0281] At this time, the chip wafer unit 1 realizes multi-color light emission. For example, the light-emitting layers 13 corresponding to multiple light-emitting areas A2 all emit light of different colors. The color of the light emitted by the light-emitting layer 13 corresponding to each light-emitting area A2 is still the same color after passing through the color conversion unit 2, thereby realizing multi-color light emission of the chip structure 10.

[0282] In other examples, the light-emitting layer 13 in at least two light-emitting areas A2 is configured to emit light of different colors.

[0283] At this time, the chip wafer unit 1 realizes monochromatic light emission, and the light-emitting layers 13 corresponding to multiple light-emitting areas A2, for example, all emit light of the same color. The color light emitted by the light-emitting layer 13 corresponding to each light-emitting area A2 remains the same color after passing through the color conversion unit 2, or is converted into light of other colors for emission, thereby realizing multi-color light emission of the chip structure 10.

[0284] Some embodiments of the present disclosure provide a chip structure 10, as shown in FIG2 , that employs a color conversion unit 2 to convert the color of light emitted by a chip wafer unit 1. Thus, even if the multiple light-emitting layers 13 of the chip wafer unit 1 are configured to emit light of the same color—for example, if all the multiple light-emitting layers 13 are configured to emit blue light—the chip structure 10 can still emit light of multiple colors.

[0285] For example, among the multiple light-emitting layers 13 included in the chip wafer unit 1, the blue light emitted by the light-emitting layer 13 in one light-emitting area A2 remains as blue light after passing through the color conversion layer 24, the blue light emitted by the light-emitting layer 13 in another light-emitting area A2 is converted into red light after passing through the color conversion layer 24, and the blue light emitted by the light-emitting layer 13 in yet another light-emitting area A2 is converted into green light after passing through the color conversion layer 24.

[0286] When the chip structure 10 is applied to the display device 100, for example, only a blue light chip wafer unit 1 needs to be produced, and the blue light emitted by the blue light chip wafer unit 1 can be maintained as blue light for output, or converted into light of other colors, such as red light or green light, for output, through the color conversion unit 2. In this way, when preparing the chip structure 10, the chip wafer unit 1 can achieve monochromatic light output, and the color conversion unit 2 converts the color of the light emitted by the chip wafer unit 1, thereby achieving multi-color light output from the chip structure 10, and further achieving multi-color display of the display device 100.

[0287] In some embodiments, the chip wafer unit can achieve multi-color light emission. At this time, the light-emitting layer in each light-emitting area of ​​the chip structure needs to emit light of different colors. The light-emitting layer is, for example, MQW. It can be understood that in this way, a plurality of MQWs that can emit light of different colors need to be used on a single chip wafer unit to prepare the light-emitting layer in each light-emitting area separately, and the preparation process is relatively cumbersome.

[0288] In some embodiments of the present disclosure, the chip wafer unit 1 realizes monochromatic light emission, and the color conversion unit 2 is used to convert the color of the light emitted by the chip structure 10, thereby realizing multi-color light emission of the chip structure 10. It can be understood that compared to realizing multi-color light emission through the chip wafer unit, in the preparation process of the chip structure 10, the same MQW, such as InGaN MQW (In-poor gallium nitride multiple quantum well), is used to form multiple light-emitting layers 13. At this time, the light-emitting layer 13 can emit blue light. The blue light emitted by the light-emitting layer 13 in each light-emitting area A2 passes through the color conversion layer 24, for example, to maintain blue light emission, or to be converted into red light or green light emission. In this way, the preparation steps of the chip structure 10 are simplified, thereby improving the preparation efficiency of the chip structure.

[0289] Exemplarily, the chip wafer unit 1 and the color conversion unit 2 are bonded together, for example, via a connecting layer 3 , and the bonding function of the connecting layer 3 may be an adhesive bonding function or a metal bonding function.

[0290] For example, the connection layer 3 is an adhesive bonding layer. Compared to metal bonding, an adhesive bonding layer provides higher shear strength and better bonding stability, effectively preventing cracking at the bonding point between the chip wafer unit 1 and the color conversion unit 2. This is merely an example of one possible embodiment and is not intended to limit the specific embodiments disclosed herein.

[0291] The following description is made by taking an example where the number of modified layers 2122 included in the plurality of sub-portions of the edge portion 212 is the same.

[0292] In some embodiments, as shown in FIG9 , the edge portion 212 includes N modified layers 2122 , where N is a positive integer and N ≥ 2. The modified layer 2122 farthest from the chip wafer unit 1 is the first modified layer 2122 ( 1 ), and the modified layer 2122 closest to the chip wafer unit 1 is the Nth modified layer 2122 ( n ).

[0293] In some examples, the distance h1 between the first modified layer 2122 ( 1 ) and the first surface 21 a of the base substrate 21 is greater than or equal to the distance h2 between any two adjacent modified layers 2122 .

[0294] The distance h1 between the first modified layer 2122 ( 1 ) and the first surface 21 a of the base substrate 21 is, for example, in the range of 15 μm to 35 μm.

[0295] Furthermore, a distance h1 between the first modified layer 2122 ( 1 ) and the first surface 21 a of the base substrate 21 is, for example, greater than or equal to 20 μm.

[0296] In some other examples, the distance h3 between the Nth modified layer 2122 (n) and the second surface 21b of the base substrate 21 is greater than or equal to the distance h2 between any two adjacent modified layers 2122 .

[0297] The distance h3 between the Nth modified layer 2122 ( n ) and the second surface 21 b of the base substrate 21 is in a range of 15 μm to 35 μm, for example.

[0298] Furthermore, a distance h3 between the Nth modified layer 2122 ( n ) and the second surface 21 b of the base substrate 21 is greater than or equal to 20 μm.

[0299] In some other examples, the distance h1 between the first modified layer 2122(1) and the first surface 21a of the base substrate 21 is greater than or equal to the distance h2 between any two adjacent modified layers 2122, and the distance h3 between the Nth modified layer 2122(n) and the second surface 21b of the base substrate 21 is greater than or equal to the distance h2 between any two adjacent modified layers 2122. Furthermore, the distance h1 between the first modified layer 2122(1) and the first surface 21a of the base substrate 21 and the distance h3 between the Nth modified layer 2122(n) and the second surface 21b of the base substrate 21 may be the same as or different from each other.

[0300] Referring to the description of the preparation method of the chip structure 10 in the previous text, during the preparation process of the chip structure 10, when the laser acts on the N focal points D in the substrate motherboard 21' in sequence for cutting, in order to avoid the cracks generated in the substrate motherboard 21' during laser cutting from extending to the surface of the substrate motherboard 21', the first focal point (1) and the Nth focal point D(n) need to maintain a certain distance from the surface of the substrate motherboard 21', such as the distances d1 and d3 shown in Figure 9, and d1 and d3 need to be greater than d2, so as to ensure that the cracks generated in the substrate motherboard 21' extend to the surface of the substrate motherboard 21'.

[0301] In this way, the chip structure 10 formed by the preparation method described above is embodied in the chip structure 10 according to the distance relationship between the N focal points D, and the distance relationship between the first focal point (1) and the Nth focal point D(n) and the surface of the substrate motherboard 21', so that the edge portion 212 includes multiple original layers 2121 and modified layers 2122, in which the distance h1 between the first modified layer 2122 and the first surface 21a of the substrate 21 is greater than or equal to the distance h2 between any two adjacent modified layers 2122, and the distance h3 between the Nth modified layer 2122 and the second surface 21b of the substrate 21 is greater than or equal to the distance h2 between any two adjacent modified layers 2122.

[0302] In this way, during the preparation process of the chip structure 10, cracks generated during laser cutting can be avoided from extending to the surface of the base substrate 21, causing problems such as cracking on the surface of the base substrate 21, thereby ensuring the preparation yield of the chip structure 10 and reducing the preparation cost of the chip structure 10.

[0303] In some embodiments, as shown in FIG2 , the color conversion unit 2 further includes a color filter layer 22, a defining dam layer 23, a color conversion layer 24, and an encapsulation layer 25. The color filter layer 22 is disposed on the side of the base substrate 21 facing the chip wafer unit 1. The color filter layer 22 includes a black matrix 221 and a plurality of filter portions 222 defined by the black matrix 221. The defining dam layer 23 is disposed on the side of the color filter layer 22 facing away from the base substrate 21. The defining dam layer 23 includes a plurality of openings 231, each of which is disposed opposite a filter portion 222. The color conversion layer 24 is disposed on the same layer as the defining dam layer 23.

[0304] 7 and 8 , in the orthographic projection onto the base substrate 21 , the black matrix 221 is located within the range enclosed by the edge portion 212 , and a portion of the encapsulation layer 25 located in the peripheral area AN overlaps with the edge portion 212 .

[0305] With reference to the description of the method for preparing the chip structure 10, it can be understood that, during the preparation process of the chip structure 10, the edge portion 212 is formed due to the structural change of the cut surface under the action of the laser when the substrate motherboard 21' is laser cut. Since the portion of the substrate 21 that is affected by the laser and undergoes structural change (e.g., the modified layer 2122 in the edge portion 212) has a lower light reflectivity than the portion that is not affected by the laser (e.g., the main body 211 and the original layer 2121 in the edge portion 212). For example, when the range of the modified layer 2122 extends into the functional area AA, when the light emitted by the chip wafer unit 1 passes through the substrate 21, the reflectivity of the portion of the light entering the modified layer 2122 is lower than that of the portion entering the main body 211 and the original layer 2121, and the transmittance of the light will decrease, thereby reducing the light extraction efficiency of the chip structure.

[0306] Therefore, in order to ensure the luminous effect of the chip structure 10, the part with structural changes on the base substrate 21 should not extend into the functional area AA, that is, the modified layer 2122 in the edge portion 212 needs to be ensured to be located outside the functional area AA (for example, located in the peripheral area AN), so as to ensure that the light emitted by the chip wafer unit 1 passes through the color conversion unit 2 and is emitted. The light can be better reflected in the process of passing through the base substrate 21 and being emitted, thereby ensuring the light extraction efficiency of the chip structure 10.

[0307] It can be understood that, according to the previous description of the edge portion 212, the edge portion 212 is the portion of the substrate substrate 21 close to the cutting surface during the laser preparation process, which is affected by the laser to form a modified layer 2122 (the laser cuts along a focus D to form a modified layer 2122). Therefore, the width of the modified layer 2122 (for example, the dimension e2 shown in Figure 2) is variable, and the width of the modified layer 2122 is less than or equal to the width of the peripheral area AN, and the functional structure main body 211 in the substrate substrate 21 is at least located in the functional area AA and can extend to the peripheral area AN.

[0308] It should be noted that, for example, the base substrate 21 is rectangular. In this case, the base substrate 21 includes four side surfaces and a "U"-shaped peripheral area AN. The peripheral area AN includes four parts corresponding to each side surface. Here, the width of the modified layer 2122 and the width of the peripheral area AN are compared with the width of the peripheral area AN corresponding to any side surface of the base substrate 21 and the width of the modified layer 2122 in the sub-portion 212 (k) of the edge portion 212 located in the peripheral area AN.

[0309] 2 , the plurality of openings 231 include a first type opening 2311 and a second type opening 2312 . The color conversion layer 24 includes a color conversion portion 241 disposed in the first type opening 2311 and a filling portion 242 disposed in the second type opening 2312 .

[0310] Exemplarily, each filter section 222 is disposed corresponding to at least one light-emitting layer 13. The plurality of filter sections 222 include, for example, a first filter section, a second filter section, and a third filter section. The first filter section, the second filter section, and the third filter section are disposed opposite to at least one light-emitting layer 13, respectively.

[0311] When each light-emitting area A2 includes multiple light-emitting layers 13, the multiple light-emitting layers 13 in each light-emitting area A2 are, for example, all arranged corresponding to the same filter portion 222; or, the multiple light-emitting layers 13 in each light-emitting area A2 are respectively arranged corresponding to multiple filter portions 222.

[0312] Exemplarily, the filter portion 222 is a color filter or a color filter film.

[0313] In some examples, the first filter portion is a red filter portion, the second filter portion is a green filter portion, and the third filter portion is a blue filter portion.

[0314] Exemplarily, the color conversion unit 241 is, for example, a quantum dot conversion unit or a fluorescent color conversion unit.

[0315] In some examples, the quantum dot conversion region includes, for example, a first quantum dot conversion region and a second quantum dot conversion region.

[0316] In other examples, the fluorescent color conversion portion includes, for example, a first fluorescent color conversion portion or a second fluorescent color conversion portion.

[0317] For example, the light-emitting layer emits blue light, and after passing through the first quantum dot conversion unit or the first fluorescent color conversion unit, the blue light is converted into red light and emitted.

[0318] For example, the light-emitting layer emits blue light, and after passing through the second quantum dot conversion unit or the second fluorescent color conversion unit, the blue light is converted into green light and emitted.

[0319] It is understandable that the color conversion portion 241 may also be made of other materials as long as it can achieve the color conversion function. This is only an example of a possible implementation and is not intended to limit the specific implementation of the present disclosure.

[0320] Exemplarily, the material of the filling portion 242 includes but is not limited to scattering particles or transparent glue.

[0321] The light-emitting layer 13 in the light-emitting area A2 corresponding to the filling portion 242 emits blue light, for example, and the chip structure 10 corresponding to the same light-emitting area A2 also emits blue light. Therefore, the light emitted by this part of the light-emitting layer 13 does not need to be converted in color. It can be understood that the filling portion 242 is configured to fill the opening area 231 corresponding to it, so that the filling in the opening area 231 is flat, and the material of the filling portion 242 should have good light transmittance, thereby ensuring the luminous effect of the chip structure 10.

[0322] It is understood that the filling portion 242 may also be made of other materials, as long as it can achieve a filling effect on the corresponding opening area 231, has good light transmittance, and does not change the color of light when the light passes through the filling portion 242. This is merely an example of a possible implementation and does not limit the specific implementation of the present disclosure.

[0323] In some embodiments, as shown in Figure 2, the distance between the boundary of the black matrix 221 and the side surface of the base substrate 21 is e1, and the size of the modified layer 2122 in the direction parallel to the first surface 21a of the base substrate 21 and perpendicular to the side surface of the base substrate 21 is e2, and e2≤e1.

[0324] It can be understood that what is compared here is the distance between any side surface of the base substrate 21 and its boundary close to the black matrix 221 .

[0325] Exemplarily, as shown in FIG. 2 , a distance e1 between a boundary of the black matrix 221 and a side surface of the base substrate 21 ranges from 10 μm to 30 μm.

[0326] Exemplarily, as shown in FIG. 2 , a dimension e2 of the modified layer 2122 in a direction parallel to the first surface 21 a of the base substrate 21 and perpendicular to the side surface of the base substrate 21 is in a range of 5 μm to 10 μm.

[0327] Exemplarily, the black matrix 221 is located in the functional area AA.

[0328] Referring to FIG. 2 and the description of the method for preparing the chip structure 10 described above, the distance e1 between the boundary of the black matrix 221 and the boundary of the base substrate 21 is formed after the base substrate motherboard 21' is cut by the laser along the cutting line Q. When cutting the base substrate motherboard 21', the laser cutting path coincides or substantially coincides with the plane perpendicular to the first surface 21'a of the base substrate motherboard 21' and the axis of symmetry of the cutting line Q. Therefore, in the multiple chip structures 10 ultimately formed, the distance e1 between the boundary of the black matrix 221 and the boundary of the base substrate 21 is approximately half of the distance d4 shown in FIG. 8 .

[0329] Specifically, using the preparation method described above, in the coupling structure C including multiple chip structures 10, the width of the cutting line Q (for example, the dimension d4 shown in Figure 8) ranges from 20μm to 50μm. Due to the laser cutting, the cutting path may not be able to completely divide the cutting line Q into two opposite parts.

[0330] Therefore, in the chip structure 10, the distance e1 between the boundary of the black matrix 221 and the boundary of the base substrate 21 is larger than that of the base substrate 21. The range will be larger.

[0331] By controlling the distance between focal point D and the surface (first surface 21'a and / or second surface 21'b) of substrate motherboard 21' during the fabrication process, the width of the peripheral area AN of chip structure 10 is reflected on the formed chip structure 10. When laser cutting substrate motherboard 21', the laser's heat-affected zone (HAZ) cannot cover the surface structures of chip structure 10 (e.g., structures within functional area AA). For example, if the 20μm mark along the cutting line is the encapsulation layer 25, and the HAZ exceeds 20μm during laser cutting, damage to the encapsulation layer 25 will occur, causing the color conversion layer 24 (e.g., color conversion portion 241) encapsulated by the encapsulation layer 25 to fail, resulting in the chip structure 10 being unable to emit light properly.

[0332] Referring to the above description of the preparation method of the chip structure 10, the cutting line mentioned here is the cutting path when the laser cuts along the path where the focus D is located, parallel to the first surface 21'a of the substrate motherboard 21', and located within the cutting path Q during the laser cutting process.

[0333] The above description is merely a specific embodiment of the present disclosure, but the scope of protection of the present disclosure is not limited thereto. Any changes or substitutions that a person skilled in the art can conceive within the technical scope disclosed in the present disclosure should be included within the scope of protection of the present disclosure. Therefore, the scope of protection of the present disclosure should be based on the scope of protection of the claims.

Claims

1. A chip structure, comprising: A chip wafer unit and a color conversion unit arranged on the light-emitting side of the chip wafer unit; wherein, The color conversion unit includes a base substrate, the base substrate includes a main body and an edge portion surrounding the main body, the edge portion includes original layers and modified layers alternately arranged along a first direction, and in the edge portion, the layers located on the outermost sides in the first direction are both original layers; the original layer and the modified layer have different light reflectances; The first direction is perpendicular to a surface of the substrate that is away from the chip wafer unit.

2. The chip structure according to claim 1, wherein: The main body portion has the same light reflectivity as that of the original layer.

3. The chip structure according to claim 1 or 2, wherein: The substrate includes a first surface and a second surface opposite to each other along the first direction, and a plurality of side surfaces connecting the first surface and the second surface, the second surface is closer to the chip wafer unit relative to the first surface, and the edge portion includes a plurality of sub-portions respectively arranged corresponding to the plurality of side surfaces; The number of modified layers included in the multiple sub-sections is the same; or, The numbers of the modified layers included in the multiple sub-sections are not completely the same.

4. The chip structure according to claim 3, wherein: At least one of the plurality of subsections comprises N modified layers, where N is a positive integer and N≥2; The modified layer farthest from the chip wafer unit is the first modified layer, and the distance between the first modified layer and the first surface is greater than the distance between any two adjacent modified layers; and / or, The modified layer closest to the chip wafer unit is the Nth modified layer, and the distance between the Nth modified layer and the second surface is greater than the distance between any two adjacent modified layers.

5. The chip structure according to claim 4, wherein: The distance between the first modified layer and the first surface is in the range of 15 μm to 35 μm; and / or, The distance between the Nth modified layer and the second surface ranges from 15 μm to 35 μm.

6. The chip structure according to claim 4 or 5, wherein: The distance between the first modified layer and the first surface is greater than or equal to 20 μm; and / or, A distance between the Nth modified layer and the second surface is greater than or equal to 20 μm.

7. The chip structure according to any one of claims 1 to 6, wherein: The color conversion unit also includes: A color filter layer is arranged on a side of the base substrate facing the chip wafer unit, and includes a black matrix and a plurality of filter portions defined by the black matrix; in an orthographic projection onto the base substrate, the black matrix is ​​located within a range surrounded by the edge portion; A limiting dam layer is arranged on a side of the color filter layer away from the base substrate, and includes a plurality of opening areas, wherein the plurality of opening areas correspond to the plurality of filter parts one by one; The color conversion layer is arranged on the same layer as the limiting dam layer.

8. The chip structure according to claim 7, wherein: The plurality of opening areas include: a first type of opening area and a second type of opening area; The color conversion layer comprises: a color conversion portion and a filling portion; the color conversion portion is arranged in the first type of opening area, and the filling portion is arranged in the second type of opening area; The color conversion unit includes a quantum dot conversion unit or a fluorescent color conversion unit; The filling part includes a scattering particle part or a transparent glue.

9. The chip structure according to claim 7 or 8, wherein: The substrate base comprises a functional area and a peripheral area surrounding the functional area, and the orthographic projection of the chip wafer unit on the substrate base is located in the functional area; The main body is at least located in the functional area, and the edge is located in the peripheral area; The color conversion unit also includes: The encapsulation layer covers the color filter layer, and in an orthographic projection onto the base substrate, a portion of the encapsulation layer located in the peripheral area overlaps with the edge portion.

10. The chip structure according to any one of claims 7 to 9, wherein: The distance between the boundary of the black matrix and the side surface of the base substrate is e1, and the size of the modified layer in a direction parallel to the first surface and perpendicular to the side surface is e2, and e2≤e1.

11. The chip structure according to claim 10, wherein: A size e2 of the modified layer in a direction parallel to the first surface and perpendicular to the side surface ranges from 5 μm to 10 μm.

12. The chip structure according to any one of claims 7 to 11, wherein: A distance e1 between a boundary of the black matrix and the side surface ranges from 10 μm to 30 μm.

13. A display device, comprising: A driving substrate and a plurality of chip structures as claimed in any one of claims 1 to 12; The driving substrate is coupled to a plurality of the chip structures.

14. A method for preparing a chip structure, comprising: forming an initial wafer; The initial wafer includes a plurality of chip wafer units; forming a color conversion substrate; The color conversion substrate comprises a substrate motherboard and a plurality of color conversion structures arranged on the substrate motherboard, each color conversion structure and its corresponding substrate motherboard being a color conversion unit; The color conversion substrate is coupled to the initial wafer to obtain a coupling structure; each chip wafer unit is opposite to one of the color conversion units; The laser is sequentially applied to a plurality of focal points inside the substrate motherboard for cutting; wherein the plurality of focal points are sequentially arranged along a first direction, and the first direction is perpendicular to a surface of the substrate motherboard away from the plurality of color conversion structures; after the substrate motherboard is cut, a plurality of substrate substrates are formed, each of which comprises a main body and an edge portion surrounding the main body, the edge portion comprises an original layer and a modified layer alternately arranged along the first direction, and The layers located on the outermost sides in the first direction are both original layers.

15. The preparation method according to claim 14, wherein: In the step of sequentially applying laser to a plurality of focal points inside the base substrate motherboard for cutting, the base substrate motherboard is cut from the color conversion substrate side of the coupling structure.

16. The preparation method according to claim 14 or 15, wherein: The substrate motherboard includes a plurality of cutting paths, and the laser performs cutting along the cutting paths; When cutting each cutting path, the number of focal points acted by the laser is the same or different.

17. The preparation method according to any one of claims 14 to 16, wherein The number of the plurality of focal points is N, N is a positive integer, and N≥2, the focal point farthest from the initial wafer is the first focal point, and the focal point closest to the initial wafer is the Nth focal point; The surface of the substrate motherboard away from the initial wafer is the first surface, and the surface of the substrate motherboard close to the initial wafer is the second surface; The distance between the first focus and the first surface is greater than or equal to the distance between any two adjacent focuses; and / or, The distance between the Nth focus and the second surface is greater than or equal to the distance between any two adjacent focuses.

18. The preparation method according to claim 17, wherein: The distance between the first focus and the first surface ranges from 15 μm to 35 μm; and / or, The distance between the Nth focus and the second surface ranges from 15 μm to 35 μm.

19. The preparation method according to any one of claims 14 to 18, wherein The distance between any two adjacent chip structures ranges from 20 μm to 50 μm.

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