Multi-level inverter

Abstract

The bootstrap circuit solves the problem of voltage drop in the bootstrap circuit. The control unit (60) replaces one of the two first voltage vectors with a zero vector and a second voltage vector. The two first voltage vectors belong to a plurality of voltage vectors, each having a reference magnitude and closest to the command voltage vector. The zero vector is defined by a combination of potential levels at each third connection node (13) of the plurality of inverter circuits (1) as high as the potential of the negative electrode (N1). The second voltage vector has the same direction as the first voltage vector and has a size that is twice as large as the first voltage vector. A control unit (60) controls a plurality of first gate drivers (61), a plurality of second gate drivers (62), a plurality of third gate drivers (63), and a plurality of fourth gate drivers (64) in a predetermined control cycle such that a voltage vector other than the first voltage vector included in the plurality of voltage vectors, another first voltage vector among the two first voltage vectors, and a second voltage vector among the two second voltage vectors, are equal to each other. A resultant vector of the zero vector and the second voltage vector is equal to the command voltage vector.

Description

Technical Field

[0001] The present disclosure relates generally to multilevel inverters, and more particularly to a multilevel inverter including a bootstrap circuit. Background Art

[0002] Patent Document 1 discloses a three-phase voltage-source PWM inverter circuit using a bootstrap circuit.

[0003] In the power converter disclosed in Patent Document 1, a three-phase voltage-type PWM inverter circuit includes six switching elements, six gate driver circuits, a microcomputer, a main DC power supply, and three bootstrap circuits.

[0004] Patent document 1 also discloses an inverter control method, the inverter control method including: applying a predetermined switching pattern to each of the three phases of a three-phase inverter to obtain a predetermined voltage vector and supplying the vector to a load, and supplying a control voltage using a bootstrap circuit of each phase. According to the inverter control method, switching control is performed to replace a voltage vector selected during a time period that does not affect an output voltage in a time period in which a bootstrap circuit of any phase maintains a discharge state with a voltage vector that charges the bootstrap circuit every predetermined time period.

[0005] The inverter control method disclosed in Patent Document 1 is a technology related to a two-level inverter and is not applicable to a multi-level inverter.

[0006] Prior art literature

[0007] Patent Literature

[0008] Patent Document 1: Japanese Patent Application Laid-Open No. 5-292755 Summary of the invention

[0009] An object of the present disclosure is to provide a multi-level inverter having the capability of reducing the possibility of causing a voltage drop in a bootstrap circuit.

[0010] A multilevel inverter according to one aspect of the present disclosure includes a DC power supply unit, a plurality of inverter circuits, and a controller. The DC power supply unit includes a positive electrode, a negative electrode, and an intermediate potential node. The plurality of inverter circuits are connected between the positive electrode and the negative electrode of the DC power supply unit. The controller controls the plurality of inverter circuits. Each of the plurality of inverter circuits includes a switching circuit, a first diode, a second diode, a third diode, a fourth diode, a fifth diode, and a sixth diode. In the switching circuit, a first switching element, a second switching element, a third switching element, and a fourth switching element are connected in series in a manner of being arranged in a row from the positive electrode toward the negative electrode. The first diode is connected in anti-parallel to the first switching element. The second diode is connected in anti-parallel to the second switching element. The third diode is connected in anti-parallel to the third switching element. The fourth diode is connected in anti-parallel to the fourth switching element. The fifth diode has a cathode connected to a first connection node between the first switching element and the second switching element, and an anode connected to the intermediate potential node. The sixth diode has an anode connected to a second connection node between the third switching element and the fourth switching element, and a cathode connected to the intermediate potential node. The controller includes a plurality of first gate drivers, a plurality of second gate drivers, a plurality of third gate drivers, a plurality of fourth gate drivers, a plurality of first bootstrap circuits, a plurality of second bootstrap circuits, a plurality of third bootstrap circuits, a power supply unit, and a control unit. Each of the first gate drivers in the plurality of first gate drivers drives a first switching element of a corresponding inverter circuit in the plurality of inverter circuits. Each of the second gate drivers in the plurality of second gate drivers drives a second switching element of a corresponding inverter circuit in the plurality of inverter circuits. Each of the third gate drivers in the plurality of third gate drivers drives a third switching element of a corresponding inverter circuit in the plurality of inverter circuits. Each of the fourth gate drivers in the plurality of fourth gate drivers drives a fourth switching element of a corresponding inverter circuit in the plurality of inverter circuits. The plurality of first bootstrap circuits are arranged one-to-one for the plurality of first gate drivers. Each of the first bootstrap circuits in the plurality of first bootstrap circuits supplies voltage to a corresponding first gate driver in the plurality of first gate drivers. The plurality of second bootstrap circuits are arranged one-to-one for the plurality of second gate drivers. Each of the second bootstrap circuits in the plurality of second bootstrap circuits supplies voltage to a corresponding second gate driver in the plurality of second gate drivers. The plurality of third bootstrap circuits are provided one-to-one for the plurality of third gate drivers. Each of the plurality of third bootstrap circuits supplies voltage to a corresponding third gate driver of the plurality of third gate drivers. The power supply unit supplies voltage to the plurality of fourth gate drivers.The control unit controls the plurality of first gate drivers, the plurality of second gate drivers, the plurality of third gate drivers, and the plurality of fourth gate drivers. The control unit selects a plurality of voltage vectors located adjacent to the command voltage vector from a group of voltage vectors, each of the voltage vectors in the group being defined by a combination of potential levels at respective third connection nodes, wherein in a corresponding inverter circuit in the plurality of inverter circuits, at each third connection node, the second switching element and the third switching element are connected to each other. Each of the voltage vectors in the group of voltage vectors is defined by a combination of potential levels at respective third connection nodes, wherein in a corresponding inverter circuit in the plurality of inverter circuits, at each third connection node, the second switching element and the third switching element are connected to each other. The control unit replaces one of the two first voltage vectors with a zero vector and a second voltage vector. The two first voltage vectors belong to the plurality of voltage vectors, each having a reference magnitude, and are located closest to the command voltage vector. The zero vector is defined by a combination of potential levels at respective third connection nodes that are as high as the potential at the negative electrode, wherein the second switching element and the third switching element are connected to each other at respective third connection nodes in the respective inverter circuits among the plurality of inverter circuits. The second voltage vector has the same direction as the first voltage vector and has a magnitude twice as large as the first voltage vector. The control unit controls the plurality of first gate drivers, the plurality of second gate drivers, the plurality of third gate drivers, and the plurality of fourth gate drivers within a predetermined control cycle so that a composite vector of voltage vectors other than the first voltage vector included in the plurality of voltage vectors, the other first voltage vector of the two first voltage vectors, the zero vector, and the second voltage vector is equal to the command voltage vector.

[0011] A multilevel inverter according to another aspect of the present disclosure includes a DC power supply unit, a plurality of inverter circuits, and a controller. The DC power supply unit includes a positive electrode, a negative electrode, and an intermediate potential node. The plurality of inverter circuits are connected between the positive electrode and the negative electrode of the DC power supply unit. The controller controls the plurality of inverter circuits. Each of the plurality of inverter circuits includes a switching circuit, a first diode, a second diode, a third diode, a fourth diode, a fifth diode, and a sixth diode. In the switching circuit, a first switching element, a second switching element, a third switching element, and a fourth switching element are connected in series in a manner of being arranged in a row from the positive electrode toward the negative electrode. The first diode is connected in anti-parallel to the first switching element. The second diode is connected in anti-parallel to the second switching element. The third diode is connected in anti-parallel to the third switching element. The fourth diode is connected in anti-parallel to the fourth switching element. The fifth diode has a cathode connected to a first connection node between the first switching element and the second switching element, and an anode connected to the intermediate potential node. The sixth diode has an anode connected to a second connection node between the third switching element and the fourth switching element, and a cathode connected to the intermediate potential node. The controller includes a plurality of first gate drivers, a plurality of second gate drivers, a plurality of third gate drivers, a plurality of fourth gate drivers, a plurality of first bootstrap circuits, a plurality of second bootstrap circuits, a plurality of third bootstrap circuits, a power supply unit, and a control unit. Each of the first gate drivers in the plurality of first gate drivers drives a first switching element of a corresponding inverter circuit in the plurality of inverter circuits. Each of the second gate drivers in the plurality of second gate drivers drives a second switching element of a corresponding inverter circuit in the plurality of inverter circuits. Each of the third gate drivers in the plurality of third gate drivers drives a third switching element of a corresponding inverter circuit in the plurality of inverter circuits. Each of the fourth gate drivers in the plurality of fourth gate drivers drives a fourth switching element of a corresponding inverter circuit in the plurality of inverter circuits. The plurality of first bootstrap circuits are arranged one-to-one for the plurality of first gate drivers. Each of the first bootstrap circuits in the plurality of first bootstrap circuits supplies voltage to a corresponding first gate driver in the plurality of first gate drivers. The plurality of second bootstrap circuits are arranged one-to-one for the plurality of second gate drivers. Each of the second bootstrap circuits in the plurality of second bootstrap circuits supplies voltage to a corresponding second gate driver in the plurality of second gate drivers. The plurality of third bootstrap circuits are provided one-to-one for the plurality of third gate drivers. Each of the plurality of third bootstrap circuits supplies voltage to a corresponding third gate driver of the plurality of third gate drivers. The power supply unit supplies voltage to the plurality of fourth gate drivers.The control unit controls the plurality of first gate drivers, the plurality of second gate drivers, the plurality of third gate drivers, and the plurality of fourth gate drivers. The control unit selects a plurality of voltage vectors located adjacent to the command voltage vector from a group of voltage vectors, each of the voltage vectors in the group being defined by a combination of potential levels at respective third connection nodes, wherein in a corresponding inverter circuit among the plurality of inverter circuits, at each third connection node, the second switching element and the third switching element are connected to each other. Each of the voltage vectors in the group is defined by a combination of potential levels at respective third connection nodes, wherein in a corresponding inverter circuit among the plurality of inverter circuits, at each third connection node, the second switching element and the third switching element are connected to each other. The control unit replaces the first voltage vector with a zero vector and a second voltage vector. The first voltage vector belongs to the plurality of voltage vectors, has a reference magnitude, and is located closest to the command voltage vector. The zero vector is defined by a combination of potential levels at respective third connection nodes that are as high as the potential at the negative electrode, wherein in a corresponding inverter circuit among the plurality of inverter circuits, at each third connection node, the second switching element and the third switching element are connected to each other. The second voltage vector has the same direction as the first voltage vector and has a magnitude twice as large as the first voltage vector. The control unit controls the plurality of first gate drivers, the plurality of second gate drivers, the plurality of third gate drivers, and the plurality of fourth gate drivers within a predetermined control period so that a composite vector of voltage vectors other than the first voltage vector included in the plurality of voltage vectors, the zero vector, and the second voltage vector is equal to the command voltage vector.

[0012] A multilevel inverter according to another aspect of the present disclosure includes a DC power supply unit, a plurality of inverter circuits and a controller. The DC power supply unit includes a positive electrode, a negative electrode and an intermediate potential node. The plurality of inverter circuits are connected between the positive electrode and the negative electrode of the DC power supply unit. The controller controls the plurality of inverter circuits. Each of the plurality of inverter circuits includes: a first switching element, a second switching element, a third switching element and a fourth switching element; and a first diode, a second diode, a third diode and a fourth diode. The first diode, the second diode, the third diode and the fourth diode are respectively connected in anti-parallel to the first switching element, the second switching element, the third switching element and the fourth switching element. In each of the plurality of inverter circuits, the first switching element and the second switching element are connected in series in a manner of being arranged in a row from the positive electrode toward the negative electrode. In each of the plurality of inverter circuits, a series circuit of the third switching element and the fourth switching element is connected between the intermediate potential node and an output node. The output contact is a connection node between the first switching element and the second switching element. The controller includes a plurality of first gate drivers, a plurality of second gate drivers, a plurality of third gate drivers, a plurality of fourth gate drivers, a plurality of bootstrap circuits, a power supply unit, and a control unit. Each of the first gate drivers in the plurality of first gate drivers drives a first switching element of a corresponding inverter circuit in the plurality of inverter circuits. Each of the second gate drivers in the plurality of second gate drivers drives a second switching element of a corresponding inverter circuit in the plurality of inverter circuits. Each of the third gate drivers in the plurality of third gate drivers drives a third switching element of a corresponding inverter circuit in the plurality of inverter circuits. Each of the fourth gate drivers in the plurality of fourth gate drivers drives a fourth switching element of a corresponding inverter circuit in the plurality of inverter circuits. The plurality of bootstrap circuits are arranged one-to-one for the plurality of first gate drivers. Each of the bootstrap circuits in the plurality of bootstrap circuits supplies voltage to a corresponding first gate driver in the plurality of first gate drivers. The power supply unit supplies voltage to the plurality of second gate drivers and the plurality of third gate drivers. The control unit controls the plurality of first gate drivers, the plurality of second gate drivers, the plurality of third gate drivers, and the plurality of fourth gate drivers. The control unit selects a plurality of voltage vectors located adjacent to the command voltage vector from a group of voltage vectors. Each voltage vector in the group of voltage vectors is defined by a combination of potential levels at a plurality of connection nodes of the plurality of inverter circuits. The control unit replaces one of the two first voltage vectors with a zero vector and a second voltage vector.The two first voltage vectors belong to the plurality of voltage vectors, each having a reference magnitude, and are located closest to the command voltage vector. The zero vector is defined by a combination of potential levels at the plurality of connection nodes of the plurality of inverter circuits that are as high as the potential at the negative electrode. The second voltage vector has the same direction as the first voltage vector and has a magnitude twice as large as the first voltage vector. The control unit controls the plurality of first gate drivers, the plurality of second gate drivers, the plurality of third gate drivers, and the plurality of fourth gate drivers within a predetermined control cycle so that a composite vector of the voltage vectors other than the first voltage vector included in the plurality of voltage vectors, the zero vector, and the second voltage vector is equal to the command voltage vector.

[0013] A multilevel inverter according to another aspect of the present disclosure includes a DC power supply unit, a plurality of inverter circuits and a controller. The DC power supply unit includes a positive electrode, a negative electrode and an intermediate potential node. The plurality of inverter circuits are connected between the positive electrode and the negative electrode of the DC power supply unit. The controller controls the plurality of inverter circuits. Each of the plurality of inverter circuits includes: a first switching element, a second switching element, a third switching element and a fourth switching element; and a first diode, a second diode, a third diode and a fourth diode. The first diode, the second diode, the third diode and the fourth diode are respectively connected in anti-parallel to the first switching element, the second switching element, the third switching element and the fourth switching element. In each of the plurality of inverter circuits, the first switching element and the second switching element are connected in series in a manner of being arranged in a row from the positive electrode toward the negative electrode. In each of the plurality of inverter circuits, a series circuit of the third switching element and the fourth switching element is connected between the intermediate potential node and an output node. The output contact is a connection node between the first switching element and the second switching element. The controller includes a plurality of first gate drivers, a plurality of second gate drivers, a plurality of third gate drivers, a plurality of fourth gate drivers, a plurality of bootstrap circuits, a power supply unit, and a control unit. Each of the first gate drivers in the plurality of first gate drivers drives a first switching element of a corresponding inverter circuit in the plurality of inverter circuits. Each of the second gate drivers in the plurality of second gate drivers drives a second switching element of a corresponding inverter circuit in the plurality of inverter circuits. Each of the third gate drivers in the plurality of third gate drivers drives a third switching element of a corresponding inverter circuit in the plurality of inverter circuits. Each of the fourth gate drivers in the plurality of fourth gate drivers drives a fourth switching element of a corresponding inverter circuit in the plurality of inverter circuits. The plurality of bootstrap circuits are arranged one-to-one for the plurality of first gate drivers. Each of the bootstrap circuits in the plurality of bootstrap circuits supplies voltage to a corresponding first gate driver in the plurality of first gate drivers. The power supply unit supplies voltage to the plurality of second gate drivers and the plurality of third gate drivers. The control unit controls the plurality of first gate drivers, the plurality of second gate drivers, the plurality of third gate drivers, and the plurality of fourth gate drivers. The control unit selects a plurality of voltage vectors located adjacent to the command voltage vector from a group of voltage vectors. Each voltage vector in the group of voltage vectors is defined by a combination of potential levels at a plurality of connection nodes of the plurality of inverter circuits. The control unit replaces each first voltage vector of the two first voltage vectors with a zero vector and a second voltage vector.The two first voltage vectors belong to the plurality of voltage vectors, each having a reference magnitude, and are located closest to the command voltage vector. The zero vector is defined by a combination of potential levels at the plurality of connection nodes of the plurality of inverter circuits that are as high as the potential at the negative electrode. The second voltage vector has the same direction as the first voltage vector and has a magnitude twice as large as the first voltage vector. The control unit controls the plurality of first gate drivers, the plurality of second gate drivers, the plurality of third gate drivers, and the plurality of fourth gate drivers within a predetermined control cycle so that a composite vector of the voltage vectors other than the first voltage vector included in the plurality of voltage vectors, the zero vector, and the second voltage vector is equal to the command voltage vector. BRIEF DESCRIPTION OF THE DRAWINGS

[0014] Figure 1 is a circuit diagram of a system including a multilevel inverter according to a first embodiment;

[0015] Figure 2 illustrating a current path in a case where a switching circuit of a multilevel inverter is in a first switching state;

[0016] Figure 3 illustrating a discharge path and a charge path in a case where a switching circuit of a multilevel inverter is in a first switching state;

[0017] Figure 4 illustrating a current path in a case where a switching circuit of a multilevel inverter is in a second switching state;

[0018] Figure 5 illustrating a discharge path and a charge path in a case where a switching circuit of a multilevel inverter is in a second switching state;

[0019] Figure 6 illustrating a current path in a case where a switching circuit of a multilevel inverter is in a third switching state;

[0020] Figure 7 illustrating a discharge path and a charge path in a case where a switching circuit of a multilevel inverter is in a third switching state;

[0021] Figure 8 showing voltage command values ​​for each phase in a multilevel inverter;

[0022] Fig. 9 A set of voltage vectors for a multi-level inverter is illustrated;

[0023] Fig.10 A set of voltage vectors more specifically relating to a multi-level inverter is illustrated;

[0024] Fig.11 is a vector diagram illustrating how the control unit operates in a multilevel inverter;

[0025] Fig.12 A illustrates a command voltage vector and a first voltage vector regarding a multilevel inverter;

[0026] Fig.12 B illustrates a command voltage vector, a zero vector, and a second voltage vector for a multilevel inverter;

[0027] Fig.13 is a timing diagram illustrating a switching state in each phase of a multilevel inverter according to a comparative example;

[0028] Fig.14 is a timing chart illustrating ON / OFF states of first to fourth switching elements of a multilevel inverter according to a comparative example;

[0029] Fig.15 is a timing chart illustrating a switching state in each phase in a case where the multilevel inverter according to the first embodiment has controlled the inverter circuit for each phase by replacing the first voltage vector with a zero vector and a second voltage vector;

[0030] Fig.16 is a timing diagram illustrating ON / OFF states of first to fourth switching elements in a case where the multilevel inverter has controlled the inverter circuit by replacing the first voltage vector with a zero vector and a second voltage vector;

[0031] Fig.17 is a timing diagram illustrating a switching state in each phase of a multilevel inverter according to a comparative example;

[0032] Fig.18 is a timing chart illustrating ON / OFF states of first to fourth switching elements of a multilevel inverter according to a comparative example;

[0033] Fig.19 is a timing chart illustrating a switching state in each phase in a case where the multilevel inverter according to the first embodiment has controlled the inverter circuit for each phase by replacing the first voltage vector with a zero vector and a second voltage vector;

[0034] Fig. 20 is a timing diagram illustrating ON / OFF states of first to fourth switching elements in a case where the multilevel inverter has controlled the inverter circuit by replacing the first voltage vector with a zero vector and a second voltage vector;

[0035] Fig.21is a timing chart illustrating a switching state in each phase in a case where the multilevel inverter according to the second embodiment has controlled the inverter circuit for each phase by replacing the first voltage vector with a zero vector and a second voltage vector;

[0036] Fig. 22 is a timing diagram illustrating ON / OFF states of first to fourth switching elements in a case where the multilevel inverter has controlled the inverter circuit by replacing the first voltage vector with a zero vector and a second voltage vector;

[0037] Fig.23 is a timing diagram illustrating switching states in each phase in a case where a multilevel inverter has controlled an inverter circuit for each phase by replacing a first voltage vector with a zero vector and a second voltage vector;

[0038] Fig.24 is a timing diagram illustrating ON / OFF states of first to fourth switching elements in a case where the multilevel inverter has controlled the inverter circuit by replacing the first voltage vector with a zero vector and a second voltage vector;

[0039] Fig.25 is a circuit diagram of a system including a multilevel inverter according to a modified example;

[0040] Fig.26 is a circuit diagram of a system including a multilevel inverter according to a third embodiment;

[0041] Fig. 27 illustrating a current path in a case where a switching circuit of a multilevel inverter is in a first switching state;

[0042] Fig.28 illustrating a discharge path in a case where a switching circuit of a multilevel inverter is in a first switching state;

[0043] Fig.29 illustrating a current path in a case where a switching circuit of a multilevel inverter is in a second switching state;

[0044] Fig.30 illustrating a discharge path in a case where a switching circuit of a multilevel inverter is in a second switching state;

[0045] Fig.31 illustrating a current path in a case where a switching circuit of a multilevel inverter is in a third switching state;

[0046] Fig.32 illustrating a discharge path and a charge path in a case where a switching circuit of a multilevel inverter is in a third switching state;

[0047] Fig.33illustrating a discharge path in a case where a switching circuit of a multilevel inverter is in a second switching state;

[0048] Fig.34 showing voltage command values ​​for each phase in a multilevel inverter;

[0049] Fig.35 A set of voltage vectors for a multi-level inverter is illustrated;

[0050] Fig.36 A set of voltage vectors more specifically relating to a multi-level inverter is illustrated;

[0051] Fig.37 is a vector diagram illustrating how the control unit operates in a multilevel inverter;

[0052] Fig.38 A illustrates a command voltage vector and a first voltage vector regarding a multilevel inverter;

[0053] Fig.38 B illustrates a command voltage vector, a zero vector, and a second voltage vector for a multilevel inverter;

[0054] Fig.39 is a timing diagram illustrating a switching state in each phase of a multilevel inverter according to a comparative example;

[0055] Fig.40 is a timing chart illustrating ON / OFF states of first to fourth switching elements in a multilevel inverter according to a comparative example;

[0056] Fig.41 is a timing chart illustrating a switching state in each phase in a case where the multilevel inverter according to the third embodiment has controlled the inverter circuit for each phase by replacing the first voltage vector with a zero vector and a second voltage vector;

[0057] Fig.42 is a timing diagram illustrating ON / OFF states of first to fourth switching elements in a case where the multilevel inverter has controlled the inverter circuit by replacing the first voltage vector with a zero vector and a second voltage vector;

[0058] Fig.43 is a timing diagram illustrating a switching state in each phase of a multilevel inverter according to a comparative example;

[0059] Fig.44 is a timing chart illustrating ON / OFF states of first to fourth switching elements in a multilevel inverter according to a comparative example;

[0060] Fig.45is a timing chart illustrating a switching state in each phase in a case where the multilevel inverter according to the third embodiment has controlled the inverter circuit for each phase by replacing the first voltage vector with a zero vector and a second voltage vector;

[0061] Fig.46 is a timing diagram illustrating ON / OFF states of first to fourth switching elements in a case where the multilevel inverter has controlled the inverter circuit by replacing the first voltage vector with a zero vector and a second voltage vector;

[0062] Fig.47 is a timing chart illustrating a switching state in each phase in a case where the multilevel inverter according to the fourth embodiment has controlled the inverter circuit for each phase by replacing the first voltage vector with a zero vector and a second voltage vector;

[0063] Fig.48 is a timing diagram illustrating ON / OFF states of first to fourth switching elements in a case where the multilevel inverter has controlled the inverter circuit by replacing the first voltage vector with a zero vector and a second voltage vector;

[0064] Fig.49 is a timing diagram illustrating switching states in each phase in a case where a multilevel inverter has controlled an inverter circuit for each phase by replacing a first voltage vector with a zero vector and a second voltage vector;

[0065] Fig.50 is a timing diagram illustrating ON / OFF states of first to fourth switching elements in a case where the multilevel inverter has controlled the inverter circuit by replacing the first voltage vector with a zero vector and a second voltage vector;

[0066] Fig.51 is a circuit diagram of a system including a multilevel inverter according to a fifth embodiment;

[0067] Fig.52 is a circuit diagram of a system including a multilevel inverter according to a sixth embodiment;

[0068] Fig.53 is a circuit diagram of a system including a multilevel inverter according to a seventh embodiment; and

[0069] Fig.54 is a circuit diagram of a system including a multilevel inverter according to an eighth embodiment. DETAILED DESCRIPTION

[0070] (First embodiment)

[0071] Now refer to Figures 1 to 12 B is used to illustrate the multilevel inverter 100 according to the first embodiment.

[0072] (1) Summary

[0073] like Figure 1 As shown, the multilevel inverter 100 may include, for example, a DC power supply unit 3, a plurality of (e.g., three) inverter circuits 1, and a controller 6. The DC power supply unit 3 includes a positive electrode P1, a negative electrode N1, and an intermediate potential node M1. The plurality of inverter circuits 1 are connected between the positive electrode P1 and the negative electrode N1 of the DC power supply unit 3. The controller 6 controls the plurality of inverter circuits 1.

[0074] The multilevel inverter 100 is a diode-clamped three-level three-phase inverter. In the multilevel inverter 100, each inverter circuit in the plurality of inverter circuits 1 has an output terminal 41. In the multilevel inverter 100, an AC load RA1 is connected to the plurality of output terminals (AC terminals) 41. The AC load RA1 may be, for example, a three-phase motor. In the multilevel inverter 100, one inverter circuit in the plurality of inverter circuits 1 is an inverter circuit 1U for outputting a U-phase voltage, another inverter circuit in the plurality of inverter circuits 1 is an inverter circuit 1V for outputting a V-phase voltage, and the remaining one inverter circuit in the plurality of inverter circuits 1 is an inverter circuit 1W for outputting a W-phase voltage.

[0075] Each of the plurality of inverter circuits 1 includes a switching circuit 10, a first diode D1, a second diode D2, a third diode D3, and a fourth diode D4. Each of the plurality of inverter circuits 1 also includes a fifth diode D5 and a sixth diode D6. In the multilevel inverter 100, the potential at the intermediate potential node M1 is clamped by the fifth diode D5 and the sixth diode D6 of each inverter circuit 1.

[0076] In each switching circuit 10 , a first switching element Q1 , a second switching element Q2 , a third switching element Q3 , and a fourth switching element Q4 are connected in series in such a manner as to be arranged in order from the positive electrode P1 toward the negative electrode N1 .

[0077] In each inverter circuit 10, a first diode D1 is connected in anti-parallel to the first switching element Q1. A second diode D2 is connected in anti-parallel to the second switching element Q2. A third diode D3 is connected in anti-parallel to the third switching element Q3. A fourth diode D4 is connected in anti-parallel to the fourth switching element Q4. A cathode of a fifth diode D5 is connected to a first connection node 11 between the first switching element Q1 and the second switching element Q2, and an anode thereof is connected to an intermediate potential node M1. An anode of a sixth diode D6 is connected to a second connection node 12 between the third switching element Q3 and the fourth switching element Q4, and a cathode thereof is connected to the intermediate potential node M1.

[0078] The controller 6 includes a plurality of (for example, three) first gate drivers 61, a plurality of (for example, three) second gate drivers 62, a plurality of (for example, three) third gate drivers 63, and a plurality of (for example, three) fourth gate drivers 64. In addition, the controller 6 also includes a plurality of (for example, three) first bootstrap circuits 71, a plurality of (for example, three) second bootstrap circuits 72, a plurality of (for example, three) third bootstrap circuits 73, a power supply unit 9, and a control unit 60.

[0079] Each of the plurality of first gate drivers 61 drives a first switching element Q1 of a corresponding inverter circuit in the plurality of inverter circuits 1. Each of the plurality of second gate drivers 62 drives a second switching element Q2 of a corresponding inverter circuit in the plurality of inverter circuits 1. A third gate driver in the plurality of third gate drivers 63 drives a third switching element Q3 of a corresponding inverter circuit in the plurality of inverter circuits 1. A fourth gate driver in the plurality of fourth gate drivers 64 drives a fourth switching element Q4 of a corresponding inverter circuit in the plurality of inverter circuits 1.

[0080] The plurality of first bootstrap circuits 71 are provided one-to-one for the plurality of first gate drivers 61. Each first bootstrap circuit in the plurality of first bootstrap circuits 71 supplies voltage to a corresponding first gate driver in the plurality of first gate drivers 61. The plurality of second bootstrap circuits 72 are provided one-to-one for the plurality of second gate drivers 62. Each second bootstrap circuit in the plurality of second bootstrap circuits 72 supplies voltage to a corresponding second gate driver in the plurality of second gate drivers 62. The plurality of third bootstrap circuits 73 are provided one-to-one for the plurality of third gate drivers 63. The third bootstrap circuit in the plurality of third bootstrap circuits 73 supplies voltage to a corresponding third gate driver in the plurality of third gate drivers 63. The power supply unit 9 supplies voltage to the plurality of fourth gate drivers 64.

[0081] The control unit 60 controls a plurality of first gate drivers 61 , a plurality of second gate drivers 62 , a plurality of third gate drivers 63 , and a plurality of fourth gate drivers 64 .

[0082] (2) Details of power converter

[0083] The DC power supply unit 3 includes a first capacitor C1 and a second capacitor C2. In the DC power supply unit 3, the first capacitor C1 and the second capacitor C2 are connected in series. In the DC power supply unit 3, the first terminal of the first capacitor C1 is connected to the first DC terminal 31, the second terminal of the first capacitor C1 is connected to the first terminal of the second capacitor C2, and the second terminal of the second capacitor C2 is connected to the second DC terminal 32. In the DC power supply unit 3, the connection node between the first capacitor C1 and the second capacitor C2 is an intermediate potential node M1. The DC power supply unit 3 also includes a first DC terminal 31 connected to the positive electrode P1 and a second DC terminal 32 connected to the negative electrode N1. The DC voltage source E1 can be connected between the first DC terminal 31 and the second DC terminal 32, for example. In this case, the output voltage Vdc of the DC voltage source E1 is applied between the positive electrode P1 and the negative electrode N1 of the DC power supply unit 3. Note that the capacitance of the second capacitor C2 is equal to the capacitance of the first capacitor C1. As used herein, the expression “the capacitance of the second capacitor C2 is equal to the capacitance of the first capacitor C1” refers not only to the case where the capacitance of the second capacitor C2 is completely equal to the capacitance of the first capacitor C1, but also to the case where the capacitance of the second capacitor C2 is equal to or greater than 95% of the capacitance of the first capacitor C1 and equal to or less than 105% of the capacitance of the first capacitor C1.

[0084] In the following description, for convenience of description, regarding the plurality of switching circuits 10, the switching circuit 10 included in the inverter circuit 1U will be referred to as “switching circuit 10U” hereinafter, the switching circuit 10 included in the inverter circuit 1V will be referred to as “switching circuit 10V” hereinafter, and the switching circuit 10 included in the inverter circuit 1W will be referred to as “switching circuit 10W” hereinafter. Likewise, regarding the plurality of output terminals 41, the output terminal 41 included in the inverter circuit 1U will be referred to as “output terminal 41U” hereinafter, the output terminal 41 included in the inverter circuit 1V will be referred to as “output terminal 41V” hereinafter, and the output terminal 41 included in the inverter circuit 1W will be referred to as “output terminal 41W” hereinafter.

[0085] In each switching circuit 10, the first switching element Q1, the second switching element Q2, the third switching element Q3 and the fourth switching element Q4 each have a control terminal, a first main terminal and a second main terminal. The first switching element Q1, the second switching element Q2, the third switching element Q3 and the fourth switching element Q4 of each switching circuit 10 can be, for example, a MOSFET. Thus, in each switching circuit 10, the control terminal, the first main terminal and the second main terminal of each switching element in the first switching element Q1, the second switching element Q2, the third switching element Q3 and the fourth switching element Q4 are respectively the gate terminal, the drain terminal and the source terminal. In each switching circuit 10, the MOSFET used as the first switching element Q1, the second switching element Q2, the third switching element Q3 and the fourth switching element Q4 can be, for example, a normally OFF n-channel MOSFET. Note that the MOSFET can be, for example, a Si-based MOSFET or a SiC-based MOSFET.

[0086] In each switching circuit 10, a control terminal of the first switching element Q1 is connected to a corresponding first gate driver among the plurality of first gate drivers 61. Furthermore, in each switching circuit 10, a control terminal of the second switching element Q2 is connected to a corresponding second gate driver among the plurality of second gate drivers 62. Furthermore, in each switching circuit 10, a control terminal of the third switching element Q3 is connected to a corresponding third gate driver among the plurality of third gate drivers 63. Furthermore, in each switching circuit 10, a control terminal of the fourth switching element Q4 is connected to a corresponding fourth gate driver among the plurality of fourth gate drivers 64.

[0087] In each switching circuit 10, the first main terminal of the first switching element Q1 is connected to the positive electrode P1 of the DC power supply unit 3, and the second main terminal of the first switching element Q1 is connected to the first main terminal of the second switching element Q2. In addition, in each switching circuit 10, the second main terminal of the second switching element Q2 is connected to the first main terminal of the third switching element Q3. In addition, in each switching circuit 10, the second main terminal of the third switching element Q3 is connected to the first main terminal of the fourth switching element Q4, and the second main terminal of the fourth switching element Q4 is connected to the negative electrode N1 of the DC power supply unit 3.

[0088] In the inverter circuit 1U, the third connection node 13 between the second switching element Q2 and the third switching element Q3 of the switching circuit 10U is connected to the output terminal 41U. In the inverter circuit 1V, the third connection node 13 between the second switching element Q2 and the third switching element Q3 of the switching circuit 10V is connected to the output terminal 41V. In the inverter circuit 1W, the third connection node 13 between the second switching element Q2 and the third switching element Q3 of the switching circuit 10W is connected to the output terminal 41W. For example, the third connection node 13 of the inverter circuit 1U is connected to the U phase of the AC load RA1 via the output terminal 41U. For example, the third connection node 13 of the inverter circuit 1V is connected to the V phase of the AC load RA1 via the output terminal 41V. For example, the third connection node 13 of the inverter circuit 1W is connected to the W phase of the AC load RA1 via the output terminal 41W.

[0089] In each inverter circuit 1, the anode of the first diode D1 is connected to the second main terminal (source terminal) of the first switching element Q1, and the cathode of the first diode D1 is connected to the first main terminal (drain terminal) of the first switching element Q1. In addition, in each inverter circuit 1, the anode of the second diode D2 is connected to the second main terminal (source terminal) of the second switching element Q2, and the cathode of the second diode D2 is connected to the first main terminal (drain terminal) of the second switching element Q2. In addition, in each inverter circuit 1, the anode of the third diode D3 is connected to the second main terminal (source terminal) of the third switching element Q3, and the cathode of the third diode D3 is connected to the first main terminal (drain terminal) of the third switching element Q3. In addition, in each inverter circuit 1, the anode of the fourth diode D4 is connected to the second main terminal (source terminal) of the fourth switching element Q4, and the cathode of the fourth diode D4 is connected to the first main terminal (drain terminal) of the fourth switching element Q4.

[0090] In each inverter circuit 1, the first diode D1 may be replaced by a parasitic diode of a MOSFET used as the first switching element Q1. In addition, in each inverter circuit 1, the second diode D2 may be replaced by a parasitic diode of a MOSFET used as the second switching element Q2. In addition, in each inverter circuit 1, the third diode D3 may be replaced by a parasitic diode of a MOSFET used as the third switching element Q3. In addition, in each inverter circuit 1, the fourth diode D4 may be replaced by a parasitic diode of a MOSFET used as the fourth switching element Q4.

[0091] In each inverter circuit 1, the cathode of the fifth diode D5 is connected to the first connection node 11 between the first switching element Q1 and the second switching element Q2. On the other hand, the anode of the fifth diode D5 is connected to the intermediate potential node M1 of the DC power supply unit 3. As used herein, the "intermediate potential node M1" refers to a node whose potential is intermediate between the potential at the positive electrode P1 of the DC power supply unit 3 and the potential at the negative electrode N1 thereof. In the first embodiment, the intermediate potential node M1 is connected to the ground terminal, and therefore, the potential at the intermediate potential node M1 is 0V. In this case, assuming that the voltage across the DC power supply unit 3 is Vdc, the potential at the positive electrode P1 is Vdc / 2 and the potential at the negative electrode N1 is -Vdc / 2.

[0092] The cathode of the sixth diode D6 is connected to the intermediate potential node M1. The anode of the sixth diode D6 is connected to the second connection node 12 between the third switching element Q3 and the fourth switching element Q4.

[0093] The plurality of first gate drivers 61 are provided one-to-one for the plurality of first switching elements Q1. Each of the plurality of first gate drivers 61 is connected to a control terminal of a corresponding first switching element in the first switching element Q1. Each of the plurality of first gate drivers 61 drives a corresponding first switching element in the first switching element Q1. The plurality of first gate drivers 61 are connected to a control unit 60. The control unit 60 outputs a plurality of first control signals S1 (reference signal S2) associated one-to-one with the plurality of first gate drivers 61. Figure 2 ). Each of the plurality of first gate drivers 61 controls the ON / OFF state of the corresponding first switching element Q1 according to the supplied first control signal S1.

[0094] The plurality of second gate drivers 62 are provided one-to-one for the plurality of second switching elements Q2. Each of the plurality of second gate drivers 62 is connected to the control terminal of the corresponding second switching element in the second switching element Q2. Each of the plurality of second gate drivers 62 drives the corresponding second switching element in the second switching element Q2. The plurality of second gate drivers 62 are connected to the control unit 60. The control unit 60 outputs a plurality of second control signals S2 (refer to Figure 2 ). Each of the plurality of second gate drivers 62 controls the ON / OFF state of the corresponding second switching element Q2 according to the supplied second control signal S2.

[0095] The plurality of third gate drivers 63 are provided one-to-one for the plurality of third switching elements Q3. Each of the plurality of third gate drivers 63 is connected to the control terminal of the corresponding third switching element in the third switching element Q3. Each of the plurality of third gate drivers 63 drives the corresponding third switching element in the third switching element Q3. The plurality of third gate drivers 63 are connected to the control unit 60. The control unit 60 outputs a plurality of third control signals S3 (reference signal S4) associated one-to-one with the plurality of third gate drivers 63. Figure 2 ). Each of the plurality of third gate drivers 63 controls the ON / OFF state of the corresponding third switching element Q3 according to the supplied third control signal S3.

[0096] The plurality of fourth gate drivers 64 are provided one-to-one for the plurality of fourth switching elements Q4. Each of the plurality of fourth gate drivers 64 is connected to the control terminal of the corresponding fourth switching element in the fourth switching element Q4. Each of the plurality of fourth gate drivers 64 drives the corresponding fourth switching element in the fourth switching element Q4. The plurality of fourth gate drivers 64 are connected to the control unit 60. The control unit 60 outputs a plurality of fourth control signals S4 (reference signal S4) associated one-to-one with the plurality of fourth gate drivers 64. Figure 2 ). Each of the plurality of fourth gate drivers 64 controls the ON / OFF state of the corresponding fourth switching element Q4 according to the supplied fourth control signal S4.

[0097] A plurality of first bootstrap circuits 71 are provided one-to-one for a plurality of first gate drivers 61. Each of the plurality of first bootstrap circuits 71 supplies voltage to a corresponding first gate driver in the first gate driver 61. Each of the plurality of first bootstrap circuits 71 includes a diode D17, a resistor R17, and a capacitor C17 (hereinafter referred to as "boost capacitor C17"). In each of the plurality of first bootstrap circuits 71, an anode of the diode D17 is connected to a positive side terminal of the power supply unit 9, and a cathode of the diode D17 is connected to a first terminal of the capacitor C17 via the resistor R17. The first terminal of the capacitor C17 is connected to a high potential power supply terminal 61H (reference voltage) of the corresponding first gate driver 61. Figure 3 ). The second terminal of the capacitor C17 is connected to the low potential power supply terminal 61L (reference Figure 3 ). The first bootstrap circuit 71 supplies a voltage required by the first gate driver 61 to turn on the first switching element Q1 to the corresponding first gate driver 61. Each of the plurality of first bootstrap circuits 71 further includes a Zener diode Z17 connected in parallel with the capacitor C17.

[0098] The plurality of second bootstrap circuits 72 are provided one-to-one for the plurality of second gate drivers 62. Each of the plurality of second bootstrap circuits 72 supplies voltage to a corresponding second gate driver in the second gate driver 62. Each of the plurality of second bootstrap circuits 72 includes a diode D27, a resistor R27, and a capacitor C27 (hereinafter referred to as a "boost capacitor C27"). In each of the second bootstrap circuits 72, an anode of the diode D27 is connected to a positive side terminal of the power supply unit 9, and a cathode of the diode D27 is connected to a first terminal of the capacitor C27 via the resistor R27. The first terminal of the capacitor C27 is connected to a high potential power supply terminal 62H (reference voltage) of the corresponding second gate driver 62. Figure 3 ). The second terminal of the capacitor C27 is connected to the low potential power supply terminal 62L of the corresponding second gate driver 62 (reference Figure 3 ). The second bootstrap circuit 72 supplies a voltage required by the second gate driver 62 to turn on the second switching element Q1 to the corresponding second gate driver 62. Each of the plurality of second bootstrap circuits 72 further includes a Zener diode Z27 connected in parallel with the capacitor C27.

[0099] A plurality of third bootstrap circuits 73 are provided one-to-one for a plurality of third gate drivers 63. Each of the plurality of third bootstrap circuits 73 supplies voltage to a corresponding third gate driver 63 among the third gate drivers 63. Each of the plurality of third bootstrap circuits 73 includes a diode D37, a resistor R37, and a capacitor C37 (hereinafter referred to as "boost capacitor C37"). In each of the third bootstrap circuits 73, an anode of the diode D37 is connected to a positive side terminal of the power supply unit 9, and a cathode of the diode D37 is connected to a first terminal of the capacitor C37 via the resistor R37. The first terminal of the capacitor C37 is connected to a high potential power supply terminal 63H (reference voltage) of the corresponding third gate driver 63. Figure 3 ). The second terminal of the capacitor C37 is connected to the low potential power supply terminal 63L (reference Figure 3 ). The third bootstrap circuit 73 supplies a voltage required by the third gate driver 63 to turn on the third switching element Q3 to the corresponding third gate driver 63. Each of the plurality of third bootstrap circuits 73 further includes a Zener diode Z37 connected in parallel with the capacitor C37.

[0100] The power supply unit 9 supplies voltage to the plurality of (three) first bootstrap circuits 71, the plurality of (three) second bootstrap circuits 72, the plurality of (three) third bootstrap circuits 73, and the plurality of (three) fourth gate drivers 64. The power supply unit 9 may be, for example, a DC power supply including an insulating DC-DC converter 91. The positive side terminal of the power supply unit 9 is connected to the high potential power supply terminal 64H (reference numeral 64H) of each of the plurality of fourth gate drivers 64. Figure 3 ), and the negative side terminal of the power supply unit 9 is connected to the low potential power supply terminal 64L (reference Figure 3 ).

[0101] The control unit 60 controls a plurality of first gate drivers 61, a plurality of second gate drivers 62, a plurality of third gate drivers 63, and a plurality of fourth gate drivers 64. This enables the control unit 60 to control a plurality of first switching elements Q1, a plurality of second switching elements Q2, a plurality of third switching elements Q3, and a plurality of fourth switching elements Q4. The agent that performs the function of the control unit 60 includes a computer system. The computer system includes a single or multiple computers. The computer system may include a processor and a memory as its main hardware components. The computer system is used as an agent that performs the function of the control unit 60 according to the present disclosure by causing the processor to execute a program stored in the memory of the computer system. The program may be pre-stored in the memory of the computer system. Alternatively, the program may also be downloaded via a telecommunication line, or distributed after being recorded in a non-transitory storage medium such as a memory card, an optical disk, or a hard disk drive (disk) (any of which is readable by the computer system). The processor of the computer system may be composed of a single or multiple electronic circuits including a semiconductor integrated circuit (IC) or a large-scale integrated circuit (LSI). These electronic circuits may be integrated together on a single chip or distributed on multiple chips, whichever is appropriate. These multiple chips may be gathered together in a single device or distributed among multiple devices without limitation.

[0102] The control unit 60 outputs a plurality of (three) first control signals S1 (reference signal) for controlling a plurality of (three) first switching elements Q1. Figure 2 ), a plurality of (three) second control signals S2 (referenced to) for controlling a plurality of (three) second switching elements Q2 Figure 2 ), a plurality of (three) third control signals S3 (referenced to) for controlling a plurality of third switching elements Q3 Figure 2 ), and a plurality of (three) fourth control signals S4 for controlling a plurality of (three) fourth switching elements Q4. Note that Figure 2 In FIG. 1 , only one of the three inverter circuits 1 is shown, and the illustration of the other two inverter circuits 1 is omitted. Figure 2, the illustration of the plurality of first gate drivers 61, the plurality of second gate drivers 62, the plurality of third gate drivers 63, the plurality of fourth gate drivers 64, the plurality of first bootstrap circuits 71, the plurality of second bootstrap circuits 72, the plurality of third bootstrap circuits 73, and the power supply unit 9 is omitted. Figure 3 In FIG. 1 , only one of the three inverter circuits 1 is shown, and the illustration of the other two inverter circuits 1 is omitted. Figure 3 In the figure, the illustration of the other two first gate drivers 61, the other two second gate drivers 62, the other two third gate drivers 63, the other two fourth gate drivers 64, the other two first bootstrap circuits 71, the other two second bootstrap circuits 72 and the other two third bootstrap circuits 73 are omitted.

[0103] The three first control signals S1 are a first control signal S1U for controlling the first switching element Q1 of the switching circuit 10U, a first control signal S1V for controlling the first switching element Q1 of the switching circuit 10V, and a first control signal S1W for controlling the first switching element Q1 of the switching circuit 10W.

[0104] The three second control signals S2 are a second control signal S2U for controlling the second switching element Q2 of the switching circuit 10U, a second control signal S2V for controlling the second switching element Q2 of the switching circuit 10V, and a second control signal S2W for controlling the second switching element Q2 of the switching circuit 10W.

[0105] The three third control signals S3 are a third control signal S3U for controlling the third switching element Q3 of the switching circuit 10U, a third control signal S3V for controlling the third switching element Q3 of the switching circuit 10V, and a third control signal S3W for controlling the third switching element Q3 of the switching circuit 10W.

[0106] The three fourth control signals S4 are a fourth control signal S4U for controlling the fourth switching element Q4 of the switching circuit 10U, a fourth control signal S4V for controlling the fourth switching element Q4 of the switching circuit 10V, and a fourth control signal S4W for controlling the fourth switching element Q4 of the switching circuit 10W.

[0107] Each of the plurality of first control signals S1, the plurality of second control signals S2, the plurality of third control signals S3, and the plurality of fourth control signals S4 may be, for example, a signal having a potential level that alternates between a first potential level (hereinafter referred to as a "low level") and a second potential level (hereinafter referred to as a "high level") that is higher than the first potential level. The first potential level may be, for example, 0V, and the second potential level is a potential level that is higher than the gate threshold voltage of the MOSFET. That is, in each of the plurality of control signals (including the plurality of first control signals S1, the plurality of second control signals S2, the plurality of third control signals S3, and the plurality of fourth control signals S4), the first potential level is a potential level for turning OFF the switching element associated with the control signal, and the second potential level is a potential level for turning ON the switching element associated with the control signal.

[0108] Each first switching element among the plurality of first switching elements Q1 turns ON when its associated first control signal S1 has a high level, and turns OFF when its associated first control signal S1 has a low level. Each second switching element among the plurality of second switching elements Q2 turns ON when its associated second control signal S2 has a high level, and turns OFF when its associated second control signal S2 has a low level. Each third switching element among the plurality of third switching elements Q3 turns ON when its associated third control signal S3 has a high level, and turns OFF when its associated third control signal S3 has a low level. Each fourth switching element among the plurality of fourth switching elements Q4 turns ON when its associated fourth control signal S4 has a high level, and turns OFF when its associated fourth control signal S4 has a low level.

[0109] In the multilevel inverter 100, each inverter circuit in the plurality of inverter circuits 1 is controlled toward one of the first switching state, the second switching state, and the third switching state. That is, in the multilevel inverter 100, in each inverter circuit in the three inverter circuits 1U, 1V, and 1W, the switching state of its switching circuit 10 is controlled toward any one of the first switching state, the second switching state, and the third switching state. The first switching state, the second switching state, and the third switching state are different from each other in the combination of the ON / OFF state of the first switching element Q1 to the fourth switching element Q4. In each inverter circuit in the plurality of inverter circuits 1, its output voltage in the first switching state, its output voltage in the second switching state, and its output voltage in the third switching state are different from each other. That is, in each inverter circuit in the plurality of inverter circuits 1, the potential level of the output voltage changes at three levels according to the state of the first switching element Q1 to the fourth switching element Q4. Note that, regarding the output voltages of the plurality of inverter circuits 1 , the output voltage of the U-phase inverter circuit 1U, the output voltage of the V-phase inverter circuit 1V, and the output voltage of the W-phase inverter circuit 1W have mutually different phases.

[0110] The first switching state herein refers to a combination in which both the first switching element Q1 and the second switching element Q2 are turned ON and both the third switching element Q3 and the fourth switching element Q4 are turned OFF. When controlled toward the first switching state, each of the plurality of inverter circuits 1 can deliver an output voltage having a potential level at the positive electrode P1 of the DC power supply unit 3. In each of the plurality of inverter circuits 1 in the first switching state, the potential at the third connection node 13 is as high as the potential level (e.g., Vdc / 2) at the positive electrode P1 of the DC power supply unit 3.

[0111] The second switching state here refers to a combination in which both the first switching element Q1 and the fourth switching element Q4 are turned OFF and both the second switching element Q2 and the third switching element Q3 are turned ON. When controlled toward the second switching state, each of the plurality of inverter circuits 1 can deliver an output voltage having a potential level at the intermediate potential node M1 of the DC power supply unit 3. In each of the plurality of inverter circuits 1 in the second switching state, the potential at the third connection node 13 is as high as the potential level (e.g., 0) at the intermediate potential node M1.

[0112] The third switching state here refers to a combination in which both the first switching element Q1 and the second switching element Q2 are turned OFF and both the third switching element Q3 and the fourth switching element Q4 are turned ON. When controlled toward the third switching state, each of the plurality of inverter circuits 1 can deliver an output voltage having a potential level at the negative electrode N1 of the DC power supply unit 3. In each of the plurality of inverter circuits 1 in the third switching state, the potential at the third connection node 13 is as high as the potential level (e.g., -Vdc / 2) at the negative electrode N1 of the DC power supply unit 3.

[0113] When the switching circuit 10 of each inverter circuit 1 is in the first switching state, the current flows along Figure 2 The path shown in FIG. 1 sequentially passes through the positive electrode P1 of the DC power supply unit 3, the first switching element Q1, the second switching element Q2, the third connection node 13, and the output terminal 41 so that the AC load RA1 (reference Figure 1 )’s output voltage is Vdc / 2.

[0114] In addition, when the switching circuit 10 of the inverter circuit 1 is in the first switching state, the capacitor C17 of the first bootstrap circuit 71 supplies the first gate driver 61 with a voltage required for the first gate driver 61 to turn on the first switching element Q1. Figure 3 As shown, the capacitor C17 of the first bootstrap circuit 71 is connected to the Figure 3 As shown, the discharge is performed sequentially through the capacitor C17, the high potential power supply terminal 61H of the first gate driver 61, the low potential power supply terminal 61L of the first gate driver 61, and the discharge path Ru1 of the capacitor C17. As a result, in the first bootstrap circuit 71, the voltage across the capacitor C17 decreases over time.

[0115] Furthermore, when the switching circuit 10 of the inverter circuit 1 is in the first switching state, the voltage required for the second gate driver 62 to turn on the second switching element Q2 is supplied from the capacitor C27 of the second bootstrap circuit 72 to the second gate driver 62. Thus, the capacitor C27 of the second bootstrap circuit 72 is discharged through the discharge path Ru2 that passes through the capacitor C27, the high potential power supply terminal 62H of the second gate driver 62, the low potential power supply terminal 62L of the second gate driver 62, and the capacitor C27 in sequence. As a result, in the second bootstrap circuit 72, the voltage across the capacitor C27 decreases with the passage of time.

[0116] In addition, if Figure 3As shown, assuming that the voltage across the capacitor C17 is Vo1, the voltage across the capacitor C27 is Vo2, the voltage across the diode D17 is Vd1, the voltage across the resistor R17 is VR1, and the voltage across the second switching element Q2 is Vf2, when the switching circuit 10 of each inverter circuit 1 is in the first switching state, if the first condition is satisfied, the capacitor C17 is charged with the charge in the capacitor C27. In this case, the first condition is Vo2>(Vo1+Vd1+VR1+Vf2). The charging path Ru1 for charging the capacitor C17 with the charge in the capacitor C27 is a path that passes through the capacitor C27, the resistor R27, the diode D17, the resistor R17, the capacitor C1, the first connection node 11, the second switching element Q2, and the capacitor C27 in sequence.

[0117] On the other hand, when the switching circuit 10 of the inverter circuit 1 is in the second switching state, the current flows along, for example, Figure 4 As shown, the current flows in a path (i.e., a path indicated by a thick solid arrow) sequentially through, for example, the intermediate potential node M1 of the DC power supply unit 3, the fifth diode D5, the second switching element Q2, the third connection node 13, and the output terminal 41, so that the voltage value of the output voltage for the AC load RA1 is equal to zero. More specifically, when the switching circuits 10U, 10V, and 10W are in the second switching state, the third switching state, and the third switching state, respectively, the current flows along a path sequentially through the intermediate potential node M1 of the DC power supply unit 3, the fifth diode D5, the second switching element Q2 of the switching circuit 10U, the third connection node 13, and the output terminal 41.

[0118] Alternatively, when the switching circuit 10 of the inverter circuit 1 is in the second switching state, the current may also be supplied via, for example, Figure 4 As shown, the current flows along the path (i.e., the path indicated by the thick dashed arrow) that passes through the output terminal 41, the third connection node, the third switching element Q3, the second connection node 12, and the sixth diode D6 in sequence, so that the voltage value of the output voltage for the AC load RA1 is equal to zero. More specifically, when the switching circuits 10U, 10V, and 10W are in the second switching state, the second switching state, and the first switching state, respectively, the current flows along the path (i.e., the path indicated by the thick dashed arrow) that passes through the output terminal 41, the third connection node, the third switching element Q3, the second connection node 12, and the sixth diode D6 of the inverter circuit 1U in sequence, so that the voltage value of the output voltage for the AC load RA1 is equal to zero.

[0119] Furthermore, when the switching circuit 10 of the inverter circuit 1 is in the second switching state, the voltage required for the second gate driver 62 to turn on the second switching element Q2 is supplied from the capacitor C27 of the second bootstrap circuit 72 to the second gate driver 62. Figure 5 As shown, the discharge is performed sequentially through the capacitor C27, the high potential power supply terminal 62H of the second gate driver 62, the low potential power supply terminal 62L of the second gate driver 62, and the discharge path Ru2 of the capacitor C27. In addition, when the switching circuit 10 of the inverter circuit 1 is in the second switching state, the voltage required for the third gate driver 63 to turn on the third switching element Q3 is supplied from the capacitor C37 of the third bootstrap circuit 73 to the third gate driver 63. Therefore, the discharge is performed from the capacitor C37 of the third bootstrap circuit 73 through the capacitor C37, the high potential power supply terminal 63H of the third gate driver 63, the low potential power supply terminal 63L of the third gate driver 63, and the discharge path Ru3 of the capacitor C37.

[0120] In addition, if Figure 5 As shown, assuming that the voltages across capacitors C17, C27, and C37 are Vo1, Vo2, and Vo3, respectively, the voltages across resistors R17 and R27 are VR1 and VR2, respectively, and the voltages across the second switching element Q2 and the third switching element Q3 are Vf2 and Vf3, respectively, when the switching circuit 10 of the inverter circuit 1 is in the second switching state, if the second condition is satisfied, the capacitor C27 is charged with the charge in the capacitor C37, and if the third condition is satisfied, the capacitor C17 is charged with the charge in the capacitor C27. The second condition is Vo3>(Vo2+Vd2+VR2+Vf3). The third condition is Vo2>(Vo1+Vd1+VR1+Vf2). The charging path Ru32 for charging the capacitor C27 with the charge in the capacitor C37 is a path that passes through the capacitor C37, the resistor R37, the diode D27, the resistor R27, the capacitor C27, the third connection node 13, the third switching element Q3, and the capacitor C37 in sequence. The charging path Ru21 for charging the capacitor C17 with the charge in the capacitor C27 is a path that passes through the capacitor C27, the resistor R27, the diode D17, the resistor R17, the capacitor C17, the first connection node 11, the second switching element Q2, and the capacitor C27 in sequence. The charging path Ru32 for charging the capacitor C27 with the charge in the capacitor C37 is a path that passes through the capacitor C37, the resistor R37, the diode D27, the resistor R27, the capacitor C27, the third connection node 13, the third switching element Q3, and the capacitor C37 in sequence.

[0121] On the other hand, when the switching circuit of the inverter circuit 1 is in the third switching state, the current flows along Figure 6 As shown, the voltage flows through the path of the negative electrode N1 of the DC power supply unit 3, the fourth switching element Q4, the third switching element Q3, the third connection node 13 and the output terminal 41U in sequence, so that the voltage value of the output voltage for the AC load RA1 is -Vdc / 2. In addition, when the switching circuit 10 of the inverter circuit 1 is in the third switching state, the capacitor C17 of the first bootstrap circuit 71 is charged, and therefore, the voltage at the capacitor C17 rises with the passage of time to finally fully charge the capacitor C17. In addition, when the switching circuit 10 of the inverter circuit 1 is in the third switching state, the second bootstrap circuit 72 (refer to Figure 1 ) is charged, and therefore, the voltage at the capacitor C27 rises with the passage of time to finally fully charge the capacitor C27. In addition, when the switching circuit 10 of the inverter circuit 1 is in the third switching state, the voltage required for the third gate driver 63 to turn the third switching element Q3 on is supplied from the capacitor C37 of the third bootstrap circuit 73 to the third gate driver 63. Thus, the capacitor C37 of the third bootstrap circuit 73 is discharged via the discharge path Ru3 that passes through the capacitor C37, the high potential power supply terminal 63H of the third gate driver 63, the low potential power supply terminal 63L of the third gate driver 63, and the capacitor C37 in sequence. In addition, as Figure 7 As shown, assuming that the voltage across the power supply unit 9 is Voo, the voltage across the capacitors C27 and C37 is Vo2 and Vo3, respectively, the voltage across the resistors R27 and R37 is VR2 and VR3, respectively, and the voltage across the third switching element Q3 and the fourth switching element Q4 is Vf3 and Vf4, respectively, when the switching circuit 10 of the inverter circuit 1 is in the third switching state, if the fourth condition is satisfied, the capacitor C37 is charged by the power supply unit 9, and if the fifth condition is satisfied, the capacitor C27 is charged with the charge in the capacitor C37. The fourth condition is Voo>(Vo3+Vd3+VR3+Vf4). The fifth condition is Vo3>(Vo2+Vd2+VR2+Vf3). The charging path Ru93 for charging the capacitor C37 with the charge in the power supply unit 9 is a path that passes through the positive side terminal of the power supply unit 9, the diode D37, the diode D27, the resistor R27, the capacitor C27, the third connection node 13, the third switching element Q3, the fourth switching element Q4, and the negative side terminal of the power supply unit 9 in sequence. The charging path Ru32 for charging the capacitor C27 with the charge in the capacitor C37 is a path that passes through the capacitor C37, the resistor R37, the diode D27, the resistor R27, the capacitor C27, the third connection node 13, the third switching element Q3, and the capacitor C37 in sequence.

[0122] The control unit 60 generates a voltage command Vu, Vv, Vw (reference voltage) related to each output voltage of the inverter circuit 1U, 1V, 1W. Figure 8 ), generating first control signals S1 to fourth control signals S4 (S1U to S4U) for the first switching element Q1 to the fourth switching element Q4 of the inverter circuit 1U, first control signals S1 to fourth control signals S4 (S1V to S4V) for the first switching element Q1 to the fourth switching element Q4 of the inverter circuit 1V, and first control signals S1 to fourth control signals S4 (S1W to S4W) for the first switching element Q1 to the fourth switching element Q4 of the inverter circuit 1W.

[0123] like Figure 8 As shown, the voltage commands Vu, Vv, Vw are sinusoidal wave signals that are 120 degrees out of phase with each other and have values ​​(voltage command values) that change over time. Note that the voltage commands Vu, Vv, Vw each have a cycle of the same length. Optionally, the control unit 60 may perform proportional integral (PI) control on the voltage commands Vu, Vv, Vw based on information provided by the detection unit 8 for detecting the state of the AC load RA1. For example, if the AC load RA1 is a three-phase motor, the information provided by the detection unit 8 includes, for example, information related to the detection results obtained by a plurality of current sensors for detecting the output currents of the U-phase, V-phase, and W-phase flowing through the AC load RA1 and / or information related to the detection results obtained by an encoder for detecting the number of revolutions, rotation angle, and other parameters of the three-phase motor.

[0124] Next, how one of the three inverter circuits 1 (for example, the U-phase inverter circuit 1U) operates will be described. The V-phase inverter circuit 1V and the W-phase inverter circuit 1W operate in the same manner as the U-phase inverter circuit 1U. The respective output voltages of the U-phase inverter circuit 1U, the V-phase inverter circuit 1V, and the W-phase inverter circuit 1W have mutually different phases.

[0125] The control unit 60 controls the plurality of first gate drivers 61 , the plurality of second gate drivers 62 , the plurality of third gate drivers 63 , and the plurality of fourth gate drivers 64 by performing voltage vector control.

[0126] Next, how the control unit 60 performs the voltage vector control will be described in more detail.

[0127] The control unit 60 stores a set of voltage vectors in advance. Each voltage vector in the set of voltage vectors is defined by a combination of respective potential levels at a connection node (third connection node 13) at which the second switching element Q2 and the third switching element Q3 are connected to each other in a corresponding inverter circuit among the plurality of inverter circuits 1. In other words, each voltage vector in the set of voltage vectors is defined by a switching state of a switching circuit 10U corresponding to the U phase, a switching state of a switching circuit 10V corresponding to the V phase, and a switching state of a switching circuit 10W corresponding to the W phase. The number of voltage vectors included in the set of voltage vectors is 3 3 (=27).

[0128] like Fig. 9 As shown, a set of voltage vectors includes three zero vectors V0p, V0n, and V0o, each of which has a magnitude of zero. In addition, a set of voltage vectors also includes three zero vectors V0p, V0n, and V0o, each of which has a magnitude of (2 / 3) 1 / 2 Six voltage vectors V1, V2, V3, V4, V5, V6 with a magnitude of 2Vdc and different directions from each other. In addition, a set of voltage vectors also includes each having (2 / 3) 1 / 2 · Twelve voltage vectors V7p, V7n, V8p, V8n, V9p, V9n, V10p, V10n, V11p, V11n, V12p, V12n of the same magnitude as Vdc. In addition, a set of voltage vectors also includes each having (2 / 3) 1 / 2 ·3 1 / 2 · Six voltage vectors V13, V14, V15, V16, V17, and V18 with the same magnitude and different directions. Fig. 9 In the figure, the angle formed between each pair of adjacent voltage vectors belonging to the six voltage vectors V1, V2, V3, V4, V5, and V6 is 60 degrees. Similarly, the angle formed between each pair of adjacent voltage vectors belonging to the six voltage vectors V13, V14, V15, V16, V17, and V18 is also 60 degrees. Note that Fig. 9 is a vector diagram illustrating a set of voltage vectors on an orthogonal dq coordinate system.

[0129] If the first switching state, the second switching state and the third switching state of each group of voltage vectors are designated by reference numerals “P”, “0” and “N”, respectively, and the switching states of the three phases are arranged in the order of U phase, V phase and W phase, then it can be as follows Fig.10 The shown diagram shows each group of voltage vectors.

[0130] like Fig.10As shown, the three zero vectors V0p, V0n, and V0o can be expressed as V0p[PPP], V0n[NNN], and V0o

[000] , respectively. For example, V0p[PPP] indicates that with respect to the zero vector V0p, the switching state of the U-phase switching circuit 10U is "P", the switching state of the V-phase switching circuit 10V is "P", and the switching state of the W-phase switching circuit 10W is "P". Voltage vectors with a suffix "p" such as V10p include "P" but do not include "N". The same statement will apply to the rest of the description. Voltage vectors with a suffix "n" such as V10n include "N" but do not include "P". The same statement will apply to the rest of the description. Voltage vectors with a suffix "o" such as V10o include "0", but neither "P" nor "N". If the switching state of the switching circuit 10 is "P", the potential at the third connection node 13 of the switching circuit 10 will be the potential at the positive electrode P1 of the DC power supply unit 3. If the switching state of the switching circuit 10 is "N", the potential at the third connection node 13 of the switching circuit 10 will be the potential at the negative electrode N1 of the DC power supply unit 3. If the switching state of the switching circuit 10 is "0", the potential at the third connection node 13 of the switching circuit 10 will be the potential at the middle potential node M1 of the DC power supply unit 3.

[0131] The six voltage vectors V1, V2, V3, V4, V5, and V6 may be represented as V1[PNN], V2[PPN], V3[NPN], V4[NPP], V5[NNP], and V6[PNP], respectively. Voltage vectors such as V1[PNN], V2[PPN], V3[NPN], V4[NPP], V5[NNP], and V6[PNP], etc., without adding suffixes "p", "n", and "o" to the numbers after "V", include "P" and "N" as two of the three-phase switching states.

[0132] The twelve voltage vectors V7p, V7n, V8p, V8n, V9p, V9n, V10p, V10n, V11p, V11n, V12p and V12n can be expressed as V7p[P00], V7n[0NN], V8p[PP0], V8n[00N], V9p[0P0], V9n[N0N], V10p[0PP], V10n[N00], V11p[00P], V11n[NN0], V12p[P0P] and V12n[0N0] respectively.

[0133] The six voltage vectors V13, V14, V15, V16, V17 and V18 may be represented as V13[P0N], V14[ONP], V15[NP0], V16[N0P], V17[ONP] and V18[PN0], respectively.

[0134] The control unit 60 converts the instantaneous value of the command voltage for the output voltage of each of the plurality of inverter circuits 1 into a command voltage vector V* (reference voltage vector V*). Fig.11 ). If the d-axis component of the command voltage vector V* in the orthogonal dq coordinate system is Vd and the q-axis component of the command voltage vector V* in the orthogonal dq coordinate system is Vq, the command voltage vector V* can be given by the following equation (1):

[0135] [Mathematical formula 1]

[0136]

[0137] The control unit 60 selects a plurality of (for example, five) voltage vectors belonging to a group of voltage vectors that are located adjacent to the command voltage vector V*. Fig.12 In the example shown in A, the multiple voltage vectors are V8p[PP0], V8n[00N], V13[P0N], V7p[P00] and V7n[0NN].

[0138] The control unit 60 uses a zero vector V0n[NNN] defined by a combination of potential levels as high as the potential at the negative electrode at each third connection node 13 (where the second switching element Q2 and the third switching element Q3 are connected to each other in the corresponding inverter circuits in the plurality of inverter circuits 1) and a second voltage vector VV2 having the same direction as the first voltage vector VV1 and having a different magnitude from the first voltage vector VV1 (for example, Fig.12 V2[PPN] in the example shown in A) is used to replace the first voltage vector VV1 (for example, Fig.11 and Fig.12 V8p[PP0] and V8n[00N] in the example shown in A of FIG. 1 ) (each of which has a reference size and is located at a position closest to the command voltage value V*). The reference size may be, for example, (2 / 3) 1 / 2 Vdc. Thus, the plurality of voltage vectors include twelve voltage vectors V7p[P00], V7n[ONN], V8p[PP0], V8n[00N], V9p[0P0], V9n[N0N], V10p[0PP], V10n[N00], V11p[00P], V11n[NN0], V12p[P0P], and V12n[0N0] as voltage vectors whose magnitudes are reference magnitudes (i.e., reference vectors). An angle formed between a first voltage vector VV1 located closest to the command voltage vector V* and the command voltage vector V* is less than 30 degrees.

[0139] The control unit 60 controls the Fig.15) controls a plurality of first gate drivers 61, a plurality of second gate drivers 62, a plurality of third gate drivers 63 and a plurality of fourth gate drivers 64 so that the plurality of voltage vectors except the first voltage vector VV1 (for example, Fig.12 The three voltage vectors (for example, V8p[PP0] and V8n[00N] in the example shown in A) other than Fig.12 The resultant vector of V13[P0N], V7p[P00] and V7n[0NN] in the example shown in FIG. 1 ), zero vector V0n[NNN] and at least one second voltage vector VV2 is equal to the command voltage vector V*. The predetermined control period Ts may be, for example, two periods of the carrier signal.

[0140] On the other hand, in a comparative example in which the control operation is performed without replacing the first voltage vector VV1 with the zero vector and the second voltage vector VV2, within the control period Ts, the resultant vector of the three vectors at the three vertices of the equilateral triangle surrounding the command voltage vector V* is made equal to the command voltage vector V*. Specifically, in the comparative example, the first voltage vector VV1 (for example, Fig.12 The voltage vector V8p[PP0] and V8n[00N] in the example shown in A of FIG. 1 ), the voltage vector V13[P0N], and the resultant vector of the voltage vectors V7p[P00] and V7n[00N] are equal to the command voltage vector V*. In the comparative example, the control period Ts is one period of the carrier signal. In the comparative example, in the two voltage vectors arranged in a row along the time series, for example, Fig.13 As shown, within the control period Ts, the switching state of only one of the U phase, V phase and W phase changes between "P" and "0" or between "0" and "N", and the same voltage vector is output twice each time. Fig.13 In the example shown, the voltage vectors are output in the order of voltage vector V8n[00N], voltage vector V13[P0N], voltage vector V7p[P00], voltage vector V8p[PP0], voltage vector V8p[PP0], voltage vector V7p[P00], voltage vector V13[P0N], and voltage vector V8n[00N]. Fig.13 In the example shown, the time allocated to the voltage vectors V8p and V8n for the control period Ts is T0, the time allocated to the voltage vector V13 is T1, and the time allocated to the voltage vectors V7p and V7n is T2. With respect to T0, T1, and T2, assuming that the voltage vectors at the three vertices of an equilateral triangle surrounding the command voltage vector V* are Va, Vb, Vc, respectively, the magnitude of the command voltage vector V* is V, and the angle is θ, T0, T1, and T2 are determined to satisfy the following equations (2) and (3). In equation (2), "j" represents an imaginary unit. Note that in Fig.13In the example shown, for example, the voltage vector Va may be the voltage vectors V8p[PP0] and V8n[00N], the voltage vector Vb may be the voltage vector V13[P0N], and the voltage vector Vc may be the voltage vectors V7p[P00] and V7n[0NN].

[0141] [Mathematical formula 2]

[0142] Va·T0+Vb·T1+Vc·T2

[0143] =VvTs·cosθ+jV·Ts·sinθ (2)

[0145] [Mathematical formula 3]

[0146] T0+T1+T2=Ts (3)

[0148] exist Fig.13 In the example shown, Fig.14 As shown, during the entire control period Ts, the second switching element Q2 will remain ON, and the magnitude of the voltage drop in the second bootstrap circuit 72 will increase.

[0149] In contrast, for example, Fig.15 As shown, the control unit 60 of the multilevel inverter 100 according to the first embodiment outputs voltage vectors in the order of voltage vector V8n[00N], voltage vector V13[P0N], voltage vector V7p[P00], voltage vector V8p[PP0], voltage vector V8p[PP0], voltage vector V7p[P00], voltage vector V13[P0N] and voltage vector V8n[00N] within two cycles of the carrier signal. The control unit 60 replaces the voltage vectors V8p[PP0] and V8p[PP0] according to the comparative example with the zero vector V0n[NNN] and the second voltage vector VV2 (V2[PPN]), respectively, thereby Fig.15 The time period during which the U-phase switching state is "N" is shown. This makes Fig.16 The multilevel inverter 100 according to the first embodiment is shown to generate a third switching state in which both the first switching element Q1 and the second switching element Q2 are OFF and both the third switching element Q3 and the fourth switching element Q4 are ON. Thus, the multilevel inverter 100 according to the first embodiment can reduce the possibility of causing a voltage drop in the capacitor C27 of the second bootstrap circuit 72.

[0150] In addition, in the comparative example, even if the command voltage vector V* is Fig.12The arrangement order of the voltage vectors in the control period Ts may be different depending on the initial value of the carrier signal at the beginning of the control period Ts. Fig.17 In the example shown, the voltage vectors are output in the order of voltage vector V8p[PP0], voltage vector V7p[P00], voltage vector V13[P0N], voltage vector V8n[00N], voltage vector V8n[00N], voltage vector V13[P0N], voltage vector V7p[P00], and voltage vector V8p[PP0]. Fig.17 In the example shown, Fig.13 As shown in the example, the time allocated to the voltage vectors V8p and V8n is T0, the time allocated to the voltage vector V13 is T1, and the time allocated to the voltage vectors V7p and V7n is T2. Fig.18 As shown, in the entire control period Ts, the third switching state will not be generated, and the magnitude of the voltage drop in the second bootstrap circuit 72 will increase.

[0151] In contrast, the control unit 60 of the multilevel inverter 100 according to the first embodiment is, for example, Fig.19 As shown in FIG. 1 , within two cycles of the carrier signal, the voltage vectors and the zero vector are output in the order of voltage vector V2[PPN], voltage vector V7p[P00], voltage vector V13[P0N], voltage vector V8n[00N], voltage vector V8n[00N], voltage vector V13[P0N], voltage vector V7p[P00] and zero vector V0n[NNN]. The control unit 60 replaces the voltage vectors V2[PPN] and V0n[NNN] with the voltage vectors V2[PPN] and V0n[NNN] respectively. Fig.17 The voltage vectors V8p[PP0], V8p[PP0] in the example shown are thus Fig.19 The time period during which the U-phase switching state is "N" is shown. This makes Fig. 20 The multilevel inverter 100 according to the first embodiment is shown to generate the third switching state within the control period Ts. Therefore, the multilevel inverter 100 according to the first embodiment can reduce the possibility of causing a voltage drop in the capacitor C27 of the second bootstrap circuit 72.

[0152] On the other hand, in the multilevel inverter 100 according to the first embodiment, the control unit 60 replaces the first voltage vector VV1 with the zero vector V0n[NNN] and the second voltage vector VV2 when the polarity of the command voltage corresponding to the command voltage vector V* is positive. In the multilevel inverter 100 according to the first embodiment, the control unit 60 does not replace the first voltage vector VV1 with the zero vector V0n[NNN] and the second voltage vector VV2 when the polarity of the command voltage corresponding to the command voltage vector V* is negative.

[0153] In addition, in the multilevel inverter 100, the control unit 60 controls multiple first gate drivers 61, multiple second gate drivers 62, multiple third gate drivers 63 and multiple fourth gate drivers 64 to prevent the respective output voltages of the multiple first bootstrap circuits 71 and the multiple second bootstrap circuits 72 from dropping to a predetermined value or less.

[0154] (3) Summary

[0155] In the multilevel inverter 100 according to the first embodiment, the control unit 60 selects a plurality of (five) voltage vectors (e.g., V8p[PP0], V8n[00N], V13[P0N], V7p[P00], and V7n[0NN]) belonging to a group (27) of voltage vectors located adjacent to the command voltage vector V*. Each voltage vector in the group of voltage vectors is defined by a combination of potential levels at respective third connection nodes 13, wherein in the respective inverter circuits in the plurality of inverter circuits 1, at each third connection node, the second switching element Q2 and the third switching element Q3 are connected to each other. The control unit 60 replaces one of the two first voltage vectors VV1 with a zero vector V0n[NNN] and a second voltage vector VV2. The two first voltage vectors VV1 belong to a plurality of voltage vectors, each having a reference magnitude, and are located at the position closest to the command voltage vector V*. The zero vector V0n[NNN] is defined by a combination of potential levels at the respective third connection nodes 13, where the second switching element Q2 and the third switching element Q3 are connected to each other at the respective third connection nodes in the corresponding inverter circuits 1 in the plurality of inverter circuits 1, and these potential levels are as high as the potential at the negative electrode N1. The second voltage vector VV2 has the same direction as the first voltage vector VV1 and has a size twice as large as the first voltage vector VV1. The control unit 60 controls the plurality of first gate drivers 61, the plurality of second gate drivers 62, the plurality of third gate drivers 63, and the plurality of fourth gate drivers 64 within a predetermined control period Ts so that the voltage vectors included in the plurality of voltage vectors other than the first voltage vector VV1, the other first voltage vector VV1 of the two first voltage vectors VV1, the zero vector V0n[NNN], and the resultant vector of the second voltage vector VV2 is equal to the command voltage vector V*.

[0156] The multilevel inverter 100 according to the first embodiment can reduce the possibility of causing a voltage drop in the bootstrap circuit. More specifically, the multilevel inverter 100 according to this aspect can reduce the possibility of causing a voltage drop in the capacitor C17 of the plurality of first bootstrap circuits 71, the capacitor C27 of the plurality of second bootstrap circuits 72, and the capacitor C37 of the plurality of third bootstrap circuits 73.

[0157] In addition, in the multilevel inverter 100 according to the first embodiment, the DC-DC converter 91 included in the power supply unit 9 supplies voltage to the plurality of fourth gate drivers 64 and the plurality of third bootstrap circuits 73. Thus, the multilevel inverter 100 according to the first embodiment can contribute to miniaturization.

[0158] (Second embodiment)

[0159] The multilevel inverter 100 according to the second embodiment has the same features as the multilevel inverter 100 according to the first embodiment (refer to Figure 1 ) and therefore, its illustration and description will be omitted in this article.

[0160] In the multilevel inverter 100 according to the first embodiment, as Fig.15 As in the example shown, the control unit 60 replaces only one of the two first voltage vectors VV1 (such as V8n[00N] and V8p[PP0]) with a zero vector V0n[NNN] and a second voltage vector VV2 (such as V2[PPN]).

[0161] On the other hand, in the multilevel inverter 100 according to the second embodiment, for example, Fig.21 As shown in the example, the control unit 60 replaces one of the two first voltage vectors VV1 (such as V8n[00N] and V8p[PP0]) with a zero vector V0n[NNN], and replaces the other first voltage vector VV1 (such as V8p[PP0]) with a second voltage vector V2 (such as V2[PPN]). In this case, Fig.21 As shown, the control unit 60 of the multilevel inverter 100 according to the second embodiment outputs the voltage vector and the zero vector in the order of the zero vector V0n[NNN], the voltage vector V13[P0N], the voltage vector V7p[P00], the voltage vector V2[PPN], the voltage vector V2[PPN], the voltage vector V7p[P00], the voltage vector V13[P0N] and the zero vector V0[NNN] within two cycles of the carrier signal. The control unit 60 replaces the zero vector V0n[NNN], the voltage vector V2[PPN], the voltage vector V2[PPN] and the zero vector V0n[NNN] respectively. Fig.13 The voltage vectors V8n[00N], V8p[PP0], V8p[PP0] and V8n[00N] in the example shown are thus Fig.21 The U-phase switching state is generated as shown in the time period of "N". This makes the multilevel inverter 100 according to the second embodiment Fig. 22As shown, the third switching state is generated within the control period Ts. Therefore, the multilevel inverter 100 according to the second embodiment can reduce the possibility of causing a voltage drop in the capacitor C27 of the second bootstrap circuit 72.

[0162] Furthermore, in the multilevel inverter 100 according to the first embodiment, Fig.19 In the example shown, the control unit 60 replaces only one first voltage vector VV1 (such as V8p[PP0]) of two first voltage vectors VV1 (such as V8n[00N] and V8p[PP0]) with a zero vector V0n[NNN] and a second voltage vector VV2 (such as V2[PPN]).

[0163] In contrast, in the multilevel inverter 100 according to the second embodiment, for example, Fig.23 As shown in the example shown in FIG. 1 , the control unit 60 replaces one of the two first voltage vectors VV1 (such as V8n[00N] and V8p[PP0]) with a zero vector V0n[NNN], and replaces the other first voltage vector VV1 (such as V8p[PP0]) with a second voltage vector VV2 (such as V2[PPN]). In this case, in the multilevel inverter 100 according to the second embodiment, as shown in FIG. Fig.23 As shown, the control unit 60 outputs the voltage vector and the zero vector in the order of voltage vector V2[PPN], voltage vector V7p[P00], voltage vector V13[P0N], zero vector V0n[NNN], zero vector V0n[NNN], voltage vector V13[P0N], voltage vector V7p[P00] and voltage vector V2[PPN] within two cycles of the carrier signal. The control unit 60 replaces the voltage vector and the zero vector V2[PPN], V0n[NNN], V0n[NNN] and V2[PPN] with the voltage vector and the zero vector V2[PPN], V0n[NNN], V0n[NNN] and V2[PPN] respectively. Fig.17 The voltage vectors V8p[PP0], V8n[00N], V8n[00N] and V8p[PP0] of the example shown are thus Fig.23 The U-phase switching state is generated as shown in the time period of "N". This makes the multilevel inverter 100 according to the second embodiment Fig.24 As shown, the third switching state is generated within the control period Ts. Therefore, the multilevel inverter 100 according to the second embodiment can reduce the possibility of causing a voltage drop in the capacitor C27 of the second bootstrap circuit 72.

[0164] In the multilevel inverter 100 according to the second embodiment, the control unit 60 replaces the first voltage vector VV1 (which belongs to a plurality of voltage vectors, has a reference magnitude, and is located at a position closest to the command voltage vector V*) with a zero vector V0n[NNN] (which is defined by a combination of potential levels at the respective third connection nodes 13 (in the respective inverter circuits in the plurality of inverter circuits 1, at the respective third connection nodes 13, the second switching element Q2 and the third switching element Q3 are connected to each other, and these potential levels are as high as the potential at the negative electrode N1) and a second voltage vector VV2 (which has the same direction as the first voltage level VV1 and has a magnitude twice as large as the first voltage vector VV1). The control unit 60 controls the plurality of first gate drivers 61, the plurality of second gate drivers 62, the plurality of third gate drivers 63, and the plurality of fourth gate drivers 64 within a predetermined control period Ts so that the resultant vector of the voltage vectors other than the first voltage vector VV1, the zero vector V0n[NNN], and the second voltage vector VV2 included in the plurality of voltage vectors is equal to the command voltage vector V*.

[0165] The multilevel inverter 100 according to the second embodiment can reduce the possibility of causing a voltage drop in the bootstrap circuit. More specifically, the multilevel inverter 100 according to this aspect can reduce the possibility of causing a voltage drop in the capacitor C17 of the plurality of first bootstrap circuits 71, the capacitor C27 of the plurality of second bootstrap circuits 72, and the capacitor C37 of the plurality of third bootstrap circuits 73.

[0166] (Other Modifications)

[0167] Note that the first and second embodiments described above are merely exemplary embodiments of the various embodiments of the present disclosure and should not be construed as limiting. On the contrary, the first and second embodiments may be easily modified in various ways according to design choices or any other factors without departing from the scope of the present disclosure.

[0168] For example, the plurality of first switching elements Q1, the plurality of second switching elements Q2, the plurality of third switching elements Q3, and the plurality of fourth switching elements Q4 do not necessarily have to be MOSFETs, but may also be insulated gate bipolar transistors (IGBTs). In this case, in each of the plurality of first switching elements Q1, the plurality of second switching elements Q2, the plurality of third switching elements Q3, and the plurality of fourth switching elements Q4, its control terminal, the first main terminal, and the second main terminal are respectively a gate terminal, a collector terminal, and an emitter terminal.

[0169] In addition, in the multilevel inverter 100 according to the first and second embodiments, the control unit 60 can replace the first voltage vector VV1 with the zero vector V0n[NNN] and the second voltage vector VV2 not only when the polarity of the command voltage corresponding to the command voltage vector V* is positive, but also when the polarity of the command voltage corresponding to the command voltage vector V* is negative.

[0170] Each of the first bootstrap circuits 71 includes a Zener diode Z17 in the above embodiment, but may have a structure not including the Zener diode Z17. Similarly, each of the second bootstrap circuits 72 includes a Zener diode Z27 in the above embodiment, but may have a structure not including the Zener diode Z27. Similarly, each of the third bootstrap circuits 73 includes a Zener diode Z37 in the above embodiment, but may have a structure not including the Zener diode Z37.

[0171] In the above embodiment, the multilevel inverter 100 is as follows: Figure 1 The figure shows that only one DC-DC converter 91 is included as the power supply unit 9 for supplying voltage to the three fourth gate drivers 64. Alternatively, as Fig.25 As shown in the multilevel inverter 100 according to the modified example, the power supply unit 9 may include a plurality of (for example, three) DC-DC converters 91. The plurality of DC-DC converters 91 are provided one-to-one for the plurality of (for example, three) fourth gate drivers 64. Each of the plurality of DC-DC converters 91 supplies voltage to the corresponding fourth gate driver in the fourth gate driver 64. In the case of the multilevel inverter 100 according to the modified example, in each of the plurality of first bootstrap circuits 71, the anode of the diode D17 is connected to the positive side terminal of the corresponding DC-DC converter in the plurality of DC-DC converters 91. In addition, in each of the second bootstrap circuits 72, the anode of the diode D27 is connected to the positive side terminal of the corresponding DC-DC converter in the plurality of DC-DC converters 91. In addition, in each of the third bootstrap circuits 73, the anode of the diode D37 is connected to the positive side terminal of the corresponding DC-DC converter in the plurality of DC-DC converters 91.

[0172] Furthermore, the multilevel inverter 100 only needs to be a multilevel inverter having at least three levels, and may be, for example, a five-level inverter.

[0173] (Third Embodiment)

[0174] Now refer to Figures 26 to 38 B is used to illustrate the multilevel inverter 100a according to the third embodiment.

[0175] (1) Summary

[0176] like Fig.26 As shown, the multilevel inverter 100a may include, for example, a DC power supply unit 3, a plurality of (e.g., three) inverter circuits 1a, and a controller 6a. The DC power supply unit 3 includes a positive electrode P1, a negative electrode N1, and an intermediate potential node M1. The plurality of inverter circuits 1a are connected between the positive electrode P1 and the negative electrode N1 of the DC power supply unit 3. The controller 6a controls the plurality of inverter circuits 1a.

[0177] The multilevel inverter 100a is a T-type three-level three-phase inverter. In the multilevel inverter 100a, each inverter circuit in the plurality of inverter circuits 1a has an output terminal 41a. In the multilevel inverter 100a, an AC load RA1 is connected to the plurality of output terminals (AC terminals) 41a. The AC load RA1 may be, for example, a three-phase motor. In the multilevel inverter 100a, one inverter circuit in the plurality of inverter circuits 1a is an inverter circuit 1Ua for outputting a U-phase voltage, another inverter circuit in the plurality of inverter circuits 1a is an inverter circuit 1Va for outputting a V-phase voltage, and the remaining one inverter circuit in the plurality of inverter circuits 1a is an inverter circuit 1Wa for outputting a W-phase voltage.

[0178] Each inverter circuit in the plurality of inverter circuits 1a includes: a first switching element Q1a, a second switching element Q2a, a third switching element Q3a, and a fourth switching element Q4a; and a first diode D1a, a second diode D2a, a third diode D3a, and a fourth diode D4a. The first diode D1a, the second diode D2a, the third diode D3a, and the fourth diode D4a are respectively connected in anti-parallel to the first switching element Q1a, the second switching element Q2a, the third switching element Q3a, and the fourth switching element Q4a. In each inverter circuit in the plurality of inverter circuits 1a, the first switching element Q1a and the second switching element Q2a are connected in series in a manner of being arranged sequentially from the positive electrode P1 toward the negative electrode N1. That is, as Fig.26 and Fig. 27 As shown, a series circuit (first circuit 11a) of a first switching element Q1a and a second switching element Q2a is connected between a positive electrode P1 and a negative electrode N1. In each of the plurality of inverter circuits 1a, a series circuit (second circuit 12a) of a third switching element Q3a and a fourth switching element Q4a is connected between an intermediate potential node M1 and an output node. The output node is a connection node 13a between the first switching element Q1a and the second switching element Q2a. The second circuit 12a includes a bidirectional switch including a third switching element Q3a, a fourth switching element Q4a, a third diode D3a, and a fourth diode D4a.

[0179] The controller 6a includes a plurality of (e.g., three) first gate drivers 61a, a plurality of (e.g., three) second gate drivers 62a, a plurality of (e.g., three) third gate drivers 63a, and a plurality of (e.g., three) fourth gate drivers 64a. The controller 6a also includes a plurality of (e.g., three) bootstrap circuits 71a (hereinafter also referred to as "first bootstrap circuits 71a"), a plurality of (e.g., three) second bootstrap circuits 72a, a power supply unit 9a, and a control unit 60a.

[0180] Each of the plurality of first gate drivers 61a drives a first switching element Q1a of a corresponding inverter circuit in the plurality of inverter circuits 1a. Each of the plurality of second gate drivers 62a drives a second switching element Q2a of a corresponding inverter circuit in the plurality of inverter circuits 1a. Each of the plurality of third gate drivers 63a drives a third switching element Q3a of a corresponding inverter circuit in the plurality of inverter circuits 1a. Each of the plurality of fourth gate drivers 64a drives a fourth switching element Q4a of a corresponding inverter circuit in the plurality of inverter circuits 1a.

[0181] The plurality of first bootstrap circuits 71a are provided one-to-one for the plurality of first gate drivers 61a. Each of the first bootstrap circuits 71a supplies voltage to the corresponding first gate driver in the plurality of first gate drivers 61a. The plurality of second bootstrap circuits 72a are provided one-to-one for the plurality of third gate drivers 63a and the plurality of fourth gate drivers 64a. Each of the second bootstrap circuits 72a supplies voltage to the corresponding third gate driver in the plurality of third gate drivers 63a and the corresponding fourth gate driver in the plurality of fourth gate drivers 64a. The power supply unit 9a supplies voltage to the plurality of second gate drivers 62a.

[0182] The control unit 60 a controls a plurality of first gate drivers 61 a , a plurality of second gate drivers 62 a , a plurality of third gate drivers 63 a , and a plurality of fourth gate drivers 64 a .

[0183] (2) Details of power converter

[0184] The DC power supply unit 3 includes a first capacitor C1 and a second capacitor C2. In the DC power supply unit 3, the first capacitor C1 and the second capacitor C2 are connected in series. In the DC power supply unit 3, the first terminal of the first capacitor C1 is connected to the first DC terminal 31, the second terminal of the first capacitor C1 is connected to the first terminal of the second capacitor C2, and the second terminal of the second capacitor C2 is connected to the second DC terminal 32. In the DC power supply unit 3, the connection node between the first capacitor C1 and the second capacitor C2 is an intermediate potential node M1. The DC power supply unit 3 also includes a first DC terminal 31 connected to the positive electrode P1 and a second DC terminal 32 connected to the negative electrode N1. For example, a DC voltage source E1 may be connected between the first DC terminal 31 and the second DC terminal 32. In this case, the output voltage Vdc of the DC voltage source E1 is applied between the positive electrode P1 and the negative electrode N1 of the DC power supply unit 3. Note that the capacitance of the second capacitor C2 is equal to the capacitance of the first capacitor C1. As used herein, the expression “the capacitance of the second capacitor C2 is equal to the capacitance of the first capacitor C1” refers not only to the case where the capacitance of the second capacitor C2 is completely equal to the capacitance of the first capacitor C1, but also to the case where the capacitance of the second capacitor C2 is equal to or greater than 95% of the capacitance of the first capacitor C1 and equal to or less than 105% of the capacitance of the first capacitor C1.

[0185] In the following description, regarding multiple output terminals 41a, for the sake of convenience, the output terminal 41a included in the inverter circuit 1Ua will be referred to as "output terminal 41Ua" below, the output terminal 41a included in the inverter circuit 1Va will be referred to as "output terminal 41Va" below, and the output terminal 41a included in the inverter circuit 1Wa will be referred to as "output terminal 41Wa" below.

[0186] In each inverter circuit 1a, the first switching element Q1a, the second switching element Q2a, the third switching element Q3a and the fourth switching element Q4a each have a control terminal, a first main terminal and a second main terminal. The first switching element Q1a, the second switching element Q2a, the third switching element Q3a and the fourth switching element Q4a of each inverter circuit 1a can be, for example, a MOSFET. Thus, in each inverter circuit 1a, the control terminal, the first main terminal and the second main terminal of each switching element in the first switching element Q1a, the second switching element Q2a, the third switching element Q3a and the fourth switching element Q4a are respectively a gate terminal, a drain terminal and a source terminal. In each inverter circuit 1a, the MOSFET used as the first switching element Q1a, the second switching element Q2a, the third switching element Q3a and the fourth switching element Q4a can be, for example, a normally-off n-channel MOSFET. Note that the MOSFET can be, for example, a Si-based MOSFET or a SiC-based MOSFET.

[0187] In each inverter circuit 1a, the control terminal of the first switching element Q1a is connected to a corresponding first gate driver among the plurality of first gate drivers 61a. In addition, in each inverter circuit 1a, the control terminal of the second switching element Q2a is connected to a corresponding second gate driver among the plurality of second gate drivers 62a. In addition, in each inverter circuit 1a, the control terminal of the third switching element Q3a is connected to a corresponding third gate driver among the plurality of third gate drivers 63a. In addition, in each inverter circuit 1a, the control terminal of the fourth switching element Q4 is connected to a corresponding fourth gate driver among the plurality of fourth gate drivers 64a.

[0188] In each inverter circuit 1a, the first main terminal of the first switching element Q1a is connected to the positive electrode P1 of the DC power supply unit 3, and the second main terminal of the first switching element Q1a is connected to the first main terminal of the second switching element Q2a. In addition, in each inverter circuit 1a, the second main terminal of the second switching element Q2a is connected to the negative electrode N1 of the DC power supply unit 3.

[0189] In each inverter circuit 1a, the first main terminal of the third switching element Q3a is connected to the intermediate potential node M1, the second main terminal of the third switching element Q3a is connected to the second main terminal of the fourth switching element Q4a, and the first main terminal of the fourth switching element Q4a is connected to the connection node 13a. Fig. 27 ) is a common source bidirectional switch that connects the respective second main terminals (source terminals) of the third switching element Q3a and the fourth switching element Q4a to each other. As used herein, "intermediate potential node M1" refers to a node whose potential is in the middle between the potential at the positive electrode P1 of the DC power supply unit 3 and the potential at the negative electrode N1 thereof. In the third embodiment, the intermediate potential node M1 is connected to the ground terminal, and therefore the potential at the intermediate potential node M1 is 0V. In this case, assuming that the voltage across the DC power supply unit 3 is Vdc, the potential at the positive electrode P1 is Vdc / 2 and the potential at the negative electrode N1 is -Vdc / 2.

[0190] In the inverter circuit 1Ua, the connection node 13a between the first switching element Q1a and the second switching element Q2a is connected to the output terminal 41Ua. In the inverter circuit 1Va, the connection node 13a between the first switching element Q1a and the second switching element Q2a is connected to the output terminal 41Va. In the inverter circuit 1Wa, the connection node 13a between the first switching element Q1a and the second switching element Q2a is connected to the output terminal 41Wa. For example, the connection node 13a of the inverter circuit 1Ua is connected to the U phase of the AC load RA1 via the output terminal 41Ua. For example, the connection node 13a of the inverter circuit 1Va is connected to the V phase of the AC load RA1 via the output terminal 41Va. For example, the connection node 13a of the inverter circuit 1Wa is connected to the W phase of the AC load RA1 via the output terminal 41Wa.

[0191] In each inverter circuit 1a, the anode of the first diode D1a is connected to the second main terminal (source terminal) of the first switching element Q1a, and the cathode of the first diode D1a is connected to the first main terminal (drain terminal) of the first switching element Q1a. In addition, in each inverter circuit 1a, the anode of the second diode D2a is connected to the second main terminal (source terminal) of the second switching element Q2a, and the cathode of the second diode D2a is connected to the first main terminal (drain terminal) of the second switching element Q2a. In addition, in each inverter circuit 1a, the anode of the third diode D3a is connected to the second main terminal (source terminal) of the third switching element Q3a, and the cathode of the third diode D3a is connected to the first main terminal (drain terminal) of the third switching element Q3a. In addition, in each inverter circuit 1a, the anode of the fourth diode D4a is connected to the second main terminal (source terminal) of the fourth switching element Q4a, and the cathode of the fourth diode D4a is connected to the first main terminal (drain terminal) of the fourth switching element Q4a.

[0192] In each inverter circuit 1a, the first diode D1a may be replaced by a parasitic diode of a MOSFET used as the first switching element Q1a. In addition, in each inverter circuit 1a, the second diode D2a may be replaced by a parasitic diode of a MOSFET used as the second switching element Q2a. In addition, in each inverter circuit 1a, the third diode D3a may be replaced by a parasitic diode of a MOSFET used as the third switching element Q3a. In addition, in each inverter circuit 1a, the fourth diode D4a may be replaced by a parasitic diode of a MOSFET used as the fourth switching element Q4a.

[0193] The plurality of first gate drivers 61a are provided one-to-one for the plurality of first switching elements Q1a. Each of the plurality of first gate drivers 61a is connected to the control terminal of the corresponding first switching element in the first switching element Q1a. Each of the plurality of first gate drivers 61a drives the corresponding first switching element in the first switching element Q1a. The plurality of first gate drivers 61a are connected to the control unit 60a. The control unit 60a outputs a plurality of first control signals S1 (reference signal S2) associated one-to-one with the plurality of first gate drivers 61a. Fig. 27 ). Each of the plurality of first gate drivers 61a controls the ON / OFF state of the corresponding first switching element Q1a according to the supplied first control signal S1a.

[0194] The plurality of second gate drivers 62a are provided one-to-one for the plurality of second switching elements Q2a. Each of the plurality of second gate drivers 62a is connected to the control terminal of the corresponding second switching element in the second switching element Q2a. Each of the plurality of second gate drivers 62a drives the corresponding second switching element in the second switching element Q2a. The plurality of second gate drivers 62a are connected to the control unit 60a. The control unit 60a outputs a plurality of second control signals S2a (refer to Fig. 27 ). Each of the plurality of second gate drivers 62a controls the ON / OFF state of the corresponding second switching element Q2a according to the supplied second control signal S2a.

[0195] The plurality of third gate drivers 63a are provided one-to-one for the plurality of third switching elements Q3a. Each of the plurality of third gate drivers 63a is connected to the control terminal of the corresponding third switching element in the third switching element Q3a. Each of the plurality of third gate drivers 63a drives the corresponding third switching element in the third switching element Q3a. The plurality of third gate drivers 63a are connected to the control unit 60a. The control unit 60a outputs a plurality of third control signals S3a (reference signal S3a) associated one-to-one with the plurality of third gate drivers 63a. Fig. 27 Each of the plurality of third gate drivers 63a controls the ON / OFF state of the corresponding third switching element Q3a according to the supplied third control signal S3a.

[0196] The plurality of fourth gate drivers 64a are provided one-to-one for the plurality of fourth switching elements Q4a. Each of the plurality of fourth gate drivers 64a is connected to the control terminal of the corresponding fourth switching element in the fourth switching element Q4a. Each of the plurality of fourth gate drivers 64a drives the corresponding fourth switching element in the fourth switching element Q4a. The plurality of fourth gate drivers 64a are connected to the control unit 60a. The control unit 60a outputs a plurality of fourth control signals S4a (reference signal S4a) associated one-to-one with the plurality of fourth gate drivers 64a. Fig. 27 Each of the plurality of fourth gate drivers 64a controls the ON / OFF state of the corresponding fourth switching element Q4a according to the supplied fourth control signal S4a.

[0197] The plurality of first bootstrap circuits 71a are provided one-to-one with respect to the plurality of first gate drivers 61a. Each of the plurality of first bootstrap circuits 71a supplies voltage to a corresponding first gate driver in the first gate driver 61a. Fig.26 and Fig.28 As shown, each of the plurality of first bootstrap circuits 71a includes a diode D11, a resistor R11, and a capacitor C11 (hereinafter referred to as a "boost capacitor C11"). In each of the first bootstrap circuits 71a, the anode of the diode D11 is connected to the positive side terminal of the power supply unit 9a, and the cathode of the diode D11 is connected to the first terminal of the capacitor C11 via the resistor R11. The first terminal of the capacitor C11 is connected to the high potential power supply terminal 61Ha (reference 61Ha) of the corresponding first gate driver 61a. Fig.28 ). The second terminal of the capacitor C11 is connected to the low potential power supply terminal 61La (reference Fig.28 ). The first bootstrap circuit 71a supplies the corresponding first gate driver 61a with a voltage required by the first gate driver 61a to turn on the first switching element Q1a. Each of the plurality of first bootstrap circuits 71 further includes a Zener diode Z11 connected in parallel with the capacitor C11.

[0198] Multiple second bootstrap circuits 72a are set one-to-one for multiple third gate drivers 63a and multiple fourth gate drivers 64a. Each second bootstrap circuit in the multiple second bootstrap circuits 72a supplies voltage to the corresponding third gate driver in the third gate driver 63a and the corresponding fourth gate driver in the fourth gate driver 64a. Each second bootstrap circuit in the multiple second bootstrap circuits 72a includes a diode D21, a resistor R21 and a capacitor C21 (hereinafter referred to as "boost capacitor C21"). In each second bootstrap circuit 72a, the anode of the diode D21 is connected to the positive side terminal of the power supply unit 9a, and the cathode of the diode D21 is connected to the first terminal of the capacitor C21 via the resistor R21. The first terminal of the capacitor C21 is connected to the high potential power supply terminal 63Ha (reference Fig.28 ) and the high potential power supply terminal 64Ha (reference Fig.28 ). The second terminal of the capacitor C21 is connected to the low potential power supply terminal 63La (reference Fig.28 ) and the low potential power supply terminal 64La (reference Fig.28 ). The second bootstrap circuit 72a supplies the corresponding third gate driver 63a with a voltage required for the third gate driver 63a to turn on the third switching element Q3a, and also supplies the corresponding fourth gate driver 64a with a voltage required for the fourth gate driver 64a to turn on the fourth switching element Q4a. Each of the plurality of second bootstrap circuits 72a further includes a Zener diode Z21 connected in parallel with the capacitor C21.

[0199] The power supply unit 9a supplies voltage to the plurality of (three) first bootstrap circuits 71a, the plurality of (three) second bootstrap circuits 72a, and the plurality of (three) second gate drivers 62a. The power supply unit 9a may be, for example, a DC power supply including an isolated DC-DC converter 91a. The positive side terminal of the power supply unit 9a is connected to the high potential power supply terminal 62Ha (reference 10) of each of the plurality of second gate drivers 62a. Fig.28 ), and the negative side terminal of the power supply unit 9a is connected to the low potential power supply terminal 62La (reference Fig.28 ).

[0200] The control unit 60a controls a plurality of first gate drivers 61a, a plurality of second gate drivers 62a, a plurality of third gate drivers 63a, and a plurality of fourth gate drivers 64a. This enables the control unit 60a to control a plurality of first switching elements Q1a, a plurality of second switching elements Q2a, a plurality of third switching elements Q3a, and a plurality of fourth switching elements Q4a. The intelligent agent that performs the function of the control unit 60a includes a computer system. The computer system includes a single or multiple computers. The computer system may include a processor and a memory as its main hardware components. The computer system is used as an intelligent agent that performs the function of the control unit 60a according to the present disclosure by causing the processor to execute a program stored in the memory of the computer system. The program may be pre-stored in the memory of the computer system. Alternatively, the program may also be downloaded via a telecommunication line, or distributed after being recorded in a non-transient storage medium such as a memory card, an optical disk, or a hard disk drive (disk) (any of which is readable for the computer system). The processor of the computer system may be composed of a single or multiple electronic circuits including a semiconductor integrated circuit (IC) or a large-scale integrated circuit (LSI). These electronic circuits may be integrated together on a single chip or distributed across multiple chips, whichever is appropriate. These multiple chips may be gathered together in a single device or distributed across multiple devices, without limitation.

[0201] The control unit 60a outputs a plurality of (three) first control signals S1a (reference signal) for controlling a plurality of (three) first switching elements Q1a. Fig. 27 ), a plurality of (three) second control signals S2a (referenced to) for controlling a plurality of (three) second switching elements Q2a Fig. 27 ), a plurality of (three) third control signals S3a (referenced to Fig. 27 ), and a plurality of (three) fourth control signals S4a for controlling a plurality of (three) fourth switching elements Q4a. Note that Fig. 27 In FIG. 1 , only one of the three inverter circuits 1a is shown, and the illustration of the other two inverter circuits 1a is omitted. Fig. 27 , the illustration of the plurality of first gate drivers 61a, the plurality of second gate drivers 62a, the plurality of third gate drivers 63a, the plurality of fourth gate drivers 64a, the plurality of first bootstrap circuits 71a, the plurality of second bootstrap circuits 72a, and the power supply unit 9a is omitted. Fig.28 In FIG. 1 , only one of the three inverter circuits 1a is shown, and the illustration of the other two inverter circuits 1a is omitted. Fig.28, the illustration of the other two first gate drivers 61a, the other two second gate drivers 62a, the other two third gate drivers 63a, the other two fourth gate drivers 64a, the other two first bootstrap circuits 71a, and the other two second bootstrap circuits 72a is omitted.

[0202] The three first control signals S1a are a first control signal S1Ua for controlling the first switching element Q1a of the inverter circuit 1Ua, a first control signal S1Va for controlling the first switching element Q1a of the inverter circuit 1Va, and a first control signal S1Wa for controlling the first switching element Q1a of the inverter circuit 1Wa.

[0203] The three second control signals S2a are a second control signal S2Ua for controlling the second switching element Q2a of the inverter circuit 1Ua, a second control signal S2Va for controlling the second switching element Q2a of the inverter circuit 1Va, and a second control signal S2Wa for controlling the second switching element Q2a of the inverter circuit 1Wa.

[0204] The three third control signals S3a are a third control signal S3Ua for controlling the third switching element Q3a of the inverter circuit 1Ua, a third control signal S3Va for controlling the third switching element Q3a of the inverter circuit 1Va, and a third control signal S3Wa for controlling the third switching element Q3a of the inverter circuit 1Wa.

[0205] The three fourth control signals S4a are a fourth control signal S4Ua for controlling the fourth switching element Q4a of the inverter circuit 1Ua, a fourth control signal S4Va for controlling the fourth switching element Q4a of the inverter circuit 1Va, and a fourth control signal S4Wa for controlling the fourth switching element Q4a of the inverter circuit 1Wa.

[0206] Each of the plurality of first control signals S1a, the plurality of second control signals S2a, the plurality of third control signals S3a, and the plurality of fourth control signals S4a may be, for example, a signal having a potential level that alternates between a first potential level (hereinafter referred to as a "low level") and a second potential level (hereinafter referred to as a "high level") that is higher than the first potential level. The first potential level may be, for example, 0V, and the second potential level may be a potential level that is higher than the gate threshold voltage of the MOSFET. That is, in each of the plurality of control signals (including the plurality of first control signals S1a, the plurality of second control signals S2a, the plurality of third control signals S3a, and the plurality of fourth control signals S4a), the first potential level is a potential level for turning OFF the switching element associated with the control signal, and the second potential level is a potential level for turning ON the switching element associated with the control signal.

[0207] Each first switching element among the plurality of first switching elements Q1a turns ON when its associated first control signal S1a has a high level, and turns OFF when its associated first control signal S1a has a low level. Each second switching element among the plurality of second switching elements Q2a turns ON when its associated second control signal S2a has a high level, and turns OFF when its associated second control signal S2a has a low level. Each third switching element among the plurality of third switching elements Q3a turns ON when its associated third control signal S3a has a high level, and turns OFF when its associated third control signal S3a has a low level. Each fourth switching element among the plurality of fourth switching elements Q4a turns ON when its associated fourth control signal S4a has a high level, and turns OFF when its associated fourth control signal S4a has a low level.

[0208] In the multilevel inverter 100a, each inverter circuit in a plurality of inverter circuits 1a is controlled toward one of the first switching state, the second switching state, and the third switching state. That is, in the multilevel inverter 100a, in each inverter circuit of the three inverter circuits 1Ua, 1Va, and 1Wa, the switching state is controlled toward any one of the first switching state, the second switching state, and the third switching state. The first switching state, the second switching state, and the third switching state are different from each other in the combination of the ON / OFF state of the first switching element Q1a to the fourth switching element Q4a. In each inverter circuit in the plurality of inverter circuits 1a, its output voltage in the first switching state, its output voltage in the second switching state, and its output voltage in the third switching state are different from each other. That is, in each inverter circuit in the plurality of inverter circuits 1a, the potential level of the output voltage changes at three levels according to the state of the first switching element Q1a to the fourth switching element Q4a. Note that, regarding the output voltages of the plurality of inverter circuits 1 a , the output voltage of the U-phase inverter circuit 1Ua, the output voltage of the V-phase inverter circuit 1Va, and the output voltage of the W-phase inverter circuit 1Wa have mutually different phases.

[0209] The first switching state herein refers to a combination in which both the first switching element Q1a and the third switching element Q3a are turned ON and both the second switching element Q2a and the fourth switching element Q4a are turned OFF. When controlled toward the first switching state, each of the plurality of inverter circuits 1a can deliver an output voltage having a potential level at the positive electrode P1 of the DC power supply unit 3. In each of the plurality of inverter circuits 1a in the first switching state, the potential at the connection node 13a is as high as the potential level (e.g., Vdc / 2) at the positive electrode P1 of the DC power supply unit 3.

[0210] The second switching state herein refers to a combination in which both the first switching element Q1a and the second switching element Q2a are turned OFF and both the third switching element Q3a and the fourth switching element Q4a are turned ON. When controlled toward the second switching state, each of the plurality of inverter circuits 1a can deliver an output voltage having a potential level at the intermediate potential node M1 of the DC power supply unit 3. In each of the plurality of inverter circuits 1a in the second switching state, the potential at the connection node 13a is as high as the potential level (e.g., 0) at the intermediate potential node M1.

[0211] The third switching state herein refers to a combination in which both the first switching element Q1a and the third switching element Q3a are turned OFF and both the second switching element Q2a and the fourth switching element Q4a are turned ON. When controlled toward the third switching state, each of the plurality of inverter circuits 1a can deliver an output voltage having a potential level at the negative electrode N1 of the DC power supply unit 3. In each of the plurality of inverter circuits 1a in the third switching state, the potential at the connection node 13a is as high as the potential level (e.g., -Vdc / 2) at the negative electrode N1 of the DC power supply unit 3.

[0212] When the inverter circuit 1a is in the first switching state, the current flows along Fig. 27 The circuit shown in FIG. 1 passes sequentially through the positive electrode P1 of the DC power supply unit 3, the first switching element Q1a, the connection node 13a and the output terminal 41a (reference Fig.26 ) path flows so that the AC load RA1 (reference Fig.26 )’s output voltage is equal to Vdc / 2.

[0213] In addition, when the inverter circuit 1a is in the first switching state, the capacitor C11 of the first bootstrap circuit 71a is not charged by the power supply unit 9a, but the voltage required for the first gate driver 61a to turn on the first switching element Q1a is supplied from the capacitor C11 of the first bootstrap circuit 71a to the first gate driver 61a. Fig.28 As shown, the capacitor C11 of the first bootstrap circuit 71a is discharged through the discharge path Ru1a that passes through the capacitor C11, the high potential power supply terminal 61Ha of the first gate driver 61a, the low potential power supply terminal 61La of the first gate driver 61a, and the capacitor C11 in sequence. As a result, in the first bootstrap circuit 71a, the voltage across the capacitor C11 decreases over time.

[0214] Furthermore, when the inverter circuit 1a is in the first switching state, the capacitor C21 of the second bootstrap circuit 72a is not charged by the power supply unit 9a, but the voltage required for the third gate driver 63a to turn on the third switching element Q3a is supplied from the capacitor C21 of the second bootstrap circuit 72a to the third gate driver 63a. Fig.28 As shown, the capacitor C21 of the second bootstrap circuit 72a is discharged through the discharge path Ru3a that passes through the capacitor C21, the high potential power supply terminal 63Ha of the third gate driver 63a, the low potential power supply terminal 63La of the third gate driver 63a, and the capacitor C21 in sequence. As a result, in the second bootstrap circuit 72a, the voltage across the capacitor C21 decreases over time.

[0215] On the other hand, when the inverter circuit 1a is in the second switching state (ie, when the state of the inverter circuit 1a has changed from the first switching state to the second switching state), for example, Fig.29 As shown, the current follows a path (refer to Fig.26 ) flows so that the voltage value of the output voltage for the AC load RA1 is zero. More specifically, when the inverter circuits 1Ua, 1Va, and 1Wa are in the second switching state, the third switching state, and the third switching state, respectively, the current flows along a path that sequentially passes through the intermediate potential node M1 of the DC power supply unit 3, the third switching element Q3a of the inverter circuit 1Ua, the fourth switching element Q4a of the inverter circuit 1Ua, the connection node 13a, and the output terminal 41Ua.

[0216] Alternatively, when the inverter circuit 1a is in the second switching state, the voltage required for the third gate driver 63a to turn on the third switching element Q3a is supplied from the capacitor C21 of the second bootstrap circuit 72a to the third gate driver 63a. Fig.30As shown, the capacitor C21 of the second bootstrap circuit 72a is discharged through the discharge path Ru3a that passes through the capacitor C21, the high potential power supply terminal 63Ha of the third gate driver 63a, the low potential power supply terminal 63La of the third gate driver 63a, and the capacitor C21 in sequence. In addition, when the inverter circuit 1a is in the second switching state, the voltage required for the fourth gate driver 64a to turn on the fourth switching element Q4a is supplied from the capacitor C21 of the second bootstrap circuit 72a to the fourth gate driver 64a. Therefore, the capacitor C21 of the second bootstrap circuit 72a is discharged through the discharge path Ru4a that passes through the capacitor C21, the high potential power supply terminal 64Ha of the fourth gate driver 64a, the low potential power supply terminal 64La of the fourth gate driver 64a, and the capacitor C21 in sequence.

[0217] On the other hand, when the inverter circuit 1a is in the third switching state, as shown in FIG. Fig.31 As shown, the current flows along a path that passes through the output terminal 41a, the connection node 13a, the second switching element Q2a, and the negative electrode N1 of the DC power supply unit 3 in sequence, so that the voltage value of the output voltage for the AC load RA1 is -Vdc / 2. In addition, when the inverter circuit 1a is in the third switching state, the capacitor C11 of the first bootstrap circuit 71a is charged by the power supply unit 9a, and therefore, the voltage at the capacitor C11 rises with the passage of time to finally fully charge the capacitor C11. The charging path Ru91 for charging the capacitor C11 by the power supply unit 9a is a path that passes through the positive side terminal of the power supply unit 9a, the diode D11, the resistor R11, the capacitor C11, the connection node 13a, the second switching element Q2a, and the negative side terminal of the power supply unit 9a in sequence.

[0218] Furthermore, when the inverter circuit 1a is in the third switching state, the capacitor C21 of the second bootstrap circuit 72a is charged by the power supply unit 9a. The charging path Ru92 for charging the capacitor C21 by the power supply unit 9a is a path that passes through the positive side terminal of the power supply unit 9a, the diode D21, the resistor R21, the capacitor C21, the fourth switching element Q4a, the connection node 13a, the second switching element Q2a, and the negative side terminal of the power supply unit 9a in sequence.

[0219] Furthermore, when the inverter circuit 1a is in the second switching state (ie, when the switching state has been changed from the third switching state to the second switching state), as shown in FIG. Fig.33 As shown, the current flows along, for example, through the output terminal 41a (reference Fig.26), the connection node 13a, the fourth switching element Q4a, the third switching element Q3a, and the intermediate potential node M1, so that the voltage value of the output voltage for the AC load RA1 is equal to zero. More specifically, when the inverter circuits 1Ua, 1Va, and 1Wa are in the second switching state, the second switching state, and the first switching state, respectively, the current flows along the path that sequentially passes through the output terminal 41a of the inverter circuit 1Ua, the connection node 13a, the fourth switching element Q4a, the third switching element Q3a, and the intermediate potential node M1, so that the voltage value of the output voltage for the AC load RA1 is equal to zero.

[0220] In this case, when the inverter circuit 1a is in the second switching state, as described above, Fig.30 The discharge paths Ru3a and Ru4a shown are used for discharge.

[0221] The control unit 60a generates a voltage command Vu, Vv, Vw (see FIG. 1 ) for each output voltage of the inverter circuits 1Ua, 1Va, and 1Wa, for example. Fig.34 ), generating first control signals S1a to fourth control signals S4a (S1Ua to S4Ua) for the first switching element Q1a to the fourth switching element Q4a of the inverter circuit 1Ua, first control signals S1a to fourth control signals S4a (S1Va to S4Va) for the first switching element Q1a to the fourth switching element Q4a of the inverter circuit 1Va, and first control signals S1a to fourth control signals S4a (S1Wa to S4Wa) for the first switching element Q1a to the fourth switching element Q4a of the inverter circuit 1Wa.

[0222] like Fig.34 As shown, the voltage commands Vu, Vv, Vw are sinusoidal wave signals whose phases differ from each other by 120 degrees and have values ​​(voltage command values) that change over time. Note that the voltage commands Vu, Vv, Vw each have a cycle of the same length. Alternatively, the control unit 60a may perform proportional integral (PI) control on the voltage commands Vu, Vv, Vw based on information provided by the detection unit 8 for detecting the state of the AC load RA1. For example, if the AC load RA1 is a three-phase motor, the information provided by the detection unit 8 includes, for example, information related to detection results obtained by a plurality of current sensors for detecting output currents of the U-phase, V-phase, and W-phase flowing through the AC load RA1 and / or information related to detection results obtained by an encoder for detecting the number of revolutions, rotation angle, and other parameters of the three-phase motor.

[0223] Next, how one of the three inverter circuits 1a (for example, the U-phase inverter circuit 1Ua) operates will be described. The V-phase inverter circuit 1Va and the W-phase inverter circuit 1Wa operate in the same manner as the U-phase inverter circuit 1Ua. The respective output voltages of the U-phase inverter circuit 1Ua, the V-phase inverter circuit 1Va, and the W-phase inverter circuit 1Wa have mutually different phases.

[0224] The control unit 60 a controls the plurality of first gate drivers 61 a , the plurality of second gate drivers 62 a , the plurality of third gate drivers 63 a , and the plurality of fourth gate drivers 64 a by performing voltage vector control.

[0225] Next, how the control unit 60a performs the voltage vector control will be described in further detail.

[0226] The control unit 60a stores a set of voltage vectors in advance. Each voltage vector in the set of voltage vectors is defined by a combination of respective potential levels at a connection node 13a (where, in a corresponding inverter circuit among the plurality of inverter circuits 1a, at each connection node 13a, the first switching element Q1a and the second switching element Q2a are connected to each other). In other words, each voltage vector in the set of voltage vectors is defined by a switching state of the inverter circuit 1Ua corresponding to the U phase, a switching state of the inverter circuit 1Va corresponding to the V phase, and a switching state of the inverter circuit 1Wa corresponding to the W phase. The number of voltage vectors included in the set of voltage vectors is 3. 3 (=27) pieces.

[0227] like Fig.35 As shown, a set of voltage vectors includes three zero vectors V0p, V0n, and V0o, each of which has a magnitude of zero. In addition, a set of voltage vectors also includes a magnitude of (2 / 3) 1 / 2 · Six voltage vectors V1, V2, V3, V4, V5, V6 with 2Vdc and different directions. In addition, a set of voltage vectors also includes each having (2 / 3) 1 / 2 · Twelve voltage vectors V7p, V7n, V8p, V8n, V9p, V9n, V10p, V10n, V11p, V11n, V12p, V12n of the same magnitude as Vdc. In addition, a set of voltage vectors also includes each having (2 / 3) 1 / 2 ·3 1 / 2 · Six voltage vectors V13, V14, V15, V16, V17, and V18 with the same magnitude and different directions. Fig.35In the figure, the angle formed between each pair of adjacent voltage vectors belonging to the six voltage vectors V1, V2, V3, V4, V5, and V6 is 60 degrees. Similarly, the angle formed between each pair of adjacent voltage vectors belonging to the six voltage vectors V13, V14, V15, V16, V17, and V18 is also 60 degrees. Note that Fig.35 is a vector diagram illustrating a set of voltage vectors on an orthogonal dq coordinate system.

[0228] If the first switching state, the second switching state, and the third switching state of a set of voltage vectors are designated by reference numerals “P”, “0”, and “N”, respectively, and the respective switching states of the three phases are arranged in the order of the U phase, the V phase, and the W phase, then it can be as follows Fig.36 The set of voltage vectors is represented as shown.

[0229] like Fig.36 As shown, the three zero vectors V0p, V0n, and V0o can be expressed as V0p[PPP], V0n[NNN], and V0o

[000] , respectively. For example, V0p[PPP] indicates that, with respect to the zero vector V0p, the switching state of the U-phase inverter circuit 1Ua is "P", the switching state of the V-phase inverter circuit 1Va is "P", and the switching state of the W-phase inverter circuit 1Wa is "P". Voltage vectors with a suffix "p" such as V10p include "P" but do not include "N". The same statement will apply to the rest of the description. Voltage vectors with a suffix "n" such as V10n include "N" but do not include "P". The same statement will apply to the rest of the description. Voltage vectors with a suffix "o" such as V10o include "0" but neither "P" nor "N". If the switching state of the inverter circuit 1a is "P", the potential at the connection node 13a of the inverter circuit 1a will be the potential at the positive electrode P1 of the DC power supply unit 3. If the switching state of the inverter circuit 1a is "N", the potential at the connection node 13a of the inverter circuit 1a will be the potential at the negative electrode N1 of the DC power supply unit 3. If the switching state of the inverter circuit 1a is "0", the potential at the connection node 13a of the inverter circuit 1a will be the potential at the middle potential node M1 of the DC power supply unit 3.

[0230] The six voltage vectors V1, V2, V3, V4, V5, and V6 may be represented as V1[PNN], V2[PPN], V3[NPN], V4[NPP], V5[NNP], and V6[PNP], respectively. Voltage vectors such as V1[PNN], V2[PPN], V3[NPN], V4[NPP], V5[NNP], and V6[PNP], which do not add suffixes "p", "n", and "o" to the numbers after "V", include "P" and "N" as two of the three-phase switching states.

[0231] The twelve voltage vectors V7p, V7n, V8p, V8n, V9p, V9n, V10p, V10n, V11p, V11n, V12p and V12n can be expressed as V7p[P00], V7n[0NN], V8p[PP0], V8n[00N], V9p[0P0], V9n[N0N], V10p[0PP], V10n[N00], V11p[00P], V11n[NN0], V12p[P0P] and V12n[0N0] respectively.

[0232] The six voltage vectors V13, V14, V15, V16, V17 and V18 may be represented as V13[P0N], V14[ONP], V15[NP0], V16[N0P], V17[ONP] and V18[PN0], respectively.

[0233] The control unit 60a converts the instantaneous value of the command voltage for the output voltage of each of the plurality of inverter circuits 1a into a command voltage vector V* (reference voltage vector V*). Fig.37 ). If the d-axis component of the command voltage vector V* in the orthogonal dq coordinate system is Vd and the q-axis component of the command voltage vector V* in the orthogonal dq coordinate system is Vq, the command voltage vector V* can be given by the following equation (4):

[0234] [Formula 4]

[0235]

[0236] The control unit 60a selects a plurality (for example, five) of voltage vectors that are adjacent to the command voltage vector V* and belong to a group of voltage vectors. Fig.38 In the example shown in A, the multiple voltage vectors are V8p[PP0], V8n[00N], V13[P0N], V7p[P00] and V7n[0NN].

[0237] The control unit 60a uses a zero vector V0n[NNN] defined by a combination of potential levels at the respective connection nodes 13a of the plurality of inverter circuits 1a (which are as high as the level at the negative electrode) and at least one second voltage vector VV2 (for example, VV2) having the same direction as the first voltage vector VV1 and having a different magnitude from the first voltage vector VV1. Fig.38 V2[PPN] in the example shown in A) to replace the two first voltage vectors VV1 (for example, Fig.37 and Fig.38A) (which belongs to a plurality of voltage vectors, each having a reference magnitude and located at a position closest to the command voltage vector V*). The reference magnitude may be, for example, (2 / 3) 1 / 2 Vdc. Thus, the plurality of voltage vectors include twelve voltage vectors V7p[P00], V7n[ONN], V8p[PP0], V8n[00N], V9p[0P0], V9n[N0N], V10p[0PP], V10n[N00], V11p[00P], V11n[NN0], V12p[P0P], and V12n[0N0] as voltage vectors whose magnitude is a reference magnitude (i.e., reference vectors). An angle formed between the two first voltage vectors VV1 located closest to the command voltage vector V* and the command voltage vector V* is less than 30 degrees.

[0238] The control unit 60a controls the Fig.41 ) controls a plurality of first gate drivers 61a, a plurality of second gate drivers 62a, a plurality of third gate drivers 63a, and a plurality of fourth gate drivers 64a so that the plurality of voltage vectors except the first voltage vector VV1 (for example, Fig.38 The three voltage vectors (for example, V8p[PP0] and V8n[00N] in the example shown in A) other than Fig.38 The resultant vector of V13[P0N], V7p[P00] and V7n[0NN] in the example shown in FIG. 1 ), zero vector V0n[NNN] and at least one second voltage vector VV2 is equal to the command voltage vector V*. The predetermined control period Ts may be, for example, two periods of the carrier signal.

[0239] On the other hand, in a comparative example in which the control operation is performed without replacing the first voltage vector with the zero vector and the second voltage vector, within the control period Ts, the composite vector of the three vectors at the three vertices of the equilateral triangle surrounding the command voltage vector V* is made equal to the command voltage vector V*. Specifically, in the comparative example, the two first voltage vectors VV1 (for example, Fig.38 A of the example shown in FIG. 1 is a first voltage vector V8p[PP0] and V8n[00N]), a voltage vector V13[P0N], and a composite vector of voltage vectors V7p[P00] and V7n[00N] equal to the command voltage vector V*. In the comparative example, the control period Ts is one period of the carrier signal. In the comparative example, in two voltage vectors arranged in a row along the time series, for example, Fig.39As shown, within the control period Ts, the switching state of only one of the U phase, V phase and W phase changes between "P" and "0" or between "0" and "N", and the same voltage vector is output twice each time. Fig.39 In the example shown, the voltage vectors are output in the order of voltage vector V8n[00N], voltage vector V13[P0N], voltage vector V7p[P00], voltage vector V8p[PP0], voltage vector V8p[PP0], voltage vector V7p[P00], voltage vector V13[P0N], and voltage vector V8n[00N]. Fig.39 In the example shown, the time allocated to the voltage vectors V8p and V8n for the control period Ts is T0, the time allocated to the voltage vector V13 is T1, and the time allocated to the voltage vectors V7p and V7n is T2. With respect to T0, T1, T2, assuming that the voltage vectors at the three vertices of the equilateral triangle surrounding the command voltage vector V* are Va, Vb, Vc, respectively, the magnitude of the command voltage vector V* is V, and the angle is θ, the control unit 60a determines T0, T1, and T2 to satisfy the following equations (5) and (6). In equation (5), "j" represents an imaginary unit. Note that in Fig.39 In the example shown, for example, the voltage vector Va may be the voltage vectors V8p[PP0] and V8n[00N], the voltage vector Vb may be the voltage vector V13[P0N], and the voltage vector Vc may be V7p[P00] and V7n[0NN].

[0240] [Formula 5]

[0241] VavT0+VbvT1+VcvT2

[0242] =V·Ts·cosθ+jV·Ts·sinθ (5)

[0244] [Mathematical formula 6]

[0245] T0+T1+T2=Ts (6)

[0246] exist Fig.39 In the example shown, Fig.40 As shown, during the entire control period Ts, the third switching element Q3a will remain ON, and the magnitude of the voltage drop in the second bootstrap circuit 72a will increase.

[0247] In contrast, for example, Fig.41As shown, the control unit 60a of the multilevel inverter 100a according to the third embodiment outputs voltage vectors in the order of voltage vector V8n[00N], voltage vector V13[P0N], voltage vector V7p[P00], voltage vector V8p[PP0], voltage vector V8p[PP0], voltage vector V7p[P00], voltage vector V13[P0N] and voltage vector V8n[00N] within two cycles of the carrier signal. The control unit 60a replaces the voltage vectors V8p[PP0] and V8p[PP0] according to the comparative example with the zero vector V0n[NNN] and the second voltage vector VV2 (V2[PPN]), respectively, thereby Fig.41 The time period during which the U-phase switching state is "N" is shown. This makes Fig.42 The multilevel inverter 100a according to the third embodiment is shown to generate a third switching state in which both the first switching element Q1a and the third switching element Q3a are OFF and both the second switching element Q2a and the fourth switching element Q4a are ON. Thus, the multilevel inverter 100a according to the third embodiment can reduce the possibility of causing a voltage drop in the capacitor C11 of the first bootstrap circuit 71a and the capacitor C21 of the second bootstrap circuit 72a.

[0248] In addition, in the comparative example, even if the command voltage vector V* is Fig.38 The arrangement order of the voltage vectors in the control period Ts may be different depending on the initial value of the carrier signal at the beginning of the control period Ts. Fig.43 In the example shown, the voltage vectors are output in the order of voltage vector V8p[PP0], voltage vector V7p[P00], voltage vector V13[P0N], voltage vector V8n[00N], voltage vector V8n[00N], voltage vector V13[P0N], voltage vector V7p[P00], and voltage vector V8p[PP0]. Fig.43 In the example shown, Fig.39 As shown in the example, the time allocated to the voltage vectors V8p and V8n is T0, the time allocated to the voltage vector V13 is T1, and the time allocated to the voltage vectors V7p and V7n is T2. Fig.44 As shown, in the entire control period Ts, the third switching state will not be generated, and the magnitude of the voltage drop in the capacitor C11 of the first bootstrap circuit 71a and the second bootstrap circuit 72a will increase.

[0249] In contrast, for example Fig.45As shown, the control unit 60a of the multilevel inverter 100a according to the third embodiment outputs the voltage vector and the zero vector in the order of voltage vector V2[PPN], voltage vector V7p[P00], voltage vector V13[P0N], voltage vector V8n[00N], voltage vector V8n[00N], voltage vector V13[P0N], voltage vector V7p[P00] and zero vector V0n[NNN] within two cycles of the carrier signal. The control unit 60a replaces the voltage vectors V2[PPN] and V0n[NNN] with the voltage vectors V2[PPN] and V0n[NNN] respectively. Fig.43 The voltage vectors V8p[PP0], V8p[PP0] in the example shown are thus Fig.45 The time period during which the U-phase switching state is "N" is shown. This makes Fig.46 The multilevel inverter 100a according to the third embodiment generates the third switching state in the control period Ts. Therefore, the multilevel inverter 100a according to the third embodiment can reduce the possibility of causing voltage drops in the capacitor C11 of the first bootstrap circuit 71a and the capacitor C21 of the second bootstrap circuit 72a.

[0250] On the other hand, in the multilevel inverter 100a according to the third embodiment, the control unit 60a replaces one of the two first voltage vectors VV1 with the zero vector V0n[NNN] and the second voltage vector VV2 when the polarity of the command voltage corresponding to the command voltage vector V* is positive. In the multilevel inverter 100a according to the third embodiment, the control unit 60a does not replace the first voltage vector VV1 with the zero vector V0n[NNN] and the second voltage vector VV2 when the polarity of the command voltage corresponding to the command voltage vector V* is negative.

[0251] In addition, in the multilevel inverter 100a, the control unit 60a controls the plurality of first gate drivers 61a, the plurality of second gate drivers 62a, the plurality of third gate drivers 63a, and the plurality of fourth gate drivers 64a to prevent the respective output voltages of the plurality of first bootstrap circuits 71a and the plurality of second bootstrap circuits 72a from dropping to a predetermined value or less.

[0252] (3) Summary

[0253] In the multilevel inverter 100a according to the third embodiment, the control unit 60a selects a plurality of (five) voltage vectors (e.g., V8p[PP0], V8n[00N], V13[P0N], V7p[P00], V7n[0NN]) located adjacent to the command voltage vector V*, belonging to a group (27) of voltage vectors. Each voltage vector in the group of voltage vectors is defined by a combination of potential levels at the connection nodes 13 of the plurality of inverter circuits 1a. The control unit 60a replaces one of the two first voltage vectors VV1 with a zero vector V0n[NNN] and a second voltage vector VV2. The two first voltage vectors VV1 belong to a plurality of voltage vectors, each having a reference size, and are located at the position closest to the command voltage vector V*. The zero vector V0n[NNN] is defined by a combination of potential levels at the connection nodes 13a of the plurality of inverter circuits 1a (which are as high as the potential at the negative electrode N1). The second voltage vector VV2 has the same direction as the first voltage vector VV1 and has a size twice as large as the first voltage vector VV1. The control unit 60a controls the plurality of first gate drivers 61a, the plurality of second gate drivers 62a, the plurality of third gate drivers 63a, and the plurality of fourth gate drivers 64a within a predetermined control period Ts so that a composite vector of the voltage vectors other than the first voltage vector VV1, the other first voltage vector VV1 of the two first voltage vectors VV1, the zero vector V0n[NNN], and the second voltage vector VV2 included in the plurality of voltage vectors is equal to the command voltage vector V*.

[0254] The multilevel inverter 100a according to the third embodiment can reduce the possibility of causing a voltage drop in the bootstrap circuit. More specifically, the multilevel inverter 100a according to the third embodiment can reduce the possibility of causing a voltage drop in the capacitors C11 of the plurality of first bootstrap circuits 71a and the capacitors C21 of the plurality of second bootstrap circuits 72a.

[0255] In addition, in the multilevel inverter 100a according to the third embodiment, the DC-DC converter 91a included in the power supply unit 9a supplies voltage to the plurality of second gate drivers 62a, the plurality of first bootstrap circuits 71a, and the plurality of second bootstrap circuits 72a. Thus, the multilevel inverter 100a according to the third embodiment can contribute to miniaturization.

[0256] (Fourth embodiment)

[0257] The multilevel inverter 100a according to the fourth embodiment has the same features as the multilevel inverter 100a according to the third embodiment (refer to Fig.26 ) and therefore, its illustration and description will be omitted in this article.

[0258] In the multilevel inverter 100a according to the third embodiment, as Fig.41 As in the example shown, the control unit 60a replaces only one of the two first voltage vectors VV1 (such as V8n[00N] and V8p[PP0], etc.) with a zero vector and a second voltage vector VV2.

[0259] On the other hand, in the multilevel inverter 100a according to the fourth embodiment, for example, Fig.47 As in the example shown, the control unit 60a replaces the two first voltage vectors VV1 (such as Fig.39 In this case, as shown in FIG. 1 , one of the first voltage vectors VV1 (such as V8n[00N], etc.) is replaced with a second voltage vector VV2 (such as V2[PPN], etc.) and another first voltage vector VV1 (such as V8p[PP0], etc.) is replaced with a second voltage vector VV2 (such as V2[PPN], etc.). Fig.47 As shown, the control unit 60a of the multilevel inverter 100a according to the fourth embodiment outputs the voltage vector and the zero vector in the order of the zero vector V0n[NNN], the voltage vector V13[P0N], the voltage vector V7p[P00], the voltage vector V2[PPN], the voltage vector V2[PPN], the voltage vector V7p[P00], the voltage vector V13[P0N] and the zero vector V0[NNN] within two cycles of the carrier signal. The control unit 60a replaces the zero vector V0n[NNN], the voltage vector V2[PPN], the voltage vector V2[PPN] and the zero vector V0n[NNN] with the zero vector V0n[NNN], the voltage vector V2[PPN], the voltage vector V2[PPN] and the zero vector V0n[NNN], respectively. Fig.39 The voltage vectors V8n[00N], V8p[PP0], V8p[PP0], V8n[00N] in the example shown are thus Fig.47 The U-phase switching state is "N" as shown in FIG. Fig.48 As shown, the third switching state is generated within the control period Ts. Therefore, the multilevel inverter 100a according to the fourth embodiment can reduce the possibility of causing a voltage drop in the capacitor C27 of the second bootstrap circuit 72a.

[0260] Furthermore, in the multilevel inverter 100a according to the third embodiment, as Fig.45 As in the example shown, the control unit 60 replaces the zero vector V0n[NNN] and the second voltage vector VV2 (such as V2[PPN], etc.) with Fig.43 Only one first voltage vector VV1 (such as V8p[PP0], etc.) of the two first voltage vectors VV1 (such as V8n[00N] and V8p[PP0], etc.) is shown.

[0261] In contrast, in the multilevel inverter 100a according to the fourth embodiment, for example, Fig.47 As in the example shown, the control unit 60a replaces the zero vector V0n[NNN] with Fig.43 One of the two first voltage vectors VV1 (such as V8n[00N] and V8p[PP0]) shown in FIG. 1 is replaced with a second voltage vector VV2 (such as V2[PPN]). In this case, in the multilevel inverter 100 according to the fourth embodiment, as shown in FIG. Fig.47 As shown, the control unit 60a outputs the voltage vector and the zero vector in the order of zero vector V0n[NNN], voltage vector V13[P0N], voltage vector V7p[P00], voltage vector V2[PPN], voltage vector V2[PPN], voltage vector V7p[P00], voltage vector V13[P0N] and zero vector V0n[NNN] within two cycles of the carrier signal. The control unit 60a replaces the zero vector V0n[NNN], V2[PPN], V2[PPN], V0n[NNN] with the voltage vectors V0n[NNN], V2[PPN], V0n[NNN], respectively. Fig.43 The voltage vectors V8p[PP0], V8n[00N], V8n[00N], V8p[PP0] of the example shown are thus Fig.47 The U-phase switching state is "N" as shown in FIG. Fig.48 As shown, the third switching state is generated within the control period Ts. Therefore, the multilevel inverter 100a according to the fourth embodiment can reduce the possibility of causing a voltage drop in the capacitor C21 of the second bootstrap circuit 72a.

[0262] In the multilevel inverter 100a according to the fourth embodiment, the control unit 60a replaces each of the two first voltage vectors VV1 (which belong to a plurality of voltage vectors, each having a reference magnitude, and located at a position closest to the command voltage vector V*) with a zero vector V0n[NNN] (which is defined by a combination of the potential levels at the respective connection nodes 13a of the plurality of inverter circuits 1a (which are as high as the potential at the negative electrode N1) and a second voltage vector VV2 (which has the same direction as the first voltage level VV1 and has a magnitude twice as large as the first voltage vector VV1). The control unit 60a controls the plurality of first gate drivers 61a, the plurality of second gate drivers 62a, the plurality of third gate drivers 63a, and the plurality of fourth gate drivers 64a within a predetermined control period Ts so that a composite vector of the voltage vectors other than the first voltage vector VV1, the zero vector V0n[NNN], and the second voltage vector VV2 included in the plurality of voltage vectors is equal to the command voltage vector V*.

[0263] The multilevel inverter 100a according to the fourth embodiment can reduce the possibility of causing a voltage drop in the bootstrap circuit. More specifically, the multilevel inverter 100a according to the fourth embodiment can reduce the possibility of causing a voltage drop in the capacitor C11 of the plurality of first bootstrap circuits 71a and the capacitor C21 of the plurality of second bootstrap circuits 72a.

[0264] In addition, in the comparative example, even if the command voltage vector V* is Fig.38 The arrangement order of the voltage vectors in the control period Ts may be different depending on the initial value of the carrier signal at the beginning of the control period Ts. Fig.43 In the example shown, the voltage vectors are output in the order of voltage vector V8p[PP0], voltage vector V7p[P00], voltage vector V13[P0N], voltage vector V8n[00N], voltage vector V8n[00N], voltage vector V13[P0N], voltage vector V7p[P00], and voltage vector V8p[PP0]. Fig.43 In the example shown, Fig.39 As shown in the example, the time allocated to the voltage vectors V8p and V8n is T0, the time allocated to the voltage vector V13 is T1, and the time allocated to the voltage vectors V7p and V7n is T2. Fig.44 As shown, in the entire control period Ts, the third switching state will not be generated, and the magnitude of the voltage drop in the second bootstrap circuit 72a will increase.

[0265] In contrast, for example, Fig.49As shown, the control unit 60a of the multilevel inverter 100a according to the fourth embodiment outputs voltage vectors and zero vectors in the order of voltage vectors V2[PPN], voltage vectors V7p[P00], voltage vectors V13[P0N], voltage vectors V0n[NNN], voltage vectors V0n[NNN], voltage vectors V13[P0N], voltage vectors V7p[P00], and voltage vectors V2[PPN] within two cycles of the carrier signal. The control unit 60a replaces the voltage vectors V2[PPN] and V0n[NNN] with the voltage vectors V2[PPN] and V0n[NNN], respectively. Fig.43 The voltage vectors V8p[PP0], V8n[00N] in the example shown are thus Fig.49 The U-phase switching state is "N" as shown in FIG. Fig.50 As shown, the third switching state is generated within the control period Ts. Thus, the multilevel inverter 100a according to the fourth embodiment can reduce the possibility of causing a voltage drop in the capacitor C21 of the second bootstrap circuit 72a.

[0266] (Fifth Embodiment)

[0267] Reference Fig.51 In the following description, the multilevel inverter 100A has the same structure as the multilevel inverter 100a according to the third embodiment (refer to Fig.26 ) will be designated by the same figure mark as the corresponding part, and its description will be omitted in this article.

[0268] In the multilevel inverter 100A, its power supply unit 9a includes a plurality of (eg, three) DC-DC converters 91a, which is different from the multilevel inverter 100a.

[0269] In the multilevel inverter 100A, a plurality of DC-DC converters 91a are arranged one-to-one for a plurality of (e.g., three) fourth gate drivers 64a. Each DC-DC converter in the plurality of DC-DC converters 91a supplies voltage to a corresponding fourth gate driver in the fourth gate driver 64a. In addition, in the multilevel inverter 100A, a plurality of DC-DC converters 91a are arranged one-to-one for a plurality of first bootstrap circuits 71a. Each DC-DC converter in the plurality of DC-DC converters 91a is connected to a corresponding first bootstrap circuit in the first bootstrap circuit 71a. More specifically, the positive side terminal of each DC-DC converter in the plurality of DC-DC converters 91a is connected to the anode of the diode D11 of the corresponding first bootstrap circuit in the first bootstrap circuit 71a, and its negative side terminal is connected to the negative electrode N1 of the DC power supply unit 3.

[0270] In the multilevel inverter 100A, the control unit 60a controls the first, second, third, and fourth gate drivers 61a, 62a, 63a, and 64a by performing the same voltage vector control as the control unit 60a of the multilevel inverter 100a.

[0271] Therefore, the multilevel inverter 100A according to the fifth embodiment can reduce the possibility of causing voltage drops in the capacitors C11 of the plurality of first bootstrap circuits 71a and the capacitors C21 of the plurality of second bootstrap circuits 72a as in the multilevel inverter 100a.

[0272] (Sixth embodiment)

[0273] Reference Fig.52 In the following description, the multilevel inverter 100B has the same structure as the multilevel inverter 100a according to the third embodiment (refer to Fig.26 ) will be designated by the same figure mark as the corresponding part, and its description will be omitted in this article.

[0274] In the multilevel inverter 100B, the bidirectional switch including the third switching element Q3a and the fourth switching element Q4a is a common drain bidirectional switch in which the first main terminals (source terminals) of the third switching element Q3a and the fourth switching element Q4a are connected to each other. In the bidirectional switch of the multilevel inverter 100B, the second main terminal of the fourth switching element Q4a is connected to the intermediate potential node M1, and the third switching element Q3a is connected to the connection node 13a.

[0275] In addition, in the multilevel inverter 100B, its power supply unit 9a includes not only a DC-DC converter 91a (hereinafter referred to as "first DC-DC converter 91a"), but also a plurality of (for example, three) second DC-DC converters 92. Note that Fig.52 , each of the plurality of second DC-DC converters 92 is represented by a symbol of a DC power source.

[0276] The first DC-DC converter 91 a supplies voltage to the plurality of second gate drivers 62 a , the plurality of first bootstrap circuits 71 a , and the plurality of second bootstrap circuits 72 a .

[0277] The plurality of second DC-DC converters 92 are provided one-to-one for the plurality of fourth gate drivers 64a. Each of the plurality of second DC-DC converters 92 supplies voltage to a corresponding fourth gate driver among the plurality of fourth gate drivers 64a. The positive side terminal of each second DC-DC converter 92 is connected to the high potential power supply terminal of the corresponding fourth gate driver 64a, and the negative side terminal thereof is connected to the intermediate potential node M1, the low potential power supply terminal of the corresponding fourth gate driver 64a, and the second main terminal of the fourth switching element Q4.

[0278] In the multilevel inverter 100B, the control unit 60a controls the first gate drivers 61a, the second gate drivers 62a, the third gate drivers 63a and the fourth gate drivers 64a by performing the same voltage vector control as the control unit 60a of the multilevel inverter 100a.

[0279] Therefore, the multilevel inverter 100B according to the sixth embodiment can reduce the possibility of causing voltage drops in the capacitors C11 of the plurality of first bootstrap circuits 71a and the capacitors C21 of the plurality of second bootstrap circuits 72a as in the multilevel inverter 100a.

[0280] (Seventh Embodiment)

[0281] Reference Fig.53 In the following description, the multilevel inverter 100C has the same structure as the multilevel inverter 100a according to the third embodiment (refer to Fig.26 ) will be designated by the same figure mark as the corresponding part, and its description will be omitted in this article.

[0282] The multilevel inverter 100C does not include the plurality of second bootstrap circuits 72a of the multilevel inverter 100a. Its power supply unit 9a includes not only a DC-DC converter 91a (hereinafter referred to as "first DC-DC converter 91a"), but also a plurality of (for example, three) second DC-DC converters 92. Note that Fig.53 , each of the plurality of second DC-DC converters 92 is represented by a symbol of a DC power source.

[0283] The first DC-DC converter 91 a supplies voltage to the plurality of second gate drivers 62 a , the plurality of first bootstrap circuits 71 a , and the plurality of second bootstrap circuits 72 a .

[0284] A plurality of second DC-DC converters 92 are provided for a plurality of third gate drivers 63a and a plurality of fourth gate drivers 64a. Each second DC-DC converter in the plurality of second DC-DC converters 92 supplies voltage to a corresponding third gate driver in the plurality of third gate drivers 63a and a corresponding fourth gate driver in the plurality of fourth gate drivers 64a. The positive side terminal of each second DC-DC converter in the plurality of second DC-DC converters 92 is connected to a high potential power supply terminal of the corresponding third gate driver 63a and a high potential power supply terminal of the corresponding fourth gate driver 64a. The negative side terminal of each second DC-DC converter in the plurality of second DC-DC converters 92 is connected to a low potential power supply terminal of the corresponding third gate driver 63a and a low potential power supply terminal of the corresponding fourth gate driver 64a.

[0285] In the multilevel inverter 100C, the control unit 60a controls the first gate drivers 61a, the second gate drivers 62a, the third gate drivers 63a and the fourth gate drivers 64a by performing the same voltage vector control as the control unit 60a of the multilevel inverter 100a.

[0286] Therefore, the multilevel inverter 100C according to the seventh embodiment can reduce the possibility of causing a voltage drop in the capacitors C11 of the plurality of first bootstrap circuits 71 a.

[0287] (Eighth Embodiment)

[0288] Reference Fig.54 In the following description, the multilevel inverter 100D has the same structure as the multilevel inverter 100C according to the seventh embodiment (see FIG. Fig.53 ) will be designated by the same figure mark as the corresponding part, and its description will be omitted in this article.

[0289] In the multilevel inverter 100D, the first DC-DC converter 91a is not connected to the plurality of first bootstrap circuits 71a, and the positive side terminal of each second DC-DC converter 92 is connected to the anode of the diode D11 of the corresponding one of the first bootstrap circuits 71a.

[0290] In the multilevel inverter 100D, the control unit 60a thereof controls a plurality of first gate drivers 61a, a plurality of second gate drivers 62a, a plurality of third gate drivers 63a, and a plurality of fourth gate drivers 64a by performing the same voltage vector control as the control unit 60a of the multilevel inverter 100a according to the third embodiment.

[0291] Therefore, the multilevel inverter 100D according to the eighth embodiment can reduce the possibility of causing a voltage drop in the capacitors C11 of the plurality of first bootstrap circuits 71 a.

[0292] (Other Modifications)

[0293] Note that the above-mentioned third to eighth embodiments are merely exemplary embodiments of the various embodiments of the present disclosure and should not be interpreted as limiting. On the contrary, the third to eighth embodiments can be easily modified in various ways according to design choices or any other factors without departing from the scope of the present disclosure.

[0294] For example, the plurality of first switching elements Q1a, the plurality of second switching elements Q2a, the plurality of third switching elements Q3a, and the plurality of fourth switching elements Q4a do not necessarily have to be MOSFETs, but may also be insulated gate bipolar transistors (IGBTs). In this case, in each of the plurality of first switching elements Q1a, the plurality of second switching elements Q2a, the plurality of third switching elements Q3a, and the plurality of fourth switching elements Q4a, its control terminal, the first main terminal, and the second main terminal are the gate terminal, the collector terminal, and the emitter terminal, respectively.

[0295] In addition, in the multilevel inverters 100a and 100A to 100D according to the third to eighth embodiments, the control unit 60a thereof can replace the first voltage vector VV1 with the zero vector V0n[NNN] and the second voltage vector VV2 not only when the polarity of the command voltage corresponding to the command voltage vector V* is positive, but also when the polarity of the command voltage corresponding to the command voltage vector V* is negative.

[0296] Each of the plurality of first bootstrap circuits 71a includes a Zener diode Z11 in the above embodiment, but may have a structure not including the Zener diode Z11. Each of the plurality of second bootstrap circuits 72a includes a Zener diode Z21 in the above embodiment, but may have a structure not including the Zener diode Z21.

[0297] Furthermore, the multilevel inverter 100a only needs to be a multilevel inverter having at least three levels, and may be a five-level inverter, for example.

[0298] (All aspects)

[0299] The foregoing description provides specific implementations of the following aspects of the present disclosure.

[0300] A multilevel inverter (100) according to a first aspect includes a DC power supply unit (3), a plurality of inverter circuits (1), and a controller (6). The DC power supply unit (3) includes a positive electrode (P1), a negative electrode (N1), and an intermediate potential node (M1). The plurality of inverter circuits (1) are connected between the positive electrode (P1) and the negative electrode (N1) of the DC power supply unit (3). The controller (6) controls the plurality of inverter circuits (1). Each inverter circuit in the plurality of inverter circuits (1) includes a switching circuit (10), a first diode (D1), a second diode (D2), a third diode (D3), a fourth diode (D4), a fifth diode (D5), and a sixth diode (D6). In the switching circuit (10), a first switching element (Q1), a second switching element (Q2), a third switching element (Q3), and a fourth switching element (Q4) are connected in series in a manner of being arranged in a row from the positive electrode (P1) toward the negative electrode (N1). The first diode (D1) is connected in anti-parallel to the first switching element (Q1). The second diode (D2) is connected in anti-parallel to the second switching element (Q2). The third diode (D3) is connected in anti-parallel to the third switching element (Q3). The fourth diode (D4) is connected in anti-parallel to the fourth switching element (Q4). The fifth diode (D5) has a cathode connected to the first connection node (11) between the first switching element (Q1) and the second switching element (Q2) and an anode connected to the intermediate potential node (M1). The sixth diode (D6) has an anode connected to the second connection node (12) between the third switching element (Q3) and the fourth switching element (Q4) and a cathode connected to the intermediate potential node (M1). The controller (6) includes a plurality of first gate drivers (61), a plurality of second gate drivers (62), a plurality of third gate drivers (63), a plurality of fourth gate drivers (64), a plurality of first bootstrap circuits (71), a plurality of second bootstrap circuits (72), a power supply unit (9) and a control unit (60). Each of the plurality of first gate drivers (61) drives the first switching element (Q1) of the corresponding inverter circuit in the plurality of inverter circuits (1). Each second gate driver among the plurality of second gate drivers (62) drives a second switching element (Q2) of a corresponding inverter circuit among the plurality of inverter circuits (1). Each third gate driver among the plurality of third gate drivers (63) drives a third switching element (Q3) of a corresponding inverter circuit among the plurality of inverter circuits (1). Each fourth gate driver among the plurality of fourth gate drivers (64) drives a fourth switching element (Q4) of a corresponding inverter circuit among the plurality of inverter circuits (1). The plurality of first bootstrap circuits (71) are provided one-to-one with respect to the plurality of first gate drivers (61). Each first bootstrap circuit among the plurality of first bootstrap circuits (71) supplies voltage to a corresponding first gate driver among the plurality of first gate drivers (61).A plurality of second bootstrap circuits (72) are provided one-to-one for a plurality of second gate drivers (62). Each second bootstrap circuit in the plurality of second bootstrap circuits (72) supplies voltage to a corresponding second gate driver in the plurality of second gate drivers (62). A plurality of third bootstrap circuits (73) are provided one-to-one for a plurality of third gate drivers (63). Each third bootstrap circuit in the plurality of third bootstrap circuits (73) supplies voltage to a corresponding third gate driver in the plurality of third gate drivers (63). A power supply unit (9) supplies voltage to a plurality of fourth gate drivers (64). A control unit (60) controls a plurality of first gate drivers (61), a plurality of second gate drivers (62), a plurality of third gate drivers (63) and a plurality of fourth gate drivers (64). The control unit (60) selects a plurality of voltage vectors located adjacent to a command voltage vector (V*) from a group of voltage vectors. Each voltage vector in the group of voltage vectors is defined by a combination of potential levels at each third connection node (13) (at each third connection node (13) at which the second switching element (Q2) and the third switching element (Q3) are connected to each other in a corresponding inverter circuit in a plurality of inverter circuits (1)). The control unit (60) replaces one of the two first voltage vectors (VV1) with a zero vector (V0n[NNN]) and a second voltage vector (VV2). The two first voltage vectors (VV1) belong to a plurality of voltage vectors, each having a reference magnitude, and being located closest to the command voltage vector (V*). The zero vector (V0n[NNN]) is defined by a combination of potential levels at each third connection node (13) that are as high as the potential at the negative electrode (N1), wherein at each third connection node (13) at which the second switching element (Q2) and the third switching element (Q3) are connected to each other in a corresponding inverter circuit in a plurality of inverter circuits (1). The second voltage vector (VV2) has the same direction as the first voltage vector (VV1) and has a size twice as large as the first voltage vector (VV1). The control unit (60) controls a plurality of first gate drivers (61), a plurality of second gate drivers (62), a plurality of third gate drivers (63) and a plurality of fourth gate drivers (64) within a predetermined control period (Ts) so that a composite vector of voltage vectors other than the first voltage vector (VV1), the other first voltage vector (VV1) of the two first voltage vectors (VV1), a zero vector (V0n[NNN]) and a second voltage vector (VV2) included in the plurality of voltage vectors is equal to a command voltage vector (V*).

[0301] This aspect can reduce the possibility of causing a voltage drop in the bootstrap circuit. More specifically, this aspect can reduce the possibility of causing a voltage drop in the capacitor (C17) of the plurality of first bootstrap circuits (71), the capacitor (C27) of the plurality of second bootstrap circuits (72), and the capacitor (C37) of the plurality of third bootstrap circuits (73).

[0302] A multilevel inverter (100) according to a second aspect includes a DC power supply unit (3), a plurality of inverter circuits (1), and a controller (6). The DC power supply unit (3) includes a positive electrode (P1), a negative electrode (N1), and an intermediate potential node (M1). The plurality of inverter circuits (1) are connected between the positive electrode (P1) and the negative electrode (N1) of the DC power supply unit (3). The controller (6) controls the plurality of inverter circuits (1). Each inverter circuit in the plurality of inverter circuits (1) includes a switching circuit (10), a first diode (D1), a second diode (D2), a third diode (D3), a fourth diode (D4), a fifth diode (D5), and a sixth diode (D6). In the switching circuit (10), a first switching element (Q1), a second switching element (Q2), a third switching element (Q3), and a fourth switching element (Q4) are connected in series in a manner of being arranged in a row from the positive electrode (P1) toward the negative electrode (N1). The first diode (D1) is connected in anti-parallel to the first switching element (Q1). The second diode (D2) is connected in anti-parallel to the second switching element (Q2). The third diode (D3) is connected in anti-parallel to the third switching element (Q3). The fourth diode (D4) is connected in anti-parallel to the fourth switching element (Q4). The fifth diode (D5) has a cathode connected to the first connection node (11) between the first switching element (Q1) and the second switching element (Q2), and an anode connected to the intermediate potential node (M1). The sixth diode (D6) has an anode connected to the second connection node (12) between the third switching element (Q3) and the fourth switching element (Q4), and a cathode connected to the intermediate potential node (M1). The controller (6) includes a plurality of first gate drivers (61), a plurality of second gate drivers (62), a plurality of third gate drivers (63), a plurality of fourth gate drivers (64), a plurality of first bootstrap circuits (71), a plurality of second bootstrap circuits (72), a power supply unit (9) and a control unit (60). Each first gate driver among the plurality of first gate drivers (61) drives a first switching element (Q1) of a corresponding inverter circuit among the plurality of inverter circuits (1). Each second gate driver among the plurality of second gate drivers (62) drives a second switching element (Q2) of a corresponding inverter circuit among the plurality of inverter circuits (1). Each third gate driver among the plurality of third gate drivers (63) drives a third switching element (Q3) of a corresponding inverter circuit among the plurality of inverter circuits (1). Each fourth gate driver among the plurality of fourth gate drivers (64) drives a fourth switching element (Q4) of a corresponding inverter circuit among the plurality of inverter circuits (1). The plurality of first bootstrap circuits (71) are provided one-to-one with respect to the plurality of first gate drivers (61). Each first bootstrap circuit among the plurality of first bootstrap circuits (71) supplies voltage to a corresponding first gate driver among the plurality of first gate drivers (61).A plurality of second bootstrap circuits (72) are provided one-to-one for a plurality of second gate drivers (62). Each second bootstrap circuit in the plurality of second bootstrap circuits (72) supplies voltage to a corresponding second gate driver in the plurality of second gate drivers (62). A plurality of third bootstrap circuits (73) are provided one-to-one for a plurality of third gate drivers (63). Each third bootstrap circuit in the plurality of third bootstrap circuits (73) supplies voltage to a corresponding third gate driver in the plurality of third gate drivers (63). A power supply unit (9) supplies voltage to a plurality of fourth gate drivers (64). A control unit (60) controls a plurality of first gate drivers (61), a plurality of second gate drivers (62), a plurality of third gate drivers (63) and a plurality of fourth gate drivers (64). The control unit (60) selects a plurality of voltage vectors located adjacent to a command voltage vector (V*) from a group of voltage vectors. Each voltage vector in the group of voltage vectors is defined by a combination of potential levels at each third connection node (13), wherein in a corresponding inverter circuit in a plurality of inverter circuits (1), at each third connection node, the second switching element (Q2) and the third switching element (Q3) are connected to each other. The control unit (60) replaces the first voltage vector (VV1) with a zero vector (Vo[NNN]) and a second voltage vector (VV2). The first voltage vector (VV1) belongs to a plurality of voltage vectors, has a reference magnitude, and is located closest to the command voltage vector (V*). The zero vector (Vo[NNN]) is defined by a combination of potential levels at each third connection node (13) that are as high as the potential at the negative electrode (N1), wherein in a corresponding inverter circuit in a plurality of inverter circuits (1), at each third connection node, the second switching element (Q2) and the third switching element (Q3) are connected to each other. The second voltage vector (VV2) has the same direction as the first voltage vector (VV1) and has a size twice as large as the first voltage vector (VV1). The control unit (60) controls a plurality of first gate drivers (61), a plurality of second gate drivers (62), a plurality of third gate drivers (63) and a plurality of fourth gate drivers (64) within a predetermined control period (Ts) so that a composite vector of voltage vectors other than the first voltage vector (VV1), a zero vector (Vo[NNN]) and the second voltage vector (VV2) included in the plurality of voltage vectors is equal to a command voltage vector (V*).

[0303] This aspect can reduce the possibility of causing a voltage drop in the bootstrap circuit. More specifically, this aspect can reduce the possibility of causing a voltage drop in the capacitor (C17) of the plurality of first bootstrap circuits (71), the capacitor (C27) of the plurality of second bootstrap circuits (72), and the capacitor (C37) of the plurality of third bootstrap circuits (73).

[0304] In a multilevel inverter (100) according to a third aspect that can be implemented in combination with the first aspect or the second aspect, when the polarity of the command voltage corresponding to the command voltage vector (V*) is positive, the control unit (60) replaces the first voltage vector (VV1) with a zero vector (V0n[NNN]) and a second voltage vector (VV2).

[0305] This aspect may reduce the number of times the first voltage vector ( VV1 ) needs to be replaced with a zero vector ( V0n[NNN]) and a second voltage vector ( VV2 ).

[0306] In a multi-level inverter (100) according to a fourth aspect that can be implemented in combination with any one of the first to third aspects, a control unit (60) controls a plurality of first gate drivers (61), a plurality of second gate drivers (62), a plurality of third gate drivers (63) and a plurality of fourth gate drivers (64) to prevent the output voltage of each of the plurality of first bootstrap circuits (71) and the plurality of second bootstrap circuits (72) from dropping to a predetermined value or less.

[0307] This aspect can prevent the output voltage of each of the plurality of first bootstrap circuits (71) and the plurality of second bootstrap circuits (72) from dropping to a predetermined value or less.

[0308] In a multilevel inverter (100) according to a fifth aspect that can be implemented in combination with any one of the first to fourth aspects, each of the plurality of first bootstrap circuits (71) and the plurality of second bootstrap circuits (72) includes a capacitor (C17), a diode (D17) and a resistor (R17). The diode (D17) is connected in series to the capacitor (C17). The resistor (R17) is connected in series to the capacitor (C17).

[0309] In the multilevel inverter (100) according to the sixth aspect which can be implemented in combination with any one of the first to fifth aspects, the power supply unit (9) includes a DC-DC converter (91). The DC-DC converter (91) supplies voltage to the plurality of fourth gate drivers (64) and the plurality of third bootstrap circuits (73).

[0310] This aspect can help reduce the size of the multilevel inverter (100).

[0311] A multilevel inverter (100a; 100A; 100B; 100C; 100D) according to the seventh aspect includes a DC power supply unit (3), a plurality of inverter circuits (1a) and a controller (6a). The DC power supply unit (3) includes a positive electrode (P1), a negative electrode (N1) and an intermediate potential node (M1). The plurality of inverter circuits (1a) are connected between the positive electrode (P1) and the negative electrode (N1) of the DC power supply unit (3). The controller (6a) controls the plurality of inverter circuits (1a). Each inverter circuit in the plurality of inverter circuits (1a) includes: a first switching element (Q1a), a second switching element (Q2a), a third switching element (Q3a) and a fourth switching element (Q4a); and a first diode (D1a), a second diode (D2a), a third diode (D3a) and a fourth diode (D4a). A first diode (D1a), a second diode (D2a), a third diode (D3a) and a fourth diode (D4a) are connected in anti-parallel to a first switching element (Q1a), a second switching element (Q2a), a third switching element (Q3a) and a fourth switching element (Q4a), respectively. In each of the plurality of inverter circuits (1a), the first switching element (Q1a) and the second switching element (Q2a) are connected in series in a manner of being arranged in a row from a positive electrode (P1) toward a negative electrode (N1). In each of the plurality of inverter circuits (1a), a series circuit of the third switching element (Q3a) and the fourth switching element (Q4a) is connected between an intermediate potential node (M1) and an output node. In each of the plurality of inverter circuits (1a), the output node is a connection node (13a) between the first switching element (Q1a) and the second switching element (Q2a). The controller (6a) includes a plurality of first gate drivers (61a), a plurality of second gate drivers (62a), a plurality of third gate drivers (63a), a plurality of fourth gate drivers (64a), a plurality of bootstrap circuits (71a), a power supply unit (9a) and a control unit (60a). Each of the plurality of first gate drivers (61a) drives a first switching element (Q1a) of a corresponding inverter circuit in a plurality of inverter circuits (1a). Each of the plurality of second gate drivers (62a) drives a second switching element (Q2a) of a corresponding inverter circuit in a plurality of inverter circuits (1a). Each of the plurality of third gate drivers (63a) drives a third switching element (Q3a) of a corresponding inverter circuit in a plurality of inverter circuits (1a). Each of the plurality of fourth gate drivers (64a) drives a fourth switching element (Q4a) of a corresponding inverter circuit in a plurality of inverter circuits (1a). A plurality of bootstrap circuits (71a) are provided one-to-one with respect to a plurality of first gate drivers (61a).Each of the plurality of bootstrap circuits (71a) supplies voltage to a corresponding first gate driver in a plurality of first gate drivers (61a). The power supply unit (9a) supplies voltage to a plurality of second gate drivers (62a) and a plurality of third gate drivers (63a). The control unit (60a) controls the plurality of first gate drivers (61a), the plurality of second gate drivers (62a), the plurality of third gate drivers (63a) and the plurality of fourth gate drivers (64a). The control unit (60a) selects a plurality of voltage vectors located adjacent to a command voltage vector (V*) from a group of voltage vectors. Each voltage vector in the group of voltage vectors is defined by a combination of potential levels at a plurality of connection nodes (13a) of a plurality of inverter circuits (1a). The control unit (60a) replaces one of the two first voltage vectors (VV1) with a zero vector (V0n[NNN]) and a second voltage vector (VV2). Two first voltage vectors (VV1) belong to a plurality of voltage vectors, each having a reference magnitude, and are located closest to a command voltage vector (V*). A zero vector (V0n[NNN]) is defined by a combination of potential levels at respective connection nodes (13a) of a plurality of inverter circuits (1a), which are as high as the potential at a negative electrode (N1). A second voltage vector (VV2) has the same direction as the first voltage vector (VV1) and has a magnitude twice as large as that of the first voltage vector (VV1). A control unit (60a) controls a plurality of first gate drivers (61a), a plurality of second gate drivers (62a), a plurality of third gate drivers (63a), and a plurality of fourth gate drivers (64a) within a predetermined control period (Ts) so that a composite vector of voltage vectors other than the first voltage vector (VV1), another first voltage vector (VV1) of the two first voltage vectors (VV1), a zero vector (V0n[NNN]), and a second voltage vector (VV2) included in the plurality of voltage vectors is equal to the command voltage vector (V*).

[0312] This aspect can reduce the possibility of causing a voltage drop in the bootstrap circuit. More specifically, this aspect can reduce the possibility of causing a voltage drop in the capacitor (C11) of the plurality of bootstrap circuits (71a).

[0313] A multilevel inverter (100a; 100A; 100B; 100C; 100D) according to an eighth aspect includes a DC power supply unit (3), a plurality of inverter circuits (1a) and a controller (6a). The DC power supply unit (3) includes a positive electrode (P1), a negative electrode (N1) and an intermediate potential node (M1). The plurality of inverter circuits (1a) are connected between the positive electrode (P1) and the negative electrode (N1) of the DC power supply unit (3). The controller (6a) controls the plurality of inverter circuits (1a). Each inverter circuit in the plurality of inverter circuits (1a) includes: a first switching element (Q1a), a second switching element (Q2a), a third switching element (Q3a) and a fourth switching element (Q4a); and a first diode (D1a), a second diode (D2a), a third diode (D3a) and a fourth diode (D4a). A first diode (D1a), a second diode (D2a), a third diode (D3a) and a fourth diode (D4a) are connected in anti-parallel to a first switching element (Q1a), a second switching element (Q2a), a third switching element (Q3a) and a fourth switching element (Q4a), respectively. In each of the plurality of inverter circuits (1a), the first switching element (Q1a) and the second switching element (Q2a) are connected in series in a manner of being arranged in a row from a positive electrode (P1) toward a negative electrode (N1). In each of the plurality of inverter circuits (1a), a series circuit of the third switching element (Q3a) and the fourth switching element (Q4a) is connected between an intermediate potential node (M1) and an output node. In each of the plurality of inverter circuits (1a), the output node is a connection node (13a) between the first switching element (Q1a) and the second switching element (Q2a). The controller (6a) includes a plurality of first gate drivers (61a), a plurality of second gate drivers (62a), a plurality of third gate drivers (63a), a plurality of fourth gate drivers (64a), a plurality of bootstrap circuits (71a), a power supply unit (9a) and a control unit (60a). Each of the plurality of first gate drivers (61a) drives a first switching element (Q1a) of a corresponding inverter circuit in a plurality of inverter circuits (1a). Each of the plurality of second gate drivers (62a) drives a second switching element (Q2a) of a corresponding inverter circuit in a plurality of inverter circuits (1a). Each of the plurality of third gate drivers (63a) drives a third switching element (Q3a) of a corresponding inverter circuit in a plurality of inverter circuits (1a). Each of the plurality of fourth gate drivers (64a) drives a fourth switching element (Q4a) of a corresponding inverter circuit in a plurality of inverter circuits (1a). A plurality of bootstrap circuits (71a) are provided one-to-one with respect to a plurality of first gate drivers (61a).Each bootstrap circuit in a plurality of bootstrap circuits (71a) supplies voltage to a corresponding first gate driver in a plurality of first gate drivers (61a). A power supply unit (9a) supplies voltage to a plurality of second gate drivers (62a) and a plurality of third gate drivers (63a). A control unit (60a) controls the plurality of first gate drivers (61a), the plurality of second gate drivers (62a), the plurality of third gate drivers (63a) and the plurality of fourth gate drivers (64a). The control unit (60a) selects a plurality of voltage vectors located adjacent to a command voltage vector (V*) from a group of voltage vectors. Each voltage vector in the group of voltage vectors is defined by a combination of potential levels at a plurality of connection nodes (13a) of a plurality of inverter circuits (1a). The control unit (60a) replaces each first voltage vector in two first voltage vectors (VV1) with a zero vector (V0[NNN]) and a second voltage vector (VV2). The two first voltage vectors (VV1) belong to a plurality of voltage vectors, each having a reference magnitude, and located closest to the command voltage vector (V*). A zero vector (V0[NNN]) is defined by a combination of potential levels at respective connection nodes (13a) of a plurality of inverter circuits (1a) which are as high as the potential at the negative electrode (N1). A second voltage vector (VV2) has the same direction as the first voltage vector (VV1) and has a size twice as large as the first voltage vector (VV1). A control unit (60a) controls a plurality of first gate drivers (61a), a plurality of second gate drivers (62a), a plurality of third gate drivers (63a) and a plurality of fourth gate drivers (64a) within a predetermined control period (Ts) so that a composite vector of voltage vectors other than the first voltage vector (VV1), the zero vector (V0[NNN]) and the second voltage vector (VV2) included in the plurality of voltage vectors is equal to a command voltage vector (V*).

[0314] This aspect can reduce the possibility of causing a voltage drop in the bootstrap circuit (71a). More specifically, this aspect can reduce the possibility of causing a voltage drop in the capacitor (C11) of the plurality of bootstrap circuits (71a).

[0315] In a multilevel inverter (100a) according to the ninth aspect which can be implemented in combination with the seventh aspect or the eighth aspect, when the polarity of the command voltage corresponding to the command voltage vector (V*) is positive, the control unit (60a) replaces the first voltage vector (VV1) with a zero vector (V0n[NNN]) and a second voltage vector (VV2).

[0316] This aspect may reduce the number of times the first voltage vector ( VV1 ) needs to be replaced with a zero vector ( V0n[NNN]) and a second voltage vector ( VV2 ).

[0317] In a multi-level inverter (100a; 100A; 100B; 100C; 100D) according to the tenth aspect which can be implemented in combination with any one of the seventh to ninth aspects, a control unit (60a) controls a plurality of first gate drivers (61a), a plurality of second gate drivers (62a), a plurality of third gate drivers (63a) and a plurality of fourth gate drivers (64a) to prevent the output voltage of a plurality of bootstrap circuits (71a) from dropping to a predetermined value or less.

[0318] This aspect can prevent the output voltage of each of the plurality of bootstrap circuits (71a) from dropping to a predetermined value or less.

[0319] In a multilevel inverter (100a; 100A; 100B; 100C; 100D) according to the eleventh aspect which can be implemented in combination with any one of the seventh to tenth aspects, each of the plurality of bootstrap circuits (71a) includes a capacitor (C11), a diode (D11) and a resistor (R11). The diode (D11) is connected in series to the capacitor (C11). The resistor (R11) is connected in series to the capacitor (C11).

[0320] In the multilevel inverter (100a; 100B; 100C; 100D) according to the twelfth aspect which can be implemented in combination with any one of the seventh to eleventh aspects, the power supply unit (9a) includes a single DC-DC converter (91a). The DC-DC converter (91a) supplies voltage to the plurality of second gate drivers (62a) and the plurality of bootstrap circuits (71a).

[0321] This aspect may help reduce the size of the multilevel inverter (100a; 100B; 100C; 100D).

[0322] In a multilevel inverter (100a; 100B; 100C; 100D) according to the thirteenth aspect which can be implemented in combination with any one of the seventh to eleventh aspects, the power supply unit (9a) includes a first DC-DC converter (91) and a plurality of second DC-DC converters (92). The first DC-DC converter (91) supplies voltage to a plurality of second gate drivers (62a) and a plurality of bootstrap circuits (71a). The plurality of second DC-DC converters (92) supply voltage to a plurality of fourth gate drivers (64a).

[0323] This aspect may help reduce the size of the multilevel inverter (100a; 100B; 100C; 100D).

[0324] Description of Reference Numerals

[0325] 1 Inverter circuit

[0326] 3DC Power Supply Unit

[0327] 6 Controller

[0328] 60 Control Unit

[0329] 61 First gate driver

[0330] 62 Second gate driver

[0331] 63 Third gate driver

[0332] 64 Fourth gate driver

[0333] 9 Power supply unit

[0334] 91DC-DC Converter

[0335] 10Switching circuit

[0336] 11First connection node

[0337] 12 Second connection node

[0338] 13 Third connection node

[0339] 71 First bootstrap circuit

[0340] 72 Second bootstrap circuit

[0341] 73 Third bootstrap circuit

[0342] 100 multi-level inverter

[0343] C17, C27, C37 capacitors

[0344] D1 First diode

[0345] D2 Second diode

[0346] D3 The third diode

[0347] D4 Fourth diode

[0348] D5 Fifth diode

[0349] D6 Sixth diode

[0350] D17, D27, D37 diodes

[0351] P1 Positive electrode

[0352] Q1 First switching element

[0353] Q2 Second switching element

[0354] Q3 The third switching element

[0355] Q4 Fourth switching element

[0356] M1 Intermediate potential node

[0357] N1 Negative electrode

[0358] R17, R27, R37 resistors

[0359] Ts control cycle

[0360] V0–V18 voltage vector

[0361] V* command voltage vector

[0362] VV1 First voltage vector

[0363] VV2 Second voltage vector

[0364] 1a Inverter Circuit

[0365] 6a Controller

[0366] 60a Control unit

[0367] 61a First gate driver

[0368] 62a Second gate driver

[0369] 63a Third gate driver

[0370] 64a Fourth gate driver

[0371] 9a Power Supply Unit

[0372] 91a DC-DC converter (first DC-DC converter)

[0373] 92 Second DC-DC converter

[0374] 13a Connection node (output node)

[0375] 71a Bootstrap circuit (first bootstrap circuit)

[0376] 72a Second bootstrap circuit

[0377] 100a,100A,100B,100C,100D multi-level inverter

[0378] C11, C21 capacitors

[0379] D1a First diode

[0380] D2a Second diode

[0381] D3a The third diode

[0382] D4a Fourth diode

[0383] D11, D21 diodes

[0384] Q1a First switching element

[0385] Q2a Second switching element

[0386] Q3a The third switching element

[0387] Q4a Fourth switching element

[0388] R11, R21 resistors

Claims

1. A multilevel inverter, comprising: A DC power supply unit including a positive electrode, a negative electrode, and an intermediate potential node; a plurality of inverter circuits connected between the positive electrode and the negative electrode of the DC power supply unit; as well as a controller configured to control the plurality of inverter circuits, Each inverter circuit of the plurality of inverter circuits comprises: a switching circuit comprising a first switching element, a second switching element, a third switching element and a fourth switching element, wherein the first switching element, the second switching element, the third switching element and the fourth switching element are connected in series in a manner of being arranged in a row from the positive electrode toward the negative electrode in sequence; a first diode connected in anti-parallel to the first switching element; a second diode connected in anti-parallel to the second switching element; a third diode connected in anti-parallel to the third switching element; a fourth diode connected in anti-parallel to the fourth switching element; a fifth diode having a cathode connected to the first connection node between the first switching element and the second switching element, and an anode connected to the intermediate potential node; and a sixth diode having an anode connected to the second connection node between the third switching element and the fourth switching element and a cathode connected to the intermediate potential node, The controller comprises: a plurality of first gate drivers, each of the plurality of first gate drivers being configured to drive the first switching element of a corresponding inverter circuit of the plurality of inverter circuits; a plurality of second gate drivers, each of the plurality of second gate drivers being configured to drive the second switching element of a corresponding inverter circuit of the plurality of inverter circuits; a plurality of third gate drivers, each of the plurality of third gate drivers being configured to drive the third switching element of a corresponding inverter circuit of the plurality of inverter circuits; a plurality of fourth gate drivers, each of the plurality of fourth gate drivers being configured to drive the fourth switching element of a corresponding inverter circuit of the plurality of inverter circuits; a plurality of first bootstrap circuits, which are arranged one-to-one for the plurality of first gate drivers, each of the plurality of first bootstrap circuits being configured to supply a voltage to a corresponding first gate driver of the plurality of first gate drivers; a plurality of second bootstrap circuits, which are arranged one-to-one for the plurality of second gate drivers, each second bootstrap circuit in the plurality of second bootstrap circuits being configured to supply a voltage to a corresponding second gate driver in the plurality of second gate drivers; a plurality of third bootstrap circuits, which are arranged one-to-one for the plurality of third gate drivers, each of the plurality of third bootstrap circuits being configured to supply a voltage to a corresponding third gate driver of the plurality of third gate drivers; a power supply unit configured to supply a voltage to the plurality of fourth gate drivers; and a control unit configured to control the plurality of first gate drivers, the plurality of second gate drivers, the plurality of third gate drivers, and the plurality of fourth gate drivers, the control unit being configured to: selecting a plurality of voltage vectors located adjacent to the command voltage vector from a group of voltage vectors, each voltage vector in the group of voltage vectors being defined by a combination of potential levels at respective third connection nodes, wherein the second switching element and the third switching element are connected to each other at respective third connection nodes in a corresponding inverter circuit among the plurality of inverter circuits; replacing one of two first voltage vectors, which belong to the plurality of voltage vectors, have a reference magnitude, and are located closest to the command voltage vector, with a zero vector and a second voltage vector, the zero vector being defined by a combination of potential levels at respective third connection nodes that are as high as the potential at the negative electrode, wherein the second switching element and the third switching element are connected to each other at respective third connection nodes in a corresponding inverter circuit among the plurality of inverter circuits, the second voltage vector having the same direction as the first voltage vector and having a magnitude twice as large as the first voltage vector; and The plurality of first gate drivers, the plurality of second gate drivers, the plurality of third gate drivers and the plurality of fourth gate drivers are controlled within a predetermined control cycle so that a composite vector of voltage vectors other than the first voltage vector included in the plurality of voltage vectors, the other first voltage vector of the two first voltage vectors, the zero vector and the second voltage vector is equal to the command voltage vector.

2. A multi-level inverter, comprising: A DC power supply unit including a positive electrode, a negative electrode, and an intermediate potential node; a plurality of inverter circuits connected between the positive electrode and the negative electrode of the DC power supply unit; as well as a controller configured to control the plurality of inverter circuits, Each inverter circuit of the plurality of inverter circuits comprises: a switching circuit comprising a first switching element, a second switching element, a third switching element and a fourth switching element, wherein the first switching element, the second switching element, the third switching element and the fourth switching element are connected in series in a manner of being arranged in a row from the positive electrode toward the negative electrode in sequence; a first diode connected in anti-parallel to the first switching element; a second diode connected in anti-parallel to the second switching element; a third diode connected in anti-parallel to the third switching element; a fourth diode connected in anti-parallel to the fourth switching element; a fifth diode having a cathode connected to the first connection node between the first switching element and the second switching element, and an anode connected to the intermediate potential node; and a sixth diode having an anode connected to the second connection node between the third switching element and the fourth switching element and a cathode connected to the intermediate potential node, The controller comprises: a plurality of first gate drivers, each of the plurality of first gate drivers being configured to drive the first switching element of a corresponding inverter circuit of the plurality of inverter circuits; a plurality of second gate drivers, each of the plurality of second gate drivers being configured to drive the second switching element of a corresponding inverter circuit of the plurality of inverter circuits; a plurality of third gate drivers, each of the plurality of third gate drivers being configured to drive the third switching element of a corresponding inverter circuit of the plurality of inverter circuits; a plurality of fourth gate drivers, each of the plurality of fourth gate drivers being configured to drive the fourth switching element of a corresponding inverter circuit of the plurality of inverter circuits; a plurality of first bootstrap circuits, which are arranged one-to-one for the plurality of first gate drivers, each of the plurality of first bootstrap circuits being configured to supply a voltage to a corresponding first gate driver of the plurality of first gate drivers; a plurality of second bootstrap circuits, which are arranged one-to-one for the plurality of second gate drivers, each second bootstrap circuit in the plurality of second bootstrap circuits being configured to supply a voltage to a corresponding second gate driver in the plurality of second gate drivers; a plurality of third bootstrap circuits, which are arranged one-to-one for the plurality of third gate drivers, each of the plurality of third bootstrap circuits being configured to supply a voltage to a corresponding third gate driver of the plurality of third gate drivers; a power supply unit configured to supply a voltage to the plurality of fourth gate drivers; and a control unit configured to control the plurality of first gate drivers, the plurality of second gate drivers, the plurality of third gate drivers, and the plurality of fourth gate drivers, the control unit being configured to: selecting a plurality of voltage vectors located adjacent to the command voltage vector from a group of voltage vectors, each voltage vector in the group of voltage vectors being defined by a combination of potential levels at respective third connection nodes, wherein the second switching element and the third switching element are connected to each other at respective third connection nodes in a corresponding inverter circuit among the plurality of inverter circuits; replacing a first voltage vector with a zero vector, the first voltage vector belonging to the plurality of voltage vectors, having a reference magnitude and being located closest to the command voltage vector, and a second voltage vector, the zero vector being defined by a combination of potential levels at respective third connection nodes being as high as the potential at the negative electrode, wherein the second switching element and the third switching element are connected to each other at respective third connection nodes in a corresponding inverter circuit among the plurality of inverter circuits, the second voltage vector having the same direction as the first voltage vector and having a magnitude twice as large as the first voltage vector; and The plurality of first gate drivers, the plurality of second gate drivers, the plurality of third gate drivers and the plurality of fourth gate drivers are controlled within a predetermined control cycle so that a composite vector of voltage vectors other than the first voltage vector included in the plurality of voltage vectors, the zero vector and the second voltage vector is equal to the command voltage vector.

3. The multilevel inverter according to claim 1 or 2, wherein: The control unit is configured to replace the first voltage vector with the zero vector and the second voltage vector if a polarity of a command voltage corresponding to the command voltage vector is positive.

4. The multilevel inverter according to any one of claims 1 to 3, wherein: The control unit is configured to control the plurality of first gate drivers, the plurality of second gate drivers, the plurality of third gate drivers, and the plurality of fourth gate drivers to prevent an output voltage of each of the plurality of first bootstrap circuits and the plurality of second bootstrap circuits from dropping to a predetermined value or less.

5. The multilevel inverter according to any one of claims 1 to 4, wherein: Each of the plurality of first bootstrap circuits and the plurality of second bootstrap circuits comprises: Capacitors; a diode connected in series to the capacitor; and resistor, which is connected in series to the capacitor.

6. The multilevel inverter according to any one of claims 1 to 5, wherein: The power supply unit includes a DC-DC converter configured to supply a voltage to the plurality of fourth gate drivers and the plurality of third bootstrap circuits.

7. A multilevel inverter, comprising: A DC power supply unit including a positive electrode, a negative electrode, and an intermediate potential node; a plurality of inverter circuits connected between the positive electrode and the negative electrode of the DC power supply unit; as well as a controller configured to control the plurality of inverter circuits, Each inverter circuit of the plurality of inverter circuits comprises: a first switching element, a second switching element, a third switching element, and a fourth switching element; and a first diode, a second diode, a third diode and a fourth diode, which are connected in anti-parallel to the first switching element, the second switching element, the third switching element and the fourth switching element, respectively, In each of the plurality of inverter circuits, the first switching element and the second switching element are connected in series so as to be arranged in a row from the positive electrode toward the negative electrode. In each of the plurality of inverter circuits, a series circuit of the third switching element and the fourth switching element is connected between the intermediate potential node and an output node, In each of the plurality of inverter circuits, the output node is a connection node between the first switching element and the second switching element, The controller comprises: a plurality of first gate drivers, each of the plurality of first gate drivers being configured to drive the first switching element of a corresponding inverter circuit of the plurality of inverter circuits; a plurality of second gate drivers, each of the plurality of second gate drivers being configured to drive the second switching element of a corresponding inverter circuit of the plurality of inverter circuits; a plurality of third gate drivers, each of the plurality of third gate drivers being configured to drive the third switching element of a corresponding inverter circuit of the plurality of inverter circuits; a plurality of fourth gate drivers, each of the plurality of fourth gate drivers being configured to drive the fourth switching element of a corresponding inverter circuit of the plurality of inverter circuits; a plurality of bootstrap circuits, which are arranged one-to-one for the plurality of first gate drivers, each of the plurality of bootstrap circuits being configured to supply a voltage to a corresponding first gate driver of the plurality of first gate drivers; a power supply unit configured to supply voltage to the plurality of second gate drivers and the plurality of third gate drivers; and a control unit configured to control the plurality of first gate drivers, the plurality of second gate drivers, the plurality of third gate drivers, and the plurality of fourth gate drivers, The control unit is configured to: selecting a plurality of voltage vectors located adjacent to the command voltage vector from a group of voltage vectors, each voltage vector in the group of voltage vectors being defined by a combination of potential levels at a plurality of connection nodes of the plurality of inverter circuits; replacing one of two first voltage vectors, the two first voltage vectors belonging to the plurality of voltage vectors, having a reference magnitude and being located closest to the command voltage vector, with a zero vector and a second voltage vector, the zero vector being defined by a combination of potential levels at the plurality of connection nodes of the plurality of inverter circuits being as high as the potential at the negative electrode, the second voltage vector having the same direction as the first voltage vector and having a magnitude twice as large as the first voltage vector; and The plurality of first gate drivers, the plurality of second gate drivers, the plurality of third gate drivers and the plurality of fourth gate drivers are controlled within a predetermined control cycle so that a composite vector of voltage vectors other than the first voltage vector included in the plurality of voltage vectors, the zero vector and the second voltage vector is equal to the command voltage vector.

8. A multilevel inverter, comprising: A DC power supply unit including a positive electrode, a negative electrode, and an intermediate potential node; a plurality of inverter circuits connected between the positive electrode and the negative electrode of the DC power supply unit; as well as a controller configured to control the plurality of inverter circuits, Each inverter circuit of the plurality of inverter circuits comprises: a first switching element, a second switching element, a third switching element, and a fourth switching element; and a first diode, a second diode, a third diode and a fourth diode, which are connected in anti-parallel to the first switching element, the second switching element, the third switching element and the fourth switching element, respectively, In each of the plurality of inverter circuits, the first switching element and the second switching element are connected in series so as to be arranged in a row from the positive electrode toward the negative electrode. In each of the plurality of inverter circuits, a series circuit of the third switching element and the fourth switching element is connected between the intermediate potential node and an output node, In each of the plurality of inverter circuits, the output node is a connection node between the first switching element and the second switching element, The controller comprises: a plurality of first gate drivers, each of the plurality of first gate drivers being configured to drive the first switching element of a corresponding inverter circuit of the plurality of inverter circuits; a plurality of second gate drivers, each of the plurality of second gate drivers being configured to drive the second switching element of a corresponding inverter circuit of the plurality of inverter circuits; a plurality of third gate drivers, each of the plurality of third gate drivers being configured to drive the third switching element of a corresponding inverter circuit of the plurality of inverter circuits; a plurality of fourth gate drivers, each of the plurality of fourth gate drivers being configured to drive the fourth switching element of a corresponding inverter circuit of the plurality of inverter circuits; a plurality of bootstrap circuits, which are arranged one-to-one for the plurality of first gate drivers, each of the plurality of bootstrap circuits being configured to supply a voltage to a corresponding first gate driver of the plurality of first gate drivers; a power supply unit configured to supply voltage to the plurality of second gate drivers and the plurality of third gate drivers; and a control unit configured to control the plurality of first gate drivers, the plurality of second gate drivers, the plurality of third gate drivers, and the plurality of fourth gate drivers, The control unit is configured to: selecting a plurality of voltage vectors located adjacent to the command voltage vector from a group of voltage vectors, each voltage vector in the group of voltage vectors being defined by a combination of potential levels at a plurality of connection nodes of the plurality of inverter circuits; replacing each of two first voltage vectors, the two first voltage vectors belonging to the plurality of voltage vectors, having a reference magnitude and being located closest to the command voltage vector, with a zero vector and a second voltage vector, the zero vector being defined by a combination of potential levels at the plurality of connection nodes of the plurality of inverter circuits being as high as the potential at the negative electrode, the second voltage vector having the same direction as the first voltage vector and having a magnitude twice as large as the first voltage vector; and The plurality of first gate drivers, the plurality of second gate drivers, the plurality of third gate drivers and the plurality of fourth gate drivers are controlled within a predetermined control cycle so that a composite vector of voltage vectors other than the first voltage vector included in the plurality of voltage vectors, the zero vector and the second voltage vector is equal to the command voltage vector.

9. The multilevel inverter according to claim 7 or 8, wherein: The control unit is configured to replace the first voltage vector with the zero vector and the second voltage vector if a polarity of a command voltage corresponding to the command voltage vector is positive.

10. The multilevel inverter according to any one of claims 7 to 9, wherein: The control unit is configured to control the plurality of first gate drivers, the plurality of second gate drivers, the plurality of third gate drivers, and the plurality of fourth gate drivers to prevent output voltages of the plurality of bootstrap circuits from dropping to a predetermined value or less.

11. The multilevel inverter according to any one of claims 7 to 10, wherein: Each of the plurality of bootstrap circuits comprises: Capacitors; a diode connected in series to the capacitor; and resistor, which is connected in series to the capacitor.

12. The multilevel inverter according to any one of claims 7 to 11, wherein: The power supply unit includes a DC-DC converter configured to supply a voltage to the plurality of second gate drivers and the plurality of bootstrap circuits.

13. The multilevel inverter according to any one of claims 7 to 11, wherein: The power supply unit comprises: a first DC-DC converter configured to supply voltage to the plurality of second gate drivers and the plurality of bootstrap circuits; and A plurality of second DC-DC converters are configured to supply voltage to the plurality of fourth gate drivers.

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