Setting performance modes of RF receiver front end

Abstract

Examples relate to setting a performance mode of an RF receiver front end. An exemplary method includes determining a power state of an input signal to an RF receiver front end; and setting a performance mode of the RF receiver front-end to one of at least three different performance modes provided by the RF receiver front-end in response, at least in part, to the determined power state of the input signal.

Description

[0001] Priority declaration

[0002] This application claims the benefit of U.S. Provisional Patent Application Serial No. 63 / 373,171, filed on August 22, 2022, entitled “CHANGING APOWER MODE OF A RECEIVER FRONTEND TO A LOWER POWER MODE IN RESPONSE TO ARADIO FREQUENCY (RF) INPUT SIGNAL LEVEL BELOW A THRESHOLD,” under 35 U.S.C. §119(e), the disclosure of which is hereby incorporated herein by reference in its entirety. Technical Field

[0003] Examples generally relate to receivers and RF receiver front ends. Some examples relate to setting performance of a receiver front end based on an input signal power state. In some examples, the performance includes sensitivity, blocking tolerance, or both. Some examples relate to operating an RF receiver front end in a default lower performance mode until the input signal power state indicates a higher performance mode. Background Art

[0004] Wireless receivers and wired receivers are used for electronic communications in a variety of operating contexts. BRIEF DESCRIPTION OF THE DRAWINGS

[0005] To easily identify the discussion of any particular element or act, the most significant digit(s) in a reference number refers to the figure number in which the element is first introduced.

[0006] Figure 1 is a graph 100 depicting information regarding input signal power and performance modes of an RF receiver according to one or more examples.

[0007] Figure 2 is a block diagram depicting an apparatus including respectively settable performance modes responsive at least in part to input signal power states according to one or more examples.

[0008] Figure 3 is a block diagram of an apparatus for determining performance settings according to one or more examples.

[0009] Figure 4 is a flow chart depicting a process of setting a performance mode of an RF receiver front end based on input signal power conditions according to one or more examples.

[0010] Figure 5is a flow chart depicting a process for operating an RF receiver front end in a default performance mode until an input signal power state indicates a change to a different performance mode according to one or more examples.

[0011] Figure 6 is a flow chart depicting a process of operating an RF receiver front end in a default performance mode when an input signal power state indicates a change from a different higher performance mode according to one or more examples.

[0012] Figure 7 is a flow chart depicting a process of determining an input signal power state of an input signal to an RF receiver front end according to one or more examples.

[0013] Figure 8 is a flowchart depicting a process of setting a performance mode of an RF receiver front end to one of at least three different performance modes provided by the RF receiver front end in response, at least in part, to a determined input signal power state according to one or more examples.

[0014] Fig. 9 is a block diagram depicting a signal processing chain including configurable performance definition blocks according to one or more examples.

[0015] Fig.10 is a block diagram depicting a signal processing chain including bypassing according to one or more examples.

[0016] Fig.11 is a block diagram depicting a control register having fields for storing values ​​of performance-defined settings according to one or more examples.

[0017] Fig.12 are block diagrams of circuit systems that, in some examples, may be used to implement various functions, operations, acts, processes, or methods disclosed herein. DETAILED DESCRIPTION

[0018] In the following detailed description, reference is made to the accompanying drawings which form a part of the present disclosure, and in the accompanying drawings are shown by way of illustration specific examples in which the present disclosure may be practiced. These examples are described in sufficient detail to enable one of ordinary skill in the art to practice the present disclosure. However, other examples may be utilized, and changes in structure, material, and process may be made without departing from the scope of the present disclosure.

[0019] The illustrations presented herein are not intended to be actual views of any particular method, system, device, or structure, but are merely idealized representations used to describe examples of the present disclosure. The drawings presented herein are not necessarily drawn to scale. For the convenience of the reader, similar structures or components in the various drawings may retain the same or similar numbering; however, the similarity of numbering does not mean that the structure or component must be the same in size, composition, configuration, or any other attribute.

[0020] The following description may include examples to help enable a person of ordinary skill in the art to practice the disclosed examples. The use of the terms "exemplary," "such as," and "for example" means that the related description is illustrative, and while the scope of the present disclosure is intended to encompass the examples and legal equivalents, the use of such terms is not intended to limit the examples or the scope of the present disclosure to the specified components, steps, features, functions, etc.

[0021] It should be readily understood that the components of the examples as generally described herein and illustrated in the accompanying drawings may be arranged and designed in a variety of different configurations. Therefore, the following description of various examples is not intended to limit the scope of the present disclosure, but is merely representative of various examples. Although various aspects of the examples may be presented in the accompanying drawings, the drawings are not necessarily drawn to scale unless specifically indicated.

[0022] In addition, the specific implementations shown and described are only examples and should not be understood as the only way to implement the present disclosure, unless otherwise specified herein. Elements, circuits, and functions can be shown in block diagram form so as not to obscure the present disclosure with unnecessary details. On the contrary, the specific implementations shown and described are only exemplary and should not be understood as the only way to implement the present disclosure, unless otherwise specified herein. Additionally, the partitioning of logic between block definitions and individual blocks is an example of a specific implementation. It will be apparent to those of ordinary skill in the art that the present disclosure can be practiced through many other partitioning solutions. In most cases, details about timing considerations, etc. have been omitted, where such details are not required to obtain a complete understanding of the present disclosure and are within the capabilities of those of ordinary skill in the relevant art.

[0023] Those of ordinary skill in the art will appreciate that information and signals may be represented using any of a variety of different technologies and techniques. For clarity of presentation and description, some of the figures may illustrate a signal as a single signal. Those of ordinary skill in the art will appreciate that a signal may represent a signal bus, where the bus may have a variety of bit widths, and that the present disclosure may be implemented on any number of data signals, including a single data signal.

[0024] The various illustrative logic blocks, modules, and circuits described in conjunction with the examples disclosed herein may be implemented or executed with a general purpose processor, a special purpose processor, a digital signal processor (DSP), an integrated circuit (IC), an application specific integrated circuit (ASIC), a field programmable gate array (FPGA) or other programmable logic device, a discrete gate or transistor logic, a discrete hardware component, or any combination thereof designed to perform the functions described herein. A general purpose processor (which may also be referred to herein as a host processor or simply a host) may be a microprocessor, but in an alternative, the processor may be any conventional processor, controller, microcontroller, or state machine. The processor may also be implemented as a combination of computing devices, such as a combination of a DSP and a microprocessor, a plurality of microprocessors, one or more microprocessors combined with a DSP core, or any other such configuration. A general purpose computer including a processor is considered a special purpose computer when the general purpose computer is configured to execute computing instructions (e.g., software code) associated with the examples disclosed herein.

[0025] Examples may be described in terms of processes depicted as flow charts, flow diagrams, structure diagrams, or block diagrams. Although flow charts may describe operable actions as continuous processes, many of these actions may be performed in another sequence, in parallel, or substantially simultaneously. In addition, the order of the actions may be rearranged. A process may correspond to a method, a thread, a function, a procedure, a subroutine, a subprogram, but is not limited thereto. In addition, the methods disclosed herein may be implemented by hardware, software, or both. If implemented in software, a function may be stored or sent to a computer-readable medium as one or more instructions or codes. Computer-readable media include both computer storage media and communication media, which include any media that facilitates transferring a computer program from one location to another.

[0026] Any reference to elements herein using names such as "first," "second," etc. does not limit the quantity or order of those elements unless such limitations are explicitly stated. Rather, these names may be used herein as a convenient method of distinguishing between two or more elements or instances of elements. Thus, reference to a first element and a second element does not mean that only two elements may be employed there, or that the first element must precede the second element in some manner. Furthermore, unless otherwise indicated, a group of elements may include one or more elements.

[0027] As used herein, the term "substantially" in reference to a given parameter, property, or condition refers to and includes the degree to which a person of ordinary skill in the art would understand that the given parameter, property, or condition is satisfied with a small degree of variance, such as, for example, within acceptable manufacturing tolerances. For example, depending on the particular parameter, property, or condition being substantially satisfied, the parameter, property, or condition may be satisfied by at least 90%, at least 95%, or even at least 99%.

[0028] As used herein, any relative terms (such as "above", "below", "on", "below", "upper", "lower", but not limited to) are used for clarity and convenience in understanding the present disclosure and the drawings, and do not imply or depend on any particular preference, orientation, or order unless the context clearly indicates otherwise.

[0029] In this description, the term "coupled" and its derivatives may be used to indicate that two elements cooperate or interact with each other. When an element is described as being "coupled" to another element, then the elements may be in direct physical or electrical contact, or there may be intervening elements or layers. In contrast, when an element is described as being "directly coupled" to another element, then there are no intervening elements or layers. The term "connected" may be used interchangeably with the term "coupled" in this specification and have the same meaning, unless otherwise expressly indicated or the context would indicate otherwise to one of ordinary skill in the art.

[0030] The sensitivity of a receiver is the threshold level at which the receiver reliably detects a signal. In the case of an RF receiver, the sensitivity is the threshold level at which the RF receiver reliably detects an RF signal. Sensitivity defines the lowest signal strength (typically measured in decibels relative to milliwatts (dBm)) that the RF receiver should be able to reliably detect and process. The sensitivity of an RF receiver depends on various signal processing blocks of the signal processing chain of the RF receiver, including, as non-limiting examples: filtering, amplification, and other signal processing. The sensitivity-defining parameters of such operations may be set and changed, including but not limited to during operation, and thus the sensitivity of the RF receiver may be set or changed, including but not limited to during operation. A particular configuration of sensitivity settings is referred to herein as a "sensitivity mode" of the RF receiver. The exemplary RF receivers discussed herein may provide a plurality of sensitivity modes, each associated with a predetermined sensitivity setting.

[0031] "Blocking power" is the interference amplitude of an interfering signal (a signal other than the target signal / signal of interest), such interfering signals are also referred to herein as "blocking signals." Interference is the degree to which a blocking signal degrades the reception of the target signal. In the context of an RF receiver, "blocking tolerance" refers to the interference amplitude that the RF receiver can reliably tolerate (e.g., filter out, but not limited to) without significantly degrading performance. Blocking tolerance is based at least in part on the filter bandwidth of the RF receiver, and thus filter bandwidth is a non-limiting example of a blocking tolerance definition parameter. A specific configuration of blocking tolerance is referred to herein as a "blocking tolerance mode" of the RF receiver. The exemplary RF receivers discussed herein may provide multiple blocking tolerance modes.

[0032] The blocking tolerance and sensitivity of an RF receiver are collectively referred to herein as the "performance" of the RF receiver, and the blocking tolerance mode and the sensitivity mode are collectively referred to herein as the "performance mode."

[0033] A typical radio frequency (RF) receiver (such as for RF receivers for communications (including, but not limited to, RF receivers for wireless communications) are configured to operate at their highest sensitivity, blocking tolerance, or both across a wide input signal power range. However, in real-world scenarios, RF receivers encounter a narrower band of input signal levels. By assigning probability curves for the entire operating range of the RF receiver, it is apparent that most of the increased sensitivity, blocking tolerance, or both are over-designed for commonly encountered input signal levels.

[0034] The probability curve of the RF receiver exhibits a significant peak corresponding to the input signal level of the narrow band commonly encountered. The probability drops sharply on both sides of the peak. The probability curve exhibits a significant peak at a medium input signal level that does not require the highest performance setting (e.g., sensitivity setting, blocking tolerance setting, or both, but not limited to this), so the medium performance setting should be sufficient in theory. Using the medium performance setting meets the requirements of the input signal and uses less power than the highest performance setting.

[0035] One or more examples relate to an RF receiver front end and an RF receiver including the RF receiver front end, the RF receiver operating at a medium performance setting, optionally by default, switching to a higher or maximum performance setting only when the input signal requires it, and switching to a lower or minimum performance setting when the input signal allows it. "Default" refers to a preset value that the RF receiver front end will use in the absence of any other instructions. In one or more examples, the default performance mode setting can be used when the device is first powered on or when no other specific performance setting is selected (e.g., by a user or application layer, but not limited to this).

[0036] Although some exemplary RF receiver front ends discussed herein provide three different performance modes (e.g., minimum, medium, and maximum, but not limited thereto), the scope of the present disclosure is not limited to providing only three sensitivity modes, and more than three modes are specifically contemplated. Furthermore, sensitivity adjustment is not limited to three or more different modes. One or more examples relate to an RF receiver that provides continuous sensitivity adjustment, thereby seamlessly adjusting in response to input signal power conditions.

[0037] Figure 1 1 is a graph 100 depicting information regarding input signal power and sensitivity patterns of an RF receiver according to one or more examples. Graph 100 includes an x-axis, a y-axis, a line 102, a line 104, a line 106, and a line 108.

[0038] The y-axis of the graph corresponds to input signal power, with the values ​​of input signal level increasing from the bottom to the top of the y-axis. In this example, the input signal power range of the RF receiver (also referred to as the "dynamic range" of the RF receiver) is defined at SP o and SP 2 Signal power is expressed in decibels relative to milliwatts (dBm). Several intermediate signal power levels are depicted on the right side of the page, i.e. dBm 1 and dBm 2 , and will be discussed below.

[0039] The positive side of the x-axis corresponds to the blocking power, which increases from left to right. Sub-ranges of blocking power that the RF receiver can tolerate in a particular performance mode are also identified (represented by lines 104, 106, and 108, as described below). "Blocking power" is the interference amplitude of an interfering signal (a signal other than the target signal). Interference is the degree to which an interfering signal reduces the reception of the target signal. In the context of an RF receiver front end, "blocking power" is used to refer to the interference amplitude that the RF receiver front end can reliably tolerate (e.g., filter out, but not limited to) without significantly degrading performance. The negative side of the x-axis corresponds to the receiver (RX) current, which increases from right to left. Rectangular boxes are depicted adjacent to the y-axis, each of which is vertically aligned with the negative side of the x-axis to indicate the power consumption (here, given as current consumption) of the corresponding performance mode.

[0040] Line 102 is a curve representing the probability that an RF receiver front end (or more generally, an RF receiver) will encounter a given input signal level on the y-axis. For a given input signal level on the y-axis, a point on line 102 that is horizontally aligned with the given input signal level corresponds to the probability that the given input signal level will be encountered. The greater the distance between a point on line 102 and the y-axis, the higher the probability. For example, point 110 is closer to the y-axis than point 112, and thus the probability curve represented by line 102 indicates that the probability of encountering the input signal level associated with point 110 is lower than the probability of encountering the input signal level associated with point 112 (much lower in this example).

[0041] Although Figure 1 Only a single probability curve is depicted, but probability curves representing the probability of encountering a target signal for a given signal level are available, and probability curves representing the probability of encountering a blocking signal for a given signal level are available.The probability curve represented by line 102 is the probability of encountering a target signal for a given signal level.

[0042] Lines 104, 106, and 108 represent signal power ranges and blocking power ranges for three exemplary different performance modes of the RF receiver front end. As described below, the respective performance modes may be characterized by different filter bandwidths, gains, DC bias current levels, and clock rates, which are selected to balance sensitivity, blocking tolerance, or both, with power consumption.

[0043] Line 104 represents the signal power SP 2 performance mode for which the highest sensitivity setting meets the requirements for the target signal and for less than the blocking power BP 0 In this example, line 104 indicates that the highest sensitivity setting will meet the full dynamic range requirements of the RF receiver front end, and at the blocking power BP 0 and lower to provide suitable blocking tolerance.

[0044] As mentioned above, not all input signal levels require the highest sensitivity or blocking tolerance. Line 106 represents the sensitivity applicable to signals below the signal power SP 2 and greater than the signal power SP 0 performance mode for signal power below the blocking power BP 1 In this example, the sensitivity setting associated with the performance mode represented by line 106 will satisfy the requirement of having a signal power greater than SP 0 Line 108 represents the requirement for the target signal with a signal power less than SP 2 and greater than the signal power SP1, and for a performance mode with a signal power less than BP 2 In this example, the sensitivity setting associated with the mode represented by line 108 will satisfy the requirement of having a signal power greater than SP 1 The signal power requirement of the target signal.

[0045] The dynamic range of the RF receiver front end is subdivided into specific (different) signal power sub-ranges or 'power states' of the target signal. The corresponding power states correspond to the corresponding performance modes. In one or more examples, the performance mode may be associated with a sensitivity mode, a blocking tolerance mode, or both a sensitivity mode and a blocking tolerance mode. The sensitivity mode may be associated with a sensitivity setting. The blocking tolerance mode may be associated with a blocking tolerance setting. The performance setting may be associated with a sensitivity setting, a blocking tolerance setting, or both a sensitivity setting and a blocking tolerance setting. The performance mode should reliably provide the associated performance setting. The sensitivity setting associated with the performance mode may be determined based on the highest sensitivity required for the range of target signal power levels within one or more power states utilized by the sensitivity mode. The blocking tolerance setting associated with the performance mode may be determined based on the highest blocking tolerance required for the range of blocking signal power levels within one or more power states utilized by the blocking tolerance mode.

[0046] In one or more examples, input signal power subranges (e.g., target signal power subranges and blocking signal power subranges, but not limited thereto) may be determined based at least in part on the probability of the RF receiver front end encountering signals within these subranges. The probability may be defined by a probability curve, such as, but not limited to, the probability curve represented by line 102. The probability curve may be determined using any suitable technique, including, as non-limiting examples, by observing the power state of the input signal in an environment representing operating conditions that the RF receiver front end may use; or using a public or private database that includes information about input signal power levels (e.g., target signal power levels and blocking signal power levels, but not limited thereto) that may be encountered in various environments, and includes probability information or information based on which the probability information may be determined.

[0047] In one or more examples, probability information and other relevant information or criteria may be used to determine thresholds that define input signal power subranges and, therefore, power states. As a non-limiting example, a cost function may be used that is intended to minimize the potential cost of failing to meet the required sensitivity and maximize the potential reward of reducing the power consumption of the RF receiver front end. Such cost functions may be weighted by the probability of encountering a signal within the corresponding subrange. In this way, the value of the threshold defining the power state may be affected by the probability information. The value of the threshold is determined at least in part based on probability information (such as, but not limited to, the probability of encountering an input signal (target signal, blocking signal, or both) with a specific power level), or may be referred to herein as a "probability-based determination", and such thresholds may be referred to herein as "probability-based thresholds".

[0048] As another non-limiting example, a calibration process may be utilized that scans a range of input signal powers (e.g., corresponding to the dynamic range of the RF receiver front end) for a corresponding performance mode (sensitivity mode, blocking tolerance mode, or both) provided by the RF receiver front end, observes the error rate exhibited by the range of input signal powers for the corresponding performance mode, and sets a threshold value such that a minimum error rate is exhibited for a sub-range of input power levels associated with the corresponding performance mode, and reduces or eliminates error rate peaks when transitioning between performance modes (e.g., such that they may be negligible or non-existent, but is not limited to such).

[0049] In one or more examples, various operating conditions may affect one or more of the following: a desired sensitivity for an input signal, a desired tolerance for blocking of an input signal, a range of input signal power levels for which a given performance mode is sufficient, or a probability of encountering a particular input signal power level. As non-limiting examples, the probability of encountering a particular input signal power level may include a probability of encountering a target signal having a particular power level, a probability of encountering a blocking signal having a particular blocking power, or both.

[0050] Non-limiting examples of operating conditions include modes provided by the RF receiver front end in addition to the performance modes and environmental conditions discussed herein. Environmental conditions include, but are not limited to, ambient temperature, altitude (e.g., atmospheric pressure affects the propagation characteristics of RF signals in the air, but is not limited to this), humidity (e.g., humidity levels can cause signal attenuation, but is not limited to this), terrain and physical obstacles (e.g., buildings, mountains, trees, but are not limited to this, which cause, for example, reflection of RF signals, diffraction of RF signals, absorption of RF signals, but are not limited to this), the presence of blocking signals (e.g., an environment full of RF sources, but is not limited to this), crowded (e.g., many transmitters, but are not limited to this) frequency bands, the distance between the receiver and the transmitter, the dynamic range of the input signal (e.g., a mixture of strong and weak input signals, but is not limited to this), the mobility of the RF receiver or device including the RF receiver front end, atmospheric conditions (e.g., weather, but is not limited to this), or combinations and sub-combinations thereof, but are not limited to this.

[0051] The operating condition may be indicated via various means, such as via a global setting for setting, indicating, or both, other modes (in addition to the performance modes described above) at the RF receiver front end, or via environmental conditions, but not limited thereto. In one or more examples, the global setting may be set at an application layer of a receiver or a device including the receiver. The global setting may be set by a user based on environmental conditions or both, but not limited thereto. Non-limiting examples of other modes of the RF receiver front end set via the global setting include: short range mode, long range mode, low power mode, high power mode, or congestion tolerance mode. "Short range mode" is an operating mode specifically designed for receiving signals at a relatively short distance (e.g., for specific applications involving receiving signals at a relatively short distance, but not limited thereto). "Long range mode" is an operating mode specifically designed for receiving signals at a relatively long distance (e.g., for specific applications involving receiving signals at a relatively long distance, but not limited thereto). "Low power mode" is an operating mode specifically designed to consume a relatively small amount (e.g., a minimum amount, but not limited to) of power (e.g., for specific applications where power resources are limited, extending the battery life of the device is a priority, or maintaining the working life of the device is a priority, or a combination or sub-combination thereof, but not limited to this). "High power mode" is an operating mode specifically designed to provide the highest sensitivity (e.g., for specific applications where sensitivity is a priority, but not limited to this). "Congestion tolerance mode" is an operating mode specifically designed to provide the highest congestion tolerance (e.g., for specific applications where congestion tolerance is a priority, but not limited to this).

[0052] In one or more examples, an environmental state is information about one or more environmental conditions. Such information may include, but is not limited to, a value representing an environmental condition, an indication of an environmental condition, or statistical information. Non-limiting examples of values ​​representing environmental conditions include: temperature values, humidity values, altitude values, distance values. Non-limiting examples of indications of environmental conditions include, but are not limited to, an indication generated by a logic circuit that determines (or detects the presence of) a particular environmental condition (such as temperature, altitude, humidity, frequency band congestion, or the presence of a physical obstacle) is greater than a predetermined threshold, or is set by a user to indicate that a predetermined environmental condition (such as temperature, altitude, humidity, frequency band congestion, or the presence of a physical obstacle) (regardless of whether such environmental condition actually exists) is greater than a predetermined threshold.

[0053] Statistical information is information about or used to determine the impact of an environmental condition (or the cumulative effect of multiple environmental conditions) on the transmitted RF signal, the reception of the RF signal, or both. As a non-limiting example, the statistical information may include information about or used to determine the suitability of the noise or environment of the environment for the transmission of RF signals, the reception of RF signals, or both at any frequency, at a specific frequency, or at a specific frequency range or band. The statistical information may be provided by a user or dynamically determined (for example, by a digital signal processor (DSP) of an RF receiver front end (for example, a DSP or other DSP that implements an automatic radio controller (discussed below), but not limited thereto) or an RF receiver or device that includes the RF receiver front end, but not limited thereto). Non-limiting examples of statistical information include: packet error rate (PER), received signal strength indicator (RSSI), interference level frequency range A, interference level frequency range B, or combinations and sub-combinations thereof. Range A and range B are different predetermined frequency ranges. Determining interference on less than or more than two frequency ranges does not exceed the scope of the present disclosure.

[0054] In one or more examples, various parameters used to determine power states, thresholds, and sensitivity settings can be based at least in part on operating conditions of the RF receiver front end, including the global settings or environmental conditions discussed above.

[0055] As non-limiting examples, one or more of an input signal power range, a probability curve, a required sensitivity for a given power level, and a required blocking tolerance for the RF receiver front end may be based at least in part on a set of predetermined operating conditions for the RF receiver front end.

[0056] As a non-limiting example, the indicated operating conditions may be associated with scenarios requiring lower or higher sensitivity or blockage tolerance than average operating conditions. Thus, to account for a higher probability of encountering a signal requiring higher sensitivity or blockage tolerance, the probability curves used to determine thresholds, sub-ranges, power states, sensitivity settings, and blockage tolerance settings may exhibit peaks that are shifted downward or widened relative to probability curves representing average operating conditions.

[0057] In one or more examples, corresponding parameter groups, such as thresholds, sub-ranges, power states, sensitivity settings, and blocking tolerance settings, may be determined for corresponding operating conditions in the set of predetermined operating conditions of the RF receiver front end, but are not limited thereto. These corresponding parameter groups and their associations with the corresponding predetermined operating conditions of the RF receiver front end may be stored, for example, in a non-volatile memory. Reference to a particular parameter group in the corresponding parameter groups may be based at least in part on an indication of an operating condition, an input signal power level, or both. A set of parameters associated with an indication of an operating condition may be selected. As discussed herein, information in the selected parameter group may be used to determine an input signal power state, a sensitivity setting, or a blocking tolerance setting.

[0058] One or more examples relate to an RF receiver front end that provides at least three performance modes. The three performance modes provide different performance settings, including different sensitivity settings, blocking tolerance settings, or both. The RF receiver front end may operate (optionally by default) in a performance mode that is lower (in terms of performance settings) than the highest performance mode provided by the RF receiver front end. In one or more examples, the RF receiver front end sets the performance mode at least in part in response to the power state of an input signal to the RF receiver front end. For example, the RF receiver front end changes to a higher performance mode (i.e., providing higher sensitivity, higher blocking tolerance, or both than the current performance mode, but not limited thereto) in response to the power state of the input signal indicating it, and changes to a lower performance mode (i.e., providing lower sensitivity, lower blocking tolerance, or both than the current performance mode, but not limited thereto) in response to the power state of the input signal indicating it.

[0059] The logic circuit determines a power state of the input signal and sets a performance mode of the RF receiver front end at least in part in response to the determined input signal power state. In one or more examples, the logic circuit determines the input signal power state and dynamically determines a performance setting (e.g., a sensitivity setting, a blocking tolerance setting, or both, but not limited thereto) based at least in part on the determined input signal power state. The logic circuit provides the performance setting to the automatic radio controller. The automatic radio controller determines parameter values ​​defining the sensitivity, blocking tolerance, or both of the RF receiver based on the performance setting, and provides the performance definition parameters to the signal processing chain of the RF receiver to set the performance mode.

[0060] Figure 2 2 is a block diagram depicting an apparatus 200 including performance modes that are respectively settable at least in part in response to input signal power conditions, according to one or more examples. The apparatus 200 may also be referred to herein as an RF receiver front end 200.

[0061] The device 200 includes a signal processing chain 202 , an automatic radio controller 206 , and logic circuitry 208 .

[0062] Signal processing chain 202 is a series of signal processing blocks that transforms input signal 210 into output signal 212 in a form suitable for further processing or output. Input signal 210 may include a target signal and may optionally include a blocking signal.

[0063] As a non-limiting example, a particular signal processing block of the signal processing chain 202 may be selected based at least in part on a particular operating condition. As a non-limiting example, the signal processing chain 202 includes Fig. 9 and Fig.10In response to the performance definition settings 216, the signal processing chain 202 can assume at least three different performance modes 204, and the RF receiver front end 200 and the RF receiver including the RF receiver front end can be understood as providing at least three different performance modes 204 that the signal processing chain 202 can assume. The corresponding performance mode provides a corresponding sensitivity setting, blocking tolerance, or sensitivity setting and blocking tolerance.

[0064] The automatic radio controller 206 is a logic circuit, or software, or a combination thereof that determines performance definition settings 216 for the signal processing chain 202. In general, the automatic radio controller 206 determines corresponding performance definition settings 216 for corresponding blocks of the signal processing chain 202 to balance performance (e.g., sensitivity, blocking tolerance, or both, but not limited thereto) and power consumption. The automatic radio controller 206 observes the performance of the signal processing chain 202 and attempts to match the observed performance with a target performance by controlling various settings of the signal processing chain 202 or its blocks through the performance definition settings 216. In one or more examples, the target performance that the automatic radio controller 206 uses to determine the performance definition settings 216 is based at least in part on the performance settings 214 provided by the logic circuit 208. The performance definition settings 216 may include one or more of gain, DC bias current, filter bandwidth, or clock rate.

[0065] The logic circuit 208 receives the input signal 210 and specifies the performance setting 214 in response thereto, at least in part. The logic circuit 208 determines an input signal power state of the input signal 210 and determines the performance setting 214 based at least in part on the determined input signal power state. The logic circuit 208 specifies one of three different performance modes by providing the performance setting 214 in response to at least in part the input signal power state, the performance setting corresponding to one of the three different performance modes.

[0066] As discussed above, the determined input signal power states of the input signal 210 may correspond to different input signal power sub-ranges. For example, a first input signal power sub-range may include input signal levels requiring a highest sensitivity setting, a lowest blocking tolerance setting, or both, a second input signal power sub-range may include input signal levels requiring a medium sensitivity setting, a blocking tolerance setting, or both, and a third input signal power sub-range may include input signal levels requiring a lowest sensitivity setting, a highest blocking tolerance setting, or both. Information regarding input signal power states, input signal power sub-ranges, thresholds associated with these sub-ranges, and associations with performance settings corresponding to performance modes may be stored in a memory of the logic circuit 208 (memory not shown) or configured at the logic circuit 208 (e.g., implemented in a combinational logic circuit of the logic circuit 208). In one or more examples, the information about performance settings and performance modes stored in a memory of logic circuit 208 or configured at logic circuit 208 may include information about a sensitivity setting corresponding to a sensitivity mode of the performance mode, information about a congestion tolerance setting corresponding to a congestion tolerance mode of the performance mode, or information about both the sensitivity setting and the congestion tolerance setting corresponding to the performance mode, as the case may be.

[0067] The value of the performance setting pre-associated with a particular power state of the input signal 210 may be provided at logic circuit 208. As non-limiting examples, the pre-association may be in the form of a lookup table (LUT), a rules engine, or a function that relates the value of the performance setting to the input signal power state.

[0068] Figure 3 is a block diagram of an apparatus 300 for determining performance settings according to one or more examples. Logic circuit 302 is Figure 2 Non-limiting example of logic circuit 208.

[0069] Logic circuit 302 includes input signal power state definition 304 and performance setting definition 308. Input signal power state definition 304 includes conditions or criteria discussed herein for determining an input signal power state based on input signal power level 306. Input signal power state definition 304 may include one or more probability-based thresholds discussed herein.

[0070] The performance setting definitions 308 include sensitivity setting definitions 314, blocking tolerance setting definitions 316, and associations of respective performance settings (or modes) with respective input signal power states. The sensitivity setting definitions 314 include sensitivity settings for respective sensitivity modes for respective performance modes of the RF receiver front end, and also include associations of respective sensitivity modes with respective input signal power states included in the input signal power state definitions 304. The blocking tolerance setting definitions 316 include blocking tolerance settings for respective blocking tolerance modes for respective performance modes of the RF receiver front end, and also include associations of respective blocking tolerance modes with respective input signal power states.

[0071] In one or more examples, logic circuit 302 determines an input signal power state based on input signal power level 306 and input signal power state definition 304 , and determines performance setting 312 based at least in part on the determined input signal power state and performance setting definition 308 .

[0072] As discussed above, operating conditions can affect input signal power states and corresponding associated performance settings. In one or more examples, logic circuit 302 optionally receives an indication of operating condition 310, which includes information about one or more operating conditions described above. In one or more examples, the indication of operating condition 310 may indicate or include an indication of a global setting or an environmental state. In one or more examples, the source of the indication of operating condition 310 may be an application layer or a DSP of an RF receiver front end or an RF receiver including the RF receiver front end, but is not limited thereto. In one or more examples, the indication of operating condition 310 may indicate or include an indication of power on, power-on reset, or reset.

[0073] Input signal power state definitions 304 may include one or more sets of input signal power state definitions associated with corresponding one or more predetermined operating conditions. The definitions may include information about power states, input signal power levels associated with the power states, and thresholds associated with a first set of input signal power definitions associated with a first operating condition in the operating conditions may be different from thresholds associated with a second set of input signal power definitions associated with a second operating condition in the operating conditions. Performance setting definitions 308 may include one or more sets of performance setting definitions associated with one or more operating conditions, respectively. The performance settings and associated power states in the first set of performance setting definitions 308 associated with the first operating condition may be different from those in the second set of performance setting definitions 308 associated with the second operating condition.

[0074] In one or more examples, logic circuit 302 selects one of the sets of input signal power state definitions 304 and one of the sets of sensitivity setting definitions 314 based at least in part on an indication of operating condition 310, and determines input signal power state and performance setting 312 based at least in part on the selected set.

[0075] It should be noted that providing an indication of operating condition 310 to logic circuit 302 or utilizing the indication of operating condition 310 by the logic circuit is optional. In one or more examples, logic circuit 302 can determine performance setting 312 with or without considering operating condition. As a non-limiting example, operating condition can include high sensitivity or congestion tolerance mode set at the application layer by global setting, however, logic circuit 302 can determine performance setting 312 corresponding to medium performance mode at power-on as a default setting.

[0076] Figure 4 4 is a flow chart depicting a process 400 of setting a performance mode of an RF receiver front end at least in part in response to an input signal power state according to one or more examples. As non-limiting examples, some or all of the operations of process 400 may be performed by apparatus 200 or apparatus 300.

[0077] Although the example process 400 depicts a particular order of operations, this order may be changed without departing from the scope of the present disclosure. For example, some of the operations depicted may be performed in parallel or in a different order without materially affecting the functionality of the process 400. In other examples, different components of an example device or system implementing the process 400 may perform functions substantially simultaneously or in a particular order.

[0078] In one or more examples, process 400 includes determining an input signal power state, which is an input signal power state of an input signal to an RF receiver front end, at operation 402. The input signal may include a target signal, a blocking signal, or both, but is not limited thereto.

[0079] In one or more examples, process 400 includes, at operation 404 , setting a performance mode of the RF receiver front end to one of at least three different performance modes provided by the RF receiver front end in response at least in part to the determined input signal power state.

[0080] Figure 5 is a flow chart depicting a process 500 for operating an RF receiver front end in a default performance mode until an input signal power state indicates a change to a different performance mode according to one or more examples. As non-limiting examples, some or all of the operations of process 500 may be performed by apparatus 200 or apparatus 300.

[0081] Although the example process 500 depicts a particular order of operations, this order may be changed without departing from the scope of the present disclosure. For example, some of the operations depicted may be performed in parallel or in a different order without materially affecting the functionality of the process 500. In other examples, different components of the example device or system implementing the process 500 may perform functions substantially simultaneously or in a particular order.

[0082] In one or more examples, process 500 includes setting a performance mode of a radio frequency (RF) receiver front end to a default performance mode at operation 502. The performance setting associated with the default performance mode is lower than the performance setting associated with another performance mode provided by the RF receiver front end. In one or more examples, the other performance modes provided by the RF receiver front end may include a performance mode associated with a higher performance setting than the default performance mode, and may include a performance mode associated with a lower performance setting than the default performance mode. In one or more examples, process 500 may set the performance mode of the RF receiver front end to the default performance mode at least in part in response to an indication of power on, power-on reset, or reset. In one or more examples, process 500 may set the performance mode of the RF receiver front end to the default performance mode at least in part in response to both: an indication of power on, power-on reset, or reset, and determining that there is no instruction to use a particular performance mode or performance setting (e.g., the absence of an instruction, but not limited to this). In one or more examples, process 500 may set the performance mode of the RF receiver front end to the default performance mode regardless of an instruction to use a higher performance mode. In one or more examples, process 500 can set the performance mode of the RF receiver front end to a default performance mode in response to an indication of power on, power on reset, or reset, regardless of an instruction to use a higher performance mode or an indication of operating conditions associated with a higher performance setting.

[0083] In one or more examples, process 500 includes determining an input signal power state, which is an input signal power state of an input signal to an RF receiver front end, at operation 504. The input signal may include a target signal, a blocking signal, or both, but is not limited thereto.

[0084] In one or more examples, process 500 includes setting the performance mode of the RF receiver front end to one of the additional performance modes provided by the RF receiver front end, at least in part in response to the determined input signal power state, at operation 506. In one or more examples, one of the additional performance modes provided by the RF receiver front end can be a higher performance mode, i.e., associated with a higher performance setting than a performance setting associated with a default performance mode.

[0085] Figure 6 6 is a flow chart depicting a process 600 of operating an RF receiver front end in a default performance mode when an input signal power state indicates a change from a different higher performance mode according to one or more examples. As non-limiting examples, some or all of the operations of process 500 may be performed by apparatus 200 or apparatus 300.

[0086] Although the example process 600 depicts a particular order of operations, this order may be changed without departing from the scope of the present disclosure. For example, some of the operations depicted may be performed in parallel or in a different order without materially affecting the functionality of the process 600. In other examples, different components of the example device or system implementing the process 600 may perform functions substantially simultaneously or in a particular order.

[0087] In one or more examples, process 600 includes setting a performance mode of a radio frequency (RF) receiver front end to a higher performance mode at operation 602. The higher performance mode can be associated with a higher performance setting than a default performance mode. Other performance modes provided by the RF receiver front end can include a performance mode associated with a lower performance setting than the default performance mode and the higher performance mode.

[0088] In one or more examples, process 600 includes determining an input signal power state, which is an input signal power state of an input signal to an RF receiver front end, at operation 604. The input signal may include a target signal, a blocking signal, or both, but is not limited thereto.

[0089] In one or more examples, process 600 includes, at operation 606, setting the performance mode of the RF receiver front end to a default performance mode, at least in part in response to the determined input signal power state. The performance setting associated with the default performance mode is lower than the performance setting associated with the higher (previous) performance mode. In this way, the RF receiver front end operates only in the higher performance mode (higher than the default performance mode) until the input signal power state indicates that the higher performance mode is not needed (or no longer indicates that the higher performance mode is needed), and then changes to the default performance mode. In one or more examples, the performance mode of the RF receiver front end can be set to the default performance mode by asserting a reset signal at an input of a logic circuit (e.g., logic circuit 208 or logic circuit 302, but not limited thereto), by providing a performance setting associated with the default performance setting, or by both.

[0090] In one or more examples, process 600 can set the performance mode of the RF receiver front end to a default performance mode in response, at least in part, to the determined input signal power state and determining that there is no instruction (e.g., the absence of an instruction) to use a particular performance mode or performance setting. In one or more examples, process 600 can set the performance mode of the RF receiver front end to the default performance mode regardless of an instruction to utilize a higher performance mode or an indication of an operating condition associated with a higher performance setting.

[0091] Figure 7 5 is a flowchart depicting a process 700 of determining an input signal power state of an input signal to an RF receiver front end according to one or more examples. As non-limiting examples, some or all of the operations of process 500 may be performed by apparatus 200 or apparatus 300.

[0092] Although the example process 700 depicts a particular order of operations, this order may be changed without departing from the scope of the present disclosure. For example, some of the operations depicted may be performed in parallel or in a different order without materially affecting the functionality of the process 700. In other examples, different components of an example device or system implementing the process 700 may perform functions substantially simultaneously or in a particular order.

[0093] In one or more examples, process 700 includes obtaining a value representing a power level of an input signal to an RF receiver front end at operation 702 .

[0094] In one or more examples, process 700 optionally includes: selecting one or more thresholds based at least in part on the indication of the operating condition, the one or more thresholds being probability-based thresholds, at operation 704. In one or more examples, the indication of the RF receiver front end mode can be a global setting set by a user at an application layer or set based on environmental conditions.

[0095] In one or more examples, process 700 includes comparing the value representing the power level to one or more thresholds at operation 706 , the one or more thresholds being probability-based thresholds.

[0096] In one or more examples, process 700 includes determining an input signal power state at least in part in response to the comparison at operation 708 .

[0097] Figure 88 is a flowchart depicting a process 800 of setting a performance mode of an RF receiver front end to one of at least three different performance modes provided by the RF receiver front end in response, at least in part, to a determined input signal power state according to one or more examples. As non-limiting examples, some or all of the operations of process 800 may be performed by apparatus 200 or apparatus 300.

[0098] Although the example process 800 depicts a particular order of operations, this order may be changed without departing from the scope of the present disclosure. For example, some of the operations depicted may be performed in parallel or in a different order without materially affecting the functionality of the process 800. In other examples, different components of the example device or system implementing the process 800 may perform functions substantially simultaneously or in a particular order.

[0099] In one or more examples, process 800 includes obtaining an input signal power state, at operation 802, which is an input signal power state of an input signal to an RF receiver front end.

[0100] In one or more examples, process 800 includes determining a performance setting based at least in part on an input signal power state at operation 804 , the determined performance setting being associated with a performance mode that is one of at least three performance modes provided by the RF receiver front end.

[0101] According to one or more examples, at operation 806 , process 800 optionally includes determining that the performance setting is a sensitivity setting or a blocking tolerance setting.

[0102] In one or more examples, process 800 includes determining performance-defining settings based at least in part on the determined performance settings at operation 808. In one or more examples, the performance-defining settings include sensitivity-defining settings, congestion tolerance-defining settings, or both sensitivity-defining settings and congestion tolerance-defining settings.

[0103] In one or more examples, process 800 optionally includes, at operation 810 , a performance definition sets a gain, a direct current (DC) bias current, a filter bandwidth, or a clock rate of a performance definition block for a signal processing chain of an RF receiver front end.

[0104] In one or more examples, process 800 includes applying the determined performance-defined settings to the RF receiver front end at operation 812. Applying the determined performance-defined settings to the RF receiver front end may include setting corresponding knobs of one or more blocks of a signal processing chain of the RF receiver front end (e.g., knobs set via fields of a control register such as control register 1100, but not limited thereto). Setting the knobs to the values ​​of the determined performance-defined settings sets the performance of the RF receiver front end to the performance settings.

[0105] Any suitable technique may be used to set the performance mode or performance of the signal processing chain. In one or more examples, Fig.11 As shown, the performance mode or performance is set via a register ("control register"). The value stored in the field of the control register sets a specific performance that defines the characteristics of the signal processing chain.

[0106] Fig. 9 is a block diagram depicting a signal processing chain 900 including a configurable performance definition block (discussed below) according to one or more examples. The signal processing chain 900 is Figure 2 . Non-limiting example of a signal processing chain 202 .

[0107] In one or more examples, the corresponding performance definition block of the signal processing chain 900 can be directly settable, indirectly settable, or both. If directly settable, the control register (e.g., Fig.11 The bits at the control register 1100 (but not limited thereto) directly set the parameters of the corresponding performance definition block. If it can be set indirectly, directly setting the parameters of another performance definition block via the bits of the control register will affect the performance definition block.

[0108] Examples of parameters of the respective blocks of the signal processing chain 900 that affect performance include: power consumption, gain, direct current (DC) bias, filter bandwidth, and clock rate.

[0109] For each of these performance defining parameters, arc defines a performance value, ie, filter rejection range, gain amount.

[0110] Current consumption is the amount of receiver current the block consumes. Gain is a measure of how much the block amplifies or attenuates the signal it is operating on. Bias is the direct current (DC) operating point current of the block, and bias is the DC level.

[0111] The signal processing chain 900 includes an antenna 902 , a low noise amplifier (LNA) 904 , a mixer 906 , a baseband amplifier (BB) 908 , a transimpedance amplifier (TIA) 910 , an analog-to-digital converter (ADC) 912 , an automatic radio controller (ARC) 914 , and a signal level detector 916 .

[0112] The antenna 902 receives a wireless signal from the air and converts it into an electrical signal, such as an analog voltage signal. The antenna 902 captures electromagnetic waves in the air and converts them into voltage. When the electromagnetic waves in the air correspond to wireless signals, the voltage generated by the antenna 902 is an electrical signal.

[0113] LNA 904 amplifies the weak electrical signal received from antenna 902 while adding limited noise to the signal. Amplifying the received signal earlier in the receiver chain improves the signal-to-noise ratio (SNR) of the received signal. The power consumption of LNA 904 can be set via gain or bias current or a combination thereof.

[0114] The mixer 906 down-converts the frequency of the received signal to a lower frequency for further processing. The mixer 906 is a non-linear device that takes the amplified signal from the LNA 904 and mixes it with a local oscillator (LO) signal to produce an intermediate frequency (IF) signal having a lower frequency than the received signal, which IF signal may be a current signal. The current consumption of the mixer 906 may be set via gain, bias current, or clock rate (or rise and fall times of the clock received at the mixer 906), or a combination thereof.

[0115] BB 908 provides some additional amplification for the received IF current signal and filters out noise. The current consumption of BB 908 can be set via gain, bias current, or filter bandwidth, or a combination thereof.

[0116] The TIA 910 is an intermediate frequency (IF) amplifier with a built-in low-pass filter. The TIA 910 converts the IF current signal from the mixer into an IF voltage signal that can be digitized by the ADC 912. The current consumption of the TIA 910 can be set via gain, bias current, or bandwidth, or a combination thereof. Here, the bandwidth determines the frequency range that the TIA can accurately amplify. If the amount of input current from the BB 908 changes rapidly, the ability of the TIA 910 to effectively track the changes depends at least in part on its bandwidth.

[0117] ADC 912 converts the analog voltage signal from TIA 910 into a digital signal that can be further processed by a digital signal processing (DSP) algorithm. The current consumption of ADC 912 can be set via bias current or bandwidth or a combination thereof.

[0118] The clock sources of mixer 906 and ADC 912 may be the same or different. Different clock sources may have different clock rates. As a non-limiting example, the rise time or fall time of a given clock signal may be set via a power supply voltage level, which may be set to set the rise time and fall time of the clock signal.

[0119] In one or more examples, the signal processing chain 900 may include one or more control registers, and the values ​​in the fields of these control registers may directly or indirectly set parameters of corresponding blocks used by the ARC 914 to set the performance of the signal processing chain 900 via the performance definition setting 920 in response to the performance setting 918.

[0120] In some examples, one or more sensitivity definition blocks of the signal processing chain 900 may provide a single-ended mode and a differential mode. The differential input mode utilizes more power than the single-ended mode, so in some examples, the ARC 914 may set the corresponding input mode of the various sensitivity definition blocks of the signal processing chain 900 to the performance definition setting 216.

[0121] Fig.10 1 is a block diagram depicting a signal processing chain 1000 including a bypass 1002 according to one or more examples. The bypass 1002 is a circuit that selectively bypasses the BB 908. The bypass 1002 provides another mechanism for the ARC 914 to set performance and control power consumption at the signal processing chain 1000. If high performance (high sensitivity or interference rejection (i.e., blocking tolerance)) is not required, the ARC 914 can bypass the BB 908 via the performance defined setting 1004 and effectively turn off the BB 908 to reduce power consumption of the BB 908 and the signal processing chain 1000 more generally.

[0122] Fig.11 is a block diagram depicting a control register 1100 having fields for storing values ​​of performance-defined settings according to one or more examples.

[0123] The fields of the control register 1100 are referred to herein as "knobs," and these knobs are set by values ​​provided by an ARC (eg, ARC 914 or automatic radio controller 206, but not limited thereto).

[0124] The control register 1100 includes an LNA knob 1102, a mixer knob 1108, a TIA knob 1116, a BBamp knob 1124, and an ADC knob 1132. The LNA knob 1102 includes a gain control knob 1104 and a DC bias current control knob 1106. The mixer knob 1108 includes a clock rate control knob 1110, a gain control knob 1112, and a DC bias current control knob 1114. The TIA knob 1116 includes a filter BW control knob 1118, a gain control knob 1120, and a DC bias current control knob 1122. The BBamp knob 1124 includes a filter BW control knob 1126, a gain control knob 1128, and a DC bias current control knob 1130. The ADC knob 1132 includes a clock rate control knob 1134 and a DC bias current control knob 1136.

[0125] Those of ordinary skill in the art will appreciate that the functional elements (eg, functions, operations, actions, processes or methods) of the examples disclosed herein may be implemented in any suitable hardware, software, firmware or a combination thereof. Fig.12 Non-limiting examples of specific implementations of the functional elements disclosed herein are illustrated.In some examples, some or all of the functional elements disclosed herein may be performed by hardware specifically configured to perform the functional elements.

[0126] Fig.12 12 is a block diagram of a circuit system 1200 that can be used to implement various functions, operations, actions, processes, or methods disclosed herein in some examples. The circuit system 1200 includes one or more processors 1202 (sometimes referred to herein as "processors 1202") that are operably coupled to one or more data storage devices 1204 (sometimes referred to herein as "storage devices 1204"). The storage devices 1204 include machine executable code 1206 stored thereon, and the processor 1202 includes logic circuit system 1208. The machine executable code 1206 describes information of functional elements that can be implemented by (e.g., executed by) the logic circuit system 1208. The logic circuit system 1208 is suitable for implementing (e.g., executing) the functional elements described by the machine executable code 1206. When executing the functional elements described by the machine executable code 1206, the circuit system 1200 should be regarded as dedicated hardware configured to perform the functional elements disclosed herein. In some examples, processor 1202 may be configured to execute the functional elements described by machine executable code 1206 sequentially, simultaneously (eg, on one or more different hardware platforms), or in one or more parallel process flows.

[0127] When implemented by the logic circuitry 1208 of the processor 1202, the machine executable code 1206 is configured to adapt the processor 1202 to perform the operations of the examples for setting the performance of the RF receiver front end discussed herein. By way of non-limiting example, the machine executable code 1206 may be configured to adapt the processor 1202 to perform some or all of the operations of one or more of the following: process 400, process 500, process 600, process 700, or process 800.

[0128] Also as a non-limiting example, the machine executable code 1206 may be configured to adapt the processor 1202 to perform some or all of the features, functions, or operations disclosed herein for one or more of the following: device 200, including signal processing chain 202, automatic radio controller 206, and logic circuit 208; device 300, including logic circuit 302; input signal power state definition 304, performance setting definition 308, sensitivity setting definition 314, and blocking tolerance setting definition 316; signal processing chain 900, including antenna 902, LNA 904, mixer 906, BB 908, TIA 910, ADC 912, or ARC 914; signal processing chain 1000, including bypass 1002; control register 1100.

[0129] The processor 1202 may include a general-purpose processor, a special-purpose processor, a central processing unit (CPU), a microcontroller, a programmable logic controller (PLC), a digital signal processor (DSP), an application-specific integrated circuit (ASIC), a field programmable gate array (FPGA) or other programmable logic device, a discrete gate or transistor logic, a discrete hardware component, other programmable devices, or any combination thereof designed to perform the functions disclosed herein. A general-purpose computer including a processor is considered a special-purpose computer, and the general-purpose computer is configured to execute functional elements corresponding to the machine executable code 1206 (e.g., software code, firmware code, hardware description) associated with the embodiments of the present disclosure. It should be noted that the general-purpose processor (also referred to as a host processor or simply a host in this article) can be a microprocessor, but in an alternative, the processor 1202 may include any conventional processor, controller, microcontroller or state machine. The processor 1202 may also be implemented as a combination of computing devices, such as a combination of a DSP and a microprocessor, multiple microprocessors, one or more microprocessors combined with a DSP core, or any other such configuration.

[0130] In some examples, storage device 1204 includes volatile data storage device (e.g., random access memory (RAM)), non-volatile data storage device (e.g., flash memory, hard disk drive, solid state drive, erasable programmable read-only memory (EPROM), but not limited thereto). In some examples, processor 1202 and storage device 1204 may be implemented as a single device (e.g., semiconductor device product, system on chip (SOC), but not limited thereto). In some examples, processor 1202 and storage device 1204 may be implemented as separate devices.

[0131] In some examples, machine executable code 1206 may include computer readable instructions (e.g., software code, firmware code). As a non-limiting example, the computer readable instructions may be stored by storage device 1204, directly accessed by processor 1202, and executed by processor 1202 using at least logic circuitry 1208. Also as a non-limiting example, the computer readable instructions may be stored on storage device 1204, transferred to a memory device (not shown) for execution, and executed by processor 1202 using at least logic circuitry 1208. Thus, in some examples, logic circuitry 1208 includes logic circuitry 1208 that is electrically configurable.

[0132] In some examples, machine executable code 1206 may describe hardware (e.g., circuitry) to be implemented in logic circuitry 1208 to perform a functional element. The hardware may be described at any of a variety of abstraction levels, from low-level transistor layout to a high-level description language. At a high level of abstraction, a hardware description language (HDL) may be used, such as an IEEE standard hardware description language (HDL). As a non-limiting example, a VERILOG TM 、SYSTEMVERILOG TM or Very Large Scale Integration (VLSI) Hardware Description Language (VHDL).

[0133] The HDL description may be converted into a description at any of a variety of other abstraction levels as desired. As a non-limiting example, the high-level description may be converted into a logic-level description such as a register transfer language (RTL), a gate-level (GL) description, a layout-level description, or a mask-level description. As a non-limiting example, the micro-operations to be performed by the hardware logic circuits (e.g., gates, flip-flops, registers, but not limited thereto) of the logic circuit system 1208 may be described in RTL and then converted into a GL description by a synthesis tool, and the GL description may be converted into a layout-level description by a placement and routing tool, which corresponds to the physical layout of an integrated circuit, discrete gate or transistor logic, discrete hardware components, or a combination thereof of a programmable logic device. Therefore, in some examples, the machine executable code 1206 may include HDL, RTL, GL description, mask-level description, other hardware descriptions, or any combination thereof.

[0134] In examples where machine executable code 1206 includes a hardware description (at any level of abstraction), a system (not shown, but including storage 1204) may be configured to implement the hardware description described by machine executable code 1206. As a non-limiting example, processor 1202 may include a programmable logic device (e.g., an FPGA or PLC), and logic circuitry 1208 may be electrically controlled to implement circuitry corresponding to the hardware description into logic circuitry 1208. Also as a non-limiting example, logic circuitry 1208 may include hardwired logic components manufactured by a manufacturing system (not shown, but including storage 1204) according to the hardware description of machine executable code 1206.

[0135] Regardless of whether the machine executable code 1206 includes computer readable instructions or a hardware description, the logic circuit system 1208 is suitable for performing the functional elements described by the machine executable code 1206 when implementing the functional elements of the machine executable code 1206. It should be noted that although the hardware description may not directly describe the functional elements, the hardware description indirectly describes the functional elements that the hardware elements described by the hardware description are capable of performing.

[0136] As used in this disclosure, the term "module" or "component" may refer to a specific hardware implementation that is configured to perform the actions of a module or component and / or software object or software routine that may be stored on and / or executed by general-purpose hardware of a computing system (e.g., a computer-readable medium, a processing device, but not limited thereto). In some examples, the different components, modules, engines, and services described in this disclosure may be implemented as objects or processes (e.g., as separate threads) that execute on a computing system. Although some of the systems and methods described in this disclosure are generally described as being implemented in software (stored on and / or executed by general-purpose hardware), specific hardware implementations or combinations of software and specific hardware implementations are also possible and contemplated.

[0137] As used in this disclosure, the term "combination" referring to a plurality of elements may include any combination of all elements or various subcombinations of certain elements. For example, the phrase "A, B, C, D, or a combination thereof" may refer to any one of A, B, C, or D; a combination of each of A, B, C, and D; and any subcombination of A, B, C, or D, such as A, B, and C; A, B, and D; A, C, and D; B, C, and D; A and B; A and C; A and D; B and C; B and D; or C and D.

[0138] The terms used in this disclosure and in particular in the appended claims (e.g., the body of the appended claims, but not limited thereto) are generally intended to be "open" terms (e.g., the term "comprising" should be interpreted as "including but not limited to," the term "having" should be interpreted as "having at least," but not limited thereto). As used herein, the term "each" means "some or all." As used herein, the terms "each and every" mean "all."

[0139] Additionally, if a specific number of introduced claim expressions is intended, such intent will be expressly recited in the claim, and in the absence of such a recitation, no such intent is present. For example, as an aid to understanding, the following appended claims may include the use of the introductory phrases "at least one" and "one or more" to introduce claim expressions. However, the use of such phrases should not be construed to imply that a claim expression introduced by the indefinite article "a" or "an" will limit any particular claim containing such introduced claim expression to an example containing only one such expression, even when the same claim includes the introductory phrases "one or more" or "at least one" and an indefinite article, such as "a" or "a kind" (e.g., "a" and / or "a" may be interpreted to mean "at least one" or "one or more", but not limited to such); the same is true when a claim expression is introduced using a definite article.

[0140] Furthermore, even if a specific number of an introduced claim recitation is explicitly recited, one skilled in the art will recognize that such recitation should be interpreted as intending at least the recited number (e.g., the unmodified recitation "two recitations" without other modifiers intends at least two recitations, or two or more recitations, but is not limited thereto). Furthermore, in those instances where a convention similar to "at least one of, but not limited to, A, B, and C" or "one or more of, but not limited to, A, B, and C" is used, such constructions are generally intended to include A alone, B alone, C alone, A and B together, A and C together, B and C together, or A, B, and C together, but are not limited thereto.

[0141] In addition, any separate word or phrase presenting two or more alternative terms, whether in the specification, claims or drawings, should be understood to include the possibility of one of the terms, any one of the terms, or both of the terms. For example, the phrase "A or B" should be understood to include the possibility of "A" or "B" or "A and B".

[0142] Additional non-limiting examples include:

[0143] Embodiment 1: A device comprising: an RF receiver front end, the RF receiver front end providing at least three different performance modes; a logic circuit, the logic circuit being used to specify one of the three different performance modes at least partially in response to an input signal power state; and an automatic radio controller, the automatic radio controller being used to set the performance mode of the RF receiver front end to a specified one of the three different performance modes.

[0144] Embodiment 2: The apparatus of embodiment 1, wherein the different performance modes include different sensitivity settings and blockage tolerance settings.

[0145] Embodiment 3: An apparatus according to one or more of embodiments 1 and 2, wherein the RF receiver front end provides one or more additional different performance modes, and wherein the corresponding performance associated with the one or more additional different performance modes is between a maximum sensitivity and a minimum sensitivity.

[0146] Embodiment 4: An apparatus according to one or more of embodiments 1 to 3, wherein the logic circuit is used to: obtain a value representing a power level of an input signal to the RF receiver front end; compare the value representing the power level of the input signal with one or more thresholds, wherein the one or more thresholds are probability-based thresholds; and determine the input signal power state at least in part in response to the comparison.

[0147] Embodiment 5: The apparatus of one or more of Embodiments 1 to 4, wherein the logic circuit is configured to select the one or more thresholds based at least in part on an indication of an RF receiver front end mode.

[0148] Embodiment 6: The apparatus of one or more of embodiments 1 to 5, wherein the logic circuit is configured to determine a performance setting based at least in part on the input signal power state, the determined performance setting being associated with the performance mode.

[0149] Embodiment 7: An apparatus according to one or more of embodiments 1 to 6, wherein the performance definition sets one or more of the gain, DC bias current, bandwidth or clock rate of a performance definition block of a signal processing chain of the RF receiver front end.

[0150] Embodiment 8: The apparatus of one or more of embodiments 1 to 7, the apparatus comprising an automatic radio controller for: determining performance definition settings based at least in part on the determined performance settings; and applying the determined performance definition settings to the RF receiver front end.

[0151] Embodiment 9: An apparatus according to one or more of embodiments 1 to 8, wherein the logic circuit comprises: an input signal power state definition, the input signal power state definition comprising one or more thresholds associated with the input signal power state; and a performance setting definition, the performance setting definition comprising one or more performance settings associated with the input signal power state.

[0152] Embodiment 10: The apparatus of one or more of embodiments 1 to 9, wherein the RF receiver front end comprises a signal processing chain comprising: a low noise amplifier; a mixer; a baseband amplifier; an intermediate frequency (IF) amplifier with a built-in low pass filter; and an analog-to-digital converter (ADC).

[0153] Embodiment 11: The apparatus according to one or more of embodiments to 10, comprising: a circuit for selectively bypassing the baseband amplifier.

[0154] Embodiment 12: An apparatus according to one or more of embodiments 1 to 11, the apparatus comprising: an automatic radio controller, the automatic radio controller being used to dynamically set one or more parameters of a power definition block of the RF receiver front end within one of the at least three different performance modes.

[0155] Embodiment 13: An apparatus according to one or more of embodiments 1 to 12, wherein the logic circuit is used to specify a default performance mode, and the performance settings associated with the default performance mode are lower than the performance settings associated with a specified one of the three different performance modes.

[0156] Embodiment 14: A method, comprising: determining a power state of an input signal to an RF receiver front end; and setting a performance mode of the RF receiver front end to one of at least three different performance modes provided by the RF receiver front end, at least in part in response to the determined power state of the input signal.

[0157] Embodiment 15: According to the method described in Embodiment 14, the method includes: obtaining a value representing the power level of the input signal to the RF receiver front end; comparing the value representing the power level of the input signal to the RF receiver front end with one or more thresholds, wherein the one or more thresholds are probability-based thresholds; and determining the power state of the input signal at least partially in response to the comparison.

[0158] Embodiment 16: The method according to one or more of embodiments 14 and 15, the method comprising: selecting the one or more thresholds based at least in part on an indication of an RF receiver front end mode, the one or more thresholds being probability-based thresholds.

[0159] Embodiment 17: A method according to one or more of embodiments 14 to 16, the method comprising: determining a performance setting based at least in part on the power state of the input signal, the determined performance setting being associated with one of at least three performance modes provided by the RF receiver front end; and determining a performance definition setting based at least in part on the determined performance setting.

[0160] Embodiment 18: A method according to one or more of embodiments 14 to 17, wherein the performance definition sets the gain, DC bias current, bandwidth or clock rate of a performance block of a signal processing chain used for the RF receiver front end.

[0161] Embodiment 19: The method according to one or more of embodiments 14 to 18 includes: applying the determined performance definition settings to the RF receiver front end.

[0162] Embodiment 20: The method of one or more of Embodiments 14 to 19, wherein the determined performance settings include one or more of a sensitivity setting or a blockage tolerance setting.

[0163] Embodiment 21: A method according to one or more of embodiments 14 to 20, the method comprising: setting the performance mode of the RF receiver front end to a default performance mode, the performance setting associated with the default performance mode being lower than the performance setting associated with one of the at least three different performance modes provided by the RF receiver front end.

[0164] Embodiment 22: A method according to one or more of embodiments 14 to 21, wherein setting the performance mode of the RF receiver front end to the default performance mode includes: at least partially in response to an indication of power-on, power-on reset, or reset, setting the performance mode of the RF receiver front end to the default performance mode.

[0165] Embodiment 23: A method according to one or more of embodiments 14 to 22, wherein the set one performance mode among at least three different performance modes provided by the RF receiver front end is a default performance mode.

[0166] Although the present disclosure describes the present invention with respect to certain illustrative examples, those of ordinary skill in the art will recognize and understand that the present invention is not so limited. Instead, many additions, deletions, and modifications may be made to the illustrative examples and the examples described without departing from the scope of the present invention as claimed below and its legal equivalents. Furthermore, features from one example may be combined with features from another example while still being included within the scope of the present invention as contemplated by the inventor.

Claims

1. A device, comprising: an RF receiver front end providing at least three different performance modes; logic circuitry for designating one of the three different performance modes responsive at least in part to an input signal power state; and An automatic radio controller is configured to set a performance mode of the RF receiver front end to a specified one of the three different performance modes.

2. The apparatus of claim 1, wherein the different performance modes include different sensitivity settings and blockage tolerance settings.

3. The apparatus of claim 1 , wherein the RF receiver front end provides one or more additional different performance modes, and wherein the corresponding performance associated with the one or more additional different performance modes is between a maximum sensitivity and a minimum sensitivity.

4. The apparatus of claim 1 , wherein the logic circuit is configured to: obtaining a value representing a power level of an input signal to the RF receiver front end; comparing the value representing the power level of the input signal to one or more thresholds, the one or more thresholds being probability-based thresholds; and The input signal power state is determined at least in part in response to the comparison.

5. The apparatus of claim 4, wherein the logic circuit is configured to: The one or more thresholds are selected based at least in part on an indication of an RF receiver front end mode.

6. The apparatus of claim 4, wherein the logic circuit is configured to: A performance setting is determined based at least in part on the input signal power state, the determined performance setting being associated with the performance mode.

7. The apparatus of claim 6, wherein the performance definition sets one or more of a gain, a DC bias current, a bandwidth, or a clock rate of a performance definition block for a signal processing chain of the RF receiver front end.

8. The apparatus of claim 6, comprising an automatic radio controller for: determining a performance definition setting based at least in part on the determined performance setting; and The determined performance defining settings are applied to the RF receiver front end.

9. The apparatus of claim 1, wherein the logic circuit comprises: an input signal power state definition, the input signal power state definition comprising one or more thresholds associated with the input signal power state; and A performance setting definition includes one or more performance settings associated with an input signal power state.

10. The apparatus of claim 1 , wherein the RF receiver front end comprises a signal processing chain comprising: Low noise amplifier; Mixer; Baseband amplifier; Intermediate frequency (IF) amplifier with built-in low-pass filter; and Analog-to-digital converter (ADC).

11. The device according to claim 10, comprising: A circuit selectively bypasses the baseband amplifier.

12. The device according to claim 1, comprising: An automatic radio controller for dynamically setting one or more parameters of a power definition block of the RF receiver front end within one of the at least three different performance modes.

13. The apparatus of claim 1, wherein the logic circuit is to designate a default performance mode, the default performance mode being associated with a performance setting that is lower than a performance setting associated with the designated one of the three different performance modes.

14. A method comprising: determining a power state of an input signal to an RF receiver front end; as well as Responsive at least in part to the determined power state of the input signal, a performance mode of the RF receiver front end is set to one of at least three different performance modes provided by the RF receiver front end.

15. The method according to claim 14, comprising: obtaining a value representing a power level of the input signal to the RF receiver front end; comparing the value representing the power level of the input signal to the RF receiver front end to one or more thresholds, the one or more thresholds being probability-based thresholds; and The power state of the input signal is determined at least in part in response to the comparison.

16. The method according to claim 15, comprising: The one or more thresholds are selected based at least in part on an indication of an RF receiver front end mode, the one or more thresholds being probability-based thresholds.

17. The method according to claim 14, comprising: determining a performance setting based at least in part on the power state of the input signal, the determined performance setting being associated with one of at least three performance modes provided by the RF receiver front end; as well as A performance definition setting is determined based at least in part on the determined performance setting.

18. The method of claim 17, wherein the performance definition sets the gain, DC bias current, bandwidth, or clock rate of a performance block of a signal processing chain for the RF receiver front end.

19. The method according to claim 17, comprising: The determined performance defining settings are applied to the RF receiver front end.

20. The method of claim 17, wherein the determined performance setting comprises one or more of a sensitivity setting or a blockage tolerance setting.

21. The method according to claim 14, comprising: The performance mode of the RF receiver front end is set to a default performance mode, the performance setting associated with the default performance mode being lower than the performance setting associated with a set one of at least three different performance modes provided by the RF receiver front end.

22. The method of claim 21 , wherein setting the performance mode of the RF receiver front end to the default performance mode comprises: Responsive at least in part to an indication of power on, power on reset, or reset, the performance mode of the RF receiver front end is set to the default performance mode.

23. The method of claim 14, wherein the set one of at least three different performance modes provided by the RF receiver front end is a default performance mode.

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