Imaging element and electronic device

Abstract

The present invention achieves low power consumption of an imaging element mounted in an electronic device such as a smartphone. An imaging element according to the present technology includes: an analog circuit section including pixels that perform photoelectric conversion; a logic circuit section that processes a signal read out from the pixel; a body potential generating section applying a body potential in a direction in which the threshold voltage is reduced to a well of each transistor forming the logic circuit section, the well being doped so as to surround the transistor structure; and a control section that controls the body potential of each externally specified operation mode.

Description

Technical Field

[0001] The present technology relates to an imaging element. Specifically, the present technology relates to an imaging element including: an analog circuit unit including pixels that perform photoelectric conversion; and a logic circuit unit that processes signals of the pixels; and an electronic device including the imaging element. Background Art

[0002] Imaging elements mounted on electronic devices such as smartphones need to improve yield and reduce power consumption. Conventionally, as a technology for improving yield, the following power supply voltage variable technology (dynamic voltage and frequency scaling: DVFS) is known: changes in the process of the imaging element are monitored outside the imaging element, and the power supply voltage of the imaging element is controlled from the outside according to the change in the process (for example, refer to non-patent document 1).

[0003] Reference List

[0004] Non-patent literature

[0005] Non-patent document 1: "A 45nm Single-Chip Application-and-Baseband ProcessorUsing an Intermittent Operation Technique" 2009 IEEE International Solid-State Circuits Conference Summary of the invention

[0006] Problems to be solved by the present invention

[0007] In the above-mentioned prior art, when there is a margin in the result state of the process of the imaging element such as TT (PMOS: Typical, NMOS: Typical), FF (PMOS: Fast, NMOS: Fast), etc., control is performed to reduce the power supply voltage of the imaging element, thereby reducing the variation in the process and improving the yield. However, in the above-mentioned conventional technology, although the variation in the process can be reduced by externally controlling the power supply voltage of the imaging element, the current consumption cannot be reduced, and the reduction of power consumption is not considered.

[0008] The present technology has been made in view of such circumstances, and its object is to achieve low power consumption of an imaging element.

[0009] Solution to the problem

[0010] The present technology has been made to solve the above-mentioned problems, and its first aspect is an imaging element, including: an analog circuit unit including pixels that perform photoelectric conversion; a logic circuit unit configured to process signals read out from the above-mentioned pixels; a body potential generating unit configured to apply a body potential in a direction of reducing a threshold voltage to a well in a transistor forming the logic circuit unit, the well being doped to surround a transistor structure; and a control unit configured to control the body potential for each operation mode specified from the outside. Therefore, there is an effect of being able to achieve low power consumption of the imaging element. The "body potential" mentioned here is a potential applied to a well, which is a region doped to surround a transistor structure of a complementary metal oxide semiconductor (CMOS).

[0011] In addition, in the first aspect, when the operation mode is the streaming operation mode, the control unit can control the body potential according to each of the still image capture mode and the motion image capture mode. Therefore, it is possible to avoid grayscale effects at certain midpoints in the still image and to sequentially cope with temperature fluctuations during 8K motion image capture.

[0012] Furthermore, in the first aspect, when the logic circuit unit is divided into a flow function block and a normally-on function block, the control unit may apply a high potential higher than or equal to 0V to the N-type well in the flow function block and apply a low potential lower than or equal to 0V to the P-type well as a body potential, as compared to the normally-on function block. Therefore, there is provided an effect of being able to improve the performance of the flow function block by lowering the threshold voltage.

[0013] In addition, in the first aspect, the body potential generating unit can apply a zero potential to a well in a transistor forming a logic circuit unit, the well being doped to surround the transistor structure. Thus, there is provided an effect that when the logic circuit unit is subjected to FBB potential control, the analog circuit unit can be subjected to normal ZBB potential control. The details of the FBB potential control and the ZBB potential control will be described later.

[0014] In addition, in the first aspect, the body potential generating unit can apply a body potential in a direction of lowering the threshold voltage to a well in the transistor forming the logic circuit unit, the well being doped to surround the transistor structure. Therefore, when the analog circuit unit is a vertical scanning unit or a comparator constituting an input stage of an analog-to-digital conversion circuit, there is provided an effect that the frame rate can be increased or the power consumption can be reduced by the amount obtained by increasing the speed.

[0015] In addition, in the first aspect, each of the transistors forming the logic circuit unit and the transistors forming the analog circuit unit is a MOS transistor having a fully depleted silicon-on-insulator structure. Therefore, it is provided that the control of the body potential in the direction of reducing the threshold voltage can simultaneously achieve lower power consumption and improve the yield through adaptive control.

[0016] In addition, a second aspect of the present technology is an imaging element including: an analog circuit unit including a pixel that performs photoelectric conversion; a logic circuit unit configured to process a signal read out from the pixel; and a body potential generating unit configured to apply a body potential in a direction of lowering a threshold voltage to a well in a transistor forming the logic circuit unit, the well being doped to surround a transistor structure. Therefore, an effect of being able to realize low power consumption of the imaging element is provided.

[0017] In the second aspect, the body potential generating unit may control the body potential in accordance with the characteristic fluctuation factor of the imaging element, thereby providing an effect of being able to absorb the deviation of the entire imaging element.

[0018] In the second aspect, the characteristic variation factor may be at least one of a variation in process, a variation in junction temperature, and a variation in power supply voltage. Thus, there is provided an effect of being able to absorb the variation of the entire imaging element.

[0019] In addition, in the second aspect, the body potential generating unit can control the body potential according to at least one of the result state of the saturated electron number of the pixel and the result state of the conversion efficiency of the pixel. Therefore, an effect capable of absorbing the deviation of the entire imaging element is provided.

[0020] In addition, in the second aspect, the body potential generating unit can apply a zero potential to a well in a transistor forming an analog circuit unit, the well being doped to surround the transistor structure. Thus, when the logic circuit unit is subjected to FBB potential control, the analog circuit unit can be subjected to normal ZBB potential control.

[0021] In addition, in the second aspect, the body potential generating unit can apply a body potential in a direction of lowering the threshold voltage to a well in the transistor forming the logic circuit unit, the well being doped to surround the transistor structure. Therefore, when the analog circuit unit is a vertical scanning unit or a comparator constituting an input stage of an analog-to-digital conversion circuit, there is provided an effect that the frame rate can be increased or the power consumption can be reduced by the amount obtained by increasing the speed.

[0022] In addition, in the second aspect, each of the transistors forming the logic circuit unit and the transistors forming the analog circuit unit is a MOS transistor having a fully depleted silicon-on-insulator structure. As a result, there is provided an effect that lower power consumption can be achieved by applying control of the body potential in the direction of lowering the threshold voltage and that the yield can be improved by adaptive control.

[0023] In addition, a third aspect of the present technology is an electronic device including: an imaging element; and an operation mode designation unit configured to designate an operation mode of the imaging element, wherein the imaging element includes: an analog circuit unit including pixels that perform photoelectric conversion; a logic circuit unit configured to process signals read out from the pixels; a body potential generation unit configured to apply a body potential in a direction of reducing a threshold voltage to a well in a transistor forming the logic circuit unit, the well being doped to surround a transistor structure; and a control unit configured to control the body potential for each operation mode designated by the operation mode designation unit. Therefore, an effect of being able to achieve low power consumption of an imaging element mounted on an electronic device is provided. BRIEF DESCRIPTION OF THE DRAWINGS

[0024] Figure 1 It is a system configuration diagram showing a configuration example of an imaging element of the present technology.

[0025] Figure 2 : is a circuit diagram showing a circuit example of a pixel (pixel circuit) in the imaging element of the present technology.

[0026] Figure 3 : is a block diagram showing a basic configuration example of an analog-to-digital conversion unit in an imaging element of the present technology.

[0027] Figure 4 is an external view showing an external configuration example of a smartphone as an example of the electronic device according to the present technology.

[0028] Figure 5 : is a block diagram showing an internal configuration embodiment of a smartphone as an embodiment of the electronic device according to the present technology.

[0029] Figure 6 2 is a cross-sectional view showing a cross-sectional structure of a CMOS transistor, for explaining a CMOS transistor having a fully depleted SOI structure compared with a bulk CMOS transistor.

[0030] Figure 7 is a characteristic diagram showing the relationship between power consumption and performance.

[0031] Figure 8 is a circuit diagram showing a circuit embodiment of an analog circuit unit.

[0032] Fig. 9 : is a block diagram showing the configuration of an imaging element according to a first embodiment of the present technology.

[0033] Fig.10 This is a table for explaining the body potential control in each operation mode in the imaging element of the first embodiment.

[0034] Fig.11 : is a state transition diagram showing the state transition of the operation mode of the imaging element of the first embodiment.

[0035] Fig.12 is a block diagram showing a configuration example of an imaging element according to a second embodiment of the present technology.

[0036] Fig.13 It is a layout diagram showing an example of a layout image of an analog circuit unit, a logic circuit unit, a body potential generating unit, a PVT change monitoring circuit, and an OTP in an imaging element according to the second embodiment.

[0037] Fig.14 : is a block diagram showing a configuration example of a characteristic fluctuation factor monitoring circuit in an imaging element according to the second embodiment.

[0038] Fig.15 It is a diagram for explaining an image in the case of monitoring the status of a processing result.

[0039] Fig.16 is a graph for explaining the relationship between the minimum operating power supply voltage and process variations.

[0040] Fig.17 : is a circuit diagram for explaining the saturation electron count Qs of a pixel and the conversion efficiency η of the pixel. DETAILED DESCRIPTION

[0041] Hereinafter, the mode for performing the present technology (hereinafter, referred to as the embodiment) will be described in detail with reference to the accompanying drawings. The present technology is not limited to the embodiment. In the following description, the same reference numerals are used for the same elements or elements with the same functions, and redundant descriptions will be omitted. Note that the description will be given in the following order.

[0042] 1. Imaging element of this technology

[0043] 1-1. Configuration Example of Imaging Element

[0044] 1-2. Pixel Circuit Example

[0045] 1-3. Configuration Example of Analog-to-Digital Conversion Unit

[0046] 2. Electronic devices of this technology

[0047] 2-1. External Configuration Example of Smartphone as Example of Electronic Device

[0048] 2-2. Internal Configuration Example of Smartphone as Example of Electronic Device

[0049] 2-3. CMOS transistor with fully depleted SOI structure

[0050] 2-4. Operation and Effect of FBB Potential Control on Analog Circuit Units

[0051] 3. First embodiment of the present technology (Example of controlling body potential in each operation mode of an imaging element)

[0052] 3-1. Configuration Example of Imaging Element According to First Embodiment

[0053] 3-2. Body potential control for each operation mode

[0054] 3-3. Operation mode switching

[0055] 4. Second Embodiment of the Present Technology (Example of Controlling Body Potential According to Characteristic Fluctuation Factor)

[0056] 4-1. Configuration Example of Imaging Element According to Second Embodiment

[0057] 4-2. Arrangement of Circuit Units Constituting the Imaging Element of the Second Embodiment

[0058] 4-3. Example of controlling body potential according to PVT changes

[0059] 4-4. 5. Modification Example of Controlling Body Potential Based on Changes in Saturated Electron Count Qs and Conversion Efficiency η

[0060] 6. Configurations that this technology can adopt

[0061] <1. Imaging element of the present technology>

[0062] One embodiment of the imaging element of the present technology is a complementary metal oxide semiconductor (CMOS) image sensor, which is a type of XY address system imaging element. A CMOS image sensor is an imaging element manufactured by applying or partially using a CMOS process.

[0063] [1-1. Configuration Example of Imaging Element]

[0064] Figure 1 1 is a block diagram showing a configuration example of an imaging element of the present technology. The imaging element 10 includes a pixel array unit 11 and a peripheral circuit unit of the pixel array unit 11. The peripheral circuit unit of the pixel array unit 11 includes, for example, a vertical scanning unit 12, a column processing unit 13, a horizontal scanning unit 14, a digital signal calculation unit 15, a timing control unit 16, and the like.

[0065] The pixel array unit 11 has a configuration in which pixels (pixel circuits) 20 that perform photoelectric conversion are arranged two-dimensionally in the row direction and the column direction, that is, arranged in a matrix form. Here, the row direction refers to the direction in which the pixels 20 in the pixel row are arranged, and the column direction refers to the direction in which the pixels 20 in the pixel column are arranged. The pixels 20 perform photoelectric conversion to generate and accumulate photoelectric charges corresponding to the amount of incident light. Figure 1 In the illustrated embodiment, the pixel array of the pixel array unit 11 is a pixel array of m rows and n columns (m and n are integers), that is, "m" represents the number of rows, and "n" represents the number of columns.

[0066] In the pixel array unit 11 , a pixel control line 31 is wired for each pixel row for a pixel array of m rows and n columns. In addition, a signal line 32 is wired for each pixel 20 .

[0067] When reading a signal from the pixel 20, the pixel control line 31 transmits a drive signal output from the vertical scanning unit 12 in units of pixel rows. Figure 1 , the pixel control line 31 is shown as one wiring, but its number is not limited to one. One end of the pixel control line 31 is connected to an output terminal corresponding to each row of the vertical scanning unit 12. The signal line 32 transmits the signal read out from the pixel 20 to the column processing unit 13.

[0068] Hereinafter, each component of the peripheral circuit unit of the pixel array unit 11 , that is, the vertical scanning unit 12 , the column processing unit 13 , the horizontal scanning unit 14 , the digital signal calculation unit 15 , and the timing control unit 16 will be described.

[0069] The vertical scanning unit 12 includes a shift register, an address decoder, etc., and controls scanning of a pixel row and an address of a pixel row based on a timing control signal supplied from the timing control unit 16 when each pixel 20 of the pixel array unit 11 is selected. Although a specific configuration of the vertical scanning unit 12 is not shown, the vertical scanning unit 12 generally includes two scanning systems, namely, a reading scanning system and a scanning scanning system.

[0070] The column processing unit 13 reads a signal from each pixel 20 of the pixel array unit 11 based on a timing control signal supplied from the timing control unit 16, performs analog-to-digital conversion processing, correlated double sampling processing (CDS processing), etc., and outputs the signal as a pixel signal. Details of the analog-to-digital conversion unit, which is one of the functional units of the column processing unit 13, will be described later.

[0071] The horizontal scanning unit 14 includes a shift register, an address decoder, etc., and sequentially selectively scans each pixel 20 of the pixel array unit 11 based on a timing control signal supplied from the timing control unit 16. By selective scanning by the horizontal scanning unit 14, the pixel signal converted into a digital signal for each unit circuit in the column processing unit 13 is sequentially output to the digital signal calculation unit 15.

[0072] The digital signal calculation unit 15 performs a predetermined digital operation on the pixel signals sequentially output from the horizontal scanning unit 14 based on the timing control signal supplied from the timing control unit 16 , and sets the calculation result as an imaging output.

[0073] The timing control unit 16 generates various timing signals, clock signals, control signals, etc. based on the synchronization signal provided from the outside. Then, the timing control unit 16 performs drive control of the vertical scanning unit 12, the column processing unit 13, the horizontal scanning unit 14, the digital signal calculation unit 15, etc. based on the generated signals.

[0074] [1-2. Circuit Example of Pixel]

[0075] Figure 2 1 is a circuit diagram showing a circuit embodiment of a pixel (pixel circuit) 20 in the imaging element 10 of the present technology. Each pixel 20 of the pixel array unit 11 includes a photoelectric conversion unit 21, a charge transfer unit 22, a charge-voltage conversion unit 23, a charge resetting unit 24, a signal amplification unit 25, and a pixel selection unit 26. A predetermined voltage is supplied from a power supply (pixel power supply) of the pixel 20 to the charge resetting unit 24 and the signal amplification unit 25.

[0076] Here, as the charge transfer unit 22, the charge resetting unit 24, the signal amplifying unit 25, and the pixel selecting unit 26, for example, an N-type MOS field effect transistor (hereinafter, referred to as a MOS transistor) can be used. However, the combination of the conductive types of the four MOS transistors 22, 24, 25, and 26 illustrated here is only an embodiment, and the combination is not limited thereto.

[0077] For the pixels 20, as with the above-mentioned pixel control lines 31, a plurality of pixel control lines are wired to be shared with the respective pixels 20 of the same pixel row. The plurality of pixel control lines are connected in units of pixel rows to output terminals corresponding to each pixel row of the vertical scanning unit 12. The vertical scanning unit 12 appropriately outputs a transfer signal TRG, a reset signal RST, and a selection signal SEL to the plurality of pixel control lines.

[0078] It should be noted that the load MOS circuit 33 is connected to one end of the signal line 32 wired for each pixel column of the pixel array unit 11. The load MOS circuit 33 includes a constant current source 34 having a MOS transistor.

[0079] The photoelectric conversion unit 21 is a PN junction photodiode (PD). The photodiode has an anode electrode connected to a low potential side power source (for example, ground), and generates and accumulates electric charge according to the amount of incident light.

[0080] The charge transfer unit 22 transfers the charge accumulated in the photoelectric conversion unit 21 to the charge-voltage conversion unit 23 according to the transfer signal TRG supplied from the vertical scanning unit 12. Specifically, the transfer signal TRG active at a high level is supplied from the vertical scanning unit 12 to the gate electrode of the transistor constituting the charge transfer unit 22. Then, the transistor constituting the charge transfer unit 22 enters a conducting state, and transfers the charge accumulated in the photoelectric conversion unit 21 to the charge-voltage conversion unit 23.

[0081] The charge-voltage conversion unit 23 is a capacitor CFD of a floating diffusion (FD) region formed between a drain region of a transistor constituting the charge transfer unit 22 and a source region of a transistor constituting the charge resetting unit 24. The charge-voltage conversion unit 23 converts the charge transferred from the photoelectric conversion unit 21 through the charge transfer unit 22 into a voltage.

[0082] The charge resetting unit 24 resets the charge accumulated in the charge-voltage conversion unit 23 according to the reset signal RST supplied from the vertical scanning unit 12. Specifically, the transistor constituting the charge resetting unit 24 is connected to the power supply voltage V DD and the charge-voltage conversion unit 23, and a reset signal RST activated at a high level is provided to the gate of the transistor from the vertical scanning unit 12. Then, when the reset signal RST becomes a high level, the transistor constituting the charge resetting unit 24 enters a conducting state, and the charge accumulated in the charge-voltage conversion unit 23 is reset.

[0083] The signal amplifying unit 25 amplifies the voltage converted by the charge-voltage converting unit 23, and outputs a pixel signal at a level corresponding to the charge accumulated in the charge-voltage converting unit 23. The gate of the transistor constituting the signal amplifying unit 25 is connected to the charge-voltage converting unit 23, and the drain is connected to the power supply voltage V DDThen, the transistor constituting the signal amplifying unit 25 is used as an input unit of a readout circuit (i.e., a source follower circuit) that reads out the charge obtained by the photoelectric conversion in the photoelectric conversion unit 21. That is, in the transistor constituting the signal amplifying unit 25, the source is connected to the signal line 32 via the pixel selecting unit 26, thereby constituting a source follower circuit with the constant current source 34 connected to one end of the signal line 32.

[0084] The pixel selection unit 26 selects any pixel 20 within the pixel array unit 11 under selective scanning by the vertical scanning unit 12. The transistor constituting the pixel selection unit 26 is connected between the source electrode of the transistor constituting the signal amplification unit 25 and the signal line 32, and the selection signal SEL activated at a high level is provided from the vertical scanning unit 12 to the gate electrode of the transistor. Then, when the selection signal SEL becomes a high level, the transistor constituting the pixel selection unit 26 enters a conductive state. As a result, the pixel 20 enters a selected state. When the pixel 20 enters the selected state, the signal output from the signal amplification unit 25 is read out to the column processing unit 13 via the signal line 32.

[0085] The pixel 20 of the above-described circuit configuration embodiment sequentially outputs a reset signal (so-called P-phase signal) which is a reset level when the charge-voltage conversion unit 23 is reset by the charge resetting unit 24, and a data signal (so-called D-phase signal) which is a signal level corresponding to the charge based on the photoelectric conversion in the photoelectric conversion unit 21. That is, the pixel signal output from the pixel 20 includes the reset signal when resetting is performed in the photoelectric conversion unit 21 and the data signal when photoelectric conversion is performed.

[0086] [1-3. Basic Configuration Example of Analog-Digital Conversion Unit]

[0087] Next, a basic configuration example of an analog-digital conversion unit as one of the functional units of the column processing unit 13 will be described. Figure 3 : is a block diagram showing a basic configuration example of an analog-digital conversion unit in the imaging element 10 of the present technology. Figure 3 Also shown are peripheral circuit units of the analog-to-digital conversion unit.

[0088] The analog-to-digital conversion unit 50, which is one of the functional units of the column processing unit 13, acquires the analog pixel signal Vsig provided from each pixel 20 of the pixel array unit 11 through the signal line 32 based on the timing control signal provided from the timing control unit 16, and sequentially converts the pixel signal Vsig into a digital pixel signal.

[0089] The analog-to-digital conversion unit 50 includes a plurality of analog-to-digital conversion circuits 51 provided corresponding to the respective pixels 20 of the pixel array unit 11. In the imaging element 10 according to the embodiment of the present technology, for example, a so-called single-slope analog-to-digital conversion circuit, which is an example of a reference signal comparison analog-to-digital conversion circuit, is used as the analog-to-digital conversion circuit 51.

[0090] In the analog-to-digital conversion unit 50 using a single-slope analog-to-digital conversion circuit, a reference signal of a slope waveform that changes linearly (e.g., decreases monotonically) with a predetermined slope over time (i.e., a reference signal RAMP of a ramp wave) is used as a reference signal at the time of analog-to-digital conversion. The reference signal RAMP of a ramp wave is generated in the reference signal generation unit 60 based on a timing control signal provided from the timing control unit 16. The reference signal generation unit 60 can be configured using, for example, a digital-to-analog conversion circuit.

[0091] The analog-to-digital conversion circuit 51 includes a comparator 52 and a column counter 53 , and is provided for each pixel 20 of the pixel array unit 11 .

[0092] The comparator 52 uses the analog pixel signal Vsig provided from each pixel 20 of the pixel array unit 11 through the signal line 32 as a comparison input, and uses the reference signal RAMP of the ramp wave generated by the reference signal generating unit 60 as a reference input to compare the two signals. Then, for example, at the timing when the reference signal RAMP of the ramp wave exceeds the voltage value of the analog pixel signal Vsig, a signal notifying this fact is output as a comparison result Vco. Therefore, the comparator 52 outputs a pulse signal having a pulse width corresponding to the signal level of the analog pixel signal Vsig (specifically, a pulse signal having a pulse width corresponding to the amplitude of the signal level) as the comparison result Vco.

[0093] At the same timing as the start timing of supply of the reference signal RAMP of the ramp wave to the comparator 52, the clock signal CLK is supplied from the timing control unit 16 to the column counter 53. The column counter 53 performs a counting operation in synchronization with the clock signal CLK, thereby measuring the cycle of the pulse width of the output pulse of the comparator 52, that is, the cycle from the start of the comparison operation to the end of the comparison operation. The counting result (count value) of the column counter 53 is supplied to the horizontal scanning unit 14 as a digital value obtained by digitizing the analog pixel signal Vsig.

[0094] As described above, the analog-to-digital conversion unit 50 including the single-slope analog-to-digital conversion circuit 51 compares the analog pixel signal Vsig output from the pixel 20 with the reference signal RAMP of the ramp wave generated by the reference signal generation unit 60. Then, a digital value can be obtained from time information starting from the moment when the amplitude relationship between the analog pixel signal Vsig of the ramp wave and the reference signal RAMP changes (i.e., the moment when the output of the comparator 52 is inverted).

[0095] <2. Electronic device of the present technology>

[0096] The imaging element 10 of the present technology described above can be used as an imaging element installed on various electronic devices. Embodiments of electronic devices equipped with imaging elements include mobile devices such as smartphones, digital cameras, tablet computers, and personal computers. However, the present technology is not limited to mobile devices. Here, a smartphone is exemplified as a specific embodiment of an electronic device (i.e., an electronic device of the present technology) on which the imaging element 10 of the present technology can be installed.

[0097] [2-1. External configuration example of a smartphone]

[0098] Figure 4 2 is an external view showing an external configuration example of a smartphone as an example of an electronic device according to the present technology. Figure 4 , "a" is an external view of the smartphone viewed from the front side, and Figure 4 "b" is an external view of the smartphone viewed from the rear side.

[0099] The smartphone 100 according to the present embodiment includes a display unit 120 on the front side of a housing 110. Further, for example, the smartphone 100 includes an imaging unit 130 in an upper portion on the rear surface side of the housing 110. Then, the imaging element 10 of the present technology can be used as the imaging unit 130.

[0100] [2-2. Internal configuration example of a smartphone]

[0101] Figure 5 : is a block diagram showing an internal configuration embodiment of a smartphone as an embodiment of the electronic device according to the present technology.

[0102] The smartphone 100 according to the present embodiment includes the imaging element 10 of the present technology as an imaging unit, and includes: an application processor 70 configured to specify an operation mode of the imaging element 10; and a power supply circuit unit 80 configured to supply a power supply voltage V to the imaging element 10 under the control of the application processor 70. DD Etc. Note that the application processor 70 is an example of an operation mode specifying unit described in the claims.

[0103] Figure 5 The illustrated imaging element 10 includes an analog circuit unit 101 , a logic circuit unit 102 , a body potential generating unit 103 , and a control unit 104 .

[0104] The analog circuit unit 101 includes a pixel array unit 11 in which pixels 20 are two-dimensionally arranged in a matrix and Figure 1 The vertical scanning unit 12, Figure 2 Load MOS circuit 33, Figure 3 The logic circuit unit 102 includes the comparator 52 and the like. Figure 3 The logic circuit unit 102 includes the column counter 53, the horizontal scanning unit 14, the digital signal calculation unit 15, etc., and processes the signal read out from the pixel 20. The logic circuit unit 102 is a digital circuit unit including the column counter 53, the horizontal scanning unit 14, the digital signal calculation unit 15, etc., but is described as the logic circuit unit 102 in this specification.

[0105] The imaging element 10 mounted on the smart phone 100 needs to improve yield and reduce power consumption. Therefore, in order to improve the yield and reduce power consumption, the imaging element 10 has a body potential generating unit 103. The body potential generating unit 103 applies a forward body bias (FBB) potential to the transistor forming the logic circuit unit 102, that is, applies a body potential in a direction of lowering the threshold voltage Vth to a well that is doped to surround the transistor structure of the CMOS. In the following, applying the body potential to the well may be simply described as applying the body potential to the transistor.

[0106] When the FBB potential is applied to the transistors forming the logic circuit unit 102, the body potential generating unit 103 applies a zero body bias (ZBB) potential (i.e., zero potential) to the transistors forming the analog circuit unit 101. However, at this time, the body potential applied to the transistors forming the analog circuit unit 101 is not limited to the control of applying the zero potential (hereinafter, described as the ZBB potential control), and the control of applying the FBB potential (hereinafter, described as the FBB potential control) may be applied.

[0107] The control unit 104 controls the body potential applied by the body potential generating unit 103 to each of the analog circuit unit 101 and the logic circuit unit 102. Specifically, under the control of the control unit 104, the body potential generating unit 103 applies the ZBB potential or the FBB potential as the body potential to the transistor forming the analog circuit unit 101, and applies the FBB potential as the body potential to the transistor forming the logic circuit unit 102.

[0108] [2-3. CMOS transistor with fully depleted SOI structure]

[0109] In the imaging element 10 having the above-mentioned configuration, in order to realize FBB potential control, it is preferred to use a CMOS transistor having a silicon-on-insulator (SOI) structure in which a device is constituted on a silicon thin film on an insulating film, particularly a CMOS transistor having a fully depleted SOI structure, as a transistor forming the analog circuit unit 101 and the logic circuit unit 102, rather than using a normal bulk CMOS transistor.

[0110] Here, in order to realize FBB potential control, a CMOS transistor having an SOI structure which is preferably used as a transistor forming the analog circuit unit 101 and the logic circuit unit 102 will be described compared to a bulk CMOS transistor.

[0111] Figure 6 2 is a cross-sectional view showing a cross-sectional structure of a CMOS transistor, for explaining a CMOS transistor having a fully depleted SOI structure compared to a bulk CMOS transistor. Figure 6 In FIG. 1 , “a” is a cross-sectional structure of a CMOS transistor having a fully depleted SOI structure, and Figure 6 The "b" in FIG. 1 is the cross-sectional structure of a bulk CMOS transistor.

[0112] Here, for a CMOS transistor having a fully depleted SOI structure and a bulk CMOS transistor, an N-type MOS transistor 201 and a P-type MOS transistor 202 connected in series with each other are shown. The N-type MOS transistor 201 and the P-type MOS transistor 202 are connected in series at a low potential side power supply voltage V SS (for example, 0.0V) and the high potential side power supply voltage V DD (e.g., 0.8V) between nodes.

[0113] As in Figure 6 The "a" and Figure 6 As shown in “b” of FIG. 1 , an N-type well 213 and a P-type well 214 are formed on a deep N-type well 212 on a P-type semiconductor substrate 211, and an N-type MOS transistor 201 and a P-type MOS transistor 202 are formed on the N-type MOS transistor 201 and the P-type MOS transistor 202. In the case of a CMOS transistor having an SOI structure, the N-type MOS transistor 201 and the P-type MOS transistor 202 are formed on a silicon-on-insulator (SOI) 215 formed on the N-type well 213 and the P-type well 214.

[0114] In a CMOS transistor having an SOI structure, an FBB potential (i.e., a potential in a direction of lowering the threshold voltage Vth) can be applied as a body potential to the N-type well 213 and the P-type well 214, which are doped to surround the transistor structure of the N-type MOS transistor 201 and the P-type MOS transistor 202. More specifically, a potential of ±0.5V or more (to ±2.0V) can be applied as a body potential. Through this FBB potential control, the threshold voltage Vth of the N-type MOS transistor 201 and the P-type MOS transistor 202 is reduced, thereby improving performance.

[0115] The FBB potential (i.e., the potential in the direction of lowering the threshold voltage Vth of the transistor) is a positive potential (e.g., 0.0V to +2.0V) in the case of the N-type MOS transistor 201, and is a negative potential (e.g., 0.0V to -2.0V) in the case of the P-type MOS transistor 202.

[0116] Also in Figure 6 In the bulk CMOS transistor shown in "b", the FBB potential can be controlled in the case of a triple well structure. However, since the diode component is turned on in the forward direction, the potential that can be applied as the bulk potential is limited to ±0.5V.

[0117] In addition, by using CMOS transistors having a fully depleted SOI structure as transistors forming the analog circuit unit 101 and the logic circuit unit 102, and reducing the threshold voltage Vth by FBB potential control to improve performance, lower power consumption can be achieved. Specifically, by increasing the margin of the minimum operating power supply voltage Vmin by the performance amount obtained by FBB potential control, power consumption can be reduced.

[0118] Figure 7 shows the relationship between power consumption and performance. Figure 7 In the characteristic curve diagram, the horizontal axis represents frequency, the vertical axis represents dynamic current consumption, and the power consumption on the lower side of the vertical axis is smaller. Figure 7 As shown in the characteristic diagram, at the power supply voltage V DD When the voltage is reduced from, for example, 0.8 V to, for example, 0.65 V, the current consumption can be reduced by FBB potential control while maintaining equivalent characteristics, thereby achieving lower power consumption.

[0119] [2-4. Operation and Effect of FBB Potential Control on Analog Circuit Unit]

[0120] Here, the operation and effect in the case where the FBB potential is applied to the transistor forming the analog circuit unit 101 will be described. Figure 1 The analog circuit unit 101, the vertical scanning unit 12, Figure 2The load MOS circuit 33 and the structure Figure 3 The comparator 52 is at the input stage of the analog-to-digital conversion circuit 51.

[0121] Figure 8 is a circuit diagram showing a circuit embodiment of the analog circuit unit 101. Figure 8 In the above example, “a” is Figure 1 A circuit embodiment of a transfer stage 121 of the vertical scanning unit 12, and Figure 8 The "b" is composed of Figure 3 A circuit embodiment of a comparator 52 at the input stage of an analog-to-digital conversion circuit 51 in FIG.

[0122] like Figure 8 As shown in "a", a transfer stage 121 of the vertical scanning unit 12 includes a transfer stage 121 connected in series with a high potential side power supply voltage V DD The node is connected to the low potential side power supply voltage V SS A P-type MOS transistor 1211 and an N-type MOS transistor 1212 are provided between the nodes of the transistor 1211 and the transistor 1212 , and level shifters 1213 and 1214 are connected to the respective gates of the two transistors 1211 and 1212 .

[0123] In one transfer stage 121 of the vertical scanning unit 12 having the above-described configuration, by performing FBB potential control on the P-type MOS transistor 1211 and the N-type MOS transistor 1212, the transconductance gm of the P-type MOS transistor 1211 and the N-type MOS transistor 1212 can be increased, so that it is possible to improve the rising time and the falling time of the output pulse of the vertical scanning unit 12. As a result, the charge transfer time of the pixel 20 becomes faster, and therefore, it is possible to increase the frame rate (fps) or reduce power consumption by an amount earned by increasing the speed.

[0124] As in Figure 8 As shown in "b" of FIG. 1 , the comparator 52 includes a differential pair of transistors 521 and 522, and the differential pair of transistors 521 and 522 include an N-type MOS transistor constituting a current mirror circuit, a constant current source 523, and P-type MOS transistors 524 and 525. A ramp wave reference signal RAMP is input to the gate of one differential pair of transistors 521, and an analog pixel signal Vsig is input to the gate of the other differential pair of transistors 522.

[0125] In the comparator 52 having the above configuration, by performing FBB potential control on the differential pair transistors 521 and 522, the transconductance gm of the two transistors 521 and 522 can be increased, so that the bandwidth of the comparator 52 can be widened. Therefore, since the operation of the comparator 52 becomes high-speed, the frame rate (fps) can be increased or the power consumption can be reduced by the amount obtained by increasing the speed.

[0126] Note that here, as the control target circuit of the analog circuit unit 101, one transfer stage 121 of the vertical scanning unit 12 and the comparator 52 constituting the input stage of the analog-to-digital conversion circuit 51 have been described. However, Figure 2 The load MOS circuit 33 in may be a control target circuit.

[0127] exist Figure 2 In the load MOS circuit 33, by performing FBB potential control on the MOS transistor constituting the constant current source 34, the change in the threshold voltage Vth of the MOS transistor can be suppressed, and therefore, the change in the constant current source 34 can be suppressed. Thus, the size of the MOS transistor constituting the constant current source 34 can be reduced to a degree that can suppress the change in the constant current source 34, and the leakage power can be reduced.

[0128] <3. First embodiment of the present technology>

[0129] The first embodiment of the present technology is an example in which the body potential is controlled for each operation mode of the imaging element.

[0130] [3-1. Configuration Example of Imaging Element According to First Embodiment]

[0131] Fig. 9 is a block diagram showing a configuration example of an imaging element according to a first embodiment of the present technology.

[0132] like Fig. 9 As shown in FIG. 1 , the imaging element 10 according to the first embodiment of the present technology has a configuration including an analog circuit unit 101, a logic circuit unit 102, a body potential generating unit 103, and a control unit 104. The functions of the analog circuit unit 101, the logic circuit unit 102, the body potential generating unit 103, and the control unit 104 are similar to those of FIG. Figure 5 The situation of the imaging element 10 shown is basically the same.

[0133] In the imaging element 10 of the first embodiment, for each operation mode of the imaging element 10 specified from the outside, the body potential applied to the transistors constituting the analog circuit unit 101 and the logic circuit unit 102 is controlled. Examples of the operation mode of the imaging element 10 include a hardware standby mode, a software standby mode, a normally-on mode, and a flow mode.

[0134] These operation modes are well-known operation modes in imaging elements installed on electronic devices such as smart phones. Specifically, the hardware standby mode is one of the power saving functions, and is a mode that puts all modules except the internal random access memory (RAM) into a reset state. The software standby mode is one of the power saving functions, and is a mode for stopping the central processing unit (CPU), oscillator, etc. The always-on mode is a mode in which power is partially supplied even when the device body is in a sleep state, and only a specific function is always in an operating state. The streaming mode is a mode in which still image capture and moving image capture are performed.

[0135] [3-2. Body potential control for each operation mode]

[0136] Fig.10 : is a table for explaining the human body potential control in each operation mode in the imaging element 10 according to the first embodiment of the present technology.

[0137] In the imaging element 10 of the first embodiment, the control unit 104 controls the body potential at the time of FBB potential control for each operation mode of the imaging element 10 specified externally, specifically, for each operation mode of the imaging element 10 specified by the external application processor 70 .

[0138] The control unit 104 controls the body potential applied to the transistors forming the analog circuit unit 101 and the logic circuit unit 102 for each of the hardware standby mode, the software standby mode, the always-on mode, and the streaming mode.

[0139] Specifically, in the hardware-standby mode, the software-standby mode, and the normally-on mode, the control unit 104 performs ZBB potential control on the body potential to be applied to the transistors forming the analog circuit unit 101 and the logic circuit unit 102. Since leakage power can be suppressed by ZBB potential control, lower power consumption can be achieved.

[0140] In addition, in the flow mode, the control unit 104 performs FBB potential control on the body potential to be applied to the transistor forming the logic circuit unit 102. This FBB potential control can improve performance. At this time, the body potential to be applied to the transistor forming the analog circuit unit 101 is subject to ZBB potential control. The flow mode includes a still image capture mode and a motion image capture mode.

[0141] When the operation mode is the streaming mode, the control unit 104 controls the human body potential according to each of the still image capturing mode and the moving image capturing mode. Specifically, in the FBB potential control in the streaming mode, the control unit 104 fixes the adaptive body bias (ABB) potential in the still image capturing mode ( Fig.10As a result, grayscale at certain midpoints in a still image can be avoided. In addition, in the FBB potential control in the streaming mode, the control unit 104 sequentially processes the ABB potential in the moving image capturing mode ( Fig.10 Note 2 in ). As a result, temperature fluctuations during 8K motion image capture can be handled sequentially.

[0142] [3-3. Switching of operation mode]

[0143] Fig.11 : is a state transition diagram showing state transition of the operation mode in the imaging element according to the first embodiment of the present technology.

[0144] When the power-off state is switched to the power-on state, the state is switched to the hardware standby mode. In the case where the sensing mode is selected in the hardware-standby mode, the state is switched to the sensing (motion detection) mode through the software-standby mode. In addition, in the case where the viewing mode is selected in the hardware-standby mode, the state is switched to the still image capture mode or the motion image capture mode through the software-standby mode.

[0145] The control unit 104 performs FBB potential control according to the state transition of the above-mentioned operation mode. In the still image capturing mode, FBB potential control is basically performed, but adaptive control for applying ABB potential (hereinafter, described as ABB potential control) can also be performed. In the moving image capturing mode, FBB potential control or ABB potential control is performed.

[0146] like Fig. 9 As shown in , the imaging element 10 according to the first embodiment of the present technology has a configuration in which the logic circuit unit 102 is divided into a stream function block 1021 that performs a stream function and an always-on function block 1022 that performs an always-on function. This block division can be achieved by a separation hole.

[0147] For the logic circuit unit 102 divided into the flow function block 1021 and the always-on function block 1022, compared with the always-on function block 1022, the control unit 104 applies a high potential above 0V to the N-type well as the body potential to be applied to the transistor forming the logic circuit unit 102 in the flow function block 1021, and applies a low potential below 0V to the P-type well.

[0148] In this way, the logic circuit unit 102 is divided into a flow function block 1021 and a normally-on function block 1022, and a high potential above 0 V is applied to the N-type well and a low potential below 0 V is applied to the P-type well in the flow function block 1021, compared to the normally-on function block 1022. Therefore, the threshold voltage can be lowered to increase the performance of the flow function block 1021.

[0149] <4. Second embodiment of the present technology>

[0150] The second embodiment of the present technology is an example of controlling body potential along with a characteristic fluctuation factor of an imaging element.

[0151] [4-1. Configuration Example of Imaging Element According to Second Embodiment]

[0152] Fig.12 is a block diagram showing a configuration example of an imaging element according to a second embodiment of the present technology.

[0153] Here, as an embodiment, two divided analog blocks (1) 101-1 and (2) 101-2 are shown as an analog circuit unit 101 as a control target circuit, and two divided logic blocks (1) 102-1 and (2) 102-2 are shown as a logic circuit unit 102 as a control target circuit. The division of the analog block (1) 101-1 and the analog block (2) 101-2 and the division of the logic block (1) 102-1 and the logic block (2) 102-2 can be achieved by separation wells.

[0154] The body potential is applied from the body potential generating circuit (1) 103-1 and the body potential generating circuit (2) 103-2 in the body potential generating unit 103 to the two logic blocks (1) 102-1 and (2) 102-2 in the logic circuit unit 102. In addition, the body potential is applied from the body potential generating circuit (3) 103-3 and the body potential generating circuit (4) 103-4 in the body potential generating unit 103 to the two analog blocks (1) 101-1 and (2) 101-2 in the analog circuit unit 101.

[0155] The control unit 104 is used to control the body potential applied to each of the analog circuit unit 101 and the logic circuit unit 102, and includes a characteristic fluctuation factor monitoring circuit 1041, an OTP (one-time memory) 1042 as an embodiment of a semiconductor switch IC, and four registers 1043-1 to 1043-4.

[0156] [4-2. Arrangement of Circuit Units Constituting Imaging Element of Second Embodiment]

[0157] Fig.13 1 shows an embodiment of the arrangement image of the analog circuit unit 101, the logic circuit unit 102, the body potential generating unit 103, the characteristic fluctuation factor monitoring circuit 1041 and the OTP 1042. Fig.13 in, omit Fig.12 Illustration of the four registers 1043-1 to 1043-4 in FIG.

[0158] In the control unit 104, the characteristic variation factor monitoring circuit 1041 monitors the characteristic variation factor of the imaging element 10, specifically, the variation of the characteristic variation factor. Examples of the variation of the characteristic variation factor include variation of the process (P), variation of the junction temperature (T), and variation of the power supply voltage (V).

[0159] The characteristic variation factor monitoring circuit 1041 provides the monitoring result of the variation of the characteristic variation factor to the body potential generating unit 103 via the OTP 1042 and the four registers 1043-1 to 1043-4. The body potential generating unit 103 controls the body potential applied to the transistors forming the analog circuit unit 101 and the logic circuit unit 102 according to the monitoring result of the variation of the characteristic fluctuation factor obtained by the characteristic fluctuation factor monitoring circuit 1041.

[0160] [4-3. Example of controlling body potential according to PVT changes]

[0161] Fig.14 : is a block diagram showing a configuration example of the characteristic fluctuation factor monitoring circuit 1041 in the imaging element according to the second embodiment.

[0162] like Fig.14 As shown, the characteristic fluctuation factor monitoring circuit 1041 includes a PVT change detection sensor 10411 and a comparison calculation unit 10412.

[0163] The PVT variation detection sensor 10411 monitors at least one of the variation of the process (P), the variation of the junction temperature (T), and the variation of the power supply voltage (V). The variation in the process can be detected as a "result state of the process", such as SS (PMOS: Slow, NMOS: Slow), TT (PMOS: Typical, NMOS: Typical), and FF (PMOS: Fast, NMOS: Fast). Here, "Slow" represents a high threshold voltage, "Fast" represents a low threshold voltage, and "Typical" represents an intermediate value.

[0164] The PVT change detection sensor 10411 may be configured, for example, by using an oscillator of a phase-locked loop (PLL) circuit, etc. The comparison calculation unit 10412 calculates a control value for controlling the body potential generating unit 103 based on the detection result of the PVT change obtained by the PVT change detection sensor 10411. The comparison calculation unit 10412 may be configured to use a table that stores the detection result of the PVT change obtained by the PVT change detection sensor 10411 and the control value to be used for controlling the body potential generating unit 103 in a corresponding relationship.

[0165] As described above, by adaptively controlling the output potential of the body potential generating unit 103 along with PVT changes, that is, the body potential to be applied to the transistors forming the analog circuit unit 101 and the logic circuit unit 102, changes in the entire imaging element can be absorbed.

[0166] Here, we will refer to Fig.15 Describes an image of the PVT variation detection sensor 10411 when monitoring the resulting state of the process (P).

[0167] exist Fig.15 In the figure, "a" is a graph for explaining the result state of processes such as SS, TT, and FF. The solid line in the figure represents TT (PMOS: Typical, NMOS: Typical). The dotted line in the figure represents SS (PMOS: Slow, NMOS: Slow), that is, the result state of the process is poor (Slow). The dot-dash line in the figure represents FF (PMOS: Fast, NMOS: Fast), that is, the result state of the process is good (Fast).

[0168] In the product inspection stage, the result state of the inspection process is a product of SS. Then, by FBB potential control, control is performed in which a predetermined body potential is applied from the body potential generation unit 103 to the transistors forming the analog circuit unit 101 and the logic circuit unit 102 to transfer the result state of the process to the TT side. For products whose result state of the process is TT or FF, FBB potential control is unnecessary because there is a margin.

[0169] exist Fig.15 In the figure, "b" shows an image of the body potential adjustment by the body potential generating unit 103. In the figure, the result state (change) of the process can be grasped from the gradient of the voltage-frequency characteristic represented by the inclined straight line (SS: dotted line, TT: solid line, FF: dot-dash line). Then, when the result state of the process is SS, FBB potential control is performed.

[0170] Next, we will refer to Fig.16 Describe the relationship between the minimum operating power supply voltage Vmin and process variation.

[0171] Fig.16 is a graph for explaining the relationship between the minimum operating power supply voltage Vmin and the variation of the process. Fig.16 In the figure, "a" shows the characteristic of the minimum operating power supply voltage Vmin under ABB potential control, and Fig.16 "b" shows the characteristics of the minimum operating power supply voltage Vmin under the ZBB potential control.

[0172] like Fig.16As shown in "a" of , lower power consumption can be achieved by FBB potential control, and yield can be improved by ABB potential control (adaptive control). As described above, by using CMOS transistors with a fully depleted SOI structure as transistors forming the analog circuit unit 101 and the logic circuit unit 102, it is possible to simultaneously achieve reduced power consumption by FBB potential control and improved yield by ABB potential control. In other words, by using CMOS transistors with a fully depleted SOI structure as transistors forming the analog circuit unit 101 and the logic circuit unit 102, it is possible to simultaneously achieve lower power consumption by FBB potential control and improved yield by ABB potential control.

[0173] By the way, if Fig.16 As shown in "b" of FIG. 1 , when the ZBB potential is applied, the characteristic degradation occurs by about 30%. That is, the process variation is large, and the SS (PMOS: Slow, NMOS: Slow) in the logic circuit unit 102 is one of the factors that reduce the yield. In order not to reduce the yield, it is necessary to increase the power and area.

[0174] [4-4. Example of controlling body potential based on changes in saturated electron count and conversion efficiency]

[0175] In the above-described embodiment, the body potential is controlled by following changes in process (P), junction temperature (T), and power supply voltage (V). However, in the present embodiment, the body potential is controlled based on changes in the saturated electron count Qs of the pixel and the conversion efficiency η (uV / e-) of the pixel.

[0176] Fig.17 : is a circuit diagram for explaining the saturated electron count Qs of a pixel and the conversion efficiency η of the pixel. Here, the saturated electron count Qs of a pixel is the saturated electron count of the photoelectric conversion unit 21 (for example, a photodiode of a PN junction). The conversion efficiency η of a pixel is the charge-to-voltage conversion efficiency (uV / e-) of the signal amplification unit 25. The change (result state) of the saturated electron count Qs and the conversion efficiency η can be grasped using a known mass production tester.

[0177] The characteristic fluctuation factor monitoring circuit 1041 (see Fig.14 ), by replacing the PVT change detection sensor 10411 with the mass production tester described above, the body potential can be controlled by FBB potential control according to the resultant state (change) of the saturated electron count Qs and the conversion efficiency η. The FBB potential control here is a FBB or ABB potential control with a fixed potential.

[0178] As described above, by adaptively controlling the body potential applied to the transistors forming the analog circuit unit 101 and the logic circuit unit 102 according to the resulting state (change) of the pixel's saturated electron count Qs and the pixel's conversion efficiency η, changes in the entire imaging element can be absorbed.

[0179] Note that here, FBB potential control is performed according to the resultant states of both the saturated electron count Qs of the pixel and the conversion efficiency η of the pixel. However, FBB potential control may be performed according to the resultant state of one of the saturated electron count Qs of the pixel and the conversion efficiency η of the pixel.

[0180] <5. Modifications>

[0181] It should be noted that the above-mentioned embodiments show examples for embodying the present technology, and the various contents in the embodiments and the various contents specifying the present invention in the claims have a corresponding relationship. Similarly, the matters specifying the present invention in the claims have a corresponding relationship with the matters with the same names in the embodiments of the present technology. However, the present technology is not limited to the embodiments, and can be embodied by applying various modifications to the embodiments without departing from the scope of the present technology.

[0182] <6. Available configurations for this technology>

[0183] It should be noted that the present technology may also have the following configurations.

[0184] (1) An imaging element, comprising:

[0185] an analog circuit unit including pixels that perform photoelectric conversion;

[0186] a logic circuit unit configured to process a signal read out from the pixel;

[0187] a body potential generating unit configured to apply a body potential in a direction of lowering a threshold voltage to a well in a transistor forming a logic circuit unit, the well being doped to surround a transistor structure; and

[0188] A control unit is configured to control the body potential for each operation mode specified from the outside.

[0189] (2) The imaging element according to (1), wherein

[0190] When the operation mode is the streaming operation mode, the control unit controls the body potential according to each of the still image capturing mode and the moving image capturing mode.

[0191] (3) The imaging element according to (2), wherein

[0192] The logic circuit unit is divided into flow function blocks and always-on function blocks, and

[0193] Compared with the normally-on functional block, the control unit applies a high potential higher than or equal to 0V to the N-type well in the flow functional block, and applies a low potential lower than or equal to 0V to the P-type well in the flow functional block as the body potential.

[0194] (4) The imaging element according to (1), wherein

[0195] The body potential generating unit applies a zero potential to a well in a transistor forming a logic circuit unit, the well being doped to surround the transistor structure.

[0196] (5) The imaging element according to (1), wherein

[0197] The body potential generating unit applies a body potential in a direction of lowering a threshold voltage to a well in a transistor forming a logic circuit unit, the well being doped to surround the transistor structure.

[0198] (6) The imaging element according to any one of (1) to (5), wherein

[0199] Each of the transistors forming the logic circuit unit and the transistors forming the analog circuit unit is a MOS transistor having a fully depleted silicon-on-insulator structure.

[0200] (7) An imaging element comprising:

[0201] an analog circuit unit including pixels that perform photoelectric conversion;

[0202] a logic circuit unit configured to process a signal read out from the pixel; and

[0203] A body potential generating unit is configured to apply a body potential in a direction of lowering a threshold voltage to a well in a transistor forming a logic circuit unit, the well being doped to surround the transistor structure.

[0204] (8) The imaging element according to (7), wherein

[0205] The body potential generating unit controls the body potential according to the characteristic fluctuation factor of the imaging element.

[0206] (9) The imaging element according to (8), wherein

[0207] The characteristic fluctuation factor is at least one of a process variation, a junction temperature variation, and a power supply voltage variation.

[0208] (10) The imaging element according to (7), wherein

[0209] The body potential generating unit controls the body potential according to at least one of a result state of a saturated electron count of the pixel and a result state of a conversion efficiency of the pixel.

[0210] (11) The imaging element according to (7), wherein

[0211] The body potential generating unit applies a zero potential to a well in a transistor forming a logic circuit unit, the well being doped to surround the transistor structure.

[0212] (12) The imaging element according to (7), wherein

[0213] The body potential generating unit applies a body potential in a direction of lowering a threshold voltage to a well in a transistor forming a logic circuit unit, the well being doped to surround the transistor structure.

[0214] (13) The imaging element according to any one of (7) to (12), wherein

[0215] Each of the transistors forming the logic circuit unit and the transistors forming the analog circuit unit is a MOS transistor having a fully depleted silicon-on-insulator structure.

[0216] (14) An electronic device comprising:

[0217] imaging element; and

[0218] an operation mode designation unit configured to designate an operation mode of the imaging element, wherein

[0219] Imaging components include:

[0220] an analog circuit unit including pixels that perform photoelectric conversion;

[0221] a logic circuit unit configured to process a signal read out from the pixel;

[0222] a body potential generating unit configured to apply a body potential in a direction of lowering a threshold voltage to a well in a transistor forming a logic circuit unit, the well being doped to surround a transistor structure; and

[0223] A control unit is configured to control the body potential for each operation mode specified by the operation mode specifying unit.

[0224] Reference Symbols List

[0225] 10 Imaging Components

[0226] 11 Pixel Array Unit

[0227] 12 vertical scanning units

[0228] 13 columns of processing units

[0229] 14 horizontal scanning units

[0230] 15 Digital signal calculation unit

[0231] 16 Timing control unit

[0232] 20 pixels (pixel circuit)

[0233] 21 Photoelectric conversion unit

[0234] 22 Charge transfer unit

[0235] 23 Charge-voltage conversion unit

[0236] 24 Charge reset unit

[0237] 25 Signal Amplification Unit

[0238] 26 pixel selection unit

[0239] 31 pixel control lines

[0240] 32 signal lines

[0241] 33 Load MOS circuit

[0242] 34 Constant current source

[0243] 50 analog-to-digital conversion units

[0244] 51 Analog-to-digital conversion circuit

[0245] 52 Comparator

[0246] 53 column counter

[0247] 60 reference signal generation unit

[0248] 70 Application Processor

[0249] 80 Power supply circuit unit

[0250] 101 Analog Circuit Unit

[0251] 102 Logic Circuit Unit

[0252] 103 Body potential generating unit

[0253] 104 Control Unit

[0254] 1041 Characteristic Fluctuation Factor Monitoring Circuit

[0255] 1042OTP (one-time storage)

[0256] 1043-1 to 1043-4 registers.

Claims

1. An imaging element, comprising: an analog circuit unit including pixels that perform photoelectric conversion; a logic circuit unit configured to process a signal read out from the pixel; a body potential generating unit configured to apply a body potential in a direction of lowering a threshold voltage to a well in a transistor forming the logic circuit unit, the well being doped to surround a transistor structure; as well as A control unit is configured to control the body potential for each operation mode specified from the outside.

2. The imaging element according to claim 1, wherein When the operation mode is a streaming operation mode, the control unit controls the body potential according to each of a still image capturing mode and a moving image capturing mode.

3. The imaging element according to claim 2, wherein: The logic circuit unit is divided into a flow function block and a normal function block, and Compared with the normally-on functional block, the control unit applies a high potential higher than or equal to 0V to the N-type well in the flow functional block, and applies a low potential lower than or equal to 0V to the P-type well in the flow functional block as the body potential.

4. The imaging element according to claim 1, wherein The body potential generating unit applies a zero potential to a well in a transistor of the analog circuit unit, the well being doped to surround a transistor structure.

5. The imaging element according to claim 1, wherein The body potential generating unit applies a body potential in a direction of lowering a threshold voltage to a well in a transistor forming the analog circuit unit, the well being doped to surround a transistor structure.

6. The imaging element according to claim 1, wherein Each of the transistors forming the logic circuit unit and the transistors forming the analog circuit unit is a metal oxide semiconductor (MOS) transistor having a fully depleted silicon-on-insulator structure.

7. An imaging element, comprising: an analog circuit unit including pixels that perform photoelectric conversion; a logic circuit unit configured to process a signal read out from the pixel; as well as A body potential generating unit is configured to apply a body potential in a direction of lowering a threshold voltage to a well in a transistor forming the logic circuit unit, the well being doped to surround the transistor structure.

8. The imaging element according to claim 7, wherein: The body potential generating unit controls the body potential along with a characteristic fluctuation factor of the imaging element.

9. The imaging element according to claim 8, wherein: The characteristic fluctuation factor is at least one of a process variation, a junction temperature variation, and a power supply voltage variation.

10. The imaging element according to claim 7, wherein: The body potential generating unit controls the body potential according to at least one of a result state of a saturated electron count of the pixel and a result state of a conversion efficiency of the pixel.

11. The imaging element according to claim 7, wherein: The body potential generating unit applies a zero potential to a well in a transistor of the analog circuit unit, the well being doped to surround a transistor structure.

12. The imaging element according to claim 7, wherein: The body potential generating unit applies a body potential in a direction of lowering a threshold voltage to a well in a transistor forming the analog circuit unit, the well being doped to surround a transistor structure.

13. The imaging element according to claim 7, wherein: Each of the transistors forming the logic circuit unit and the transistors forming the analog circuit unit is a MOS transistor having a fully depleted silicon-on-insulator structure.

14. An electronic device comprising: Imaging element; as well as an operation mode designation unit configured to designate an operation mode of the imaging element, wherein: The imaging element comprises: an analog circuit unit including pixels that perform photoelectric conversion; a logic circuit unit configured to process a signal read out from the pixel; a body potential generating unit configured to apply a body potential in a direction of lowering a threshold voltage to a well in a transistor forming the logic circuit unit, the well being doped to surround a transistor structure; and A control unit is configured to control the body potential for each operation mode specified by the operation mode specifying unit.

Images