Solid-state imaging device and comparison device

Abstract

[Problem] To perform comparison of high-speed and high-performance signals. [Solution] A solid-state imaging device includes a comparison circuit, a first switch, a second switch, a third switch, a first capacitor, and a second capacitor. The comparison circuit includes a non-inverting input terminal and an inverting input terminal. The first switch is connected to the inverting input terminal. The second switch is connected to the inverting input terminal and is controlled at a time different from a time of the first switch. The third switch is connected between the output terminal and the inverting input terminal of the comparison circuit. One end of the first capacitor is connected to the inverting input terminal via the first switch, and a reference signal is applied to the other end of the first capacitor. One end of the second capacitor is connected to the inverting input terminal via the second switch, and the other end of the second capacitor is applied with a reference signal.

Description

Technical Field

[0001] The present disclosure relates to a solid-state imaging device and a comparison device. Background Art

[0002] The technology of providing a column analog-to-digital converter (ADC) in an image sensor and performing AD conversion on each column of pixels is widely used. In the case of accelerating AD conversion or adapting to a global shutter, a device that converts the output of a pixel into the output of a comparator instead of an analog signal by building a differential amplifier circuit in the pixel can be used as a device to accelerate signal transmission.

[0003] In this method, since the charge output from the photodiode is directly sampled to the capacitor, it is difficult to increase the capacitance value, and the influence of the sampling switch on the kT / C noise is large. In addition, it is difficult to automatically reset the differential amplifier circuit. As a result, it is impossible to eliminate the offset of the differential input circuit and the change of the reset voltage, and it is necessary to increase the range of the reset voltage, that is, to extend the reading time of the reset voltage. As a result, there is a problem of extending the AD conversion time or reducing the dynamic range instead of shortening the AD conversion time. Citation List Patent Literature

[0004] Patent Document 1: U.S. Patent Application Publication No. 2016 / 0360138 Summary of the invention Problem that the invention aims to solve

[0005] Therefore, in the present disclosure, a comparison of high-speed and high-performance signals is achieved. Note that the problem to be solved by the embodiments of the present disclosure may be a problem corresponding to the effects described in the embodiments as some non-limiting examples. That is, a problem corresponding to at least one of the effects described in the description of the embodiments of the present disclosure may be solved in the present disclosure. Solution to the problem

[0006] According to the embodiment, a solid-state imaging device includes a comparison circuit, a first switch, a second switch, a third switch, a first capacitor, and a second capacitor. The comparison circuit includes a non-inverting input terminal and an inverting input terminal. The first switch is connected to the inverting input terminal. The second switch is connected to the inverting input terminal and is controlled at a timing different from that of the first switch. The third switch is connected between the output terminal of the comparison circuit and the inverting input terminal. One end of the first capacitor is connected to the inverting input terminal via the first switch, and the other end is applied with a reference signal. One end of the second capacitor is connected to the inverting input terminal via the second switch, and the other end is applied with the reference signal.

[0007] The comparison circuit may include: a first transistor having a control terminal connected to the non-inverting input terminal and one end connected to a positive-side power supply voltage; and A second transistor has a control terminal connected to the inverting input terminal, one end connected to the other end of the first transistor, the other end of the second transistor is connected to the third switch, and an output signal is output from the other end of the second transistor.

[0008] The non-inverting input terminal may be connected to a floating diffusion region in the pixel circuit.

[0009] The third switch may be turned on at a time when the signal is sampled.

[0010] At the time of sampling the reset level of the floating diffusion region, The first switch may be turned on, The second switch may continue to be in an open state, The first capacitor may sample the signal based on the reset level using the standard value of the reference signal as a standard potential via the comparison circuit and the third switch, and The first switch may be turned off after the first capacitor performs sampling.

[0011] At the time of sampling the signal level output from the light receiving element, The first switch may continue to be in an open state, The second switch may be turned on at the sampling time, The second capacitor may sample the signal level using a standard value of the reference signal as a standard potential via the floating diffusion, the comparison circuit, and the third switch, and The second switch may be turned off after the second capacitor performs sampling.

[0012] The third switch may be turned off at the time of the comparison signal.

[0013] At the time of reading the reset level of the floating diffusion region, The first switch may be turned on, The second switch may continue to be in an open state, A ramp signal may be input to the other end of the first capacitor as the reference signal, and The first switch may be turned off after a signal output from the comparison circuit is inverted.

[0014] At the time of reading the signal level output from the light receiving element, The first switch may continue to be in an open state, The second switch may be turned on, A ramp signal may be input to the other end of the second capacitor as the reference signal, and The second switch may be turned off after a signal output from the comparison circuit is inverted.

[0015] A plurality of light receiving elements may be connected.

[0016] Each of the plurality of light receiving elements may include the first switch, the first capacitor, the second switch, and the second capacitor.

[0017] According to an embodiment, a comparison device includes a comparison circuit, a first switch, a second switch, a third switch, a first capacitor, and a second capacitor. The comparison circuit includes a non-inverting input terminal and an inverting input terminal. The first switch is connected to the inverting input terminal. The second switch is connected to the inverting input terminal and is controlled at a timing different from that of the first switch. The third switch is connected between the output terminal of the comparison circuit and the inverting input terminal. One end of the first capacitor is connected to the inverting input terminal via the first switch, and the other end is applied with a reference signal. One end of the second capacitor is connected to the inverting input terminal via the second switch, and the other end is applied with the reference signal. BRIEF DESCRIPTION OF THE DRAWINGS

[0018] Figure 1 is a diagram showing an example of a pixel circuit according to the embodiment. Figure 2 is a diagram showing an example of a timing chart of a pixel circuit comparator according to the embodiment. Figure 3 is a diagram showing an example of a pixel circuit according to the embodiment. Figure 4 is a diagram showing an example of a pixel circuit according to the embodiment. Figure 5 is a diagram showing an example of a pixel circuit according to the embodiment. Figure 6 is a diagram showing a mounting example of a semiconductor chip according to the embodiment. Figure 7 is a diagram showing a mounting example of a semiconductor chip according to the embodiment. Figure 8 is a block diagram showing an example of a schematic configuration of a vehicle control system. Fig. 9 1 is an explanatory diagram showing an example of the installation positions of the vehicle exterior information detection section and the imaging section. DETAILED DESCRIPTION

[0019] The embodiments of the present disclosure are described below with reference to the accompanying drawings. The accompanying drawings are for illustration, and the shape and size of each component in the actual device, the size ratio with other components, etc. are not necessarily as shown in the accompanying drawings. In addition, since the accompanying drawings are shown in a simplified manner, it should be understood that components other than those shown in the accompanying drawings are appropriately provided for implementation.

[0020] (First Implementation Method) Figure 1 is a diagram showing an example of a pixel circuit according to an embodiment. The pixel circuit 1 includes a light receiving element P, a transmission switch Trg, a reset switch Rst, an FD capacitor Cfd, a comparison circuit Cmp, a first switch Sw1, a first capacitor C1, a second switch Sw2, a second capacitor C2, and a third switch Sw3. The pixel circuit 1 converts a signal corresponding to the intensity of the received light into a digital timing signal and outputs the digital timing signal. For example, the pixel circuit 1 can be adopted in a light receiving unit of a solid-state imaging device.

[0021] For example, the light receiving element P includes a photodiode. The light receiving element P converts light incident on a light receiving area into an analog signal through photoelectric conversion, and outputs a signal based on the intensity of the incident light.

[0022] The transfer switch Trg is connected between the output terminal (cathode) of the light receiving element P and the floating diffusion region FD. The transfer switch Trg is a switch that transfers the signal output from the light receiving element P to the floating diffusion region FD at an appropriate time. When the transfer switch Trg is turned on, the analog signal converted by the light receiving element P is transferred to the floating diffusion region FD.

[0023] The reset switch Rst is connected between the positive side power supply voltage VDD and the floating diffusion region FD. The switch resets the floating diffusion region FD with the power supply voltage VDD at an appropriate time. When the reset switch Rst is turned on, the potential of the floating diffusion region FD is reset to a predetermined potential (reset level).

[0024] The FD capacitor Cfd is connected between the floating diffusion region FD and a negative power supply voltage (eg, ground potential). The FD capacitor Cfd is charged and discharged by a current flowing into or out of the floating diffusion region FD, and is a capacitance that appropriately defines the potential of the floating diffusion region FD.

[0025] The potential of the floating diffusion region FD is determined by charging and discharging the electric charge of the FD capacitor Cfd by the transfer switch Trg and the reset switch Rst.

[0026] In the comparison circuit Cmp, a non-inverting input terminal is connected to the floating diffusion region FD, an inverting input terminal is connected to the first switch Sw1 and the second switch Sw2, and an output terminal is connected via the third switch Sw3 in a negative feedback state. The comparison circuit Cmp is driven in two modes: a sampling mode and a comparator mode.

[0027] In the sampling mode, the comparison circuit Cmp feeds back a current based on a signal input from the non-inverting input terminal to the inverting input terminal side. Each capacitor samples the potential of the floating diffusion region FD by the feedback current.

[0028] In the comparator mode, the non-inverting input terminal of the comparison circuit Cmp is connected to the floating diffusion region FD without performing negative feedback. The comparison circuit Cmp compares the voltage of the floating diffusion region FD with the reference voltage input from the inverting input terminal, converts the comparison result into a digital signal, and outputs the digital signal. With respect to the output signal, the time when the signal is inverted in an external circuit such as a counter is acquired, and the intensity of the incident light converted by the light receiving element P can be acquired as a digital value.

[0029] The first switch Sw1 is connected between the first capacitor C1 and the inverting input terminal of the comparison circuit Cmp. The second switch Sw2 is connected between the second capacitor C2 and the inverting input terminal of the comparison circuit Cmp.

[0030] The third switch Sw3 is connected between the output terminal and the inverting input terminal of the comparison circuit Cmp. The third switch Sw3 is turned on at the sampling time, and is turned off at the signal comparison time.

[0031] These switches are turned on / off at predetermined times, and perform the following operations: charging and discharging the capacitor in the sampling mode, and outputting a comparison result based on the potential charged in the capacitor in the comparator mode.

[0032] One end of the first capacitor C1 is connected to the first switch Sw1, and a reference signal is applied to the other end. One end of the second capacitor C2 is connected to the second switch Sw2, and a reference signal is applied to the other end.

[0033] Figure 2 1 is a diagram showing a timing chart according to an embodiment of the present invention. From the top, the on / off states of the transmission switch Trg, the reset switch Rst, the first switch Sw1, the second switch Sw2, and the third switch Sw3, and the potential transitions of the reference signal REF, the floating diffusion region FD, the region VN, and the output voltage OUT are shown.

[0034] In the state where the third switch Sw3 is turned on, that is, in the signal sampling state, the reset switch Rst is turned on, and the floating diffusion region FD is set to the reset level. In this state, the region VN changes to a potential based on the reset level of the floating diffusion region FD via the third switch Sw3. The first switch Sw1 and the second switch Sw2 remain in the off state.

[0035] By turning on the first switch Sw1 in this state, a potential based on the reset level is applied to the first capacitor C1. At this time, the reference voltage REF maintains the standard voltage (initial value) of the ramp signal to be compared. Therefore, the potential of the first capacitor C1 rises from the standard level of the reference voltage REF by a potential based on the reset level of the floating diffusion region FD.

[0036] After a time sufficient to read the reset level has passed, the first switch Sw1 is turned off. At this time, the potential based on the reset level of the floating diffusion region FD is held in the region FD via the third switch Sw3.

[0037] After the first switch Sw1 is turned off, the transmission switch Trg is turned on to transmit the signal level output from the light receiving element P to the floating diffusion region FD. When the floating diffusion region FD becomes the signal level, the region VN is converted to a potential based on the signal level via the comparison circuit Cmp and the turned-on third switch Sw3. After a sufficient time has passed from the start of the signal transmission, the transmission switch Trg is turned off.

[0038] In this state, by turning on the second switch Sw2, a potential based on the signal level is applied to the second capacitor C2. Therefore, the potential of the second capacitor C2 rises from the standard level of the reference voltage REF by a potential based on the signal level of the floating diffusion region FD.

[0039] After a time sufficient to read the signal level has passed, the second switch Sw2 is turned off. Through this series of operations, a potential based on the reset level is set to the first capacitor C1, and a potential based on the signal level is set to the second capacitor C2.

[0040] As described above, in the pixel circuit 1 , a potential based on the reset level and a potential based on the signal level are set in the capacitor on the inverting input terminal side of the comparison circuit Cmp.

[0041] Subsequently, the pixel circuit 1 is changed to a comparator mode, in which the comparison circuit Cmp operates as a comparator. In the comparator mode, the third switch Sw3 is turned off. That is, at the time of signal comparison, the third switch Sw3 is turned off.

[0042] After the third switch Sw3 is turned off, the reset switch Rst is turned on to set the floating diffusion region FD to a reset level.

[0043] Next, the first switch Sw1 is turned on, and a ramp signal is input to the reference signal REF. When the first capacitor C1 is connected to the inverting input terminal and the reference signal REF is used as the ramp signal, a ramp signal based on the potential stored in the first capacitor C1 is applied to the inverting input terminal of the comparison circuit Cmp. When the potential applied to the inverting input terminal becomes equal to the potential of the non-inverting input terminal, that is, when the potential becomes equal to the voltage sampled by the first capacitor C1, the output of the comparison circuit Cmp is inverted, and the output voltage VOUT is turned from high to low.

[0044] After a sufficient time has passed since the output voltage VOUT was inverted, the first switch Sw1 is turned off. For example, the time may be the time until the ramp signal reaches a predetermined value.

[0045] When the output voltage VOUT is high, the reset level is detected by reading a count value synchronized with the ramp signal through a latch, a counter, or the like provided outside the pixel circuit 1 .

[0046] Subsequently, the pixel circuit 1 reads the signal level. When reading the signal level, the second switch Sw2 is turned on, and the ramp signal is input to the reference signal REF. When the second capacitor C2 is connected to the inverting input terminal and the reference signal REF is used as the ramp signal, the ramp signal based on the potential stored in the second capacitor C2 is applied to the inverting input terminal of the comparison circuit Cmp. Similar to the above, when the potential applied to the inverting input terminal becomes equal to the potential of the non-inverting input terminal, the output voltage VOUT changes from high to low.

[0047] After a sufficient time has passed since the output voltage VOUT was inverted, the second switch Sw2 is turned off. For example, the time may be the time until the ramp signal reaches a predetermined value.

[0048] When the output voltage VOUT is high, the signal level is detected by reading the count value synchronized with the ramp signal by a latch, a counter, etc. provided outside the pixel circuit 1. By obtaining the difference between the signal level and the reset level, a digital signal of the signal level from which noise has been removed can be obtained.

[0049] As described above, according to the present embodiment, the solid-state imaging device can set the output of the comparison circuit Cmp as the output of the pixel circuit 1. By performing the comparison in the pixel circuit, it is possible to output an appropriate comparison signal at high speed for each pixel without reducing the dynamic range. In the ADC configured outside the pixel circuit, it is possible to appropriately acquire a signal based on the intensity of light incident on the light receiving element by reading a counter synchronized with a ramp signal.

[0050] (Second Implementation Method) Figure 3 1 is a diagram showing an example of mounting a pixel circuit according to the embodiment. The pixel circuit 1 can be mounted separately in a pixel chip including a light receiving element P and a logic chip of an output comparison circuit Cmp.

[0051] For example, a pixel chip includes a light receiving area of ​​a pixel array, and includes a light receiving element and a circuit for appropriately outputting an analog signal. For example, a logic chip is a chip including a circuit that performs signal sampling and comparison and outputs a high / low digital signal as an output voltage, an ADC that performs subsequent processing, a signal processing circuit, an image processing circuit, a storage circuit, an input / output interface, etc.

[0052] Each of the transfer switch Trg and the reset switch Rst may be composed of an n-type MOSFET. By applying an appropriate voltage to the gate at an appropriate time, the resetting and signal transmission processing of the floating diffusion region FD is performed.

[0053] On the output end (e.g., cathode) side of the light receiving element P, a discharge transistor Ofg and a transfer transistor Trg may be provided. The discharge transistor Ofg is a transistor that discharges the charge accumulated on the output end side of the light receiving element P at an appropriate time. For example, the discharge transistor Ofg may be composed of an n-type MOSFET. The discharge transistor Ofg discharges and resets the charge accumulated on the output end of the light receiving element P by applying an appropriate voltage to the gate at an appropriate time.

[0054] The comparison circuit Cmp includes a first transistor M1, a second transistor M2, and a third transistor M3.

[0055] For example, the first transistor M1 is an n-type MOSFET, and its gate operates as a non-inverting input terminal of the comparison circuit Cmp. For example, the drain of the first transistor M1 is connected to the positive side power supply voltage VDD.

[0056] For example, the second transistor M2 is a p-type MOSFET, and its gate operates as an inverting input terminal of the comparison circuit Cmp. For example, the source of the first transistor M2 is connected to the source of the first transistor M1, and its drain is connected to the output terminal of the comparison circuit Cmp.

[0057] For example, the third transistor M3 is an n-type MOSFET, whose drain is connected to the drain of the second transistor M2, whose source is connected to the negative side power supply voltage (e.g., ground voltage), and the bias voltage is applied to the gate of the third transistor M3. For example, the bias voltage can be a signal for selecting a row in the pixel array. That is, the output of the comparison circuit Cmp can be controlled by the voltage applied to the gate of the third transistor M3.

[0058] For example, each of the first switch Sw1, the second switch Sw2, and the third switch Sw3 may be an n-type MOSFET. In each of these switches, a signal for performing drive control is applied to a gate at an appropriate time, and the above-described operation is performed.

[0059] According to the example Figure 3 In the configuration of the present invention, when the third switch Sw3 is turned on in the sampling mode, the comparison circuit Cmp operates as a voltage follower having the voltage of the floating diffusion region FD as an input. As a result, the output impedance can be reduced, and appropriate signals can be maintained in the first capacitor C1 and the second capacitor C2 regardless of the load of the first switch Sw1 and the second switch Sw2, and the kT / C noise caused by these switches can be reduced. In addition, according to this circuit configuration, since a voltage follower and a comparator can also be used, the area of ​​the circuit can be maintained small.

[0060] In addition, in the sampling mode, the reset level is held in the first capacitor C1, and the held potential can be read out in the comparator mode. That is, the reset level can be read from the reset state. Therefore, before reading the reset level, signal comparison can be started without performing the automatic zero setting of the circuit charge state again. As a result, it is possible to shorten the AD conversion time and expand the dynamic range without increasing the automatic zero execution time.

[0061] (Third Implementation Option) For example, in a pixel chip, the pixel circuits described in the above embodiments are arranged in a two-dimensional array in the row direction and the column direction to form a pixel array. In the pixel array, for example, a light receiving element is specified by a horizontal direction control circuit for selecting a row and a vertical direction control circuit for specifying a column. The signal from the specified light receiving element is transmitted to the circuit of the logic chip, and processing such as AD conversion is performed.

[0062] Figure 4 1 is a diagram showing a connection example of a pixel circuit according to an embodiment. In this diagram, only one column of pixel circuits is shown, but the pixel circuit and circuits such as ADC are appropriately provided for each column or each plurality of columns.

[0063] Each pixel circuit 1 provided in a column is connected to a column unit circuit 20. The column unit circuit 20 is a circuit provided for each column in a logic chip. The column unit circuit 20 includes a latch / counter 200, an input transistor 202, and a current source 204.

[0064] The latch / counter 200 calculates a count value based on the high / low signal output from the pixel circuit 1, subtracts a reset level from the signal level, and acquires a pixel value from which noise is removed. For example, the latch / counter 200 counts the number of clocks synchronized with the rise (or fall) of the ramp signal to acquire the count value of the ramp signal, and calculates the pixel value based on the acquired count value.

[0065] For example, the input transistor 202 is an n-type MOSFET. When a signal output from the pixel circuit 1 is applied to the gate and a high signal is applied to the gate, a drain current flows. When a low signal is applied to the gate, a current output from the current source 204 flows to the latch / counter 200.

[0066] That is, when the output of the pixel circuit 1 is high, the current output from the current source 204 flows to the latch / counter 200, and flows to the ground point when the output of the pixel circuit 1 is low. As a result, the latch / counter 200 can perform appropriate counting based on the current flowing from the current source 204.

[0067] Note that in the above description, a column unit circuit, that is, a circuit operating as a column ADC has been described, but the present invention is not limited to this. For example, a circuit operating as an ADC may be set as a circuit in units of pixels, a circuit in units of multiple columns, or a circuit in units of areas.

[0068] Furthermore, a switch may be provided between the pixel circuit 1 and the column unit circuit 20. The switch is a switch that is turned on in the selected row, and through the switch, the output from the selected pixel circuit 1 can be acquired.

[0069] In the case of a circuit in units of multiple columns or a circuit in units of area, the switch can be operated as a switch that is turned on when the switch is specified by row and column. Through this operation, these circuits can perform AD conversion on the signal from the appropriate pixel.

[0070] (Fourth Implementation Scheme) Figure 5 1 is a diagram showing an example of a pixel circuit 1 according to an embodiment. In each of the above embodiments, one comparison circuit is provided for one light receiving element, but the mode of the present disclosure is not limited thereto. That is, a plurality of light receiving elements may share a comparison circuit.

[0071] At least a portion of the comparison circuit Cmp may be shared by a plurality of pixels (a plurality of light receiving elements). Figure 5 As shown, some transistors (the second transistor M2 and the third transistor M3 ) of the comparison circuit Cmp can be shared between the pixel 1 and the pixel 2 .

[0072] As shown in the figure, a transfer transistor Trg, a reset transistor Rst, and a drain transistor Ofg are provided for each pixel, and first transistors M1_1 and M1_2 are provided as part of a comparison circuit Cmp so as to be connected to floating diffusion regions FD1 and FD2 , respectively.

[0073] In this case, selection transistors Sel1 and Sel2 for selectively driving the pixels may also be provided between the drain of the first transistor and the power supply voltage to control the driving of each pixel.

[0074] The same signal can be input to the transfer transistor, the reset transistor, and the drain transistor at the same time. In this case, by appropriately driving the selection transistor, the output of pixel 1 and the output of pixel 2 can be switched.

[0075] On the logic chip side, a capacitor for sampling and reading is provided for each pixel. By providing a capacitor for each pixel in this way, the same-phase input / output can be realized collectively.

[0076] For example, first, the output of pixel 1 is realized by turning on the selection transistor Sel1 and turning off the selection transistor Sel2. Similar to the above sampling mode, the reset level of pixel 1 is sampled by the first capacitor C1_1 by controlling the first switch Sw1_1, the second switch Sw2_1 and the third switch Sw3 at this time.

[0077] Subsequently, the reset level of the pixel 2 is sampled by the first capacitor C1_2 by turning off the selection transistor Sel1 , turning on the selection transistor Sel2 , and controlling the first switch Sw2_2 , the second switch Sw2_2 , and the third switch Sw3 .

[0078] Subsequently, by turning on the selection transistor Sel1, turning off the selection transistor Sel2 and further driving the transfer transistor, the signal values ​​generated by the light receiving elements P1 and P2 are read into the floating diffusion regions FD1 and FD2, respectively. Then, by controlling the first switch Sw1_1, the second switch Sw2_1 and the third switch Sw3, the signal level of the pixel 1 is sampled by the second capacitor C2_1.

[0079] Subsequently, the signal level of the pixel 1 is sampled by the second capacitor C2_2 by turning off the selection transistor Sel1 , turning on the selection transistor Sel2 , and controlling the first switch Sw1_2 , the second switch Sw2_2 , and the third switch Sw3 .

[0080] Note that this order is not limited to this. For example, after sampling of the reset level is completed, the signal level of pixel 2 can be sampled in the second capacitor C2_2 without changing the state of the selection transistor, and then the signal level of pixel 1 can be sampled in the second capacitor C2_1 after controlling the selection state.

[0081] Furthermore, the floating diffusion region FD may be shared.

[0082] In the above description, although the mode in which two pixels share a part of the comparison circuit Cmp has been described, three or more light receiving elements may share a part of the comparison circuit Cmp. Also in this case, the signal value of each pixel can be appropriately acquired by switching in a similar manner.

[0083] As described above, according to the configuration of the pixel circuit of this embodiment, the circuit area can be further reduced compared to each of the above embodiments. In this case as well, the accuracy of the signal value can be improved compared to the ordinary pixel circuit, and the time of AD conversion can be reduced without deteriorating the dynamic range.

[0084] Figure 6 1 is a non-limiting example of an image sensor chip 3 including the pixel circuit 1 according to the above-described embodiment. In the solid-state imaging device, the image sensor chip 3 may be formed of a first semiconductor layer 31 and a second semiconductor layer 32 as different semiconductor layers. The first semiconductor layer 31 includes a light receiving region 300 in which the pixel circuits 1 are arranged in a two-dimensional array, and the second semiconductor layer 32 includes a storage circuit 302 and a processing circuit 304.

[0085] For example, in Figure 3 and Figure 5 In the embodiment, the first semiconductor layer 31 is a pixel chip, and the second semiconductor layer 32 is a logic chip.

[0086] The first semiconductor layer 31 and the second semiconductor layer 32 are stacked to form an integrated semiconductor device and operate. For example, the first semiconductor layer 31 is arranged closer to an optical system for converging incident light on a light receiving element than the second semiconductor layer 32, and light passing through the optical system is received by the first semiconductor layer 31, and a signal is output to the second semiconductor layer 32.

[0087] Figure 7It is another embodiment different from the above. The solid-state imaging element can be mounted on the first semiconductor layer 31, the second semiconductor layer 32, and the third semiconductor layer 33 as different semiconductor layers. The first semiconductor layer 31 includes a light receiving area 300, the second semiconductor layer 32 includes a processing circuit 304, and the third semiconductor layer 33 includes a storage circuit 302. The first semiconductor layer 31, the second semiconductor layer 32, and the third semiconductor layer 33 are stacked and formed into an integrated semiconductor device, and operate. For example, the first semiconductor layer 31 is arranged closest to the optical system, the light via the optical system is received by the first semiconductor layer 31, and the signal is output to at least one of the second semiconductor layer 32 and the third semiconductor layer 33.

[0088] exist Figure 6 and Figure 7 In the case of the form shown, for example, the semiconductor layer may adopt a chip on chip (CoC: chip on chip) method in which the semiconductor layer is cut from a wafer, separated into individual pieces, and then vertically stacked and bonded to each other. In addition, a chip on wafer (CoW: chip on wafer) method may be adopted in which any layer is cut out and separated into individual pieces, which are then bonded to a wafer. Alternatively, a wafer on wafer (WoW: wafer on wafer) method may be adopted in which a plurality of wafers are bonded to each other and then separated into individual pieces.

[0089] To bond the semiconductor layers, vias, micro bumps, micro pads, plasma bonding, etc. may be used as non-limiting examples. By this method, the semiconductor layers are properly electrically connected and formed to be able to send and receive signals.

[0090] The technology according to the present disclosure can be applied to various products. For example, the technology according to the present disclosure can also be implemented as a device installed on any type of mobile body such as an automobile, an electric car, a hybrid electric car, a motorcycle, a bicycle, a personal mobile device, an airplane, an unmanned aerial vehicle, a ship, a robot, a construction machine, or an agricultural machine (tractor).

[0091] Figure 8 7000 is a block diagram showing an example of a schematic configuration of a vehicle control system 7000 as an example of a mobile body control system to which the disclosed technology is applied. The vehicle control system 7000 includes a plurality of electronic control units connected to each other via a communication network 7010. Figure 8In the example shown, the vehicle control system 7000 includes a drive system control unit 7100, a body system control unit 7200, a battery control unit 7300, an external information detection unit 7400, an internal information detection unit 7500, and an integrated control unit 7600. For example, the communication network 7010 connecting the plurality of control units to each other may be an in-vehicle communication network conforming to any standard such as a controller area network (CAN), a local interconnect network (LIN), a local area network (LAN), FlexRay (registered trademark), or the like.

[0092] Each control unit includes: a microcomputer that executes algorithm processing according to various programs; a storage unit that stores programs executed by the microcomputer, parameters for various operations, etc.; and a drive circuit that drives various control object devices. Each control unit also includes: a network interface (I / F) for communicating with other control units via the communication network 7010; and a communication I / F for communicating with devices, sensors, etc. inside and outside the vehicle through wired or wireless communication. Figure 8 , a microcomputer 7610, a general communication I / F 7620, a dedicated communication I / F 7630, a positioning unit 7640, a beacon receiving unit 7650, an in-vehicle device I / F 7660, a sound / image output unit 7670, an in-vehicle network I / F 7680, and a storage unit 7690 are shown as the functional configuration of the integrated control unit 7600. Other control units also include a microcomputer, a communication I / F, a storage unit, and the like.

[0093] The drive system control unit 7100 controls the operation of devices related to the drive system of the vehicle according to various programs. For example, the drive system control unit 7100 is used as a control device for the following devices: a drive force generating device such as an internal combustion engine, a drive motor, etc. for generating the drive force of the vehicle, a drive force transmitting mechanism for transmitting the drive force to the wheels, a steering mechanism for adjusting the steering angle of the vehicle, a braking device for generating the braking force of the vehicle, etc. The drive system control unit 7100 may have a function as a control device for an anti-lock braking system (ABS), an electronic stability control (ESC), etc.

[0094] The drive system control unit 7100 is connected to the vehicle state detection unit 7110. For example, the vehicle state detection unit 7110 includes at least one of a gyro sensor for detecting the angular velocity of the axial rotational motion of the vehicle body, an acceleration sensor for detecting the acceleration of the vehicle, and a sensor for detecting the amount of operation of the accelerator pedal, the amount of operation of the brake pedal, the steering angle of the steering wheel, the engine speed, or the wheel speed, etc. The drive system control unit 7100 performs algorithm processing using the signal input from the vehicle state detection unit 7110, and controls the internal combustion engine, the drive motor, the electric steering device, the brake device, etc.

[0095] The body system control unit 7200 controls the operation of various devices provided on the body according to various programs. For example, the body system control unit 7200 is used as a control device for a keyless entry system, a smart key system, a power window device, or various lights such as headlights, reverse lights, brake lights, turn signals, fog lights, etc. In this case, radio waves or signals of various switches transmitted from a mobile device as a substitute for a key may be input to the body system control unit 7200. The body system control unit 7200 receives these input radio waves or signals and controls the door lock device, power window device, lights, etc. of the vehicle.

[0096] The battery control unit 7300 controls the secondary battery 7310 as a power source for driving the motor according to various programs. For example, information about the battery temperature, the battery output voltage, the remaining amount of power in the battery, etc. is provided to the battery control unit 7300 from the battery device including the secondary battery 7310. The battery control unit 7300 performs algorithm processing using these signals, and performs control for adjusting the temperature of the secondary battery 7310 or control of a cooling device provided in the battery device, etc.

[0097] The vehicle exterior information detection unit 7400 detects information about the exterior of the vehicle including the vehicle control system 7000. For example, the vehicle exterior information detection unit 7400 is connected to at least one of the imaging unit 7410 and the vehicle exterior information detection unit 7420. The imaging unit 7410 includes at least one of a time-of-flight (ToF) camera, a stereo camera, a monocular camera, an infrared camera, and other cameras. For example, the vehicle exterior information detection unit 7420 includes at least one of an environmental sensor for detecting current atmospheric conditions or weather conditions and a peripheral information detection sensor for detecting other vehicles, obstacles, pedestrians, and the like around the vehicle including the vehicle control system 7000.

[0098] For example, the environmental sensor may be at least one of a raindrop sensor for detecting rain, a fog sensor for detecting fog, a sunshine sensor for detecting the degree of sunshine, and a snow sensor for detecting snowfall. The peripheral information detection sensor may be at least one of an ultrasonic sensor, a radar device, and a LIDAR (LIDAR: light detection and ranging or laser imaging detection and ranging) device. Each of the imaging unit 7410 and the vehicle exterior information detection unit 7420 may be provided as an independent sensor or device, or may be provided as a device in which a plurality of sensors or devices are integrated.

[0099] here, Fig. 9A diagram showing an example of the installation position of the imaging unit 7410 and the vehicle exterior information detection unit 7420. For example, the imaging units 7910, 7912, 7914, 7916 and 7918 are arranged at least one of the positions on the front nose, side mirrors, rear bumper and rear door of the vehicle 7900 and the position on the upper part of the windshield inside the vehicle. The imaging unit 7910 arranged on the front nose and the imaging unit 7918 arranged on the upper part of the windshield inside the vehicle mainly obtain images in front of the vehicle 7900. The imaging units 7912 and 7914 arranged on the side mirrors mainly obtain images on the side of the vehicle 7900. The imaging unit 7916 arranged on the rear bumper or rear door mainly obtains images behind the vehicle 7900. The imaging unit 7918 arranged on the upper part of the windshield inside the vehicle is mainly used to detect the front vehicle, pedestrians, obstacles, signals, traffic signs, lanes, etc.

[0100] Notice, Fig. 9 Examples of imaging ranges of the respective imaging units 7910, 7912, 7914, and 7916 are shown. Imaging range a represents the imaging range of the imaging unit 7910 provided on the front nose. Imaging ranges b and c represent the imaging ranges of the imaging units 79124 and 79142 provided on the side mirrors, respectively. Imaging range d represents the imaging range of the imaging unit 7916 provided on the rear bumper or the rear door. For example, a bird's-eye view image of the vehicle 7900 viewed from above can be obtained by superimposing image data imaged by the imaging units 7910, 7912, 7914, and 7916.

[0101] For example, the vehicle exterior information detection units 7920, 7922, 7924, 7926, 7928, and 7930 disposed at the front, rear, sides, and corners of the vehicle 7900 and the upper portion of the windshield inside the vehicle may be ultrasonic sensors or radar devices. For example, the vehicle exterior information detection units 7920, 7926, and 7930 disposed at the front nose of the vehicle 7900, the rear bumper, the rear door of the vehicle 7900, and the upper portion of the windshield inside the vehicle may be LIDAR devices. These vehicle exterior information detection units 7920-7930 are mainly used to detect vehicles ahead, pedestrians, obstacles, and the like.

[0102] Return to Figure 8, continue to explain. The vehicle exterior information detection unit 7400 enables the imaging unit 7410 to image the image outside the vehicle and receive the image data of the imaging. In addition, the vehicle exterior information detection unit 7400 receives detection information from the vehicle exterior information detection unit 7420 connected to the vehicle exterior information detection unit 7400. In the case where the vehicle exterior information detection unit 7420 is an ultrasonic sensor, a radar device or a LIDAR device, the vehicle exterior information detection unit 7400 transmits ultrasonic waves, electromagnetic waves, etc., and receives information of the received reflected waves. The vehicle exterior information detection unit 7400 can perform detection processing of objects such as people, vehicles, obstacles, signs, characters on the road surface, etc. based on the received information, or perform detection processing of the distance therebetween. The vehicle exterior information detection unit 7400 can perform environmental recognition processing of identifying rainfall, fog, road conditions, etc. based on the received information. The vehicle exterior information detection unit 7400 can calculate the distance to the object outside the vehicle based on the received information.

[0103] In addition, the vehicle exterior information detection unit 7400 can perform image recognition processing for identifying people, vehicles, obstacles, signs, characters on the road surface, etc. based on the received image data, or perform detection processing of the distance therebetween. The vehicle exterior information detection unit 7400 can perform processing such as distortion correction, alignment, etc. on the received image data, and synthesize the image data imaged by multiple different imaging units 7410 to generate a bird's-eye view image or a panoramic image. The vehicle exterior information detection unit 7400 can perform viewpoint conversion processing using the image data imaged by the imaging unit 7410 including different imaging parts.

[0104] The in-vehicle information detection unit 7500 detects information about the interior of the vehicle. For example, the in-vehicle information detection unit 7500 is connected to a driver state detection unit 7510 that detects the driver's state. The driver state detection unit 7510 may include a camera that images the driver, a biosensor that detects the driver's biometric information, a microphone that collects sounds inside the vehicle, and the like. For example, the biosensor is arranged in a seat surface, a steering wheel, and the like, and detects the biometric information of an occupant sitting in a seat or a driver holding the steering wheel. The in-vehicle information detection unit 7500 can calculate the driver's fatigue level or the driver's concentration level based on the detection information input from the driver state detection unit 7510, or can determine whether the driver is taking a nap. The in-vehicle information detection unit 7500 can perform processing such as noise elimination processing on the audio signal obtained by sound collection.

[0105] The integrated control unit 7600 controls the overall operation within the vehicle control system 7000 according to various programs. The integrated control unit 7600 is connected to the input unit 7800. For example, the input unit 7800 is implemented by a device such as a touch panel, a button, a microphone, a switch, a joystick, etc., which can be input by the occupant. Data obtained by voice recognition of a voice input via a microphone can be supplied to the integrated control unit 7600. For example, the input unit 7800 can be a remote control device using infrared or other radio waves, or an external connection device such as a mobile phone, a personal digital assistant (PDA), etc. that supports the operation of the vehicle control system 7000. For example, the input unit 7800 can be a camera. In this case, the occupant can input information through gestures. Alternatively, data obtained by detecting the movement of a wearable device worn by the occupant can be input. In addition, for example, the input unit 7800 may include an input control circuit that generates an input signal based on information input by the occupant or the like using the above-mentioned input unit 7800 and outputs the generated input signal to the integrated control unit 7600. The occupant or the like inputs various data or gives instructions for processing operations to the vehicle control system 7000 through the operation input unit 7800 .

[0106] The storage unit 7690 may include a read-only memory (ROM) storing various programs executed by the microcomputer and a random access memory (RAM) storing various parameters, operation results, sensor values, etc. In addition, the storage unit 7690 may be implemented by a magnetic storage device such as a hard disk drive (HDD), a semiconductor storage device, an optical storage device, a magneto-optical storage device, or the like.

[0107] The general communication I / F 7620 is a widely used communication I / F that mediates communication with various devices present in the external environment 7750. The general communication I / F 7620 may implement cellular communication protocols such as Global System for Mobile Communications (GSM (registered trademark)), Worldwide Interoperability for Microwave Access (WiMAX (registered trademark)), Long Term Evolution (LTE (registered trademark)), Advanced LTE (LTE-A), or other wireless communication protocols such as wireless LAN (also known as Wireless Fidelity (Wi-Fi (registered trademark)), Bluetooth (registered trademark), etc.). For example, the general communication I / F 7620 may be connected to a device (e.g., an application server or a control server) present on an external network (e.g., the Internet, a cloud network, or a company private network) via a base station or an access point. In addition, for example, the general communication I / F 7620 may be connected to a terminal present near the vehicle (e.g., the terminal is a terminal of a driver, a pedestrian, or a store, or a machine type communication (MTC) terminal) using a peer-to-peer (P2P) technology.

[0108] The dedicated communication I / F 7630 is a communication I / F that supports a communication protocol developed for vehicle use. For example, the dedicated communication I / F 7630 may implement a standard protocol such as Wireless Access in Vehicular Environments (WAVE), a dedicated short range communication (DSRC), or a cellular communication protocol that is a combination of the Institute of Electrical and Electronics Engineers (IEEE) 802.11p as a lower layer and IEEE 1609 as an upper layer. The dedicated communication I / F 7630 generally performs V2X communication as a concept including one or more of communication between vehicles (vehicle to vehicle), communication between roads and vehicles (vehicle to infrastructure), communication between vehicles and residences (vehicle to residence), and communication between pedestrians and vehicles (vehicle to pedestrian).

[0109] For example, the positioning unit 7640 performs positioning by receiving a GNSS satellite signal (e.g., a GPS signal from a Global Positioning System (GPS) satellite) from a satellite of a Global Navigation Satellite System (GNSS), and generates position information including the latitude, longitude, and altitude of the vehicle. Incidentally, the positioning unit 7640 may identify the current position by exchanging signals with a wireless access point, or may obtain position information from a terminal such as a mobile phone, a personal handyphone system (PHS), or a smart phone having a positioning function.

[0110] For example, the beacon receiving unit 7650 receives radio waves or electromagnetic waves transmitted from a radio station installed on the road, etc., thereby obtaining information on the current position, congestion, closed roads, necessary time, etc. Incidentally, the function of the beacon receiving unit 7650 may be included in the above-mentioned dedicated communication I / F 7630.

[0111] The in-vehicle device I / F 7660 is a communication interface that mediates the connection between the microcomputer 7610 and various in-vehicle devices 7760 present in the vehicle. The in-vehicle device I / F 7660 can establish a wireless connection using a wireless communication protocol such as wireless LAN, Bluetooth (registered trademark), near field communication (NFC), or wireless universal serial bus (WUSB). In addition, the in-vehicle device I / F 7660 can establish a wired connection through a universal serial bus (USB), a high-definition multimedia interface (HDMI (registered trademark)), a mobile high-definition link (MHL), etc. via a connection terminal not shown in the figure (if necessary, it can also be via a cable). For example, the in-vehicle device 7760 may include at least one of a mobile device and a wearable device owned by an occupant and an information device carried into or attached to the vehicle. The in-vehicle device 7760 may also include a navigation device that searches for a path to an arbitrary destination. The in-vehicle device I / F 7660 exchanges control signals or data signals with these in-vehicle devices 7760.

[0112] The in-vehicle network I / F 7680 is an interface which mediates communication between the microcomputer 7610 and the communication network 7010. The in-vehicle network I / F 7680 transmits and receives signals and the like according to a predetermined protocol supported by the communication network 7010.

[0113] The microcomputer 7610 of the integrated control unit 7600 controls the vehicle control system 7000 according to various programs based on information obtained via at least one of the general communication I / F 7620, the dedicated communication I / F 7630, the positioning unit 7640, the beacon receiving unit 7650, the in-vehicle device I / F 7660, and the in-vehicle network I / F 7680. For example, the microcomputer 7610 can calculate the control target value of the driving force generation device, the steering mechanism, or the braking device based on the information obtained about the inside and outside of the vehicle, and output a control command to the drive system control unit 7100. For example, the microcomputer 7610 can perform cooperative control aimed at realizing the functions of the advanced driver assistance system (ADAS), which include vehicle collision avoidance or collision mitigation, follow-up driving based on the following distance, vehicle speed maintenance driving, vehicle collision warning, lane departure warning of the vehicle, etc. In addition, the microcomputer 7610 can perform cooperative control aimed at automatic driving, which makes the vehicle automatically travel without relying on the operation of the driver, etc. by controlling the driving force generation device, the steering mechanism, the braking device, etc. based on the information obtained about the surroundings of the vehicle.

[0114] The microcomputer 7610 can generate three-dimensional distance information between the vehicle and objects such as surrounding structures and people based on information obtained via at least one of the general communication I / F 7620, the dedicated communication I / F 7630, the positioning unit 7640, the beacon receiving unit 7650, the in-vehicle device I / F 7660, and the vehicle network I / F 7680, and generate local map information including information about the surroundings of the current position of the vehicle. In addition, the microcomputer 7610 can predict dangers such as vehicle collision, approach of pedestrians, etc., entering a closed road, etc. based on the obtained information, and generate a warning signal. For example, the warning signal can be a signal for generating a warning sound or lighting a warning light.

[0115] The sound / image output unit 7670 transmits an output signal of at least one of sound and image to an output device, which can visually or auditorily notify the vehicle occupants or the outside of the vehicle of information. Figure 8In the example of , an audio speaker 7710, a display unit 7720, and an instrument panel 7730 are shown as output devices. For example, the display unit 7720 may include at least one of an in-vehicle display and a head-up display. The display unit 7720 may have an augmented reality (AR) display function. The output device may be a device other than these devices, and may be other devices such as headphones, wearable devices such as glasses-type displays worn by passengers, projectors, lights, etc. In the case where the output device is a display device, the display device visually displays the results obtained by various processes performed by the microcomputer 7610 or information received from other control units in various forms such as text, images, tables, charts, etc. In addition, in the case where the output device is an audio output device, the audio output device converts an audio signal composed of reproduced audio data or sound data, etc. into an analog signal, and outputs the analog signal audibly.

[0116] Note that Figure 8 In the example shown, at least two control units connected to each other via the communication network 7010 can be integrated into one control unit. Alternatively, each control unit may include multiple control units. In addition, the vehicle control system 7000 may include other control units not shown in the figure. In addition, part or all of the functions performed by one of the control units in the above description can be assigned to other control units. In other words, as long as information is sent and received via the communication network 7010, the predetermined algorithm processing can be performed by any control unit. Similarly, a sensor or device connected to one of the control units in the control unit can be connected to other control units, and multiple control units can send and receive detection information to each other via the communication network 7010.

[0117] Note that for implementations including reference Figures 1 to 7 The computer program for each function of the solid-state imaging device of the pixel circuit 1 of the illustrated embodiment or the electronic device including the solid-state imaging device can be installed on any control unit, etc. In addition, a computer-readable recording medium storing such a computer program can be provided. The recording medium is, for example, a magnetic disk, an optical disk, a magneto-optical disk, a flash memory, etc. In addition, without using a recording medium, the above-mentioned computer program can be distributed via, for example, a network.

[0118] In the vehicle control system 7000, the Figures 1 to 7 The solid-state imaging device of the pixel circuit 1 of the illustrated embodiment or an electronic device including the solid-state imaging device can be applied to, for example, Figure 8 The imaging unit 7410, the vehicle exterior information detection unit 7420, or the driver state detection unit 7510 of the illustrated application example performs at least a part of the imaging unit.

[0119] In addition, refer to Figures 1 to 7 At least a subset of the components of the illustrated pixel circuit 1 may be in Figure 8 The integrated control unit 7600 shown in FIG. 7600 is implemented in a module (eg, an integrated circuit module including a bare chip). Figure 6 and Figure 7 The image sensor chip 3 described can be used in Figure 8 The vehicle control system 7000 shown is implemented on multiple control units.

[0120] The above-mentioned embodiment may have the following modes. (1) A solid-state imaging device comprising: a comparison circuit having a non-inverting input terminal and an inverting input terminal; a first switch connected to the inverting input terminal; a second switch connected to the inverting input terminal and controlled at a different time than that of the first switch; a third switch connected between the output terminal of the comparison circuit and the inverting input terminal; a first capacitor having one end connected to the inverting input terminal via the first switch and the other end to which a reference signal is applied; and A second capacitor has one end connected to the inverting input terminal via the second switch and the reference signal applied to the other end. (2) The solid-state imaging device according to (1), wherein The comparison circuit comprises: a first transistor having a control terminal connected to the non-inverting input terminal and one end connected to a positive-side power supply voltage; and A second transistor has a control terminal connected to the inverting input terminal, one end connected to the other end of the first transistor, the other end of the second transistor is connected to the third switch, and an output signal is output from the other end of the second transistor. (3) The solid-state imaging device according to (1) or (2), wherein: The non-inverting input terminal is connected to a floating diffusion region in the pixel circuit. (4) The solid-state imaging device according to (3), wherein The third switch is turned on at a time when a signal is sampled. (5) The solid-state imaging device according to (4), wherein At the time of sampling the reset level of the floating diffusion region, The first switch is turned on, The second switch continues to be in the off state, The first capacitor samples the signal based on the reset level using the standard value of the reference signal as a standard potential via the comparison circuit and the third switch, and The first switch is turned off after the first capacitor performs sampling. (6) The solid-state imaging device according to (4) or (5), wherein At the time of sampling the signal level output from the light receiving element, The first switch continues to be in an off state, The second switch is turned on at the sampling time, The second capacitor samples the signal level using a standard value of the reference signal as a standard potential via the floating diffusion, the comparison circuit, and the third switch, and The second switch is turned off after the second capacitor performs sampling. (7) The solid-state imaging device according to any one of (3) to (6), wherein The third switch is turned off at the time of the comparison signal. (8) The solid-state imaging device according to (7), wherein At the time of reading the reset level of the floating diffusion region, The first switch is turned on, The second switch continues to be in the off state, A ramp signal is input to the other end of the first capacitor as the reference signal, and The first switch is turned off after the signal output from the comparison circuit is inverted. (9) The solid-state imaging device according to (7) or (8), wherein At the time of reading the signal level output from the light receiving element, The first switch continues to be in an off state, The second switch is turned on, A ramp signal is input to the other end of the second capacitor as the reference signal, and The second switch is turned off after the signal output from the comparison circuit is inverted. (10) The solid-state imaging device according to any one of (1) to (9), wherein A plurality of light receiving elements are connected. (11) The solid-state imaging device according to (10), wherein Each of the plurality of light receiving elements includes the first switch, the first capacitor, the second switch, and the second capacitor. (12) A comparison device, comprising: a comparison circuit having a non-inverting input terminal and an inverting input terminal; a first switch connected to the inverting input terminal; a second switch connected to the inverting input terminal and controlled at a different time than that of the first switch; a third switch connected between the output terminal of the comparison circuit and the inverting input terminal; a first capacitor having one end connected to the inverting input terminal via the first switch and the other end to which a reference signal is applied; and A second capacitor has one end connected to the inverting input terminal via the second switch and the reference signal applied to the other end.

[0133] The aspects of the present disclosure are not limited to the above-mentioned embodiments, but include various conceivable deformations, and the effects of the present disclosure are not limited to the above-mentioned contents. The components in each embodiment can be appropriately combined and applied. That is, various additions, deformations and partial deletions can be made without departing from the conceptual ideas and key points of the present disclosure derived from the contents defined in the claims and their equivalents, etc.

[0134] 1 pixel circuit Sw1 first switch Sw2 second switch Sw3 third switch C1 first capacitor C2 Second capacitor Cmp comparison circuit M1 first transistor M2 second transistor M3 third transistor Trg transfer switch Rst reset switch Ofg discharge transistor FD floating diffusion area CfdFD capacitor P light receiving element 20 columns of unit circuits 200 latch / counter 202 Input transistor 204 Current Source 3Image sensor chip 31 first semiconductor layer 32 second semiconductor layer 33 Third semiconductor layer 300 light receiving area 302 storage circuit 304 processing circuit

Claims

1. A solid-state imaging device, comprising: a comparison circuit having a non-inverting input terminal and an inverting input terminal; a first switch connected to the inverting input terminal; a second switch connected to the inverting input terminal and controlled at a different time than that of the first switch; a third switch connected between the output terminal of the comparison circuit and the inverting input terminal; a first capacitor having one end connected to the inverting input terminal via the first switch and the other end to which a reference signal is applied; and A second capacitor has one end connected to the inverting input terminal via the second switch and the reference signal applied to the other end.

2. The solid-state imaging device according to claim 1, wherein The comparison circuit comprises: a first transistor having a control terminal connected to the non-inverting input terminal and one end connected to a positive-side power supply voltage; and A second transistor has a control terminal connected to the inverting input terminal, one end connected to the other end of the first transistor, the other end of the second transistor is connected to the third switch, and an output signal is output from the other end of the second transistor.

3. The solid-state imaging device according to claim 1, wherein The non-inverting input terminal is connected to a floating diffusion region in the pixel circuit.

4. The solid-state imaging device according to claim 3, wherein The third switch is turned on at a time when a signal is sampled.

5. The solid-state imaging device according to claim 4, wherein At the time of sampling the reset level of the floating diffusion region, The first switch is turned on, The second switch continues to be in the off state, The first capacitor samples the signal based on the reset level using the standard value of the reference signal as a standard potential via the comparison circuit and the third switch, and The first switch is turned off after the first capacitor performs sampling.

6. The solid-state imaging device according to claim 4, wherein At the time of sampling the signal level output from the light receiving element, The first switch continues to be in an off state, The second switch is turned on at the sampling time, The second capacitor samples the signal level using a standard value of the reference signal as a standard potential via the floating diffusion region, the comparison circuit, and the third switch, and The second switch is turned off after the second capacitor performs sampling.

7. The solid-state imaging device according to claim 3, wherein: The third switch is turned off at the time of the comparison signal.

8. The solid-state imaging device according to claim 7, wherein At the time of reading the reset level of the floating diffusion region, The first switch is turned on, The second switch continues to be in the off state, A ramp signal is input to the other end of the first capacitor as the reference signal, and The first switch is turned off after the signal output from the comparison circuit is inverted.

9. The solid-state imaging device according to claim 7, wherein: At the time of reading the signal level output from the light receiving element, The first switch continues to be in an off state, The second switch is turned on, A ramp signal is input to the other end of the second capacitor as the reference signal, and The second switch is turned off after the signal output from the comparison circuit is inverted.

10. The solid-state imaging device according to claim 1, wherein A plurality of light receiving elements are connected.

11. The solid-state imaging device according to claim 10, wherein Each of the plurality of light receiving elements includes the first switch, the first capacitor, the second switch, and the second capacitor.

12. A comparison device, comprising: a comparison circuit having a non-inverting input terminal and an inverting input terminal; a first switch connected to the inverting input terminal; a second switch connected to the inverting input terminal and controlled at a different time than that of the first switch; a third switch connected between the output terminal of the comparison circuit and the inverting input terminal; a first capacitor having one end connected to the inverting input terminal via the first switch and the other end to which a reference signal is applied; and A second capacitor has one end connected to the inverting input terminal via the second switch and the reference signal applied to the other end.

Images