Back-side and front-side contacts for semiconductor devices

Abstract

Backside and front side contact structures surrounding the source / drain regions provide increased contact area for electrical connections and allow for increased silicide area. Sidewall metallization of the epitaxially grown source / drain regions provides source / drain sidewall contacts that enable formation of wrap-around contacts on both the front side and the back side of the semiconductor device layer. Front side and back side contact metallization over the source / drain sidewall contacts allows for wrap-around contact structures on both sides of the device layer.

Description

Technical Field

[0001] The present invention relates generally to the electrical, electronic and computer fields and, more particularly, to a FET architecture having backside and frontside contacts and methods for forming such contacts. Background Art

[0002] As the size of various integrated circuit components has shrunk, transistors such as field effect transistors (FETs) have experienced significant improvements in both performance and power consumption. These improvements can be largely attributed to the reduction in the size of the components used therein, which generally translates into reduced capacitance, resistance, and increased throughput current from the transistor. Metal oxide semiconductor field effect transistors are well suited for use in high density integrated circuits. As the size of MOSFETs and other devices has decreased, the size of the source / drain regions, channel regions, and gate electrodes of the devices has also decreased.

[0003] FinFETs, nanosheets, and vertical transfer FETs are already under development for possible use in tight pitch applications. A nanosheet FET includes multiple channel layers, each separated by a gate stack that includes a conductive gate material layer and a gate dielectric layer. The gate stack surrounds all sides of the channel layer, forming a gate-all-around (GAA) structure. The epitaxial regions on the ends of the nanosheet channel layer form the source / drain regions of the nanosheet FET.

[0004] The use of both front side contacts and back side contacts can facilitate the manufacture and performance of the integrated circuit. By providing contacts on both sides of the chip, the contact spacing can be greater than if only one side (e.g., the front side) included all contacts for the FET. The back side power rail can be electrically connected to the back side source / drain contacts. Summary of the invention

[0005] An exemplary monolithic semiconductor structure includes a device layer having a front side and a back side, an interlayer dielectric layer, and a field effect transistor in the interlayer dielectric layer, the field effect transistor including a channel region and first and second source / drain regions extending laterally from the channel region. Each of the first source / drain region and the second source / drain region includes a top surface, a bottom surface, and a sidewall surface extending between the top surface and the bottom surface. The device layer also includes a first metal source / drain sidewall contact and a second metal source / drain sidewall contact, the first metal source / drain sidewall contact directly contacts the sidewall surface of the first source / drain region and has a top end and a bottom end, the second metal source / drain sidewall contact directly contacts the sidewall surface of the second source / drain region, and the second metal source / drain sidewall contact also has a top end and a bottom end. The back side source / drain contact directly contacts the bottom surface of the first source / drain region and the bottom end of the first metal source / drain sidewall contact. The front side source / drain contact directly contacts the top surface of the second source / drain region and the top end of the second metal source / drain sidewall contact. The back side and front side source / drain contacts include metal.

[0006] The second monolithic semiconductor structure includes a device layer having a front side and a back side. The device layer includes a field effect transistor and an interlayer dielectric layer. The field effect transistor is located in the interlayer dielectric layer. Each of the field effect transistors includes a channel region and a first source / drain region and a second source / drain region extending laterally from the channel region. Each of the first source / drain region and the second source / drain region includes a top surface, a bottom surface, and a sidewall surface extending between the top surface and the bottom surface. The metal source / drain sidewalls contact and abut the sidewall surfaces of the first and second source / drain regions of each field effect transistor, respectively. The back side source / drain contact extends from the back side of the device layer. Each back side source / drain contact in the back side source / drain contact includes metal and directly contacts the bottom surface of the first source / drain region of a field effect transistor in the field effect transistor and the bottom end of the source / drain sidewall contact on the sidewall surface of the first source / drain region.

[0007] According to another aspect of the present invention, a method for manufacturing a monolithic semiconductor structure including a backside contact and a frontside contact is provided. The method includes obtaining a device layer, the device layer including an interlayer dielectric layer and a field effect transistor in the interlayer dielectric layer. The field effect transistor includes a channel region and a first source / drain region and a second source / drain region extending laterally from the channel region, each of the first source / drain region and the second source / drain region including a top surface, a bottom surface, and a sidewall surface extending between the top surface and the bottom surface. A first metal source / drain sidewall contact is formed directly on the sidewall surface of the first source / drain region, and a second metal source / drain sidewall contact is formed directly on the sidewall surface of the second source / drain region. The first metal source / drain sidewall contact and the second metal source / drain sidewall contact each have a top end and a bottom end. The method also includes forming a front source / drain contact directly on the top surface of the second source / drain region and the top end of the second metal source / drain sidewall contact, and forming a back source / drain contact directly on the bottom surface of the first source / drain region and the bottom end of the first metal source / drain sidewall contact.

[0008] The techniques and structures disclosed herein can provide substantially beneficial technical effects. By way of example only and not limitation, one or more embodiments can provide one or more of the following advantages:

[0009] Manufacturing flexibility;

[0010] Benefits of backside power delivery network technology;

[0011] Increased backside and frontside contact / silicide areas;

[0012] Wrap around back and front contacts.

[0013] These and other features and advantages will become apparent from the following detailed description of illustrative embodiments thereof, which is to be read in conjunction with the accompanying drawings. BRIEF DESCRIPTION OF THE DRAWINGS

[0014] The following drawings are presented by way of example only and not limitation, wherein like reference numerals (when used) indicate corresponding elements throughout the several views, and wherein:

[0015] Figure 1 is a top plan view of a layout including a sacrificial gate over a nanosheet stack, showing x and y cross sections according to an exemplary embodiment;

[0016] Figure 1A is along Figure 1 A schematic cross-sectional view of an x-cross section;

[0017] Figure 1B is a schematic cross-sectional view thereof taken along the y cross section;

[0018] Figure 2A is a schematic cross-sectional view along the x-section, showing the bottom layer of the nanosheet stack after removal. Figure 1A The structure depicted in;

[0019] Figure 2B is a schematic cross-sectional view thereof taken along the y cross section;

[0020] Figure 3A After forming the spacer layer and the bottom dielectric isolation layer Figure 2A A schematic cross-sectional view of the structure shown in ;

[0021] Figure 3B yes Figure 3A A schematic cross-sectional view of the structure shown taken along the y-cross section;

[0022] Figure 4A yes Figure 3A A schematic cross-sectional view of the structure shown after deposition and etch recession of an interlayer dielectric layer;

[0023] Figure 4B is a schematic cross-sectional view taken along the y-section;

[0024] Figure 5A is a graph showing the nanosheet stack after etching back and forming the inner spacer Figure 4A A schematic cross-sectional view of the structure of;

[0025] Figure 5B is a schematic cross-sectional view thereof taken along the y cross section;

[0026] Fig. 6A After backside contact patterning Figure 5A A schematic cross-sectional view of the structure shown in ;

[0027] Figure 6B is a schematic cross-sectional view thereof taken along the y cross section;

[0028] Fig. 7A After forming the sacrificial placeholder for the backside contact Fig. 6A A schematic cross-sectional view of the structure shown;

[0029] Figure 7B is a schematic cross-sectional view thereof taken along the y cross section;

[0030] Fig. 8A After the source / drain regions are formed Fig. 7A a schematic cross-sectional view of the structure shown;

[0031] Figure 8Bis a schematic cross-sectional view thereof taken along the y cross section;

[0032] Fig. 9A is taken along the x-cross section after the dielectric liner deposition forming the dielectric fill material Fig. 8A A schematic cross-sectional view of the structure shown in ;

[0033] Fig. 9B is a schematic cross-sectional view thereof taken along the y cross section;

[0034] Fig. 10A After the Replacement Metal Gate (RMG) process Fig. 9A A schematic cross-sectional view of the structure shown in ;

[0035] Fig. 10B is a schematic cross-sectional view thereof taken along the y cross section;

[0036] Fig.11A After the formation of the metal gate recess and dielectric gate capping layer, Fig. 10A A schematic cross-sectional view of the structure shown in;

[0037] Fig. 11B is a schematic cross-sectional view thereof taken along the y cross section;

[0038] Fig. 12A After the dielectric fill material is etched back Fig.11A a schematic cross-sectional view of the structure shown;

[0039] Fig. 12B is a schematic cross-sectional view thereof taken along the y cross section;

[0040] Fig.13A After selectively removing portions of the dielectric liner Fig. 12A a schematic cross-sectional view of the structure shown;

[0041] Fig. 13B is a schematic cross-sectional view thereof taken along the y cross section;

[0042] Fig.14A After forming the metal sidewall contacts adjacent to the source / drain regions Fig.13A a schematic cross-sectional view of the structure shown;

[0043] Fig. 14B It is taken along the y cross section Fig.14A a schematic cross-sectional view of the structure shown;

[0044] Fig.15A After the formation of the middle process metal contact, the formation of the back-end process interconnect layer, and the bonding of the carrier wafer Fig.14A A schematic cross-sectional view of the structure shown in ;

[0045] Fig. 15B is a schematic cross-sectional view thereof taken along the y cross section;

[0046] Fig.16A After removing the semiconductor substrate layer Fig.15A A schematic cross-sectional view of the structure shown;

[0047] Fig. 16B is a schematic cross-sectional view thereof taken along the y cross section;

[0048] Fig.17A yes Fig.16A a schematic cross-sectional view of the structure shown after removal of the etch stop layer and another semiconductor substrate layer;

[0049] Fig. 17B is a schematic cross-sectional view thereof taken along the y cross section;

[0050] Fig.18A After depositing and planarizing the backside interlayer dielectric layer Fig.17A A schematic cross-sectional view of the structure shown;

[0051] Fig.18B is a schematic cross-sectional view thereof taken along the y cross section;

[0052] Fig.19A After removing the sacrificial placeholder Fig.18A a schematic cross-sectional view of the structure shown;

[0053] Fig.19B is a schematic cross-sectional view thereof taken along the y cross section;

[0054] Fig. 20A yes Fig.19A A schematic cross-sectional view of the structure shown after side etching of the backside interlayer dielectric layer;

[0055] Fig. 20B is a schematic cross-sectional view thereof taken along the y cross section;

[0056] Fig.21A After the backside contact metallization and the formation of the backside interconnect layer Fig. 20A A schematic cross-sectional view of the structure shown in ; and

[0057] Fig.21B It is a schematic cross-sectional view taken along the y section.

[0058] It should be appreciated that elements in the figures are illustrated for simplicity and clarity. Common but well-understood elements that may be useful or necessary in a commercially feasible embodiment may not be depicted in order to facilitate a less obstructed view of the illustrated embodiments. DETAILED DESCRIPTION

[0059] The principles of the present invention will be described herein in the context of illustrative embodiments. However, it should be understood that the specific embodiments and / or methods illustratively shown and described herein are considered to be exemplary and not restrictive. In addition, in view of the teachings herein, it will become apparent to those skilled in the art that many modifications may be made to the illustrated embodiments, which modifications are within the scope of the claims. That is, no limitation on the embodiments illustrated and described herein is intended or should be inferred.

[0060] Using backside contacts in addition to frontside contacts can facilitate the manufacture and performance of integrated circuits, particularly those that include relatively small components and increased packaging density. Gate-all-around (GAA) transistors such as nanosheet transistors and fin field effect transistors (FinFETs) are among the components employed in high-density, high-performance applications.

[0061] exist Figure 1 An exemplary sequence of steps that can be used to manufacture an integrated circuit including a backside contact is shown in and subsequent figures. Figure 1 The schematic top plan view of provides a perspective view of the orientation of the x and y cross sections relative to a fin including a nanosheet stack 20 and a sacrificial gate 22 extending perpendicularly relative to the fin. It should be understood that the techniques described herein are applicable to architectures including FinFETs as well as architectures including nanosheet transistors.

[0062] Figure 1 , Figure 1A and Figure 1B The monolithic structure shown in FIG. 1 comprises a stack of nanosheets 20 including a semiconductor channel layer 21 and a sacrificial silicon germanium layer 26 formed above a substrate. The nanosheets may be formed, for example, on a bulk semiconductor substrate. Figure 1A and Figure 1B , the substrate includes a silicon layer 24 and an etch stop layer 28 within the silicon substrate layer 24. The etch stop layer may be, for example, a buried oxide (BOX) layer or a silicon germanium layer.

[0063] In one or more exemplary embodiments, the semiconductor nanosheet (channel) layers 21 each have a thickness in the range of 4 to 10 nanometers (4-10nm). The number of semiconductor (channel) layers in the semiconductor layer stack can vary depending on the desired use and capabilities of the nanosheet transistor to be manufactured. In some embodiments, the semiconductor channel layers 21 are substantially single crystal silicon layers and are spaced ten to twenty nanometers (10-20nm) apart. In some embodiments, the width of each semiconductor channel layer 21 in the top fin portion of the exemplary monolithic structure is fifteen nanometers (15nm) or greater (as observed in the y cross section). The size of the channel layer and the vertical spacing of the channel layer should be considered exemplary rather than limiting.

[0064] The silicon and silicon germanium layers 21, 26 can be epitaxially grown on the semiconductor substrate in an alternating sequence to obtain a stack having a desired number of silicon (channel) layers. The terms "epitaxial growth and / or deposition" and "epitaxially grown and / or deposited" mean the growth of semiconductor material on a deposition surface of semiconductor material, wherein the grown semiconductor material has the same crystalline properties as the semiconductor material of the deposition surface. In the epitaxial deposition process, the chemical reactants provided by the source gas are controlled and the system parameters are set so that the deposited atoms arrive at the deposition surface of the semiconductor substrate with sufficient energy to move around on the surface and orient themselves to the crystal arrangement of atoms of the deposition surface. Therefore, the epitaxial semiconductor material has the same crystalline properties as the deposition surface on which it is formed.

[0065] Figure 1 , Figure 1A and Figure 1B The monolithic structure shown in is obtained by first growing silicon and silicon germanium nanosheet layers in an alternating order on a substrate. The sacrificial silicon germanium layer 26 (which is replaced by a metal gate and gate dielectric material later in the process) can have a thickness in the range of 6 to 20 nanometers (6-20nm). The size ranges of the channel layer and the sacrificial silicon germanium layer should be considered exemplary and not limiting. The sacrificial silicon germanium layer 26 can have a composition of Si 1-x Ge x , where x is between 0.2 and 0.3 to allow for selective etching relative to silicon and the underlying silicon germanium substrate layer 26'. In one exemplary embodiment, the sacrificial silicon germanium layer 26 has a composition Si 1-x Ge x , wherein x is about 0.3, and the silicon germanium substrate layer 26' has a composition Si 1-x Ge x, where x is about 0.55. The thickness of the top silicon germanium substrate layer 26' can be the same or different from the thickness of the sacrificial silicon germanium layer 26 adjacent to the silicon channel layer 21. Using a patterned hard mask (e.g., silicon nitride), an initial reactive ion etch (RIE) is performed to obtain a multi-layer fin-shaped semiconductor structure with a dielectric cap (not shown) formed by the hard mask. The multi-layer fin-shaped semiconductor structure (nanosheet stack 20) ​​extends vertically from the semiconductor substrate 24, 26. The remaining portion of the hard mask is removed.

[0066] like Figure 1B As shown, a cavity is formed in the semiconductor substrate between the nanosheet stacks 20. The bottom of the cavity is above the top surface of the etch stop layer 28. Shallow trench isolation (STI) regions 34 are formed in the cavity in the substrate 24 to provide electrical isolation of active regions including adjacent transistors or other devices that may be formed on the substrate 24. Silicon dioxide or other suitable dielectric materials may be deposited to form such regions.

[0067] A sacrificial gate layer is formed over the stack 20 of nanosheet layers. The sacrificial gate layer may include, for example, a thin layer of SiO2 and amorphous silicon (a-Si) or polycrystalline silicon (poly-Si). The sacrificial gate material used to form the sacrificial gate layer may be formed using, for example, physical vapor deposition (PVD), chemical vapor deposition (CVD), plasma enhanced chemical vapor deposition (PECVD), inductively coupled plasma chemical vapor deposition (ICP CVD), or any combination thereof. A hard mask (e.g., SiNx or a combination of SiNx and SiO2) is deposited and patterned on the top surface of the sacrificial gate layer. The sacrificial gate layer is then reactively ion etched. The resulting structure includes a sacrificial gate 22 extending vertically relative to the parallel nanosheet stack 20. The patterned gate hard mask 32 is adjacent to the top surface of the sacrificial gate. The sacrificial gate 22 extends through both the nFET and pFET regions of the exemplary structure, as shown in FIG. Figure 1 shown.

[0068] The top substrate layer 26' is selectively removed, thereby forming a space 36 between the top surface of the semiconductor layer 24 and the nanosheet stack 20. As described above, the top substrate layer 26' has a higher germanium content than the sacrificial silicon germanium layer 26 within the nanosheet stack 20, and can therefore be selectively etched relative to such a layer. A selective etching process such as dry HCl etching can be used to selectively remove the top substrate layer 26' relative to the silicon channel layer 21 and the sacrificial silicon germanium layer 26. Figure 2A and Figure 2B Cross-sectional views of the x and y cross sections of the resulting structure are provided, respectively.

[0069] A dielectric layer is deposited on the resulting structure and fills the space 36 below the nanosheet stack 20. The dielectric gate spacer may include, for example, SiN, SiBCN, SiOCN, and / or SiCO or other suitable dielectric materials. Such materials may be deposited using ALD (atomic layer deposition). In an exemplary embodiment, a silicon nitride liner is deposited on the monolithic structure. The silicon nitride liner is selectively etched back to remove its unprotected horizontal portions, thereby forming a vertical top sidewall gate spacer 38 on the sidewalls of the nanosheet stack 20 and the sacrificial gate 22. The spacer material below the nanosheet stack is protected and remains in the space 36 after the etch back, thereby forming a bottom dielectric isolation layer. Figure 3A and Figure 3B A cross-sectional view of the resulting structure including vertical gate spacers 38 and a bottom dielectric isolation layer (horizontal spacers 38A) beneath the nanosheet stack 20 is provided.

[0070] An interlayer dielectric (ILD) layer 40 is deposited on the structure using a deposition technique including, but not necessarily limited to, chemical vapor deposition (CVD), plasma enhanced CVD (PECVD), radio frequency CVD (RFCVD), physical vapor deposition (PVD), atomic layer deposition (ALD), molecular beam deposition (MBD), pulsed laser deposition (PLD) and / or liquid source mist chemical deposition (LSMCD), spin coating, sputtering and / or electroplating. The ILD layer 40 may include, but is not necessarily limited to, a low-k material (e.g., k less than about 4.0), such as, for example, porous silicates, carbon-doped oxides, silicon dioxide, silicon oxynitride, carbon-doped silicon oxide (SiCOH) and porous variants thereof, silsesquioxanes, siloxanes, or other dielectric materials having, for example, a dielectric constant in the range of about 2 to about 4. For example, a SiCOH dielectric film having a dielectric constant (k) of about 2.7-2.8 may include one or more ILD layers. Such a dielectric film may be deposited using PECVD. In some embodiments, the ILD layer may include an ultra low k (ULK) dielectric material having a dielectric constant of 2.5 or less. In some embodiments, the ILD layer includes multiple layers. The ILD layer 40 is recessed downward to the top surface of the nanosheet stack. Figure 4B As schematically shown in FIG. 4 , ILD layer 40 fills the spaces between gate spacers 38 and extends down to the top surface of STI regions 34 .

[0071] refer to Figure 5A and 5B, the portion of the nanosheet stack 20 outside the area protected by the sacrificial gate 22, the hard mask 32, and the gate spacer 38 is subjected to reactive ion etching until a horizontal spacer 38A of the bottom dielectric isolation (BDI) layer is formed. The resulting structure is subjected to a timed wet etching process to selectively etch back the silicon germanium layer 26 within the nanosheet stack 20. In some embodiments, hydrogen chloride gas is used to selectively remove silicon germanium, leaving the silicon nanosheet (channel) layer 21 substantially intact. Alternatively, a wet etching process containing ammonia and hydroperoxide can be used to etch SiGe that is selective to other materials. Each exposed end of the silicon germanium layer 26 can be etched back, for example, three to seven nanometers (3-7nm). After the timed etching, the width of the silicon germanium layer 26 is less than the width of the silicon (channel) layer 21. The stack of semiconductor nanosheet layers accordingly includes a dent between the ends of each pair of silicon (channel) layers 21.

[0072] The dielectric spacer material is deposited in the trenches created by the reactive ion etching of the stack of semiconductor layers. The dielectric spacer material is etched back to form an inner spacer 44 within each indentation in the stack of nanosheet semiconductor layers. A selective wet etch may be employed to remove the dielectric inner spacer material outside of the indentations between the silicon layers. Figure 5A and 5B 50 is schematically shown in FIG. The inner spacer 44 of the structure may include, for example, a low-k dielectric material. In some embodiments, silicon oxynitride, SiBCN (silicon boron carbon nitride), SiOCN (silicon oxycarbon nitride) and / or SiOC (silicon carbide oxide) inner spacers may be formed. If a relatively low-k silicon nitride-based material is used to form the inner spacer, it can be selectively etched using, for example, phosphoric acid. Various techniques for forming inner spacers for nanosheet transistors have been discussed in the literature and continue to be developed. The specific materials and steps discussed with respect to the formation of the inner spacer should accordingly be considered as exemplary rather than restrictive.

[0073] An organic planarization layer (OPL) 46 is deposited and then patterned to obtain Fig. 6A and Figure 6B The structure 60 shown. A photolithographically patterned hard mask (not shown) may be used to form vertical placeholder trenches 48 extending through the OPL 46 down to the etch stop layer 28 in the substrate. Figure 6B As shown, each trench 48 extends between a pair of STI regions 34. A placeholder material layer is deposited in the placeholder trenches 48. The placeholder material layer is gradually retreated to form a structure 70, as shown in FIG. Fig. 7A and Figure 7BSchematically shown in . The placeholder material layer includes a sacrificial placeholder 52 within the substrate, which is later replaced by a metal backside contact, as described below. The sidewalls of the sacrificial placeholder 52 are substantially vertical. The bottom surface of the sacrificial placeholder abuts the etch stop layer 28. The top surface of the sacrificial placeholder can extend above the bottom surface of the BDI layer 38A, but below the level of the bottom of the nanosheet stack 20. Silicon carbide, aluminum oxide, and titanium oxide are materials that can include the sacrificial placeholder 52.

[0074] The OPL 46 is removed to expose the other end of the channel nanosheet layer 21 of the nanosheet stack 20. Ashing or other suitable processes may be used to remove the OPL. Source / drain regions 56-1, 56-2 are epitaxially grown on the exposed edges of the silicon nanosheet channel layer 21. Selected source / drain regions 56-1 are grown directly above the sacrificial placeholder 52. Other source / drain regions 56-2 are grown on the BDI layer 38A, such as Fig. 8A and Figure 8B As shown in the exemplary structure 80 shown. The epitaxial growth of the source / drain regions 56-1, 56-2 is timed to control the height and width dimensions. As is known in the art, dopants can be introduced in situ using appropriate precursors. "In situ" refers to the introduction of dopants indicating the conductivity type of the doped layer during a process step (e.g., epitaxial deposition) to form the doped layer. As used herein, the term "conductivity type" refers to a p-type or n-type doped region. As used herein, "p-type" refers to the addition of impurities to an intrinsic semiconductor, which produces a defect in valence electrons. In silicon-containing substrates, examples of p-type doping (i.e., impurities) include, but are not limited to: boron, aluminum, gallium, and indium. As used herein, "n-type" refers to the addition of impurities that contribute free electrons to the intrinsic semiconductor. In silicon-containing substrates, examples of n-type doping (i.e., impurities) include, but are not limited to, antimony, arsenic, and phosphorus. Exemplary epitaxial growth processes suitable for forming silicon and / or silicon germanium epitaxy include rapid thermal chemical vapor deposition (RTCVD), low energy plasma deposition (LEPD), ultra-high vacuum chemical vapor deposition (UHVCVD), atmospheric pressure chemical vapor deposition (APCVD), and molecular beam epitaxy (MBE). Figure 1 , the nFET region contains transistors with n-type source / drain regions, while the pFET region contains p-type source / drain regions. The source / drain regions of the nanosheet device are usually grown before the RMG process.

[0075] refer to Fig. 9A and Fig. 9B, a dielectric liner 54 (such as a silicon nitride liner) is conformally deposited over the source / drain regions 56-1, 56-2, the ILD layer 40, and the spacers 38. A dielectric fill layer 58 is then deposited over the dielectric liner 54 and planarized down to the top surface of the hard mask 32. The planarization may be performed using a chemical mechanical planarization (CMP) process. The dielectric fill layer 58 may be, for example, a silicon dioxide layer. Fig. 9A and Fig. 9B A monolithic structure 90 is shown.

[0076] The hard mask 32 and sacrificial gate layer 22 are removed from the structure 90. The silicon germanium layer 26 is then selectively removed, leaving a stack of silicon (channel) layers 21 separated by spaces (not shown). In some embodiments, hydrogen chloride gas is used to selectively remove the silicon germanium, leaving substantially intact silicon nanosheets. Alternatively, a wet etching process containing ammonia and hydroperoxide can be used to etch SiGe that is selective to other materials. The gate stack 62 is formed in abutting relationship with the nanosheet (channel) layer 21. The gate dielectric layer forms part of the gate stack that replaces the sacrificial silicon germanium layer. The gate stack is adjacent to the silicon nanosheet channel layer 21. Non-limiting examples of suitable materials for the gate dielectric layer include oxides, nitrides, oxynitrides, silicates (e.g., metal silicates), aluminates, titanates, nitrides, or any combination thereof. Examples of high-k gate dielectric materials (having a dielectric constant greater than 7.0) include, but are not limited to, metal oxides such as hafnium oxide, hafnium silicon oxide, hafnium silicon oxynitride, lanthanum oxide, lanthanum aluminum oxide, zirconium oxide, zirconium silicon oxide, zirconium silicon oxynitride, tantalum oxide, titanium oxide, barium strontium titanium oxide, barium titanium oxide, strontium titanium oxide, yttrium oxide, aluminum oxide, lead scandium tantalum oxide, and lead zinc niobate. High-k materials may also include dopants such as lanthanum and aluminum. The gate dielectric layer may be formed by a suitable deposition process, such as chemical vapor deposition (CVD), plasma enhanced chemical vapor deposition (PECVD), atomic layer deposition (ALD), evaporation, physical vapor deposition (PVD), chemical solution deposition, or other similar processes. The thickness of the gate dielectric material may vary depending on the deposition process and the composition and amount of the high-k dielectric material used. In an exemplary embodiment, a high-k dielectric layer having a thickness of 2.5 nm is employed. In some embodiments, the gate dielectric layer includes a plurality of dielectric layers.

[0077] The conductive gate material is deposited in the space previously filled by the sacrificial gate 22 and the silicon germanium nanosheet layer 26. The deposited metal gate material forms the metal gate of the nanosheet field effect transistor of the resulting structure 100. In some embodiments, the conductive gate includes a work function metal (WFM) layer. The WFM has a dual purpose: Vt setting and gate conductor. Non-limiting examples of suitable work function metals include p-type work function metal materials and n-type work function metal materials. P-type work function materials include compositions such as ruthenium, palladium, platinum, cobalt, nickel and conductive metal oxides, titanium nitride or any combination thereof. N-type metal materials include, for example, hafnium, zirconium, titanium, tantalum, aluminum, metal carbides (e.g., hafnium carbide, zirconium carbide, titanium carbide and aluminum carbide), aluminides or any combination thereof. The work function metal can be deposited by a suitable deposition process, such as a conformal ALD process.

[0078] In one exemplary embodiment, an n-type WFM layer having a thickness of three nanometers (3 nm) may be formed on the gate dielectric layer. The thickness of the WFM layer may, for example, be in the range of two to ten nanometers (2-10 nm), with thinner layers being used as device scaling decreases. The n-type WFM layer is intended to be used in association with n-type transistors. Portions of the n-type WFM layer that may also be deposited in the pFET region may be replaced accordingly later in the process. The n-type WFM layer and the gate dielectric may fill the space between the silicon channel layer 21 and the region previously occupied by the sacrificial gate 22.

[0079] The n-type WFM layer in the nFET region can be protected by a patterned OPL (not shown). The exposed portion of the n-type WFM layer in the pFET region is removed, leaving an open space between the silicon channel layer 21 in the pFET region. Thus, the gate metal is removed from the pFET region while the protected nFET region remains intact. SC1 etching or other suitable etching processes can be used to selectively remove the gate metal while leaving the gate dielectric layer substantially intact. The etching duration sufficient to allow all gate metal to be removed from the pFET region does not affect the gate metal in the nFET region. After removing the originally deposited n-type WFM layer from the pFET region, a new gate metal that is considered suitable for a pFET transistor is deposited. A p-type WFM layer is deposited in an embodiment in which the first deposited metal is n-type. It should be understood that in some alternative embodiments, the process can be reversed and n-type metal can be deposited after the p-type metal is deposited. Chemical mechanical planarization can be used to remove the metal capping layer. Accordingly, a FEOL layer including FETs and other electronic devices (not shown) within the possible ILD layer 40 is provided. Fig. 10A and Fig. 10B A cross-sectional view of an exemplary structure 100 is provided.

[0080] The gate stack 62 is recessed, and a self-aligned contact dielectric gate cap (SAC cap) layer 64 is formed on the structure. The dielectric gate cap layer is planarized down to the top surface of the dielectric fill layer 58. The composition of the dielectric gate cap layer 64 is different from the composition of the gate spacers 38. For example, a silicon carbide (SiC) gate cap layer 64 is formed in some exemplary embodiments. Fig.11A and Fig. 11B An exemplary structure 110 obtained after gate stack recess and gate cap layer formation is shown.

[0081] The dielectric fill layer 58 is recessed to stop on the dielectric liner 54. A groove 66 is formed between portions of the gate cap layer 64, such as Fig. 12A As shown. Fig. 12A and Fig. 12B The structure 120 is shown. The horizontal portion of the dielectric liner 54 is selectively removed relative to the gate cap layer 64 and the source / drain regions 56-1, 56-2. Fig.13A As shown in the x-cross section depicted in FIG. 1 , the vertical portion of the dielectric liner 54 remains. Reactive ion etching may be used to remove the horizontal portion of the dielectric liner, thereby exposing the top surface of the source / drain regions 56-1, 56-2. The unprotected portion of the gate spacer 38 is also selectively removed down to the STI region 34, thereby exposing the sidewall surface of the source / drain region, as shown in FIG. Fig. 13B As shown. The top portion of the source / drain region may also be removed at this time, because the spacer pull-down process may not be perfectly selective to the source / drain epitaxy. The resulting structure 130 includes a vertical space between the sidewalls of the source / drain region and the sidewalls of the adjacent portion of the ILD layer 40. The vertical space extends through the device layer 65, the top end of the device layer 65 is open and the bottom end of the device layer 65 is adjacent to the STI region 34.

[0082] Metal sidewall source / drain contacts 68-1 are formed in the vertical space between source / drain regions 56-1, 56-2 and ILD layer 40. In some embodiments, titanium (Ti) is deposited using an atomic layer deposition (ALD) process to fill the vertical space. Other metals or conductive compositions or combinations thereof, such as nickel (Ni), nickel platinum (NiPt), or Ti / TiN, may be deposited instead during sidewall metallization. An isotropic etch back process may be used to obtain the vertical space between source / drain regions 56-1, 56-2 and ILD layer 40. Fig.14A and Fig. 14B The structure 140 is shown. The structure can be annealed to form a metal silicide layer between the contact metal and the source / drain epitaxy. The source / drain sidewall contact 68-1 is incorporated into the device layer 65 and extends between the top surface of the ILD layer 40 and its bottom surface. Fig. 14BAs further shown in FIG. 1 , the source / drain sidewall contacts extend through the openings in the BDI layer 38A and have bottom ends abutting the STI regions 34. Each sidewall source / drain contact 68-1 forms an electrical connection to one of the source / drain regions 56-1, 56-2. Fig. 14B As shown in FIG. 1 , as viewed in the y cross section, the opposing sidewall surfaces of the source / drain regions 56-1, 56-2 are in direct contact with the sidewall contact metal. The sidewall contact 68-1 on each source / drain region is electrically isolated from the sidewall contact of the adjacent source / drain region by portions of the ILD layer 40 and the STI region 34.

[0083] refer to Fig.15A and Fig. 15B , forming front-side contacts in middle-of-line (MOL) processing. Silicon-based devices typically include multiple interconnect metallization layers above the device (front-end of line / FEOL) layer 65 containing field effect transistors (FETs) and / or other electronic structures. FEOL processing includes high-temperature steps for manipulating semiconductor conductivity. Middle-of-line (MOL) processing includes steps typically used to make metal contacts for logic circuit system components such as field effect transistors (FETs), resistors, diodes, and capacitors. MOL processing may include intermediate temperature steps for forming semiconductor-metal compounds (e.g., silicides, germanium silicides) for electrical contacts. Back-end of line (BEOL) processing involves the creation of metal interconnect wires that connect the devices formed in the FEOL processing to form circuits, and may include silicidation as discussed above with respect to MOL processing.

[0084] The MOL ILD layer 40' is deposited over the device layer and patterned. The openings in the MOL ILD layer extend downward to the top surface of the selected source / drain region 56-2 and the sidewall contacts 68-1 associated therewith, respectively. The top (front side) source / drain contact 68-F and the gate contact (not shown) may include conductive materials, including but not limited to silicide layers (such as Ti, Ni, NiPt) and metal adhesion layers (such as TiN, TaN) and conductive metal fillers (such as tungsten (W), aluminum (Al), copper (Cu), cobalt (Co), ruthenium (Ru), molybdenum (Mo)) or any other suitable conductive materials and combinations thereof. The metal silicide layer may be formed on the source / drain region 56-2 by depositing a metal liner (such as a titanium liner) on the source / drain region 56-2 before depositing the metal fill layer. Such a titanium liner may be deposited using physical vapor deposition (PVD) and subsequently annealed at a temperature between about 200 degrees Celsius and 800 degrees Celsius to form a metal silicide. Sidewall contacts 68-1 and front side contacts 68-F together form a front side wraparound contact (WAC) that contacts the sidewalls and top (front) surface of selected source / drain regions 56-2, as shown in FIG. Fig. 15B The electrical connection between such a WAC and the source / drain region 56-2 is enhanced by the relatively large contact area therebetween. At this stage of the manufacturing process, the recesses 66 in the gate cap layer 64 above the other source / drain regions 56-1 of the structure 150 remain filled with the ILD material.

[0085] After the MOL process, metal interconnects are formed in one or more BEOL layers 75 that connect the devices in the FEOL (device) layer 65 to form a circuit. The BEOL layer is formed on the front side of the device layer 65. Metal lines including interconnect wires are deposited in sequence (e.g., M1, M2, M3, etc.) on the FEOL layer and include a dielectric layer. The interconnect wires in each metal line are electrically connected to the interconnect wires in other metal lines and are electrically connected to the devices in the FEOL (device) layer 65. The BEOL process typically includes low temperature steps for forming metal lines and preserving temperature-sensitive FEOL and MOL structures. The BEOL process involves forming an interconnect layer above the MOL layer. A chip may have multiple BEOL interconnect layers. Each interconnect layer with a wiring scheme is connected to another interconnect layer through vias. The wires and vias are in dielectric layers, one or more of which may include low-k materials.

[0086] A carrier wafer 72 is bonded to the resulting structure and abuts the BEOL layers 75 . Fig.15A and Fig. 15B The exemplary monolithic semiconductor structure 150 shown in FIG. 1 includes a FEOL (device) layer 65 and a MOL layer, the FEOL layer 65 including nFET and pFET transistors, sidewall contacts 68-1 adjacent to the sidewalls of the source / drain regions 56-1, 56-2 of the transistors, and optionally other electronic devices, the MOL layer including a front side contact 68-F, a BEOL layer 75, and the BEOL layer 75 is electrically connected to the devices in the device layer. The structure 150 also includes a carrier wafer 72. The front side contact 68-F and the sidewall contact 68-1 form an integral wraparound contact that surrounds and extends over the source / drain region 56-2 in the device layer 65, thereby forming a relatively large contact area therebetween. The wraparound contact electrically connects the selected source / drain region 56-2 to the BEOL layer 75.

[0087] The monolithic structure 150 is flipped over and the portion of the silicon substrate layer 24 beneath the etch stop layer 28 is removed therefrom. Ammonium hydroxide (NH4OH) or tetramethylammonium hydroxide (TMAH) may be used for this removal because of their high selectivity to silicon germanium. (As described above, the etch stop layer may include silicon germanium.) Fig.16A and Fig. 16B The monolithic structure 160 is schematically shown in FIG. 1 (shown facing up). The etch stop layer 28 and the remaining portion of the silicon substrate layer 24 are then selectively removed, thereby obtaining a monolithic structure 160 as shown in FIG. Fig.17A and Fig. 17B Structure 170 is shown (also shown with the front side facing up). After this removal, sacrificial placeholders 52 are exposed on the back side of the structure.

[0088] A backside ILD layer 40" is deposited on the inverted structure 170 and planarized down to the backside surface of the sacrificial placeholder 52. The backside surface of the sacrificial placeholder is facing the top during this processing. Although not required, the backside ILD layer 40" can have the same composition as the previously formed ILD layers 40, 40' discussed above. The backside surface of the sacrificial placeholder 52 is exposed in the resulting structure 180, as shown in FIG. Fig.18A and Fig.18B shown.

[0089] The sacrificial placeholder 52 is selectively removed using a conventional dry or wet etch process. A cavity 76 replacing the sacrificial placeholder 52 is formed in the backside ILD layer 40 ″, such as Fig.19A and Fig.19B The back surface of the source / drain region 56-1 of the resulting structure 190 is exposed at the top of the cavity 76. The cavity 76 expands laterally to form a Fig. 20A and Fig. 20B The structure 200 shown. Fig. 20B As shown, the bottom surface of the sidewall contact 68-1 adjacent to the source / drain region 56-1 is exposed when the cavity 76 is laterally expanded. An isotropic dry or wet etch may be used to laterally expand the cavity 76. The etch selectively removes portions of the backside ILD layer 40″ and the STI region 34 while leaving the source / drain region 56-1 and the sidewall contact 68-1 on the source / drain region 56-1 substantially intact.

[0090] The backside contact metallization is followed by metal capping layer removal to form backside source / drain contacts 68-B. The source / drain sidewall contacts 68-1 and the source / drain backside contacts 68-B form an integral wraparound contact structure that contacts the sidewall surfaces and backside (bottom) surface of the source / drain region 56-1. The backside source / drain contacts 68-B may or may not include the same metal / metal silicide used to form the frontside source / drain contacts 68-F and the sidewall source / drain contacts 68-1. The presence of the BEOL layer 75 at this stage of the process may preclude high temperature thermal annealing. The relatively large contact area between the source / drain region 56-1 and the WAC formed by the backside and sidewall source / drain contacts 68-B, 68-1 helps mitigate possible contact resistance issues due to the absence of a high temperature thermal anneal during the backside metallization process. Since the sidewall source / drain contacts 68-1 are formed on the sidewalls of the source / drain regions 56-1 before forming the BEOL interconnect layer 75, only the portion of the backside wraparound contact structure that contacts the backside surface of the source / drain regions 56-1 needs to take into account possible temperature limitations due to the BEOL layer 75 during backside metallization and annealing.

[0091] Each backside source / drain contact 68-B has a width greater than the width of the backside surface of the corresponding source / drain region 56-1, the "backside" surface being located on top of the structure during backside metallization after wafer flipping, as described above. The backside source / drain contacts 68-B extend within the backside ILD layer 40". Portions of the backside source / drain contacts 68-B may contact the bottom sidewall surfaces of the sidewall source / drain contacts 68-1 as well as the backside (bottom) surface thereof, as described above. Fig.21B As shown schematically in Fig.21A As shown, top portions of backside source / drain contacts 68 -B may further extend partially within BDI layer 38A.

[0092] A backside interconnect structure is formed over the backside ILD layer 40 ″. In some embodiments, the backside interconnect structure includes a backside power rail (BPR) and a backside power delivery network (BSPDN). Fig.21A and Fig.21B The backside interconnect structure 78 is schematically shown in FIG. The backside source / drain contacts 68 -B are electrically connected to the backside interconnect structure 78 .

[0093] The above-described manufacturing techniques can be used to obtain Fig.21A and Fig.21BThe monolithic semiconductor structure 210 shown. The structure 210 includes a device layer 65 formed in the FEOL process and has a front side and a back side. Field effect transistors and possible other electronic devices (not shown) are incorporated in the device layer. The device layer 65 includes a FET, which includes a channel region (a stacked silicon nanosheet channel layer 21 in the exemplary structure), source / drain regions 56-1, 56-2 extending laterally from the channel region, and a gate stack 62, all of which are embedded in the ILD layer 40. The back-end process interconnect layer 75 is located on the front side of the device layer 65 and is electrically connected to the field effect transistor. The sidewall source / drain contact 68-1 abuts the sidewalls of the source / drain region 56-1, 56-2. The front side source / drain contact 68-F abuts the top surface of the selected source / drain region 56-2 and the sidewall source / drain contact 68-1 associated with such source / drain region. The front side source / drain contact 68-F and the sidewall source / drain contact 68-1 form an integral wraparound contact structure for electrically connecting the source / drain region 56-2 to the BEOL interconnect layer 75. The back side source / drain contact 68-B abuts the backside surfaces of other selected source / drain regions 56-1 and the sidewall source / drain contacts 68-1 associated with such source / drain regions. The back side source / drain contact 68-B and the sidewall source / drain contact 68-1 form an integral wraparound contact structure for electrically connecting the source / drain region 56-1 to the backside interconnect layer 78. The bottom dielectric isolation layer 38A below the gate stack 62 also extends over portions of the top surfaces of the back side source / drain contacts 68-B, as shown. Fig.21A shown.

[0094] In some embodiments, the field effect transistor (or FETs) within the device layer 65 includes one source / drain region 56-2 electrically connected to the BEOL layer 75 through a front side contact 68-F and another source / drain region 56-1 electrically connected to the backside interconnect layer 78 through a back side contact 68-B. Some FETs in the device layer 65 may have source / drain regions electrically connected only to the BEOL interconnect layer 75 through the front side contact, while the source / drain regions of other FETs may be electrically connected only to the backside interconnect layer 78 through the back side contact. In embodiments where the backside interconnect layer 78 includes both signal lines and power lines instead of only power lines, an integrated circuit including FETs may have source / drain regions of the FETs electrically connected to the backside interconnect layer through the back side contact. A wraparound contact structure that provides contact to the source / drain sidewall surface as well as the top or bottom source / drain surface allows for larger silicide areas for both the front side and back side contacts. Providing wraparound source / drain contacts on both sides of the device layer is facilitated by providing source / drain sidewall contacts 68-1 that extend completely through the device layer 65 prior to front and back side contact formation.

[0095] The accompanying drawings discussed above depict exemplary processing steps / stages in the manufacture of exemplary structures. Although the overall manufacturing method and the structure formed thereby are completely new, certain individual processing steps required to implement the method can utilize conventional semiconductor manufacturing techniques and conventional semiconductor manufacturing tools. In view of the teachings of this article, these techniques and tools will be familiar to ordinary technicians in the relevant field. In addition, one or more processing steps and tools for manufacturing semiconductor devices are also described in many readily available publications, including, for example, James D. Plummer et al. Silicon VLSI Technology: Fundamentals, Practice, and Modeling (Silicon VLSI Technology: Fundamentals, Practice, and Modeling) First Edition, Prentice Hall, 2001, which is incorporated herein by reference. It is emphasized that although some individual processing steps are set forth herein, those steps are merely illustrative, and those skilled in the art may be familiar with several equally suitable alternatives that will apply.

[0096] It should be understood that the various layers and / or regions shown in the drawings may not be drawn to scale. In addition, for ease of explanation, one or more semiconductor layers or other layers of a type commonly used in such integrated circuit devices may not be explicitly shown in a given figure. This does not mean that semiconductor layers or other layers not explicitly shown are omitted in actual integrated circuit devices.

[0097] At least a portion of the above techniques can be implemented in an integrated circuit. In forming an integrated circuit, identical die are typically fabricated in a repeating pattern on the surface of a semiconductor wafer. Each bare die contains the devices described herein and may contain other structures and / or circuits. Individual die are cut or diced from the wafer and then packaged as an integrated circuit. Those skilled in the art will know how to cut wafers and package die to produce an integrated circuit.

[0098] Those skilled in the art will appreciate that the exemplary structures discussed above may be distributed in raw form (i.e., a single wafer having multiple unpackaged chips), as bare die, in a packaged form, or incorporated as part of an intermediate or final product that would benefit from having, for example, FET devices and contacts formed in accordance with one or more exemplary embodiments.

[0099] There are many techniques used by those skilled in the art to remove material at various stages of creating a semiconductor structure. As used herein, these processes are generally referred to as "etching". For example, etching includes wet etching, dry etching, chemical oxide removal (COR) etching, and reactive ion etching (RIE) techniques, which are all known techniques for removing selected materials when forming a semiconductor structure. Standard Clean 1 (SC1) contains a strong base (usually ammonium hydroxide) and hydrogen peroxide. SC2 contains a strong acid, such as hydrochloric acid and hydrogen peroxide. The techniques and applications of etching are well understood by those skilled in the art, and therefore, a more detailed description of these processes is not given herein.

[0100] The illustrations of the embodiments described herein are intended to provide a general understanding of the various embodiments, and they are not intended to serve as a complete description of all elements and features of the devices and systems that may utilize the circuits and techniques described herein. In view of the teachings herein, many other embodiments will become apparent to those skilled in the art; other embodiments are utilized and derived therefrom so that structural and logical substitutions and changes can be made without departing from the scope of the present invention. It should also be noted that in some alternative embodiments, some steps of the exemplary method may not occur in the order shown in the figures. For example, two steps shown in succession may actually be performed substantially simultaneously, or certain steps may sometimes be performed in the opposite order, depending on the functions involved. The drawings are also merely representative and are not drawn to scale. Therefore, the specification and drawings are to be considered illustrative rather than restrictive.

[0101] Embodiments may be referred to herein individually and / or collectively by the term "embodiment," which is merely for convenience and is not intended to limit the scope of the present application to any single embodiment or inventive concept (if more than one is actually shown). Thus, although specific embodiments have been shown and described herein, it should be understood that arrangements that achieve the same purpose may be substituted for the specific embodiments shown. Combinations of the above embodiments, as well as other embodiments not specifically described herein, will become apparent to those skilled in the art in view of the teachings herein.

[0102] The terms used herein are only used for the purpose of describing specific embodiments, and are not restrictive. As used herein, the singular forms "one", "an" and "the" are intended to also include plural forms, unless the context clearly states otherwise. It will be further understood that when used in this specification, the terms "include" and / or "comprise" specify the presence of the features, steps, operations, elements and / or parts, but do not exclude the presence or addition of one or more other features, steps, operations, elements, parts and / or their groups. Terms such as "above" and "below" and "vertical" are used to indicate the relative positioning of elements or structures relative to each other, rather than relative height. If the layer of the structure is described as "above" another layer in this article, it should be understood that there may or may not be an intermediate element or layer between two specified layers. If a layer is described as "directly on" another layer, the direct contact of the two layers is indicated.

[0103] The corresponding structures, materials, actions, and equivalents of any means or step plus function elements in the following claims are intended to include any structure, material, or action for performing a function in conjunction with other claimed elements as specifically claimed. The descriptions of various embodiments have been presented for purposes of illustration and description, but are not intended to be exhaustive or limited to the disclosed forms. Many modifications and variations will be apparent to those of ordinary skill in the art without departing from the scope of the invention. The embodiments are selected and described in order to best explain the principles and practical applications, and to enable those of ordinary skill in the art to understand the various embodiments with various modifications suitable for the intended specific use.

[0104] The Abstract is provided to comply with 37 CFR §1.72(b). It is understood that the Abstract will not be used to interpret or limit the scope or meaning of the claims. Additionally, in the foregoing Detailed Description, it can be seen that various features are grouped together in a single embodiment for the purpose of simplifying the disclosure. This method of disclosure should not be interpreted as reflecting an intention that the claimed embodiments require more features than are expressly recited in each claim. On the contrary, as reflected in the appended claims, the claimed subject matter may lie in less than all the features of a single embodiment. Therefore, the appended claims are hereby incorporated into the Detailed Description, with each claim standing on its own as a separately claimed subject matter.

[0105] Given the teachings provided herein, one of ordinary skill in the art will be able to envision other implementations and applications of the technology and disclosed embodiments. Although illustrative embodiments have been described herein with reference to the accompanying drawings, it should be understood that the illustrative embodiments are not limited to those precise embodiments, and that various other changes and modifications may be made therein by one skilled in the art without departing from the scope of the appended claims.

[0106] In the preferred embodiment of the present invention described above, a monolithic semiconductor structure is provided, comprising: a device layer including a front side and a back side, the device layer including: a field effect transistor; an interlayer dielectric layer, the field effect transistor being located in the interlayer dielectric layer; each of the field effect transistors including a channel region and a first source / drain region and a second source / drain region extending laterally from the channel region, each of the first source / drain region and the second source / drain region including a top surface, a bottom surface and a sidewall surface extending between the top surface and the bottom surface; and a source / drain sidewall contact, which includes a metal and and adjacent to the sidewall surfaces of the first and second source / drain regions of each field effect transistor, respectively, each source / drain sidewall contact having a top and a bottom; and a backside source / drain contact extending from the back side of the device layer, each of the backside source / drain contacts comprising a metal and directly contacting the bottom surface of the first source / drain region of one of the field effect transistors and the bottom end of one of the source / drain sidewall contacts on the sidewall surface of the first source / drain region of the field effect transistor in the field effect transistor. Preferably, the device layer includes an integrated circuit, and the second source / drain regions of the plurality of field effect transistors are electrically connected to the front side source / drain contacts extending from the front side of the device layer, respectively. The structure may also include a bottom dielectric isolation layer adjacent to the bottom end of the second source / drain region and the top surface of each of the backside source / drain contacts. The structure may also include: a front side source / drain contact extending from the front side of the device layer, each of the front side source / drain contacts including metal and directly contacting the top surface of one of the second source / drain regions and the top of one of the source / drain sidewall contacts on the sidewall surface of one of the second source / drain regions, respectively; a back-end process interconnect layer on the front side of the device layer, the front side source / drain contact electrically connected to the back-end process interconnect layer; and a back-end interconnect layer on the back side of the device layer, the back-end source / drain contact electrically connected to the back-end interconnect layer. The structure may also include an inter-process dielectric layer between the device layer and the back-end process interconnect layer, the front side source / drain contact extending through the inter-process dielectric layer; and a back-end dielectric layer between the device layer and the back-end interconnect layer, the back-end source / drain contact extending through the back-end dielectric layer. Preferably, the channel region of each field effect transistor includes a stack of nanosheet semiconductor layers. The structure may also include: a gate stack between the nanosheet semiconductor layers of each field effect transistor; and a bottom dielectric isolation layer adjacent to the gate stack, the bottom end of each of the second source / drain regions, and the top surface of each of the backside source / drain contacts. The structure may also include a carrier wafer bonded to the top surface of the back-end process interconnect layer.

Claims

1. A monolithic semiconductor structure comprising: A device layer having a front side and a back side, the device layer comprising: interlayer dielectric layer; a field effect transistor in the interlayer dielectric layer, the field effect transistor comprising a channel region and first and second source / drain regions extending laterally from the channel region, each of the first and second source / drain regions comprising a top surface, a bottom surface, and a sidewall surface extending between the top surface and the bottom surface; a first metal source / drain sidewall contact directly contacting a sidewall surface of the first source / drain region, the first metal source / drain sidewall contact having a top end and a bottom end; and A second metal source / drain sidewall contact portion directly contacts the sidewall surface of the second source / drain region, wherein the second metal source / drain sidewall contact portion has a top end and a bottom end; a backside source / drain contact comprising metal and directly contacting a bottom surface of the first source / drain region and a bottom end of the first metal source / drain sidewall contact; and A front side source / drain contact comprises metal and directly contacts a top surface of the second source / drain region and a top end of the second metal source / drain sidewall contact.

2. The monolithic semiconductor structure of claim 1 , further comprising: a back-end processing interconnect layer on the front side of the device layer, the front side source / drain contacts being electrically connected to the back-end processing interconnect layer; and A backside interconnect layer is on the backside of the device layer, the backside source / drain contacts being electrically connected to the backside interconnect layer. 3 . The monolithic semiconductor structure of claim 2 , further comprising a bottom dielectric isolation layer adjoining a bottom end of the second source / drain region and a top surface of the backside source / drain contact.

4. The monolithic semiconductor structure of claim 2, further comprising: an inter-process dielectric layer between the device layer and the back-end interconnect layer, the front-side source / drain contact extending through the inter-process dielectric layer; and A backside dielectric layer is provided between the device layer and the backside interconnect layer, the backside source / drain contacts extending through the backside dielectric layer.

5. The monolithic semiconductor structure of claim 4, wherein the channel region comprises a stack of nanosheet semiconductor layers.

6. The monolithic semiconductor structure of claim 5, further comprising: a gate stack between the nanosheet semiconductor layers; and A bottom dielectric isolation layer adjoins the gate stack, a bottom end of the second source / drain region, and a top surface of the backside source / drain contact.

7. The monolithic semiconductor structure of claim 5, further comprising a carrier wafer bonded to a top surface of the back end processing interconnect layer.

8. The monolithic semiconductor structure of claim 5, wherein the first metal source / drain sidewall contacts and the second metal source / drain sidewall contacts comprise metal silicide layers.

9. A method of manufacturing a monolithic semiconductor structure comprising a backside contact and a frontside contact, comprising: A device layer having a front side and a back side is obtained, the device layer comprising: an interlayer dielectric layer; and a field effect transistor in the interlayer dielectric layer, the field effect transistor comprising a channel region and first and second source / drain regions extending laterally from the channel region, each of the first and second source / drain regions comprising a top surface, a bottom surface, and a sidewall surface extending between the top surface and the bottom surface; forming a first metal source / drain sidewall contact directly on the sidewall surface of the first source / drain region, and forming a second metal source / drain sidewall contact directly on the sidewall surface of the second source / drain region, wherein the first metal source / drain sidewall contact and the second metal source / drain sidewall contact each have a top end and a bottom end; forming a front side source / drain contact comprising metal directly on a top surface of the second source / drain region and the top end of the second metal source / drain sidewall contact; and A backside source / drain contact comprising metal is formed directly on the bottom surface of the first source / drain region and the bottom end of the first metal source / drain sidewall contact.

10. The method of claim 9, further comprising a substrate on the back side of the device layer and a sacrificial placeholder extending within the substrate, the sacrificial placeholder directly below the first source / drain region, the method further comprising: removing the substrate; forming a backside interlayer dielectric layer on the backside of the device layer; removing the sacrificial placeholder, thereby forming a cavity in the backside interlayer dielectric layer and exposing a bottom surface of the first source / drain region; and Wherein forming the backside source / drain contacts further comprises filling the cavity with a contact metal. 11 . The method of claim 10 , wherein the device layer further comprises a bottom dielectric isolation layer extending below the second source / drain region, wherein the backside interlayer dielectric layer is partially formed on the bottom dielectric isolation layer.

12. The method according to claim 10, further comprising: forming a back-end process interconnection layer on the device layer; bonding a carrier wafer to the back-end process interconnect layer; and A backside interconnect layer is formed on the backside interlayer dielectric layer.

Images