Display substrate and display device

Abstract

A display substrate comprises a first display area (A1). The first display area (A1) comprises a plurality of display island areas (A11) arranged in an array mode and light-transmitting areas (A121 and A122) located between the adjacent display island areas (A11). The display island area (A11) includes a plurality of first pixel circuits (11) and a plurality of first light emitting elements (13) provided on a substrate. The at least one first pixel circuit (11) is electrically connected with the at least one first light-emitting element (13) and is configured to drive the at least one first light-emitting element (13) to emit light. The first pixel circuits (11) in the adjacent display island areas (A11) are connected through a plurality of first signal wires in the first direction (X), and the first pixel circuits (11) in the adjacent display island areas (A11) are connected through a plurality of second signal wires in the second direction (Y). The plurality of second signal wires are made of transparent conductive materials, or the plurality of first signal wires and the plurality of second signal wires are made of metal materials.

Description

Display substrate and display device

[0001] This application claims priority to the Chinese patent application filed with the China Patent Office on May 31, 2022, with application number 202210615748.7 and invention name “Display Substrate and Display Device”, the contents of which should be understood as incorporated into this application by reference. Technical Field

[0002] This article relates to the field of display technology, and in particular to a display substrate and a display device. Background Art

[0003] Organic light-emitting diodes (OLEDs) and quantum-dot light-emitting diodes (QLEDs) are active light-emitting display devices with the advantages of self-luminescence, wide viewing angle, high contrast, low power consumption, extremely high response speed, light weight, flexibility and low cost.

[0004] Summary of the Invention

[0005] The following is a summary of the subject matter described in detail herein. This summary is not intended to limit the scope of the claims.

[0006] Embodiments of the present disclosure provide a display substrate and a display device.

[0007] On the one hand, this embodiment provides a display substrate, comprising: a first display area, the first display area comprising: a plurality of display island areas arranged in an array, and a light-transmitting area located between adjacent display island areas. The display island areas comprise: a plurality of first pixel circuits and a plurality of first light-emitting elements disposed on a substrate, at least one of the plurality of first pixel circuits being electrically connected to at least one of the plurality of first light-emitting elements, and the at least one first pixel circuit being configured to drive the at least one first light-emitting element to emit light. First pixel circuits in adjacent display island areas are connected in a first direction via a plurality of first signal lines, and first pixel circuits in adjacent display island areas are connected in a second direction via a plurality of second signal lines; the first direction intersects the second direction. The material of the plurality of second signal lines comprises a transparent conductive material, or the materials of the plurality of first signal lines and the plurality of second signal lines both comprise a metal material.

[0008] In some exemplary embodiments, the film layer where the plurality of second signal traces are located is located on a side of the film layer where the plurality of first signal traces are located away from the substrate.

[0009] In some exemplary embodiments, the material of the plurality of first signal lines includes a metal material, the material of the plurality of second signal lines includes a transparent conductive material, and the plurality of second signal lines are in a same-layer structure.

[0010] In some exemplary embodiments, at least a portion of the plurality of second signal traces are located in the light-transmitting area.

[0011] In some exemplary embodiments, the light-transmitting area includes: a first light-transmitting area located between display island areas adjacent along the second direction, and a second light-transmitting area located between display island areas adjacent along the first direction; the area of ​​the first light-transmitting area is larger than that of the second light-transmitting area.

[0012] In some exemplary embodiments, the plurality of first signal lines and the plurality of second signal lines are both made of metal, the plurality of second signal lines are in the same layer, or at least one of the plurality of second signal lines is in a different layer from the remaining second signal lines.

[0013] In some exemplary embodiments, the light-transmitting area includes at least: a first light-transmitting area located between display island areas adjacent to each other along the second direction; the display substrate further includes: a first routing area located between adjacent first light-transmitting areas, the first routing area being connected to the display island areas; and the plurality of second signal routing lines are located in the first routing area.

[0014] In some exemplary embodiments, the plurality of second signal lines include: a plurality of data connection lines for transmitting data signals to the plurality of first pixel circuits in the display island area respectively, and at least one first power connection line for transmitting a first voltage signal to the plurality of first pixel circuits in the display island area.

[0015] In some exemplary embodiments, the plurality of first pixel circuits in the display island region are electrically connected to the same first power connection line.

[0016] In some exemplary embodiments, the plurality of first pixel circuits in the display island area are electrically connected to a plurality of first power connection lines, respectively, and the plurality of data connection lines and the plurality of first power connection lines are arranged at intervals.

[0017] In some exemplary embodiments, the plurality of first pixel circuits in the display island area are arranged sequentially along the first direction, and the data connection line connected to the first first pixel circuit among the plurality of first pixel circuits and the data connection lines connected to the remaining first pixel circuits are of a different layer structure.

[0018] In some exemplary embodiments, at least one first signal line among the plurality of first signal lines is in a different-layer structure from the remaining first signal lines.

[0019] In some exemplary embodiments, the plurality of first signal lines include: a first initial connection line for transmitting a first initial signal, a first scan connection line for transmitting a first scan signal, a second scan connection line for transmitting a second scan signal, and a light-emission control connection line for transmitting a light-emission control signal. The first scan connection line, the second scan connection line, and the light-emission control connection line are co-layered.

[0020] In some exemplary embodiments, at least one display island area among the multiple display island areas includes: three first pixel circuits and three first light-emitting elements, the three first pixel circuits and the three first light-emitting elements are electrically connected one-to-one, and the three first pixel circuits are arranged in sequence along the first direction.

[0021] In some exemplary embodiments, the three first light-emitting elements include: a first light-emitting element emitting a first color light, a first light-emitting element emitting a second color light, and a first light-emitting element emitting a third color light. The first light-emitting element emitting the first color light and the first light-emitting element emitting the second color light are arranged in the same column, the first light-emitting element emitting the third color light and the first light-emitting element emitting the first color light are arranged in different columns, and the first light-emitting element emitting the first color light, the first light-emitting element emitting the second color light, and the first light-emitting element emitting the third color light are arranged in different rows.

[0022] In some exemplary embodiments, the area of ​​the light-emitting region of the first light-emitting element that emits the second color light is larger than the area of ​​the light-emitting region of the first light-emitting element that emits the first color light, and the area of ​​the light-emitting region of the first light-emitting element that emits the third color light is larger than the area of ​​the light-emitting region of the first light-emitting element that emits the first color light.

[0023] In some exemplary embodiments, the orthographic projection of the light-emitting region of the first light-emitting element emitting light of the first color on the substrate at least partially overlaps with the orthographic projection of the first pixel circuit connected to the first light-emitting element emitting light of the first color on the substrate. The orthographic projection of the light-emitting region of the first light-emitting element emitting light of the second color on the substrate does not overlap with the orthographic projection of the first pixel circuit connected to the first light-emitting element emitting light of the second color on the substrate. The orthographic projection of the light-emitting region of the first light-emitting element emitting light of the third color on the substrate at least partially overlaps with the orthographic projection of the first pixel circuit connected to the first light-emitting element emitting light of the third color on the substrate.

[0024] In some exemplary embodiments, an overlapping area between the light-emitting region of the first light-emitting element that emits the third color light and the first pixel circuit connected to the first light-emitting element that emits the third color light is greater than an overlapping area between the light-emitting region of the first light-emitting element that emits the first color light and the first pixel circuit connected to the first light-emitting element that emits the first color light.

[0025] In some exemplary embodiments, the display substrate further includes: a second display area located on at least one side of the first display area; the second display area includes: a plurality of second pixel circuits and a plurality of second light-emitting elements arranged on the substrate, at least one second pixel circuit among the plurality of second pixel circuits is electrically connected to at least one second light-emitting element among the plurality of second light-emitting elements, and the at least one second pixel circuit is configured to drive the at least one second light-emitting element to emit light.

[0026] On the other hand, this embodiment provides a display device including the display substrate as described above.

[0027] On the other hand, this embodiment provides a display substrate, comprising: a first display area. The first display area comprises: a plurality of display island areas arranged in an array, and a light-transmitting area located between adjacent display island areas. The light-transmitting area comprises a first light-transmitting area, and the first light-transmitting area is located between adjacent display island areas along the second direction. At least one display island area among the plurality of display island areas and the first light-transmitting area are alternately arranged along the second direction. The display island area comprises: a plurality of first pixel circuits and a plurality of first light-emitting elements arranged on a substrate. At least one first pixel circuit among the plurality of first pixel circuits is electrically connected to at least one first light-emitting element among the plurality of first light-emitting elements. At least one first pixel circuit is configured to drive the at least one first light-emitting element to emit light. The first pixel circuits in adjacent display island areas are connected in the first direction by a plurality of first signal lines, and the first pixel circuits in adjacent display island areas are connected in the second direction by a plurality of second signal lines; the first direction intersects with the second direction.

[0028] In some exemplary embodiments, the first light-transmissive region is located between the plurality of second signal traces along the first direction.

[0029] In some exemplary embodiments, the light-transmitting region may further include a second light-transmitting region. The second light-transmitting region is located between adjacent display island regions along the first direction. The area of ​​the first light-transmitting region may be larger than that of the second light-transmitting region.

[0030] In some example embodiments, the second light-transmitting region is located between the plurality of first signal lines.

[0031] In some exemplary embodiments, at least one display island region among the plurality of display island regions includes: three first pixel circuits and three first light-emitting elements. The three first pixel circuits are electrically connected to the three first light-emitting elements in a one-to-one correspondence, and the three first pixel circuits are arranged sequentially along the first direction. The three first light-emitting elements include: a first light-emitting element that emits a first color light, a first light-emitting element that emits a second color light, and a first light-emitting element that emits a third color light. The light-emitting region of the first light-emitting element that emits the first color light at least partially overlaps with the orthographic projection of the substrate on the substrate of the first pixel circuit connected to the first light-emitting element that emits the first color light. The light-emitting region of the first light-emitting element that emits the second color light at least partially overlaps with the orthographic projection of the substrate on the substrate of the first pixel circuit connected to the first light-emitting element that emits the second color light. The light-emitting region of the first light-emitting element that emits the third color light at least partially overlaps with the orthographic projection of the substrate on the substrate of the first pixel circuit connected to the first light-emitting element that emits the third color light.

[0032] Still other aspects will become apparent upon reading and understanding the accompanying drawings and detailed description.

[0033] Summary of the Figures

[0034] The accompanying drawings are intended to provide a further understanding of the technical solutions of the present disclosure and constitute part of the specification. Together with the embodiments of the present disclosure, they are used to explain the technical solutions of the present disclosure and do not constitute a limitation of the technical solutions of the present disclosure. The shapes and sizes of one or more components in the accompanying drawings do not reflect the actual scale and are intended only to illustrate the contents of the present disclosure.

[0035] FIG1 is a schematic diagram of a display substrate according to at least one embodiment of the present disclosure;

[0036] FIG2 is an equivalent circuit diagram of a pixel circuit according to at least one embodiment of the present disclosure;

[0037] FIG3 is a partial schematic diagram of a first display area according to at least one embodiment of the present disclosure;

[0038] 4 is a schematic diagram illustrating the arrangement of a first pixel circuit and a first light-emitting element in a first display area according to at least one embodiment of the present disclosure;

[0039] FIG5 is a schematic diagram of a partial top view of area S1 in FIG4 ;

[0040] FIG6 is a schematic diagram of the display substrate after the semiconductor layer is formed in FIG5 ;

[0041] FIG7A is a schematic diagram of the display substrate after the first conductive layer is formed in FIG5 ;

[0042] FIG7B is a schematic diagram of the first conductive layer in FIG7A ;

[0043] FIG8A is a schematic diagram of the display substrate after the second conductive layer is formed in FIG5 ;

[0044] FIG8B is a schematic diagram of the second conductive layer in FIG8A ;

[0045] FIG9 is a schematic diagram of the display substrate after forming the third insulating layer in FIG5 ;

[0046] FIG10A is a schematic diagram of the display substrate after forming the third conductive layer in FIG5 ;

[0047] FIG10B is a schematic diagram of the third conductive layer in FIG10A ;

[0048] FIG11 is a schematic diagram of the display substrate after forming the fourth insulating layer in FIG5 ;

[0049] FIG12A is a schematic diagram of the display substrate after the transparent conductive layer is formed in FIG5 ;

[0050] FIG12B is a schematic diagram of the transparent conductive layer in FIG12A;

[0051] FIG13 is a schematic diagram of the display substrate after the fifth insulating layer is formed in FIG5 ;

[0052] FIG14A is a schematic diagram of the display substrate after forming the fourth conductive layer in FIG5 ;

[0053] FIG14B is a schematic diagram of the fourth conductive layer in FIG14A;

[0054] FIG15 is a schematic diagram of the display substrate after the sixth insulating layer is formed in FIG5 ;

[0055] FIG16A is a schematic diagram of the display substrate after the anode layer is formed in FIG5 ;

[0056] FIG16B is a schematic diagram of the anode layer in FIG16A;

[0057] FIG17A is another schematic diagram of the first display area according to at least one embodiment of the present disclosure;

[0058] FIG17B is another schematic diagram of the first display area according to at least one embodiment of the present disclosure;

[0059] FIG17C is another schematic diagram of the first display area according to at least one embodiment of the present disclosure;

[0060] FIG18 is a partial top view of area S2 in FIG17A ;

[0061] FIG19 is a schematic diagram of the display substrate after the first conductive layer is formed in FIG18;

[0062] FIG20 is a schematic diagram of the display substrate after forming the second conductive layer in FIG18;

[0063] FIG21A is a schematic diagram of the display substrate after forming the third conductive layer in FIG18;

[0064] FIG21B is a schematic diagram of the third conductive layer in FIG21A ;

[0065] FIG22 is a schematic diagram of the display substrate after the fifth insulating layer is formed in FIG18;

[0066] FIG23A is a schematic diagram of the display substrate after forming the fourth conductive layer in FIG18;

[0067] FIG23B is a schematic diagram of the fourth conductive layer in FIG23A;

[0068] FIG24 is a schematic diagram of the display substrate after the sixth insulating layer is formed in FIG18;

[0069] FIG25 is a schematic diagram of the display substrate after the anode layer is formed in FIG18;

[0070] FIG26 is another partial schematic top view of area S2 in FIG17A ;

[0071] FIG27 is a schematic diagram of the display substrate after the second conductive layer is formed in FIG26;

[0072] FIG28A is a schematic diagram of the display substrate after forming the third conductive layer in FIG26;

[0073] FIG28B is a schematic diagram of the third conductive layer in FIG28A ;

[0074] FIG29 is a schematic diagram of the display substrate after the fifth insulating layer is formed in FIG26;

[0075] FIG30A is a schematic diagram of the display substrate after forming the fourth conductive layer in FIG26;

[0076] FIG30B is a schematic diagram of the fourth conductive layer in FIG30A ;

[0077] FIG31 is a schematic diagram of a display device according to at least one embodiment of the present disclosure.

[0078] Details

[0079] The embodiments of the present disclosure will be described in detail below with reference to the accompanying drawings. The embodiments can be implemented in a variety of different forms. A person skilled in the art can easily understand that the method and content can be transformed into other forms without departing from the purpose and scope of the present disclosure. Therefore, the present disclosure should not be interpreted as being limited to the contents described in the following embodiments. In the absence of conflict, the embodiments and features in the embodiments of the present disclosure can be combined with each other in any manner.

[0080] In the drawings, the size of one or more components, layer thicknesses, or regions may be exaggerated for clarity. Therefore, one embodiment of the present disclosure is not necessarily limited to these dimensions, and the shapes and sizes of one or more components in the drawings do not reflect true proportions. Furthermore, the drawings schematically illustrate idealized examples, and one embodiment of the present disclosure is not limited to the shapes or values ​​shown in the drawings.

[0081] In this specification, ordinal numbers such as "first," "second," and "third" are provided to avoid confusion among constituent elements, and are not intended to limit the number. "Multiple" in this disclosure means two or more.

[0082] In this specification, for convenience, words and phrases indicating orientation or positional relationships, such as "middle," "upper," "lower," "front," "back," "vertical," "horizontal," "top," "bottom," "inside," and "outside," are used to illustrate the positional relationships of constituent elements with reference to the accompanying drawings. This is merely for the purpose of facilitating the description of this specification and simplifying the description, and is not intended to indicate or imply that the device or element referred to must have a specific orientation, be constructed, or operate in a specific orientation. Therefore, they should not be construed as limitations on the present disclosure. The positional relationships of constituent elements may be appropriately changed depending on the orientation of the constituent elements being described. Therefore, the present disclosure is not limited to the words and phrases described in the specification and may be appropriately replaced depending on the circumstances.

[0083] In this specification, unless otherwise specified or limited, the terms "mounted," "connected," and "connected" should be understood broadly. For example, they can refer to fixed connections, removable connections, or integral connections; they can refer to mechanical connections or connections; they can refer to direct connections, indirect connections through intermediaries, or internal communication between two components. Those skilled in the art will understand the meaning of these terms in this disclosure based on the circumstances.

[0084] In this specification, "electrically connected" includes components connected together via an element having some electrical function. There are no particular limitations on the "element having some electrical function" as long as it enables transmission of electrical signals between the connected components. Examples of "element having some electrical function" include not only electrodes and wiring, but also switching elements such as transistors, resistors, inductors, capacitors, and other components with multiple functions.

[0085] In this specification, a transistor refers to a device that includes at least three terminals: a gate, a drain, and a source. A transistor has a channel region between the drain (drain electrode terminal, drain region, or drain electrode) and the source (source electrode terminal, source region, or source electrode), and current can flow through the drain, channel region, and source. In this specification, the channel region refers to the region through which current primarily flows.

[0086] In this specification, the first electrode can be referred to as the drain and the second electrode as the source, or vice versa. The functions of "source" and "drain" are sometimes interchanged when using transistors with opposite polarity or when the direction of current changes during circuit operation. Therefore, in this specification, the terms "source" and "drain" can be interchanged. Furthermore, the gate electrode can also be referred to as the control electrode.

[0087] In this specification, "parallel" refers to a state where the angle formed by two straight lines is greater than -10° and less than 10°, and thus also includes a state where the angle is greater than -5° and less than 5°. Furthermore, "perpendicular" refers to a state where the angle formed by two straight lines is greater than 80° and less than 100°, and thus also includes a state where the angle is greater than 85° and less than 95°.

[0088] In this specification, circles, ellipses, triangles, rectangles, trapezoids, pentagons or hexagons are not in the strict sense, but may be approximate circles, approximate ellipses, approximate triangles, approximate rectangles, approximate trapezoids, approximate pentagons or approximate hexagons, etc. There may be some small deformations caused by tolerances, such as chamfers, arc edges and deformations.

[0089] The term "light transmittance" in this disclosure refers to the ability of light to pass through a medium, and is the percentage of the luminous flux passing through a transparent or translucent body to the incident luminous flux.

[0090] In the present disclosure, "about" and "substantially" are used without strict limits and allow for process and measurement errors. In the present disclosure, "substantially the same" means that the numerical values ​​differ by less than 10%.

[0091] In this disclosure, "A extends along direction B" means that A may include a main portion and a secondary portion connected to the main portion, the main portion being a line, line segment, or strip, extending along direction B, and the length of the main portion extending along direction B being greater than the length of the secondary portion extending along other directions. In this disclosure, "A extends along direction B" means "the main portion of A extends along direction B."

[0092] The present embodiment provides a display substrate, comprising: a first display area. The first display area comprises: a plurality of display island areas arranged in an array, and a light-transmitting area located between adjacent display island areas. The display island area comprises: a plurality of first pixel circuits and a plurality of first light-emitting elements arranged on a substrate. At least one first pixel circuit among the plurality of first pixel circuits is electrically connected to at least one first light-emitting element among the plurality of first light-emitting elements, and at least one first pixel circuit is configured to drive at least one first light-emitting element to emit light. The first pixel circuits in adjacent display island areas are connected in a first direction through a plurality of first signal lines, and the first pixel circuits in adjacent display island areas are connected in a second direction through a plurality of second signal lines. The first direction intersects with the second direction. The material of the plurality of second signal lines comprises a transparent conductive material, or the materials of the plurality of first signal lines and the plurality of second signal lines both comprise metal materials.

[0093] The display substrate provided in this embodiment can reduce the number of isolated islands and slits by centrally arranging multiple first pixel circuits and multiple first light-emitting elements in the display island area, which is beneficial for reducing the diffraction effect of the display substrate and facilitating smoothing processing, thereby reducing display defects (mura) in the first display area and improving the photography effect.

[0094] In some exemplary embodiments, the material of the multiple first signal traces may include a metal material, the material of the multiple second signal traces may include a transparent conductive material, and the multiple second signal traces may be a single-layer structure. In this example, by configuring the multiple second signal traces to include a transparent conductive material, the spacing between adjacent display islands is increased, the routing freedom of the second signal traces is increased, the line width of the second signal traces is increased, display defects caused by excessive resistance of the second signal traces are alleviated, and the light-transmitting area is increased. By configuring the multiple first signal traces to include a metal material, lateral display defects caused by excessive impedance of the transparent conductive material are reduced, the process is simplified, and excessive hole opening processes are avoided, thereby reducing costs.

[0095] In some exemplary embodiments, the materials of the plurality of first signal lines and the plurality of second signal lines may all include metal materials. The plurality of second signal lines may be of the same layer structure, or at least one of the plurality of second signal lines may be of a different layer structure than the remaining second signal lines. In this example, by configuring the plurality of first signal lines and the plurality of second signal lines to all include metal materials, poor lateral or vertical display caused by excessive impedance resulting from the use of transparent conductive materials can be reduced. Furthermore, the process can be simplified to avoid excessive openings, thereby reducing costs. Furthermore, the space occupied by the lines can be reduced, which is beneficial for improving light transmittance.

[0096] The solution of this embodiment is illustrated below through some examples.

[0097] Figure 1 is a schematic diagram of a display substrate of at least one embodiment of the present disclosure. In some examples, as shown in Figure 1, the display substrate may include: a display area AA and a peripheral area BB located outside the display area AA. The display area AA of the display substrate may include at least: a first display area A1 and a second display area A2. The second display area A2 may at least partially surround the first display area A1. For example, the second display area A2 may surround the first display area A1. The peripheral area BB may surround the second display area A2. However, this embodiment is not limited to this. In other examples, the display area may include only the first display area, and the peripheral area may surround the first display area.

[0098] In some examples, as shown in Figure 1, the first display area A1 may be a light-transmitting display area, and may also be referred to as an under-screen camera (FDC, Full Display With Camera) area. The second display area A2 may be referred to as a normal display area. For example, the orthographic projection of a light-sensitive sensor (such as hardware such as a camera) on the display substrate may be located within the first display area A1 of the display substrate. In some examples, as shown in Figure 1, the first display area A1 may be circular, and the size of the orthographic projection of the light-sensitive sensor on the display substrate may be less than or equal to the size of the first display area A1. However, this embodiment is not limited to this. In other examples, the first display area A1 may be rectangular, and the size of the orthographic projection of the light-sensitive sensor on the display substrate may be less than or equal to the size of the inscribed circle of the first display area A1.

[0099] In some examples, as shown in FIG1 , the first display area A1 can be located at the top center of the display area AA. The second display area A2 can surround the first display area A1. However, this embodiment is not limited to this. For example, the first display area A1 can be located at other locations, such as the upper left corner, lower left corner, lower right corner, or upper right corner of the display area AA. For example, the second display area A2 can surround at least one side of the first display area A1.

[0100] In some examples, as shown in FIG1 , the display area AA may be a rectangle, such as a rounded rectangle. The first display area A1 may be circular or elliptical. However, this embodiment is not limited thereto. For example, the first display area A1 may be a rectangle, a semicircle, a pentagon, or other shapes.

[0101] In some examples, the display area AA may be provided with a plurality of sub-pixels. At least one sub-pixel may include a pixel circuit and a light-emitting element. The pixel circuit may be configured to drive the connected light-emitting element. For example, the pixel circuit may be configured to provide a driving current to drive the light-emitting element to emit light. The pixel circuit may include a plurality of transistors and at least one capacitor. For example, the pixel circuit may be a 3T1C, 4T1C, 5T1C, 5T2C, 6T1C, 7T1C, or 8T1C structure. In the above circuit structure, T refers to a thin film transistor, C refers to a capacitor, the number before T represents the number of thin film transistors in the circuit, and the number before C represents the number of capacitors in the circuit.

[0102] In some examples, the multiple transistors in the pixel circuit can be P-type transistors or N-type transistors. Using the same type of transistors in the pixel circuit can simplify the process flow, reduce the difficulty of display substrate processing, and improve product yield. In other examples, the multiple transistors in the pixel circuit can include P-type transistors and N-type transistors.

[0103] In some examples, multiple transistors in the pixel circuit may use low-temperature polysilicon thin-film transistors, or may use oxide thin-film transistors, or may use low-temperature polysilicon thin-film transistors and oxide thin-film transistors. The active layer of the low-temperature polysilicon thin-film transistor uses low-temperature polysilicon (LTPS), and the active layer of the oxide thin-film transistor uses oxide semiconductor (Oxide). Low-temperature polysilicon thin-film transistors have the advantages of high mobility and fast charging, and oxide thin-film transistors have the advantages of low leakage current. Integrating low-temperature polysilicon thin-film transistors and oxide thin-film transistors on a display substrate, i.e., LTPS+Oxide (LTPO for short) display substrate, can take advantage of the advantages of both, achieve low-frequency driving, reduce power consumption, and improve display quality.

[0104] In some examples, the light-emitting element may be any one of a light-emitting diode (LED), an organic light-emitting diode (OLED), a quantum dot light-emitting diode (QLED), a micro-LED (including mini-LED or micro-LED), etc. For example, the light-emitting element may be an OLED, which may emit red light, green light, blue light, or white light, etc. when driven by its corresponding pixel circuit. The color of the light emitted by the light-emitting element may be determined as needed. In some examples, the light-emitting element may include: an anode, a cathode, and an organic light-emitting layer located between the anode and the cathode. The anode of the light-emitting element may be electrically connected to the corresponding pixel circuit. However, this embodiment is not limited to this.

[0105] In some examples, a pixel unit in display area AA may include three sub-pixels. For example, the three sub-pixels may be a red sub-pixel, a green sub-pixel, and a blue sub-pixel. However, this embodiment is not limited to this. In some examples, a pixel unit may include four sub-pixels, and the four sub-pixels may be a red sub-pixel, a green sub-pixel, a blue sub-pixel, and a white sub-pixel.

[0106] In some examples, the shape of the light-emitting element can be a rectangle, a rhombus, a pentagon, or a hexagon. When a pixel unit includes three sub-pixels, the light-emitting elements of the three sub-pixels can be arranged horizontally, vertically, or in a triangular pattern. When a pixel unit includes four sub-pixels, the light-emitting elements of the four sub-pixels can be arranged horizontally, vertically, or in a square pattern. However, this embodiment is not limited to this.

[0107] FIG2 is an equivalent circuit diagram of a pixel circuit according to at least one embodiment of the present disclosure. The pixel circuit of this example is described using a 7T1C structure as an example.

[0108] 2 , the pixel circuit of this example may include seven transistors (ie, first to seventh transistors T1 to T7 ) and a storage capacitor Cst. The light emitting element EL may include an anode, a cathode, and an organic light emitting layer disposed between the anode and the cathode.

[0109] In some examples, as shown in Figure 2, the display substrate may include: a first scan line GL1, a second scan line GL2, a third scan line GL3, a data line DL, a first power line VDD, a second power line VSS, an emission control line EML, a first initial signal line INIT1 and a second initial signal line INIT2.

[0110] In some examples, the first power line VDD can be configured to provide a constant first voltage signal to the pixel circuit, the second power line VSS can be configured to provide a constant second voltage signal to the pixel circuit, and the first voltage signal can be greater than the second voltage signal. The first scan line GL1 can be configured to provide a first scan signal SCAN1 to the pixel circuit; the data line DL can be configured to provide a data signal to the pixel circuit; the emission control line EML can be configured to provide an emission control signal EM to the pixel circuit; the second scan line GL2 can be configured to provide a second scan signal SCAN2 to the pixel circuit; and the third scan line GL3 can be configured to provide a third scan signal SCAN3 to the pixel circuit.

[0111] In some examples, the second scan line GL2 electrically connected to the pixel circuit in the nth row can be electrically connected to the first scan line GL1 electrically connected to the pixel circuit in the n-1th row, so as to be input with the first scan signal SCAN1(n-1), that is, the second scan signal SCAN2(n) and the first scan signal SCAN1(n-1) can be the same. The third scan line GL3 of the pixel circuit in the nth row can be electrically connected to the first scan line GL1 of the pixel circuit in the nth row, so as to be input with the first scan signal SCAN1(n), that is, the third scan signal SCAN3(n) and the first scan signal SCAN1(n) can be the same. Wherein, n is an integer greater than 0. In this way, the signal lines of the display substrate can be reduced, and a narrow frame design of the display substrate can be achieved. However, this embodiment is not limited to this.

[0112] In some examples, the first initial signal line INIT1 can be configured to provide a first initial signal to the pixel circuit, and the second initial signal line INIT2 can be configured to provide a second initial signal to the pixel circuit. For example, the first initial signal can be different from the second initial signal. The first initial signal and the second initial signal can be constant voltage signals, and their magnitudes can be, for example, between the first voltage signal and the second voltage signal, but are not limited thereto. In other examples, the first initial signal and the second initial signal can be the same, and only the first initial signal line can be provided to provide the first initial signal.

[0113] In some examples, as shown in FIG2 , the gate of the third transistor T3 is electrically connected to the first node N1, the first electrode of the third transistor T3 is electrically connected to the second node N2, and the second electrode of the third transistor T3 is electrically connected to the third node N3. The third transistor T3 may also be referred to as a driving transistor. The gate of the fourth transistor T4 is electrically connected to the first scan line GL1, the first electrode of the fourth transistor T4 is electrically connected to the data line DL, and the second electrode of the fourth transistor T4 is electrically connected to the first electrode of the third transistor T3. The fourth transistor T4 may also be referred to as a data write transistor. The gate of the second transistor T2 is electrically connected to the first scan line GL1, the first electrode of the second transistor T2 is electrically connected to the gate of the third transistor T3, and the second electrode of the second transistor T2 is electrically connected to the second electrode of the third transistor T3. The second transistor T2 may also be referred to as a threshold compensation transistor. The gate of the fifth transistor T5 is electrically connected to the emission control line EML, the first electrode of the fifth transistor T5 is electrically connected to the first power line VDD, and the second electrode of the fifth transistor T5 is electrically connected to the first electrode of the third transistor T3. The gate of the sixth transistor T6 is electrically connected to the emission control line EML, the first electrode of the sixth transistor T6 is electrically connected to the second electrode of the third transistor T3, and the second electrode of the sixth transistor T6 is electrically connected to the anode of the light-emitting element EL. The fifth transistor T5 and the sixth transistor T6 may also be referred to as emission control transistors. The first transistor T1 is electrically connected to the gate of the third transistor T3 and is configured to reset the gate of the third transistor T3. The seventh transistor T7 is electrically connected to the anode of the light-emitting element EL and is configured to reset the anode of the light-emitting element EL. The gate of the first transistor T1 is electrically connected to the second scan line GL2, the first electrode of the first transistor T1 is electrically connected to the first initial signal line INIT1, and the second electrode of the first transistor T1 is electrically connected to the gate of the third transistor T3. The gate of the seventh transistor T7 is electrically connected to the third scan line GL3, the first electrode of the seventh transistor T7 is electrically connected to the second initial signal line INIT2, and the second electrode of the seventh transistor T7 is electrically connected to the anode of the light-emitting element EL. The first transistor T1 and the seventh transistor T7 may also be referred to as reset control transistors. A first plate of the storage capacitor Cst is electrically connected to the gate of the third transistor T3 , and a second plate of the storage capacitor Cst is electrically connected to the first power line VDD.

[0114] In this example, the first node N1 is the connection point of the storage capacitor Cst, the first transistor T1, the third transistor T3 and the second transistor T2, the second node N2 is the connection point of the fifth transistor T5, the fourth transistor T4 and the third transistor T3, the third node N3 is the connection point of the third transistor T3, the second transistor T2 and the sixth transistor T6, and the fourth node N4 is the connection point of the sixth transistor T6, the seventh transistor T7 and the light-emitting element EL.

[0115] The operation process of the pixel circuit is described below. The pixel circuit shown in FIG2 includes a plurality of transistors, all of which are P-type transistors. In this example, the third scan signal provided by the third scan line GL3 may be the same as the first scan signal provided by the first scan line GL1.

[0116] In some examples, during a frame display period, the operation process of the pixel circuit may include: a first stage, a second stage, and a third stage.

[0117] The first phase is called the reset phase. The second scan signal SCAN2 provided by the second scan line GL2 can be a low-level signal, turning on the first transistor T1. The first initial signal provided by the first initial signal line INIT1 is provided to the first node N1, initializing the first node N1 and clearing the existing data voltage in the storage capacitor Cst. The first scan signal SCAN1 provided by the first scan line GL1 can be a high-level signal, and the emission control signal EM provided by the emission control line EML can be a high-level signal, turning off the fourth transistor T4, the second transistor T2, the fifth transistor T5, the sixth transistor T6, and the seventh transistor T7. During this phase, the light-emitting element EL does not emit light.

[0118] The second phase is called the data writing phase or the threshold compensation phase. The first scan signal SCAN1 provided by the first scan line GL1 can be a low-level signal, the second scan signal SCAN2 provided by the second scan line GL2, and the emission control signal EM provided by the emission control line EML can both be high-level signals, and the data line DL outputs the data signal DATA. During this phase, since the first plate of the storage capacitor Cst is at a low level, the third transistor T3 is turned on. The first scan signal SCAN1 is a low-level signal, turning on the second transistor T2, the fourth transistor T4, and the seventh transistor T7. The second transistor T2 and the fourth transistor T4 are turned on, causing the data voltage Vdata output by the data line DL to be provided to the first node N1 via the second node N2, the turned-on third transistor T3, the third node N3, and the turned-on second transistor T2. The difference between the data voltage Vdata output by the data line DL and the threshold voltage of the third transistor T3 is then charged into the storage capacitor Cst. The voltage on the first plate of the storage capacitor Cst (i.e., the first node N1) is Vdata - |Vth|, where Vdata is the data voltage output by the data line DL and Vth is the threshold voltage of the third transistor T3. The seventh transistor T7 is turned on, so that the second initialization signal provided by the second initialization signal line INIT2 is provided to the anode of the light-emitting element EL, initializing (resetting) the anode of the light-emitting element EL and clearing the pre-stored voltage therein, completing the initialization and ensuring that the light-emitting element EL does not emit light. The second scan signal SCAN2 provided by the second scan line GL2 can be a high-level signal, turning off the first transistor T1. The emission control signal EM provided by the emission control signal line EML is a high-level signal, turning off the fifth transistor T5 and the sixth transistor T6.

[0119] The third phase is called the light-emitting phase. The light-emitting control signal EM provided by the light-emitting control line EML is a low-level signal, while the first scan signal SCAN1 provided by the first scan line GL1 and the second scan signal SCAN2 provided by the second scan line GL2 are high-level signals. The light-emitting control signal EM provided by the light-emitting control line EML is a low-level signal, turning on the fifth transistor T5 and the sixth transistor T6. The first voltage signal output from the first power line VDD provides a driving voltage to the anode of the light-emitting element EL through the turned-on fifth transistor T5, third transistor T3, and sixth transistor T6, driving the light-emitting element EL to emit light.

[0120] During the pixel circuit driving process, the driving current flowing through the third transistor T3 is determined by the voltage difference between its gate and the first electrode. Since the voltage of the first node N1 is Vdata-|Vth|, the driving current of the third transistor T3 is: I=K×(Vgs-Vth) 2 =K×[(Vdd-Vdata+|Vth|)-Vth] 2=K×[Vdd-Vdata] 2 .

[0121] Wherein, I is the driving current flowing through the third transistor T3, that is, the driving current driving the light-emitting element EL, K is a constant, Vgs is the voltage difference between the gate and the first electrode of the third transistor T3, Vth is the threshold voltage of the third transistor T3, Vdata is the data voltage output by the data line DL, and Vdd is the first voltage signal output by the first power line VDD.

[0122] It can be seen from the above formula that the current flowing through the light emitting element EL has nothing to do with the threshold voltage of the third transistor T3. Therefore, the pixel circuit of this embodiment can better compensate for the threshold voltage of the third transistor T3.

[0123] In some examples, as shown in FIG1 , the first display area A1 may include: a plurality of first pixel circuits 11 and a plurality of first light-emitting elements 13 , wherein at least one of the plurality of first pixel circuits 11 is electrically connected to at least one of the plurality of first light-emitting elements 13 , and the at least one pixel circuit 11 may be configured to drive the at least one first light-emitting element 13 to emit light. The orthographic projection of the first light-emitting element 13 on the substrate may at least partially overlap with the orthographic projection of the first pixel circuit 11 to which it is connected. For example, the plurality of first pixel circuits 11 and the plurality of first light-emitting elements 13 may be electrically connected in a one-to-one correspondence.

[0124] In some examples, as shown in FIG1 , the second display area A2 may include: a plurality of second pixel circuits 12 and a plurality of second light-emitting elements 14. At least one of the plurality of second pixel circuits 12 is electrically connected to at least one of the plurality of second light-emitting elements 14, and the at least one second pixel circuit 12 may be configured to drive the at least one second light-emitting element 14 to emit light. The orthographic projection of the second light-emitting element 14 on the substrate may at least partially overlap with the orthographic projection of the second pixel circuit 12 to which it is connected. For example, the plurality of second pixel circuits 12 and the plurality of second light-emitting elements 14 may be electrically connected in a one-to-one correspondence.

[0125] FIG3 is a partial schematic diagram of the first display area of ​​at least one embodiment of the present disclosure. In some examples, as shown in FIG3 , the first display area A1 may include, within a plane parallel to the display substrate, a plurality of display island areas A11 arranged in an array. Each display island area A11 may be configured to display an image. The plurality of display island areas A11 may be arranged in an array along a first direction X and a second direction Y. The first direction X and the second direction Y may intersect, for example, the first direction X may be perpendicular to the second direction Y. The plurality of display island areas A11 arranged along the first direction X may be referred to as a row of display island areas, and the plurality of display island areas arranged along the second direction Y may be referred to as a column of display island areas.

[0126] In some examples, as shown in FIG3 , the shapes of the multiple display islands A11 can be substantially the same in a plane parallel to the display substrate. For example, the display islands A11 can be irregularly shaped to provide sufficient light-emitting area to ensure a good display effect. The display islands A11 can also have smooth edges to reduce light diffraction effects, thereby improving image quality.

[0127] In some examples, as shown in FIG3 , a light-transmitting area is provided between adjacent display island areas A11. Each light-transmitting area can be configured to provide a light transmission space. For example, the light-transmitting area may include: a first light-transmitting area A121 and a second light-transmitting area A122. The first light-transmitting area A121 may be located between two adjacent rows of display island areas (for example, the kth row and the k+1th row of display island areas, where k is an integer greater than 0). Multiple first light-transmitting areas A121 and multiple rows of display island areas A11 may be spaced apart. Multiple second light-transmitting areas A122 may be located between two adjacent columns of display island areas A11 (for example, the mth column and the m+1th column of display island areas, where m is an integer greater than 0). For example, multiple second light-transmitting areas A122 may be independently provided. Multiple second light-transmitting areas A122 may be arranged in sequence along the second direction Y, and the second light-transmitting areas A122 may not be connected to the first light-transmitting areas A121. A second light-transmitting region A122 may be located between two adjacent display island regions A11 in a row of display island regions A11. For example, the area of ​​a single first light-transmitting region A121 may be larger than the area of ​​a single second light-transmitting region A122. However, this embodiment is not limited to this. For example, a second light-transmitting region A122 may be connected to a first light-transmitting region A121 adjacent to the first light-transmitting region A121 in the second direction Y.

[0128] In some examples, as shown in FIG3 , a plurality of first routing areas A131 may be further provided between the display island areas A11. The plurality of first routing areas A131 may be provided independently. The first routing area A131 may be located between two adjacent display island areas A11 in a row of display island areas A11. Adjacent display island areas A11 in a row of display island areas A11 may be connected through the first routing area A131. The second light-transmitting area A122 may be surrounded by the first routing area A131; alternatively, the second light-transmitting area A122 may be surrounded by the first routing area A131 and the display island area A11. In this example, signal transmission along the first direction X between the display island areas A11 is achieved by providing the first routing area A131.

[0129] Figure 4 is a schematic diagram illustrating the arrangement of the first pixel circuit and the first light-emitting element in the first display area of ​​at least one embodiment of the present disclosure. In some examples, as shown in Figure 4 , a display island A11 may include a first pixel unit, each of which may include three first sub-pixels, each of which may include a first pixel circuit and a first light-emitting element. The three first sub-pixels within display island A11 may be configured to emit light of different colors.

[0130] In some examples, as shown in FIG4 , the display island area A11 may include: three first pixel circuits (e.g., including first pixel circuits 11a, 11b, and 11c), and three first light-emitting elements (e.g., including first light-emitting elements 13a, 13b, and 13c). The three first pixel circuits and the three first light-emitting elements may be electrically connected in a one-to-one correspondence. The first pixel circuit 11a may be electrically connected to the first light-emitting element 13a, the first pixel circuit 11b may be electrically connected to the first light-emitting element 13b, and the first pixel circuit 11c may be electrically connected to the first light-emitting element 13c.

[0131] In some examples, first light-emitting element 13a can be configured to emit a first color of light, first light-emitting element 13b can be configured to emit a second color of light, and first light-emitting element 13c can be configured to emit a third color of light. In some examples, the first color of light can be red, the second color of light can be green, and the third color of light can be blue. That is, first light-emitting element 13a can be a red light-emitting element, first light-emitting element 13b can be a green light-emitting element, and first light-emitting element 13c can be a blue light-emitting element.

[0132] In some examples, as shown in FIG4 , the first pixel circuits 11 a , 11 b , and 11 c in one display island A11 may be sequentially arranged along the first direction X. A plurality of first pixel circuits in a row of display islands A11 may be arranged as a row along the first direction X, and a plurality of first pixel circuits in a column of display islands A11 may be arranged as three columns along the second direction Y.

[0133] In some examples, as shown in FIG4 , the first light-emitting elements 13a and 13b within a display island A11 can be arranged sequentially along the second direction Y, and the first light-emitting element 13c can be located on the same side of the first light-emitting elements 13a and 13b in the first direction X. A plurality of first light-emitting elements 13a within a row of display islands A11 can be arranged in the i-th row, a plurality of first light-emitting elements 13c can be arranged in the i+1-th row, and a plurality of first light-emitting elements 13b can be arranged in the i+2-th row. Multiple rows of first light-emitting elements can be arranged repeatedly according to the above rule. The first light-emitting elements 13a and the first light-emitting elements 13b within the display island A11 can be arranged alternately in the second direction Y. Multiple first light-emitting elements 13a and multiple first light-emitting elements 13b within a column of display islands A11 can be arranged alternately in the j-th column, and a plurality of first light-emitting elements 13c can be arranged sequentially in the j+1-th column. Multiple columns of first light-emitting elements can be arranged repeatedly according to the above rule. Wherein, i and j are both integers greater than 0. In this example, three rows of first light-emitting elements may be arranged in one row of the display island area A11 , and two columns of first light-emitting elements may be arranged in one column of the display island area A11 .

[0134] In some examples, as shown in FIG4 , the first light-emitting element 13a may have a light-emitting region 130a, the first light-emitting element 13b may have a light-emitting region 130b, and the first light-emitting element 13c may have a light-emitting region 130c. The light-emitting region 130a of the first light-emitting element 13a, the light-emitting region 130b of the first light-emitting element 13b, and the light-emitting region 130c of the first light-emitting element 13c may all be substantially circular or elliptical. The area of ​​the light-emitting region 130a of the first light-emitting element 13a may be smaller than the area of ​​the light-emitting region 130b of the first light-emitting element 13b, and may be smaller than the area of ​​the light-emitting region 130c of the first light-emitting element 13c. The area of ​​the light-emitting region 130b of the first light-emitting element 13b may be substantially the same as the area of ​​the light-emitting region 130c of the first light-emitting element 13c. The light-emitting region of the light-emitting element in this example refers to the portion of the light-emitting element located at the pixel opening of the pixel definition layer.

[0135] In some examples, as shown in FIG4 , the orthographic projection of the light-emitting region 130a of the first light-emitting element 13a on the substrate may partially overlap with the orthographic projection of the first pixel circuit 11a on the substrate. The orthographic projection of the light-emitting region 130b of the first light-emitting element 13b on the substrate may not overlap with the orthographic projection of the connected first pixel circuit 11b on the substrate, and the orthographic projection of the light-emitting region 130b on the substrate may partially overlap with the orthographic projection of the first pixel circuit 11a on the substrate. The orthographic projection of the light-emitting region 130c of the first light-emitting element 13c on the substrate may at least partially overlap with the orthographic projection of the connected first pixel circuit 11c on the substrate. For example, the orthographic projection of the light-emitting region 130c on the substrate may be located within the range of the orthographic projection of the first pixel circuit 11c on the substrate.

[0136] The arrangement of the three first pixel circuits and the three first light-emitting elements of the display substrate of this example is conducive to centralized arrangement. By arranging the three first pixel circuits and the three first light-emitting elements as a first pixel unit in a display island area, it is convenient to arrange the display island areas in an array, and the space between the display island areas can be increased, avoiding the large number of display islands and recessed slits caused by separately arranging a first pixel circuit and a first light-emitting element in each display island area. By reducing the number of islands and slits, the light diffraction condition of the first display area can be improved, and the edges of the display island areas can be smoothed.

[0137] Fig. 5 is a partial top view of the area S1 in Fig. 4. Fig. 5 illustrates four display islands A11 arranged in a 2×2 array.

[0138] In some examples, in a direction perpendicular to the display substrate, the display substrate may include: a substrate, a circuit structure layer, and a light-emitting structure layer sequentially disposed on the substrate. The circuit structure layer of the first display area may include at least a plurality of first pixel circuits, and the light-emitting structure layer may include at least a plurality of first light-emitting elements. The first light-emitting elements may include at least an anode, an organic light-emitting layer, and a cathode, and the anodes of the first light-emitting elements may be connected to corresponding first pixel circuits.

[0139] In some examples, in a direction perpendicular to the display substrate, the circuit structure layer of the first display area may include: a semiconductor layer, a first conductive layer, a second conductive layer, a third conductive layer, a transparent conductive layer, and a fourth conductive layer, sequentially disposed on the substrate. A first insulating layer may be disposed between the semiconductor layer and the first conductive layer, a second insulating layer may be disposed between the first conductive layer and the second conductive layer, a third insulating layer may be disposed between the second conductive layer and the third conductive layer, a fourth insulating layer may be disposed between the third conductive layer and the transparent conductive layer, a fifth insulating layer may be disposed between the transparent conductive layer and the fourth conductive layer, and a sixth insulating layer may be disposed on the side of the fourth conductive layer away from the substrate.

[0140] In some examples, the light-emitting structure layer may include at least: an anode layer, a pixel definition layer, an organic light-emitting layer and a cathode layer sequentially arranged on the substrate. The anode layer can be electrically connected to the first pixel circuit of the circuit structure layer, the organic light-emitting layer can be connected to the anode layer, and the cathode layer can be connected to the organic light-emitting layer. The organic light-emitting layer emits light of corresponding colors under the drive of the anode layer and the cathode layer. An encapsulation structure layer can be provided on the side of the light-emitting structure layer away from the substrate. The encapsulation structure layer may include a stacked first encapsulation layer, a second encapsulation layer and a third encapsulation layer. The first encapsulation layer and the third encapsulation layer may be made of inorganic materials, the second encapsulation layer may be made of organic materials, and the second encapsulation layer may be provided between the first encapsulation layer and the third encapsulation layer to form an inorganic material / organic material / inorganic material stacked structure, which can ensure that external water vapor cannot enter the light-emitting structure layer. In some possible implementations, the display substrate may also include other film layers, such as a touch structure layer, a color filter layer, etc., which are not limited in the present disclosure.

[0141] The structure and preparation process of the display substrate of this example are exemplarily described below. The "patterning process" mentioned in this disclosure includes processes such as coating photoresist, mask exposure, development, etching, and stripping photoresist for metal materials, inorganic materials or transparent conductive materials, and includes processes such as coating organic materials, mask exposure and development for organic materials. Deposition can be carried out by any one or more of sputtering, evaporation, and chemical vapor deposition, coating can be carried out by any one or more of spraying, spin coating and inkjet printing, and etching can be carried out by any one or more of dry etching and wet etching, which are not limited in this disclosure. "Thin film" refers to a thin film made by deposition, coating or other processes on a substrate of a certain material. If the "thin film" does not require a patterning process during the entire production process, the "thin film" can also be called a "layer". If the "thin film" requires a patterning process during the entire production process, it is called a "thin film" before the patterning process and a "layer" after the patterning process. The "layer" after the patterning process contains at least one "pattern".

[0142] The “A and B are arranged in the same layer” or “A and B are of the same layer structure” mentioned in the present disclosure means that A and B are formed simultaneously through the same patterning process. “A and B are of different layer structures” means that A and B are formed separately through at least two patterning processes. The “thickness” of the film layer is the dimension of the film layer in the direction perpendicular to the display substrate. In the exemplary embodiments of the present disclosure, “the orthographic projection of B is within the range of the orthographic projection of A” or “the orthographic projection of A includes the orthographic projection of B” means that the boundary of the orthographic projection of B falls within the boundary of the orthographic projection of A, or the boundary of the orthographic projection of A overlaps with the boundary of the orthographic projection of B. The “shape of A” mentioned in the present disclosure refers to the shape of the orthographic projection of A on the substrate.

[0143] In some examples, the manufacturing process of the display substrate of this example may include the following operations: The structure of each first pixel circuit region in the circuit structure layer of the display substrate is substantially the same, and the structure of the first first pixel circuit region is used as an example for description below.

[0144] (1-1) Provide a substrate. In some examples, the substrate can be a rigid substrate or a flexible substrate. For example, the rigid substrate can be, but is not limited to, one or more of glass and quartz, and the flexible substrate can be, but is not limited to, one or more of polyethylene terephthalate, polyethylene terephthalate, polyetheretherketone, polystyrene, polycarbonate, polyarylate, polyarylate, polyimide, polyvinyl chloride, polyethylene, and textile fiber. In some examples, the flexible substrate can include a first flexible material layer, a first inorganic material layer, a second flexible material layer, and a second inorganic material layer stacked thereon. The materials of the first flexible material layer and the second flexible material layer can be polyimide (PI), polyethylene terephthalate (PET), or a surface-treated polymer soft film, and the materials of the first inorganic material layer and the second inorganic material layer can be silicon nitride (SiNy, y>0) or silicon oxide (SiOx, x>0), etc., to improve the substrate's resistance to water and oxygen.

[0145] (1-2) Forming a semiconductor layer. In some examples, a semiconductor thin film is deposited on a substrate and patterned using a patterning process to form a semiconductor layer disposed on the substrate, as shown in FIG6 . FIG6 is a schematic diagram of the display substrate after the semiconductor layer is formed in FIG5 .

[0146] In some examples, as shown in Figure 6, the semiconductor layer of a single display island area in the display substrate may include at least: a first active layer 21 of a first transistor T1 of three first pixel circuits, a second active layer 22 of a second transistor T2, a third active layer 23 of a third transistor T3, a fourth active layer 24 of a fourth transistor T4, a fifth active layer 25 of a fifth transistor T5, a sixth active layer 26 of a sixth transistor T6, and a seventh active layer 27 of a seventh transistor T7.

[0147] In some examples, the first active layer 21, second active layer 22, third active layer 23, fourth active layer 24, fifth active layer 25, sixth active layer 26, and seventh active layer 27 of each first pixel circuit can be interconnected as an integral structure. The fifth active layer 25 and the sixth active layer 26 can be located on one side of the third active layer 23 in the second direction Y, and the fourth active layer 24, the second active layer 22, the first active layer 21, and the seventh active layer 27 can be located on the other side of the third active layer 23 in the second direction Y. The first active layer 21 can be located on a side of the second active layer 22 away from the third active layer 23 in the second direction Y. The seventh active layer 27 can be located on a side of the second active layer 22 away from the fourth active layer 24 in the first direction X. The active layers of the transistors of adjacent first pixel circuits within a display island can be independently arranged.

[0148] In some examples, the shape of the first active layer 21 can be roughly U-shaped, the shape of the second active layer 22 can be roughly L-shaped, the shape of the third active layer 23 can be roughly n-shaped, and the shapes of the fourth active layer 24, the fifth active layer 25, the sixth active layer 26 and the seventh active layer 27 can be roughly I-shaped.

[0149] In some examples, the active layer of each transistor may include: a first region, a second region, and a channel region located between the first and second regions. In some examples, the first region 211 of the first active layer 21 is connected to the first region 271 of the seventh active layer 27. The first region 211 of the first active layer 21 may also serve as the first region 271 of the seventh active layer 27. The second region 212 of the first active layer 21 is connected to the first region 221 of the second active layer 22. The second region 212 of the first active layer 21 may also serve as the first region 221 of the second active layer 22. The first region 231 of the third active layer 23 may be connected to the second region 242 of the fourth active layer 24 and the second region 252 of the fifth active layer 25. The first region 231 of the third active layer 23 may also serve as the second region 242 of the fourth active layer 24 and the second region 252 of the fifth active layer 25, forming a second node of the first pixel circuit. The second region 232 of the third active layer 23 can be connected to the second region 222 of the second active layer 22 and the first region 261 of the sixth active layer 26. The second region 232 of the third active layer 23 can simultaneously serve as the second region 222 of the second active layer 22 and the first region 261 of the sixth active layer 26, forming a third node of the first pixel circuit. The first region 241 of the fourth active layer 24, the first region 251 of the fifth active layer 25, the second region 252 of the sixth active layer 26, and the second region 272 of the seventh active layer 27 can be provided separately. The first region 241 of the fourth active layer 24 can be located on a side of the second region 212 of the first active layer 21 away from the first region 211 of the first active layer 21 in the first direction X. The first region 251 of the fifth active layer 25 can be located on a side of the third active layer 23 away from the first region 241 of the fourth active layer 24 in the second direction Y. The second region 262 of the sixth active layer 26 may be adjacent to the first region 251 of the fifth active layer 25 in the first direction X. The second region 272 of the seventh active layer 27 may be adjacent to the second region 222 of the second active layer 22 in the first direction X.

[0150] In some examples, semiconductor layers in adjacent display islands may be spaced apart from each other. For example, the active layers of multiple transistors in a first pixel circuit in adjacent display islands along a first direction X may not be connected, and the active layers of multiple transistors in a first pixel circuit in adjacent display islands along a second direction Y may not be connected.

[0151] (1-3) Forming a first conductive layer. In some examples, a first insulating film and a first conductive film are sequentially deposited on the substrate having the aforementioned pattern formed thereon. The first conductive film is patterned using a patterning process to form a first insulating layer disposed on the semiconductor layer and a first conductive layer disposed on the first insulating layer. In some examples, the first conductive layer may also be referred to as a first gate metal layer. The first insulating layer may also be referred to as a first gate insulating layer.

[0152] Figure 7A is a schematic diagram of the display substrate after the first conductive layer is formed in Figure 5. Figure 7B is a schematic diagram of the first conductive layer in Figure 7A. In some examples, as shown in Figures 7A and 7B, the first conductive layer of a single display island in the first display area may include at least: a first scan line 31, a second scan line 32, a light emission control line 33, and first plates 281 of storage capacitors of three first pixel circuits.

[0153] In some examples, the shapes of the first scan line 31, the second scan line 32, and the light-emitting control line 33 can all be linear shapes whose main parts extend along the first direction X, for example, they can be straight lines extending along the first direction X. The second scan line 32, the first scan line 31, and the light-emitting control line 33 in the display island area can be arranged sequentially along the second direction Y. The first scan line 31 can be located on one side of the second scan line 32 in the second direction Y, and the light-emitting control line 33 can be located on one side of the first scan line 31 in the second direction Y. The first scan line 31 can be located between the second scan line 32 and the light-emitting control line 33. The first plate 281 of the storage capacitor of the first pixel circuit can be located between the first scan line 31 and the light-emitting control line 33. The first plates 281 of the storage capacitors of the three first pixel circuits can be arranged sequentially along the first direction X.

[0154] In some examples, the orthographic projection of the first plate 281 of the storage capacitor on the substrate can be substantially rectangular, for example, a rounded rectangle. The orthographic projection of the first plate 281 of the storage capacitor on the substrate can at least partially overlap with the orthographic projection of the third active layer 13 of the third transistor T3 on the substrate. The first plate 281 can serve as both the lower plate of the storage capacitor and the gate of the third transistor T3.

[0155] In some examples, the second scan line 32 may partially overlap with the orthographic projection of the first active layer 21 of the first transistor T1 on the substrate. The overlapping region of the second scan line 32 and the first active layer 21 may serve as the gate of the first transistor T1 with a dual-gate structure.

[0156] In some examples, the area where the first scan line 31 overlaps with the fourth active layer 24 of the fourth transistor T4 can serve as the gate of the fourth transistor T4. The area where the first scan line 31 overlaps with the seventh active layer 27 of the seventh transistor T7 can serve as the gate of the seventh transistor T7. The area where the first scan line 31 overlaps with the second active layer 22 of the second transistor T2 can serve as the first gate of the second transistor T2.

[0157] In some examples, a scan extension segment 31-1 may be provided on a side of the first scan line 31 near the second scan line 32. The scan extension segment 31-1 may be provided in each pixel circuit. The first end of the scan extension segment 31-1 is connected to the first scan line 31, and the second end of the scan extension segment 31-1 extends toward the second scan line 32. The region where the scan extension segment 31-1 overlaps with the second active layer 22 may serve as the second gate of the second transistor T2, thereby implementing a dual-gate structure for the second transistor T2. Multiple scan extension segments 31-1 and the first scan line 31 may be interconnected as an integrated structure.

[0158] In some examples, the area where the emission control line 33 overlaps the fifth active layer 25 of the fifth transistor T5 can serve as the gate of the fifth transistor T5. The area where the emission control line 33 overlaps the sixth active layer 26 of the sixth transistor T6 can serve as the gate of the sixth transistor T6.

[0159] In some examples, the first conductive layer of the first routing area between adjacent display island areas in the first direction X may include at least: a first scan connection line 71, a second scan connection line 72, and a light-emitting control connection line 73. The first scan connection line 71, the second scan connection line 72, and the light-emitting control connection line 73 may all be in the shape of lines with their main portions extending along the first direction X. For example, the second scan connection line 72 and the light-emitting control connection line 73 may be straight lines extending along the first direction X, and the first scan connection line 71 may be in the shape of a broken line or an arc extending along the first direction X. The first scan connection line 71 may be bent toward one side of the second scan connection line 72. The first scan connection line 71 may be located on one side of the second scan connection line 72 in the second direction Y, and the light-emitting control connection line 73 may be located on one side of the first scan connection line 71 in the second direction Y. The first scan connection line 71 may be located between the second scan connection line 72 and the light-emitting control connection line 73.

[0160] In some examples, the boundary of the second light-transmitting area along the second direction Y can be limited by the first scan connection line 71 and the light-emitting control connection line 73. This example is advantageous in increasing the area of ​​the second light-transmitting area by adopting a design in which the first scan connection line 71 is bent toward the side of the second scan connection line 72. In other examples, the second scan connection line 72 can be designed to bend toward the side away from the first scan connection line 71, and the light-emitting control connection line 73 can be designed to bend toward the side away from the first scan connection line 71 to increase the area of ​​the second light-transmitting area. In other examples, the light-emitting control connection line 73 can be designed to bend toward the side close to the first scan connection line 71, so that the first light-transmitting area and the second light-transmitting area can be connected, thereby improving the diffraction caused by the isolated slits.

[0161] In some examples, the first scan lines 31 in adjacent display islands along the first direction X can be connected via a first scan connection line 71. The two ends of the first scan connection line 71 can be respectively connected to the first scan lines 31 in two adjacent display islands. The second scan lines 32 in adjacent display islands along the first direction X can be connected via a second scan connection line 72. The two ends of the second scan connection line 72 can be respectively connected to the second scan lines 32 in two adjacent display islands. The light-emission control lines 33 in adjacent display islands along the first direction X can be connected via a light-emission control connection line 73. The two ends of the light-emission control connection line 73 can be respectively connected to the light-emission control lines 33 in two adjacent display islands.

[0162] In some examples, after forming the first conductive layer pattern, the first conductive layer can be used as a shield to perform conductorization on the semiconductor layer. The semiconductor layer in the area shielded by the first conductive layer forms the channel region of the first transistor T1 to the seventh transistor T7, and the semiconductor layer in the area not shielded by the first conductive layer can be conductorized, that is, the first and second areas of the first active layer 21 to the seventh active layer 27 can both be conductorized.

[0163] (1-4) Forming a second conductive layer. In some examples, a second insulating film and a second conductive film are sequentially deposited on the substrate having the aforementioned pattern formed thereon. The second conductive film is patterned using a patterning process to form a second insulating layer disposed on the first conductive layer and a second conductive layer disposed on the second insulating layer. In some examples, the second conductive layer may also be referred to as a second gate metal layer. The second insulating layer may also be referred to as a second gate insulating layer.

[0164] Figure 8A is a schematic diagram of the display substrate after the second conductive layer is formed in Figure 5. Figure 8B is a schematic diagram of the second conductive layer in Figure 8A. In some examples, as shown in Figures 8A and 8B, the second conductive layer of a single display island in the first display area may include at least: a first initial signal line 34 and second plates 282 of storage capacitors of three first pixel circuits.

[0165] In some examples, the first initial signal line 34 may be shaped as a straight line with a main portion extending along the first direction X. The orthographic projection of the first initial signal line 34 on the substrate may be located on a side of the orthographic projection of the second scan line 32 on the substrate that is away from the orthographic projection of the first scan line 31 on the substrate. The orthographic projection of the first initial signal line 34 on the substrate may partially overlap with the orthographic projection of the second scan line 32 on the substrate, or may not overlap.

[0166] In some examples, the second plate 282 of the storage capacitor of the first pixel circuit can be located on one side of the first initial signal line 34 in the second direction Y. The orthographic projection of the second plate 282 of the storage capacitor on the substrate can partially overlap with the orthographic projection of the first plate 281 on the substrate. For example, the orthographic projection of the second plate 282 on the substrate can be approximately L-shaped. The second plates 282 of the storage capacitors of the three first pixel circuits can be arranged sequentially along the first direction X.

[0167] In some examples, an initial connection block 34-1 may be provided on a side of the first initial signal line 34 away from the second electrode plate 282, and the initial connection block 34-1 may be provided in each pixel circuit of the display island area. A first end of the initial connection block 34-1 is connected to the first initial signal line 34, and a second end of the initial connection block 34-1 extends in a direction away from the second electrode plate 282. The initial connection block 34-1 may be configured to be electrically connected to the first connection electrode 41 through a ninth via hole V9 formed subsequently. In some examples, the first initial signal line 34 and the plurality of initial connection blocks 34-1 may be an integrated structure connected to each other.

[0168] In some examples, the second conductive layer of the first routing area between adjacent display island areas in the first direction X may include at least a first initial connection line 74. The first initial connection line 74 may be in the shape of a straight line with a main portion extending along the first direction X. The orthographic projection of the first initial connection line 74 on the substrate may be located on a side of the orthographic projection of the second scan connection line 72 on the substrate that is away from the orthographic projection of the first scan connection line 71 on the substrate.

[0169] In some examples, the first initial signal lines 34 in adjacent display islands along the first direction X may be connected by a first initial connection line 74. Both ends of the first initial connection line 74 may be connected to the first initial signal lines 34 in adjacent display islands, respectively.

[0170] (1-5) Forming a third insulating layer. In some examples, a third insulating film is deposited on the substrate having the aforementioned pattern formed thereon, and the third insulating film is patterned using a patterning process to form a third insulating layer. The third insulating layer may be provided with a plurality of vias. The third insulating layer may also be referred to as an interlayer insulating layer.

[0171] FIG9 is a schematic diagram of the display substrate after the third insulating layer is formed in FIG5. In some examples, the plurality of vias in the third insulating layer of a single display island region may include at least a first via V1, a second via V2, a third via V3, a fourth via V4, a fifth via V5, a sixth via V6, a seventh via V7, an eighth via V8, and a ninth via V9.

[0172] In some examples, the orthographic projection of the first via hole V1 on the substrate may be located within the range of the orthographic projection of the first region 211 of the first active layer 21 on the substrate. The third insulating layer, the second insulating layer, and the first insulating layer within the first via hole V1 may be etched away to expose a portion of the surface of the first region 211 of the first active layer 21. The first via hole V1 may be configured to connect a subsequently formed first connection electrode to the first region 211 of the first active layer 21 through the via hole.

[0173] In some examples, the orthographic projection of the second via V2 on the substrate can be located within the range of the orthographic projection of the second region 212 of the first active layer 21 on the substrate. The third insulating layer, the second insulating layer, and the first insulating layer within the second via V2 can be etched away to expose a portion of the surface of the second region 212 of the first active layer 21. The second via V2 can be configured to connect a subsequently formed second connection electrode to the second region 212 of the first active layer 21 through the via.

[0174] In some examples, the orthographic projection of the third via V3 on the substrate can be located within the range of the orthographic projection of the first region 241 of the fourth active layer 24 on the substrate. The third insulating layer, the second insulating layer, and the first insulating layer within the third via V3 can be etched away to expose a portion of the surface of the first region 241 of the fourth active layer 24. The third via V3 can be configured to connect a subsequently formed third connection electrode to the first region 241 of the fourth active layer 24 through the via.

[0175] In some examples, the orthographic projection of the fourth via hole V4 on the substrate can be located within the range of the orthographic projection of the first region 251 of the fifth active layer 25 on the substrate. The third insulating layer, the second insulating layer, and the first insulating layer within the fourth via hole V4 can be etched away, exposing a portion of the surface of the first region 251 of the fifth active layer 25. The fourth via hole V4 can be configured to connect a subsequently formed fourth connection electrode to the first region 251 of the fifth active layer 25 through the via hole.

[0176] In some examples, the orthographic projection of the fifth via V5 on the substrate can be located within the range of the orthographic projection of the second region 262 of the sixth active layer 26 on the substrate. The third insulating layer, the second insulating layer, and the first insulating layer within the fifth via V5 can be etched away to expose a portion of the surface of the second region 262 of the sixth active layer 26. The fifth via V5 can be configured to connect a subsequently formed fifth connecting electrode to the second region 262 of the sixth active layer 26 through the via.

[0177] In some examples, the orthographic projection of the sixth via V6 on the substrate can be located within the range of the orthographic projection of the second region 272 of the seventh active layer 27 on the substrate. The third insulating layer, the second insulating layer, and the first insulating layer within the sixth via V6 can be etched away, exposing a portion of the surface of the second region 272 of the seventh active layer 27. The sixth via V6 can be configured to connect a subsequently formed fifth connection electrode to the second region 272 of the seventh active layer 27 through the via.

[0178] In some examples, the orthographic projection of the seventh via V7 on the substrate can be located within the range of the orthographic projection of the first electrode plate 281 on the substrate. The third insulating layer and the second insulating layer within the seventh via V7 can be etched away to expose a portion of the surface of the first electrode plate 281. The seventh via V7 can be configured to connect a subsequently formed second connection electrode to the first electrode plate 281 through the via.

[0179] In some examples, the orthographic projection of the eighth via V8 on the substrate can be located within the orthographic projection of the second electrode plate 282 on the substrate. The third insulating layer and the second insulating layer within the eighth via V8 can be etched away to expose a portion of the surface of the second electrode plate 282. The eighth via V8 can be configured to connect a subsequently formed fourth connection electrode to the second electrode plate 282 through the via.

[0180] In some examples, the orthographic projection of the ninth via V9 on the substrate can be located within the orthographic projection of the initial connection block 34-1 of the first initial signal line 34 on the substrate. The third insulating layer within the ninth via V9 can be etched away to expose a portion of the surface of the initial connection block 34-1. The ninth via V9 can be configured to connect a subsequently formed first connection electrode to the initial connection block 34-1 through the via.

[0181] (1-6) Forming a third conductive layer. In some examples, a third conductive film is deposited on the substrate having the aforementioned pattern formed thereon. The third conductive film is patterned using a patterning process to form a third conductive layer disposed on the third insulating layer. In some examples, the third conductive layer may also be referred to as a first source / drain metal layer.

[0182] Figure 10A is a schematic diagram of the display substrate after the third conductive layer is formed in Figure 5. Figure 10B is a schematic diagram of the third conductive layer in Figure 10A. In some examples, as shown in Figures 10A and 10B, the third conductive layer in a single display island region of the first display area may include at least a first connecting electrode 41, a second connecting electrode 42, a third connecting electrode 43, a fourth connecting electrode 44, a fifth connecting electrode 45, and a sixth connecting electrode 46.

[0183] In some examples, the shape of the first connection electrode 41 can be substantially L-shaped. The first connection electrode 41 can be connected to the first region 211 of the first active layer 21 through a first via V1, and can also be connected to the initial connection block 34-1 through a ninth via V9. Because the initial connection block 34-1 is connected to the first initial signal line 34, the first initial signal transmitted by the first initial signal line 34 can be provided to the first transistor T1 and the seventh transistor T7 through the first connection electrode 41.

[0184] In some examples, the second connection electrode 42 can be substantially L-shaped. The second connection electrode 42 can be connected to the second region 212 of the first active layer 21 of the first transistor T1 through a second via V2, and can also be electrically connected to the first electrode plate 281 through a seventh via V7. The second connection electrode 42 can electrically connect the first transistor, the second transistor, the third transistor, and the first electrode plate 281 of the storage capacitor, and can constitute a first node of the first pixel circuit.

[0185] In some examples, the third connection electrode 43 may be substantially rectangular, such as a rounded rectangle, and may be connected to the first region 241 of the fourth active layer 24 of the fourth transistor T4 through a third via hole V3.

[0186] In some examples, the fourth connection electrode 44 may be shaped like a 7. The fourth connection electrode 44 may be connected to the first region 251 of the fifth active layer 25 of the fifth transistor T5 through a fourth via V4 and may be connected to the second electrode plate 282 through an eighth via V8.

[0187] In some examples, the fifth connection electrode 45 may be shaped substantially like a zigzag line. The fifth connection electrode 45 may be connected to the second region 262 of the sixth active layer 26 of the sixth transistor T6 through a fifth via V5, and may also be connected to the second region 272 of the seventh active layer 27 of the seventh transistor T7 through a sixth via V6.

[0188] In some examples, the sixth connection electrode 46 can be substantially rectangular, such as a rounded rectangle. The sixth connection electrode 46 can be located on one side of the first connection electrode 41 in the first direction X. The orthographic projection of the sixth connection electrode 46 on the substrate can partially overlap with the orthographic projections of the first initial signal line 34 and the second scan line 32 on the substrate. The sixth connection electrode 46 can be configured to be electrically connected to the first power connection line through a fifteenth via hole formed subsequently.

[0189] (1-7) Forming a fourth insulating layer. In some examples, a fourth insulating film is deposited on the substrate having the aforementioned pattern formed thereon, and the fourth insulating film is patterned using a patterning process to form a fourth insulating layer. The fourth insulating layer may have a plurality of vias. In some examples, the fourth insulating layer may also be referred to as a passivation layer.

[0190] Figure 11 is a schematic diagram of the display substrate after the fourth insulating layer is formed in Figure 5. In some examples, the plurality of via holes in the fourth insulating layer of a single display island region may include at least an eleventh via hole V11, a twelfth via hole V12, a thirteenth via hole V13, a fourteenth via hole V14, and a fifteenth via hole V15.

[0191] In some examples, the orthographic projection of the eleventh via hole V11 on the substrate can be located within the range of the orthographic projection of the first connection electrode 41 on the substrate. The fourth insulating layer within the eleventh via hole V11 can be removed to expose a portion of the surface of the first connection electrode 41. The eleventh via hole V11 can be configured to connect a subsequently formed first conductive block to the first connection electrode 41 through the via hole.

[0192] In some examples, the orthographic projection of the twelfth via hole V12 on the substrate can be located within the range of the orthographic projection of the third connection electrode 43 on the substrate. The fourth insulating layer within the twelfth via hole V12 can be removed to expose a portion of the surface of the third connection electrode 43. The twelfth via hole V12 can be configured to allow a subsequently formed data line to be connected to the third connection electrode 43 through the via hole.

[0193] In some examples, the orthographic projection of the thirteenth via hole V13 on the substrate can be located within the range of the orthographic projection of the fourth connection electrode 44 on the substrate. The fourth insulating layer within the thirteenth via hole V13 can be removed, exposing a portion of the surface of the fourth connection electrode 44. The thirteenth via hole V13 can be configured to connect the first power connection portion of a subsequently formed first power connection line to the fourth connection electrode 44 through the via hole.

[0194] In some examples, the orthographic projection of the fourteenth via hole V14 on the substrate can be located within the range of the orthographic projection of the fifth connection electrode 45 on the substrate. The fourth insulating layer within the fourteenth via hole V14 can be removed to expose a portion of the surface of the fifth connection electrode 45. The fourteenth via hole V14 can be configured to connect a subsequently formed first anode connection electrode to the fifth connection electrode 45 through the via hole.

[0195] In some examples, the orthographic projection of the fifteenth via hole V15 on the substrate can be located within the range of the orthographic projection of the sixth connection electrode 46 on the substrate. The fourth insulating layer within the fifteenth via hole V15 can be removed to expose a portion of the surface of the sixth connection electrode 46. The fifteenth via hole V15 can be configured to connect the second power connection portion of the subsequently formed first power connection line to the sixth connection electrode 46 through the via hole.

[0196] (1-8) Forming a transparent conductive layer. In some examples, a transparent conductive film is deposited on the substrate having the aforementioned pattern, and the transparent conductive film is patterned by a patterning process to form a transparent conductive layer disposed on the fourth insulating layer.

[0197] Figure 12A is a schematic diagram of the display substrate after the transparent conductive layer is formed in Figure 5. Figure 12B is a schematic diagram of the transparent conductive layer in Figure 12A. In some examples, as shown in Figures 12A and 12B, the transparent conductive layer of a single display island in the first display area may include at least: three data lines (for example, including data lines 51a, 51b, and 51c), three first conductive blocks 52, and three first anode connection electrodes (for example, including first anode connection electrodes 53a, 53b, and 53c).

[0198] In some examples, the shape of each data line in the display island area can be roughly the same, for example, it can be a broken line shape with the main part extending along the second direction Y. The three data lines 51a, 51b and 51c can be arranged in sequence along the first direction X. The extension directions of the three data lines 51a, 51b and 51c can be roughly parallel. The data line 51a can be electrically connected to the third connection electrode 43 of the first first pixel circuit through the twelfth via V12, so as to be configured to provide a data signal to the first electrode of the fourth transistor T4 of the first first pixel circuit. The data line 51b can be configured to provide a data signal to the first electrode of the fourth transistor of the second first pixel circuit. The data line 51c can be configured to provide a data signal to the first electrode of the fourth transistor of the third first pixel circuit.

[0199] In some examples, the three first conductive blocks 52 in the display island region can have substantially the same shape, for example, all being rectangular, such as a rounded rectangle. The first conductive block 52 can be electrically connected to the first connection electrode 41 through the eleventh via V11. The first conductive block 52 is not electrically connected to the subsequently prepared conductive film layer. The first conductive block 52 can be connected in parallel with the first connection electrode 41 to reduce the resistance of the first connection electrode 41, thereby ensuring the transmission quality of the first initial signal. In other examples, the first conductive block can be omitted.

[0200] In some examples, the three first anode connection electrodes within the display island region can have substantially the same shape, for example, a substantially rectangular shape. The first anode connection electrode 53a can be located between data lines 51a and 51b, the first anode connection electrode 53b can be located between data lines 51b and 51c, and the first anode connection electrode 53c can be located on the side of data line 51c away from data line 51b. The first anode connection electrode 53a can be connected to the fifth connection electrode 45 of the first first pixel circuit via a fourteenth via hole V14. The first anode connection electrode 53a can be configured to be electrically connected to the anode of a subsequently formed first first light-emitting element, thereby electrically connecting the first first pixel circuit to the first first light-emitting element. The first anode connection electrode 53b can be configured to be electrically connected to the fifth connection electrode of the second first pixel circuit, thereby subsequently electrically connecting the second first pixel circuit to the second first light-emitting element. The first anode connection electrode 53c can be configured to be electrically connected to the fifth connection electrode of the third first pixel circuit, thereby subsequently electrically connecting the third first pixel circuit to the third first light-emitting element.

[0201] In some examples, the transparent conductive layer in the first light-transmitting area between adjacent display island areas in the second direction Y may include at least: a plurality of first power connection lines (for example, including first power connection lines 76a, 76b, and 76c), and a plurality of data connection lines (for example, including data connection lines 75a, 75b, and 75c). The plurality of data connection lines and the plurality of first power connection lines may be arranged at intervals. The plurality of data connection lines and the plurality of first power connection lines may be shaped substantially like a zigzag line with a main portion extending along the second direction Y.

[0202] In some examples, data lines 51a in adjacent display islands in the second direction Y can be connected via a data connection line 75a. A first end of the data connection line 75a is connected to a data line 51a in one display island, and a second end is connected to a data line 51a in another display island. Data lines 51b in adjacent display islands can be connected via a data connection line 75b. Data lines 51c in adjacent display islands can be connected via a data connection line 75c. The data connection line and the connected data lines can be an integrated structure that is interconnected.

[0203] In some examples, the first power connection line can be located between two adjacent data lines. The spacing between the first power connection line 76a and the data line 75a can be smaller than the spacing between the first power connection line 76a and the data line 75b. The first power connection line can extend along the second direction Y into the display island area.

[0204] In some examples, the first power connection line 76a can have a first power connection portion 76a-1 and a second power connection portion 76a-2. The first power connection portion 76a-1 of the first power connection line 76a can be electrically connected to the fourth connection electrode of the first first pixel circuit in the display island area through the thirteenth via V13, thereby being configured to provide a first voltage signal to the storage capacitor and the fifth transistor of the first first pixel circuit. The second power connection portion 76a-2 of the first power connection line 76a can extend to another display island area and be electrically connected to the sixth connection electrode of the first first pixel circuit in the other display island area through the fifteenth via V15. The second power connection line 76b can be configured to provide a first voltage signal to the second first pixel circuit in the display island area. The second power connection line 76c can be configured to provide a first voltage signal to the third first pixel circuit in the display island area.

[0205] (1-9) Forming a fifth insulating layer. In some examples, a fifth insulating film is coated on the substrate having the aforementioned pattern formed thereon, and the fifth insulating film is patterned using a patterning process to form the fifth insulating layer. The fifth insulating layer may have a plurality of vias. In some examples, the fifth insulating layer may also be referred to as a first planar layer.

[0206] Figure 13 is a schematic diagram of the display substrate after forming the fifth insulating layer in Figure 5. In some examples, the plurality of via holes in the fifth insulating layer of a single display island region may include at least a sixteenth via hole V16, a seventeenth via hole V17, an eighteenth via hole V18, and a nineteenth via hole V19.

[0207] In some examples, the orthographic projection of the sixteenth via hole V16 on the substrate can be located within the range of the orthographic projection of the data line 51a on the substrate. The fifth insulating layer within the sixteenth via hole V16 can be removed to expose a portion of the surface of the data line 51a. The sixteenth via hole V16 can be configured to allow a subsequently formed second conductive block to be connected to the data line 51a through the via hole.

[0208] In some examples, the orthographic projection of the seventeenth via V17 on the substrate can be located within the orthographic projection of the second power connection portion 76a-2 of a first power connection line on the substrate. The fifth insulating layer within the seventeenth via V17 can be removed, exposing a portion of the surface of the second power connection portion 76a-2 of a first power connection line. The seventeenth via V17 can be configured to allow a subsequently formed second power connection line to be connected to the second power connection portion 76a-2 of a first power connection line through the via.

[0209] In some examples, the orthographic projection of the eighteenth via V18 on the substrate can be located within the orthographic projection of the first power connection portion 76a-1 of another first power connection line on the substrate. The fifth insulating layer within the eighteenth via V18 can be removed, exposing a portion of the surface of the first power connection portion 76a-1 of another first power connection line. The eighteenth via V18 can be configured to allow a subsequently formed second power connection line to be connected to the first power connection portion 76a-1 of another first power connection line through the via.

[0210] In some examples, the orthographic projection of the nineteenth via hole V19 on the substrate can be located within the orthographic projection of the first anode connecting electrode 53a on the substrate. The fifth insulating layer within the nineteenth via hole V19 can be removed, exposing a portion of the surface of the first anode connecting electrode 53a. The nineteenth via hole V19 can be configured to connect a subsequently formed second anode connecting electrode to the first anode connecting electrode 53a through the via hole.

[0211] (1-10) Forming a fourth conductive layer. In some examples, a fourth conductive film is deposited on the substrate having the aforementioned pattern formed thereon. The fourth conductive film is patterned using a patterning process to form a fourth conductive layer disposed on the fifth insulating layer. In some examples, the fourth conductive layer may also be referred to as a second source / drain metal layer.

[0212] FIG14A is a schematic diagram of the display substrate after the fourth conductive layer is formed in FIG5 . FIG14B is a schematic diagram of the fourth conductive layer in FIG14A . In some examples, as shown in FIG14A and FIG14B , the fourth conductive layer of a single display island region in the first display region may include at least three second power connection lines (e.g., including second power connection lines 61 a, 61 b, and 61 c), three second conductive blocks 62, and three second anode connection electrodes (e.g., including second anode connection electrodes 63 a, 63 b, and 63 c).

[0213] In some examples, three second conductive blocks 62 and three second power connection lines may be spaced apart in the first direction X. The second anode connection electrode 63 a may be located between one second conductive block 62 and the second power connection line 61 a in the first direction X. The second anode connection electrodes 63 b and 63 c may be located on one side of the second power connection lines 61 b ​​and 61 c in the second direction Y.

[0214] In some examples, the three second conductive blocks 62 can have substantially the same shape, for example, a substantially rectangular shape, such as a rounded rectangle. The three second conductive blocks 62 can be electrically connected to the three data lines in a one-to-one correspondence. For example, one second conductive block 62 can be electrically connected to the data line 51a through the sixteenth via V16. By being connected in parallel with the corresponding data line, the second conductive block 62 can reduce the resistance of the data line, thereby ensuring the transmission quality of the data signal. In other examples, the second conductive block can be omitted.

[0215] In some examples, the shapes of the three second power connection lines can be roughly the same, for example, they can be roughly in the shape of a broken line with the main part extending along the second direction Y. The extension directions of the three second power connection lines can be roughly parallel. The three second power connection lines can be arranged in sequence in the three first pixel circuits. The second power connection line 61a can be connected to the second power connection part 76a-2 of a first power connection line 76a through the seventeenth via V17, and can also be connected to the first power connection part 76a-1 of another first power connection line 76a through the eighteenth via V18. The first power connection line 61a can realize the longitudinal transmission of the first voltage signal in the first first pixel circuit. The first power connection line 61b can realize the longitudinal transmission of the first voltage signal in the second first pixel circuit. The first power connection line 61c can realize the longitudinal transmission of the first voltage signal in the third first pixel circuit.

[0216] In some examples, the shape of the second anode connection electrode 63a can be substantially a zigzag shape, with the main portion extending along the second direction Y. The second anode connection electrode 63a can be electrically connected to the first anode connection electrode 53a through the nineteenth via V19. In this example, the first anode connection electrode 53a and the second anode connection electrode 63a can be used to electrically connect the first first pixel circuit and the first first light-emitting element. In this example, the position of the first light-emitting element can be changed by adjusting the shape and position of the second anode connection electrode 63a.

[0217] In some examples, the second anode connection electrodes 63b and 63c can have substantially the same shape, for example, both can be substantially rectangular. The second anode connection electrode 63b can be electrically connected to the first anode connection electrode 53b to subsequently electrically connect the second first pixel circuit to the second first light-emitting element. The second anode connection electrode 63c can be electrically connected to the first anode connection electrode 53c to subsequently electrically connect the third first pixel circuit to the third first light-emitting element.

[0218] (1-11) Forming a sixth insulating layer. In some examples, a sixth insulating film is coated on the substrate having the aforementioned pattern formed thereon, and the sixth insulating film is patterned using a patterning process to form the sixth insulating layer. The sixth insulating layer may have a plurality of vias. In some examples, the sixth insulating layer may also be referred to as a second planar layer.

[0219] Figure 15 is a schematic diagram of the display substrate after the sixth insulating layer is formed in Figure 5. In some examples, the plurality of via holes in the sixth insulating layer of a single display island region may include at least a twenty-first via hole V21, a twenty-second via hole V22, and a twenty-third via hole V23.

[0220] In some examples, the orthographic projection of the twenty-first via hole V21 on the substrate can be located within the range of the orthographic projection of the second anode connecting electrode 63a on the substrate. The sixth insulating layer within the twenty-first via hole V21 can be removed, exposing a portion of the surface of the second anode connecting electrode 63a. The twenty-first via hole V21 can be configured to connect the anode of a first first light-emitting element formed subsequently to the second anode connecting electrode 63a through the via hole.

[0221] In some examples, the orthographic projection of the twenty-second via hole V22 on the substrate can be located within the orthographic projection of the second anode connecting electrode 63b on the substrate. The sixth insulating layer within the twenty-second via hole V22 can be removed, exposing a portion of the surface of the second anode connecting electrode 63b. The twenty-second via hole V22 can be configured to connect the anode of a subsequently formed second first light-emitting element to the second anode connecting electrode 63b through the via hole.

[0222] In some examples, the orthographic projection of the twenty-third via hole V23 on the substrate can be located within the orthographic projection of the second anode connecting electrode 63c on the substrate. The sixth insulating layer within the twenty-third via hole V23 can be removed, exposing a portion of the surface of the second anode connecting electrode 63c. The twenty-third via hole V23 can be configured to connect the anode of a subsequently formed first first light-emitting element to the second anode connecting electrode 63c through the via hole.

[0223] In some examples, after forming the sixth insulating layer, the first routing area may include: a substrate, a first insulating layer sequentially arranged on the substrate, a first conductive layer (for example, including a first scanning connection line 71, a second scanning connection line 72 and a light-emitting control connection line 73), a second insulating layer, a second conductive layer (for example, including a first initial connection line 74), a third insulating layer, a fourth insulating layer, a fifth insulating layer and a sixth insulating layer.

[0224] In some examples, after forming the sixth insulating layer, the first light-transmitting area may include: a substrate, a first insulating layer, a second insulating layer, a third insulating layer, a fourth insulating layer, a transparent conductive layer (for example, including a first power connection line and a data connection line), a fifth insulating layer, and a sixth insulating layer, which are sequentially arranged on the substrate.

[0225] In some examples, after forming the sixth insulating layer, the second light-transmitting region may include: a substrate, a first insulating layer, a second insulating layer, a third insulating layer, a fourth insulating layer, a fifth insulating layer, and a sixth insulating layer sequentially disposed on the substrate.

[0226] In this example, the first signal lines connecting first pixel circuits in adjacent display islands may include: a first scan connection line, a second scan connection line, and a light-emission control connection line located on the first conductive layer, and a first initial connection line located on the second conductive layer. The second signal lines connecting first pixel circuits in adjacent display islands may include: a first power connection line and a data connection line located on the transparent conductive layer.

[0227] (1-12) Forming an anode layer. In some examples, an anode thin film is deposited on the substrate having the aforementioned pattern formed thereon, and the anode thin film is patterned by a patterning process to form an anode layer.

[0228] FIG16A is a schematic diagram of the display substrate after the anode layer is formed in FIG5 . FIG16B is a schematic diagram of the anode layer in FIG16A . In some examples, as shown in FIG16A and FIG16B , the anode layer of a single display island region may include at least three anodes (e.g., including anodes 131 a, 131 b, and 131 c).

[0229] In some examples, the shapes of anodes 131a, 131b, and 131c can be substantially the same, for example, circular or elliptical. The area of ​​anode 131a can be smaller than that of anode 131b, and smaller than that of anode 131c. The areas of anodes 131b and 131c can be substantially the same.

[0230] In some examples, an anode connection block 131a-1 may be provided on a side of the anode 131a near the anode 131c. The anode connection block 131a-1 may be provided in the first first pixel circuit. A first end of the anode connection block 131a-1 is connected to the anode 131a, and a second end extends in a direction away from the anode 131a along the first direction X. The anode connection block 131a-1 may be electrically connected to the second anode connection electrode 63a through a twenty-first via hole V21. The anode connection block 131a-1 and the anode 131a may be an integral structure connected to each other.

[0231] In some examples, an anode connection block 131b-1 may be provided on a side of the anode 131b near the anode 131c. At least a portion of the anode connection block 131b-1 may be provided in the second first pixel circuit. A first end of the anode connection block 131b-1 is connected to the anode 131b, and a second end extends away from the anode 131b along the first direction X. The anode connection block 131b-1 may be electrically connected to the second anode connection electrode 63b through the twenty-second via hole V22. The anode connection block 131b-1 and the anode 131b may be an integral structure connected to each other.

[0232] In some examples, an anode connection block 131c-1 may be provided on a side of the anode 131c near the anode 131b. The anode connection block 131c-1 may be provided in the third first pixel circuit. A first end of the anode connection block 131c-1 is connected to the anode 131c, and a second end extends away from the anode 131c along the second direction Y. The anode connection block 131c-1 may be electrically connected to the second anode connection electrode 63c through the twenty-third via hole V23. The anode connection block 131c-1 and the anode 131c may be an integral structure connected to each other.

[0233] (1-13) Forming a pixel definition layer. In some examples, a pixel definition film is coated on the substrate having the aforementioned pattern, and a pixel definition layer (PDL) is formed through masking, exposure, and development processes.

[0234] In some examples, as shown in FIG5 , the pixel definition layer of a single display island region may form three pixel openings (e.g., including a first pixel opening OP1, a second pixel opening OP2, and a third pixel opening OP3). The first pixel opening OP1 may expose a portion of the surface of the anode 131 a, the second pixel opening OP2 may expose a portion of the surface of the anode 131 b, and the third pixel opening OP3 may expose a portion of the surface of the anode 131 c.

[0235] In some examples, the pixel definition layer of the first display area can be made of black material. The black pixel definition layer can absorb stray light to reduce the effect of diffraction and optimize the shooting effect. For example, the pixel definition layer of the first light-transmitting area and the second light-transmitting area can be removed to ensure light transmittance. The pixel definition layer of the first wiring area can be retained to shield the wiring in the first wiring area to avoid diffraction caused by light transmission. However, this embodiment is not limited to this. In other examples, the display substrate can shield the first wiring area by setting a black matrix (BM). In other examples, the display substrate can be provided with a bottom shielding metal (BSM) to shield the display island area and the first wiring area, and the bottom shielding metal can be located on the side of the semiconductor layer close to the substrate.

[0236] (1-14) Forming an organic light-emitting layer, a cathode layer, and an encapsulation layer. In some examples, organic light-emitting layers can be formed within the plurality of pixel openings formed above, and the organic light-emitting layers are connected to corresponding anodes. Subsequently, a cathode film is deposited and patterned through a patterning process to form a cathode layer. The cathode layer can be electrically connected to the organic light-emitting layer and the second power line, respectively. Subsequently, an encapsulation layer is formed on the cathode layer. The encapsulation layer can include a laminated structure of inorganic material / organic material / inorganic material.

[0237] In some examples, the first conductive layer, the second conductive layer, the third conductive layer, and the fourth conductive layer can be made of metal materials, such as any one or more of silver (Ag), copper (Cu), aluminum (Al), and molybdenum (Mo), or alloy materials of the above metals, such as aluminum neodymium alloy (AlNd) or molybdenum niobium alloy (MoNb), and can be a single layer structure or a multilayer composite structure, such as Mo / Cu / Mo. The transparent conductive layer can be made of a transparent conductive material, such as indium tin oxide (ITO). The first to fourth insulating layers can be made of any one or more of silicon oxide (SiOx, x>0), silicon nitride (SiNy, y>0), and silicon oxynitride (SiON), and can be a single layer, a multilayer, or a composite layer. The fifth insulating layer and the sixth insulating layer can be made of organic materials such as polyimide, acrylic, or polyethylene terephthalate. The pixel definition layer can be made of organic materials such as polyimide, acrylic, or polyethylene terephthalate. The anode layer may be made of a reflective material such as metal, and the cathode layer may be made of a transparent conductive material. However, this embodiment is not limited thereto.

[0238] In some examples, as shown in FIG1 , the second display area A2 may include multiple second pixel circuits 12 and multiple second light-emitting elements 14. At least one second pixel circuit 12 may be electrically connected to at least one second light-emitting element 14, and the at least one second pixel circuit 12 may be configured to drive the electrically connected at least one second light-emitting element 14 to emit light. For example, the multiple second pixel circuits 12 and the multiple second light-emitting elements 14 may be electrically connected in a one-to-one correspondence. The multiple second light-emitting elements 14 in the second display area A2 may include: a second light-emitting element emitting a first color light, a second light-emitting element emitting a second color light, and a second light-emitting element emitting a third color light. The arrangement of the multiple second light-emitting elements may be similar to the arrangement of the multiple first light-emitting elements, and therefore will not be described in detail here. In some examples, the orthographic projection of the light-emitting area of ​​the second light-emitting element on the substrate may overlap with the orthographic projection of the electrically connected second pixel circuit on the substrate. In some examples, adjacent second pixel circuits in the second display area may not need to be electrically connected via traces of a transparent conductive layer, and the second display area may not need to be provided with a transparent conductive layer. The rest of the film structure of the second display area may be similar to that of the first display area, and thus will not be described in detail here.

[0239] The structure of the display substrate and its fabrication process in this embodiment are merely illustrative. In some examples, the corresponding structure can be modified and patterning processes can be added or removed as needed. The fabrication process of this exemplary embodiment can be implemented using currently available manufacturing equipment and is well compatible with existing fabrication processes. The process is simple to implement, easy to implement, and offers high production efficiency, low production costs, and a high yield rate.

[0240] In some implementations, a single display island area of ​​the first display area can be provided with a first light-emitting element and a first pixel circuit, and the first pixel circuit can be located below the first light-emitting element to make the light-transmitting area as large as possible. However, when a single first pixel circuit is provided in the display island area, the spacing between the display island areas is small, and the winding space of the first signal line and the second signal line electrically connecting adjacent first pixel circuits will be limited, resulting in the first signal line and the second signal line being longer and having a smaller line width and line spacing. When the first signal line and the second signal line are made of transparent conductive material, taking ITO as an example, due to the large square resistance of ITO, the longer first signal line and the second signal line have a larger load, which will affect the display effect and cause poor display. Compared with the solution of setting a first light-emitting element and a first pixel circuit in a single display island area and covering the first pixel circuit with the first light-emitting element, the display substrate provided in this embodiment can increase the space between adjacent display island areas, increase the arrangement freedom of the second signal line located in the transparent conductive layer, increase the wiring space of the second signal line, and thus increase the line width of the second signal line to reduce the resistance of the second signal line, avoid poor display of the display substrate due to the load of the second signal line, and support a higher refresh rate.

[0241] The first signal traces of the display substrate of this embodiment are made of a metal material, which can reduce the cost of using a mask for a transparent conductive layer and reduce lateral display defects caused by the resistance of the first signal traces. Furthermore, by making the first signal traces of a metal material, the spacing between adjacent display islands in the first direction can be reduced. While maintaining the total size of the first pixel circuit, the size of the display islands in the second direction can be reduced by increasing the size of the display islands in the first direction. This, in turn, increases the spacing between adjacent display islands in the second direction, thereby increasing the light transmittance of the second light-transmitting area. Furthermore, by making the first signal traces of a metal material, the drilling process between adjacent display islands in the first direction can be avoided, reducing the space occupied by the first signal traces and reducing costs.

[0242] Furthermore, in a solution where a single display island region is provided with a first light-emitting element and a first pixel circuit, with the first light-emitting element covering the first pixel circuit, there are numerous raised display islands and recessed slits, which can easily exacerbate light diffraction effects in the first display region and degrade image quality. The display substrate provided in this embodiment, by centrally arranging multiple first pixel circuits in the display island region, can reduce the number of islands and slits, increase the size of the light-transmitting area between adjacent display island regions, effectively reduce light diffraction effects, and facilitate smoothing of the edges of the display island regions.

[0243] Figure 17A is another schematic diagram of the first display area of ​​at least one embodiment of the present disclosure. In some examples, as shown in Figure 17A , the first display area A1 may include a plurality of display islands A11 arranged in an array within a plane parallel to the display substrate. The plurality of display islands A11 may be arranged in an array along a first direction X and a second direction Y. The plurality of display islands A11 may have substantially the same shape. For example, the display islands may have irregular shapes with smooth edges. The smooth edges of the display islands A11 may reduce light diffraction effects, thereby improving image quality.

[0244] In some examples, as shown in FIG17A , a first light-transmitting area A121 may be provided between adjacent display island areas A11. The first light-transmitting area A121 may be located between adjacent display island areas A11 along the second direction Y. Multiple first light-transmitting areas A121 may be formed independently. Adjacent first light-transmitting areas A121 may not be connected. Multiple first light-transmitting areas A121 may be arranged in an array along the first direction X and the second direction Y. For example, the first light-transmitting areas A121 may be elliptical, or may be other shapes such as a rounded polygon.

[0245] In some examples, as shown in FIG17A , a routing area may be further provided between adjacent display island areas A11. For example, the routing area may include: a first routing area A131 and a second routing area A132. The first routing area A131 may be located between adjacent display island areas A11 along the first direction X. The second routing area A132 may be located between adjacent first light-transmitting areas A121 along the first direction X. The first routing area A131 and the second routing area A132 may be connected in the second direction Y. A plurality of second routing areas A132 and a plurality of first light-transmitting areas A121 may be arranged at intervals along the first direction X. Adjacent display island areas A11 along the first direction X may be connected through the first routing area A131, and adjacent display island areas A11 along the second direction Y may be connected through the second routing area A132.

[0246] Figure 17B is another schematic diagram of the first display area of ​​at least one embodiment of the present disclosure. In some examples, as shown in Figure 17B, within a plane parallel to the display substrate, the first display area A1 may include: a plurality of display island areas A11 arranged in an array, a first light-transmitting area A121 and a second light-transmitting area A122 located between adjacent display island areas A11, and a first routing area A131 and a second routing area A132 located between adjacent display island areas A11. The first light-transmitting area A121 may be located between adjacent display island areas A11 along the second direction Y, and the second light-transmitting area A122 may be located between adjacent display island areas A11 along the first direction X. The second light-transmitting area A122 may be surrounded by the first routing area A131, or may be surrounded by the first routing area A131 and the display island areas A11. The first light-transmitting area A121 may be surrounded by the second routing area A132 and the display island areas A11. The shapes of the first light-transmitting area A121 and the second light-transmitting area A122 can be substantially the same, for example, both can be elliptical. The area of ​​a single first light-transmitting area A121 can be larger than the area of ​​a single second light-transmitting area A122. However, this embodiment is not limited to this. For example, the shapes of the first light-transmitting area and the second light-transmitting area can be different, for example, different shapes with smooth edges. For the description of the second light-transmitting area, please refer to the description of the previous embodiment.

[0247] Figure 17C is another schematic diagram of the first display area of ​​at least one embodiment of the present disclosure. In some examples, as shown in Figure 17C, in a plane parallel to the display substrate, the first display area A1 may include: a plurality of display island areas A11 arranged in an array, a first light-transmitting area A121 and a second light-transmitting area A122 located between adjacent display island areas A11, and a first wiring area A131 and a second wiring area A132 located between adjacent display island areas A11. The shapes of the first light-transmitting area A121 and the second light-transmitting area A122 can be substantially the same, for example, both can be circular. However, this embodiment is not limited to this. In other examples, the shapes of the first light-transmitting area and the second light-transmitting area can be other shapes with smooth edges, such as rounded rectangles, rounded polygons, etc. The remaining description of the display substrate of this example can refer to the description of the aforementioned embodiment.

[0248] Fig. 18 is a partial top view of the area S2 in Fig. 17A , which shows four display islands A11 arranged in a 2×2 array.

[0249] In some examples, in a direction perpendicular to the display substrate, the circuit structure layer of the first display area may include: a semiconductor layer, a first conductive layer, a second conductive layer, a third conductive layer, and a fourth conductive layer sequentially disposed on the substrate. A first insulating layer may be disposed between the semiconductor layer and the first conductive layer, a second insulating layer may be disposed between the first and second conductive layers, a third insulating layer may be disposed between the second and third conductive layers, a fourth insulating layer and a fifth insulating layer may be disposed between the third and fourth conductive layers, and a sixth insulating layer may be disposed on the side of the fourth conductive layer away from the substrate.

[0250] The structure and preparation process of the display substrate of this example are exemplarily described below. In some examples, the preparation process of the display substrate of this example may include the following operations.

[0251] (2-1) Provide a substrate.

[0252] (2-2) Forming a semiconductor layer. In some examples, a semiconductor thin film is deposited on a substrate, and the semiconductor thin film is patterned by a patterning process to form a semiconductor layer disposed on the substrate. In some examples, the semiconductor layer of a single display island region may include at least: a first active layer of a first transistor of three first pixel circuits, a second active layer of a second transistor, a third active layer of a third transistor, a fourth active layer of a fourth transistor, a fifth active layer of a fifth transistor, a sixth active layer of a sixth transistor, and a seventh active layer of a seventh transistor. The description of the semiconductor layer of the display substrate of this example can refer to the description of the aforementioned embodiment, and therefore will not be repeated here.

[0253] (2-3) Forming a first conductive layer. In some examples, a first insulating film and a first conductive film are sequentially deposited on the substrate having the aforementioned pattern formed thereon. The first conductive film is patterned using a patterning process to form a first insulating layer disposed on the semiconductor layer and a first conductive layer disposed on the first insulating layer.

[0254] FIG19 is a schematic diagram of the display substrate after the first conductive layer is formed in FIG18 . In some examples, as shown in FIG19 , the first conductive layer of a single display island region may include at least: a first scan line 31, a second scan line 32, a light-emitting control line 33, and the first plates 281 of the storage capacitors of the three first pixel circuits. The first conductive layer of the first routing region between adjacent display island regions in the first direction X may include at least: a first scan connection line 71, a second scan connection line 72, and a light-emitting control connection line 73. The shapes of the first scan connection line 71, the second scan connection line 72, and the light-emitting control connection line 73 may all be straight lines with the main body extending along the first direction X. The remaining description of the first conductive layer of the display substrate of this example can refer to the description of the aforementioned embodiment, so it will not be repeated here.

[0255] (2-4) Forming a second conductive layer. In some examples, a second insulating film and a second conductive film are sequentially deposited on the substrate having the aforementioned pattern formed thereon. The second conductive film is patterned using a patterning process to form a second insulating layer disposed on the first conductive layer and a second conductive layer disposed on the second insulating layer.

[0256] Figure 20 is a schematic diagram of the display substrate after the second conductive layer is formed in Figure 18. In some examples, as shown in Figure 20, the second conductive layer of a single display island region may include at least a first initial signal line 34 and second plates 282 of storage capacitors for three first pixel circuits. The second conductive layer of the first routing region between adjacent display island regions in the first direction X may include at least a first initial connection line 74. The description of the second conductive layer of the display substrate in this example can be found in the description of the previous embodiment, and therefore will not be repeated here.

[0257] (2-5) Forming a third insulating layer and a third conductive layer. In some examples, a third insulating film is deposited on the substrate having the aforementioned pattern formed thereon, and the third insulating film is patterned using a patterning process to form a third insulating layer. The third insulating layer may be provided with a plurality of vias. The description of the third insulating layer in this example can be referred to the description of the previous embodiment and is therefore not repeated here.

[0258] In some examples, a third conductive film is deposited on the substrate on which the aforementioned pattern is formed, and the third conductive film is patterned through a patterning process to form a third conductive layer disposed on the third insulating layer.

[0259] Figure 21A is a schematic diagram of the display substrate after the third conductive layer is formed in Figure 18. Figure 21B is a schematic diagram of the third conductive layer in Figure 21A. In some examples, as shown in Figures 21A and 21B, the third conductive layer of a single display island in the first display area may include at least a first connecting electrode 41, a second connecting electrode 42, a third connecting electrode 43, a fourth connecting electrode 44, a fifth connecting electrode 45, and a sixth connecting electrode 46. The description of the third conductive layer in this example can be found in the description of the previous embodiment, and therefore will not be repeated here.

[0260] (2-6) Forming a fourth insulating layer and a fifth insulating layer. In some examples, a fourth insulating film is deposited on the substrate forming the aforementioned structure, followed by coating with a fifth insulating film. The fifth insulating film and the fourth insulating film are patterned using a patterning process to form the fourth insulating layer and the fifth insulating layer. The fifth insulating layer and the fourth insulating layer may have a plurality of vias.

[0261] Figure 22 is a schematic diagram of the display substrate after the fifth insulating layer is formed in Figure 17. In some examples, the plurality of via holes in the fifth insulating layer of a single display island region may include at least a thirty-first via hole V31, a thirty-second via hole V32, a thirty-third via hole V33, and a thirty-fourth via hole V34.

[0262] In some examples, the orthographic projection of the thirty-first via hole V31 on the substrate can be located within the range of the orthographic projection of the third connection electrode 43 on the substrate. The fifth insulating layer and the fourth insulating layer within the thirty-first via hole V31 can be removed to expose a portion of the surface of the third connection electrode 43. The thirty-first via hole V31 can be configured to connect a subsequently formed data line to the third connection electrode 43 through the via hole.

[0263] In some examples, the orthographic projection of the thirty-second via hole V32 on the substrate can be located within the range of the orthographic projection of the fourth connection electrode 44 on the substrate. The fifth insulating layer and the fourth insulating layer within the thirty-second via hole V32 can be removed to expose a portion of the surface of the fourth connection electrode 44. The thirty-second via hole V32 can be configured to connect a subsequently formed second power connection line to the fourth connection electrode 44 through the via hole.

[0264] In some examples, the orthographic projection of the thirty-third via hole V33 on the substrate can be located within the range of the orthographic projection of the fifth connection electrode 45 on the substrate. The fifth insulating layer and the fourth insulating layer within the thirty-third via hole V33 can be removed, exposing a portion of the surface of the fifth connection electrode 45. The thirty-third via hole V33 can be configured to connect a subsequently formed second anode connection electrode to the fifth connection electrode 45 through the via hole.

[0265] In some examples, the orthographic projection of the thirty-fourth via hole V34 on the substrate can be located within the range of the orthographic projection of the sixth connection electrode 46 on the substrate. The fifth insulating layer and the fourth insulating layer within the thirty-fourth via hole V34 can be removed, exposing a portion of the surface of the sixth connection electrode 46. The thirty-fourth via hole V34 can be configured to connect a subsequently formed second power connection line to the sixth connection electrode 46 through the via hole.

[0266] (2-7) Forming a fourth conductive layer. In some examples, a fourth conductive film is deposited on the substrate having the aforementioned pattern, and the fourth conductive film is patterned by a patterning process to form a fourth conductive layer disposed on the fifth insulating layer.

[0267] FIG23A is a schematic diagram of the display substrate after the fourth conductive layer is formed in FIG18 . FIG23B is a schematic diagram of the fourth conductive layer in FIG23A . In some examples, as shown in FIG23A and FIG23B , the fourth conductive layer in a single display island region of the first display area may include at least three data lines (e.g., data lines 51a, 51b, and 51c), three second power connection lines (e.g., second power connection lines 61a, 61b, and 61c), and three second anode connection electrodes (e.g., second anode connection electrodes 63a, 63b, and 63c).

[0268] In some examples, the data lines 51a, 51b, and 51c can be arranged sequentially along the first direction X. The data line 51a can be shaped substantially like a zigzag line with a main portion extending along the second direction Y. The data line 51a can be electrically connected to the third connection electrode 43 of the first first pixel circuit through the thirty-first via hole V31 to be configured to provide a data signal to the first electrode of the fourth transistor T4 of the first first pixel circuit.

[0269] In some examples, the shape of the data line 51b can be roughly a zigzag shape with the main portion extending along the second direction Y. The data line 51b can be configured to provide a data signal to the first electrode of the fourth transistor of the second first pixel circuit. The data line 51b can be provided with a first data connection portion 51b-1 on a side of the display island area near the previous row, and the first data connection portion 51b-1 can extend at least along the first direction X. The first data connection portion 51b-1 can extend in the first direction X toward the direction close to the data line 51a. The first data connection portion 51b-1 and the data line 51b can be an integrated structure connected to each other.

[0270] In some examples, the data line 51b may be provided with a second data connection portion 51b-2 on a side adjacent to the display island area of ​​the next row. The second data connection portion 51b-2 may extend along a third direction F1. The third direction F1 may intersect both the first direction X and the second direction Y. For example, the clockwise angle between the third direction F1 and the first direction X may be approximately 40 to 60 degrees, such as approximately 45 degrees. The second data connection portion 51b-2 and the data line 51b may be an integral, interconnected structure.

[0271] In some examples, the data line 51c can be shaped roughly like a zigzag line with a main portion extending along the second direction Y. The data line 51c can be configured to provide a data signal to the first electrode of the fourth transistor of the third first pixel circuit. The data line 51c can be provided with a third data connection portion 51c-1 on a side adjacent to the display island area of ​​the previous row. The third data connection portion 51c-1 can extend away from the data line 51c along the third direction F1. The third data connection portion 51c-1 and the data line 51c can be an integrally connected structure.

[0272] In some examples, a fourth data connection portion 51c-2 may be provided on a side of the data line 51c near the display island area of ​​the next row. The fourth data connection portion 51c-2 may extend at least along the first direction X. The fourth data connection portion 51c-2 may extend in a direction away from the data line 51b in the first direction X. The fourth data connection portion 51c-2 and the data line 51c may be an integral structure connected to each other.

[0273] In some examples, the second power connection lines 61a, 61b, and 61c can be arranged sequentially along the first direction X. The second power connection line 61a can be located between the data lines 51a and 51b, the second power connection line 61b can be located between the data lines 51b and 51c, and the second power connection line 61c can be located on a side of the data line 51c away from the data line 51b. In the display island area, the second power connection lines and the data lines can be arranged alternately.

[0274] In some examples, the second power connection line 61a can be shaped approximately like a zigzag with a main portion extending along the second direction Y. The extension direction of the second power connection line 61a can be approximately the same as the extension direction of the data line 51a. The second power connection line 61a can be electrically connected to the fourth connection electrode 44 in the first first pixel circuit through the thirty-second via V32, and can also be electrically connected to the sixth connection electrode 46 in the first first pixel circuit through the thirty-fourth via V34. The second power connection line 61a can be configured to provide a first voltage signal to the first first pixel circuit.

[0275] In some examples, the second power connection line 61b can be shaped substantially like a zigzag line with a main portion extending along the second direction Y. The extension direction of the second power connection line 61b can be substantially the same as the extension direction of the data line 51b. The second power connection line 61b can be configured to provide a first voltage signal to the second first pixel circuit.

[0276] In some examples, the second power connection line 61b may be provided with a first power extension portion 61b-1 on a side close to the display island area of ​​the previous row. The first power extension portion 61b-1 may extend at least along the first direction X. The first power extension portion 61b-1 may extend toward a side close to the data line 51c in the first direction X. The first data connection portion 51b-1 and the first power extension portion 61b-1 of the data line 51b may extend in opposite directions in the first direction X. The first power extension portion 61b-1 and the second power connection line 61b may be an integral structure connected to each other.

[0277] In some examples, the second power supply connection line 61b may be provided with a second power supply extension portion 61b-2 on a side adjacent to the next row of display islands. The second power supply extension portion 61b-2 may extend along a fourth direction F2. The fourth direction F2 may intersect both the first direction X and the second direction Y. For example, the clockwise angle between the fourth direction F2 and the first direction X may be approximately 120 to 150 degrees, such as approximately 135 degrees. The fourth direction F2 may intersect the third direction F1; for example, the fourth direction F2 may be perpendicular to the third direction F1. The second power supply extension portion 61b-2 may extend in the fourth direction F2 along a side adjacent to the data line 51c. The second power supply extension portion 61b-2 and the second power supply connection line 61b may be an integral, interconnected structure.

[0278] In some examples, the second power connection line 61c can be shaped substantially like a zigzag line with a main portion extending along the second direction Y. The extension direction of the second power connection line 61c can be substantially the same as the extension direction of the data line 51c. The second power connection line 61c can be configured to provide a first voltage signal to the third first pixel circuit.

[0279] In some examples, the second power connection line 61c may be provided with a third power extension portion 61c-1 on a side away from the data line 51c. The third power extension portion 61c-1 may extend along the first direction X toward the side away from the data line 51c. The third power extension portion 61c-1 and the second power connection line 61c may be an integrated structure connected to each other.

[0280] In some examples, the shape of the second anode connection electrode 63a can be substantially a zigzag shape, with the main portion extending along the second direction Y. The second anode connection electrode 63a can be electrically connected to the fifth connection electrode 45 via a thirty-third via hole V33. In this example, the second anode connection electrode 63a can be used to electrically connect the first first pixel circuit and the first first light-emitting element. In this example, the position of the first light-emitting element can be changed by adjusting the shape and position of the second anode connection electrode 63a.

[0281] In some examples, the second anode connection electrodes 63b and 63c can have substantially the same shape, for example, both can be substantially rectangular. The second anode connection electrode 63b can be electrically connected to the sixth transistor of the second first pixel circuit, so as to subsequently electrically connect the second first pixel circuit to the second first light-emitting element. The second anode connection electrode 63c can be electrically connected to the sixth transistor of the third first pixel circuit, so as to subsequently electrically connect the third first pixel circuit to the third first light-emitting element.

[0282] In some examples, the fourth conductive layer of the second routing area between adjacent display island areas along the second direction Y may include at least: a plurality of first power connection lines (for example, including first power connection lines 76a, 76b, and 76c), and a plurality of data connection lines (for example, including data connection lines 75a, 75b, and 75c). The plurality of data connection lines and the plurality of first power connection lines may be arranged at intervals. The data connection lines 75a, 75b, and 75c and the first power connection lines 76a, 76b, and 76c may be substantially straight lines extending along the second direction Y.

[0283] In some examples, three first power connection lines and three data connection lines can be arranged in a second routing area. For example, the second routing area between the mth column display island area and the m+1th column display island area may include: a first power connection line 76b connected to the second column first pixel circuit in the mth column display island area, a data connection line 75c and a first power connection line 76c connected to the third column first pixel circuit in the mth column display island area, a data connection line 75a and a first power connection line 76a connected to the first column first pixel circuit in the m+1th column display island area, and a data connection line 75b connected to the second column first pixel circuit in the m+1th column display island area. The first power connection line 76b, data connection line 75c, first power connection line 76c, data connection line 75a, first power connection line 76a, and data connection line 75b in the second routing area can be arranged sequentially along the first direction X.

[0284] In some examples, the data lines 51a in adjacent display islands in the second direction Y can be connected by a data connection line 75a. The first end of the data connection line 75a can be connected to the data line 51a in the display island in the kth row and mth column, and the second end can be connected to the data line 51a in the display island in the k+1th row and mth column. The data line 51a and the data connection line 75a can be an integrated structure connected to each other.

[0285] In some examples, the data lines 51b in adjacent display islands in the second direction Y can be connected via a data connection line 75b. The first end of the data connection line 75b can be connected to the second data connection portion 51b-2 of the data line 51b in the display island in the kth row and mth column, and the second end can be connected to the first data connection portion 51b-1 of the data line 51b in the display island in the k+1th row and mth column. The data line 51b and the data connection line 75b can be an integral structure connected to each other.

[0286] In some examples, the data lines 51c in adjacent display islands in the second direction Y can be connected via a data connection line 75c. The first end of the data connection line 75c can be connected to the fourth data connection portion 51c-2 of the data line 51c in the display island in the k-th row and m-th column, and the second end can be connected to the third data connection portion 51c-1 of the data line 51c in the display island in the k+1-th row and m-th column. The data line 51c and the data connection line 75c can be an integral structure connected to each other.

[0287] In some examples, the second power connection lines 61a in adjacent display islands in the second direction Y can be connected via the first power connection line 76a. The first end of the first power connection line 76a can be connected to the second power connection line 61a in the display island in the kth row and mth column, and the second end can be connected to the second power connection line 61a in the display island in the k+1th row and mth column. The second power connection line 61a and the first power connection line 76a can be an integrated structure connected to each other.

[0288] In some examples, the second power connection lines 61b in adjacent display islands in the second direction Y can be connected via a first power connection line 76b. The first end of the first power connection line 76b can be connected to the second power extension portion 61b-2 of the second power connection line 61b in the display island in the kth row and mth column, and the second end can be connected to the first power extension portion 61b-1 of the second power connection line 61b in the display island in the k+1th row and mth column. The second power connection line 61b and the first power connection line 76b can be an integral structure connected to each other.

[0289] In some examples, the second power connection lines 61c in adjacent display islands in the second direction Y can be connected via the first power connection line 76c. The first power connection line 76c can extend from the second routing area to the first routing area between adjacent display islands in the first direction X. The first power connection line 76c can be shaped like a broken line with a main portion extending along the second direction Y. The portion of the first power connection line 76c in the second routing area can be shaped like a straight line extending along the second direction Y. The first power connection line 76c can be connected to the third power extension portion 61c-1 of the second power connection line 61c in the first routing area. The first power connection line 76c and the second power connection line 61c can be an integrated structure connected to each other.

[0290] The data line of this example can be connected to the data connection line through a data connection part with a different extension direction, and the second power connection line can be connected to the first power connection line through a power extension part with a different extension direction, which can help to smooth the edge of the display island area and improve the diffraction of the display substrate.

[0291] (2-8) Forming a sixth insulating layer. In some examples, a sixth insulating film is coated on the substrate on which the aforementioned pattern is formed, and the sixth insulating film is patterned by a patterning process to form the sixth insulating layer.

[0292] Figure 24 is a schematic diagram of the display substrate after the sixth insulating layer is formed in Figure 18. In some examples, the plurality of via holes in the sixth insulating layer of a single display island region may include at least a thirty-fifth via hole V35, a thirty-sixth via hole V36, and a thirty-seventh via hole V37.

[0293] In some examples, the orthographic projection of the thirty-fifth via hole V35 on the substrate can be located within the range of the orthographic projection of the second anode connecting electrode 63a on the substrate. The sixth insulating layer within the thirty-fifth via hole V35 can be removed, exposing a portion of the surface of the second anode connecting electrode 63a. The thirty-fifth via hole V35 can be configured to connect the anode of the first first light-emitting element formed subsequently to the second anode connecting electrode 63a through the via hole.

[0294] In some examples, the orthographic projection of the thirty-sixth via hole V36 on the substrate can be located within the orthographic projection of the second anode connecting electrode 63b on the substrate. The sixth insulating layer within the thirty-sixth via hole V36 can be removed, exposing a portion of the surface of the second anode connecting electrode 63b. The thirty-sixth via hole V36 can be configured to connect the anode of the first first light-emitting element formed subsequently to the second anode connecting electrode 63b through the via hole.

[0295] In some examples, the orthographic projection of the thirty-seventh via hole V37 on the substrate can be located within the orthographic projection of the second anode connecting electrode 63c on the substrate. The sixth insulating layer within the thirty-seventh via hole V37 can be removed, exposing a portion of the surface of the second anode connecting electrode 63c. The thirty-seventh via hole V37 can be configured to connect the anode of a subsequently formed first first light-emitting element to the second anode connecting electrode 63c through the via hole.

[0296] In some examples, after forming the sixth insulating layer, the first light-transmitting region may include: a substrate, a first insulating layer, a second insulating layer, a third insulating layer, a fourth insulating layer, a fifth insulating layer, and a sixth insulating layer sequentially disposed on the substrate. The first routing region may include: a substrate, a first insulating layer sequentially disposed on the substrate, a first conductive layer (e.g., including a first scan connection line 71, a second scan connection line 72, and a light-emitting control connection line 73), a second insulating layer, a second conductive layer (e.g., including a first initial connection line 74), a third insulating layer, a fourth insulating layer, a fifth insulating layer, a fourth conductive layer (e.g., including a first power connection line 76c), and a sixth insulating layer. The second routing region may include: a substrate, a first insulating layer, a second insulating layer, a third insulating layer, a fourth insulating layer, a fifth insulating layer, a fourth conductive layer (e.g., including data connection lines 75a, 75b, and 75c, and first power connection lines 76a, 76b, and 76c), and a sixth insulating layer sequentially disposed on the substrate.

[0297] In this example, the first signal lines connecting first pixel circuits in adjacent display islands may include: a first scan connection line, a second scan connection line, and a light-emission control connection line located on the first conductive layer, and a first initial connection line located on the second conductive layer. The second signal lines connecting first pixel circuits in adjacent display islands may include: a first power connection line and a data connection line located on the fourth conductive layer.

[0298] In other examples, a second light-transmitting area can be formed between display island areas adjacent to each other along the first direction X. For example, the edge of the second light-transmitting area can be defined by the first scanning connection line, the light-emitting control connection line, the first power connection line 76c and the data line 51a. These lines are bent to achieve a smooth edge of the second light-transmitting area to improve diffraction.

[0299] (2-9) Forming an anode layer. In some examples, an anode thin film is deposited on the substrate having the aforementioned pattern formed thereon, and the anode thin film is patterned by a patterning process to form an anode layer.

[0300] Figure 25 is a schematic diagram of the display substrate after the anode layer is formed in Figure 18. In some examples, as shown in Figure 25, the anode layer of a single display island region may include at least three anodes (eg, including anodes 131a, 131b, and 131c).

[0301] In some examples, an anode connection block 131a-1 may be provided on a side of the anode 131a near the anode 131c. The anode connection block 131a-1 may be provided in the first first pixel circuit. A first end of the anode connection block 131a-1 is connected to the anode 131a, and a second end extends in a direction away from the anode 131a along the first direction X. The anode connection block 131a-1 may be electrically connected to the second anode connection electrode 63a through the thirty-fifth via hole V35. The anode connection block 131a-1 and the anode 131a may be an integral structure connected to each other.

[0302] In some examples, an anode connection block 131b-1 may be provided on a side of the anode 131b near the anode 131c. At least a portion of the anode connection block 131b-1 may be provided in the second first pixel circuit. A first end of the anode connection block 131b-1 is connected to the anode 131b, and a second end extends in a direction away from the anode 131b along the first direction X. The anode connection block 131b-1 may be electrically connected to the second anode connection electrode 63b through a thirty-sixth via hole V36. The anode connection block 131b-1 and the anode 131b may be an integral structure connected to each other.

[0303] In some examples, an anode connection block 131c-1 may be provided on a side of the anode 131c near the anode 131b. The anode connection block 131c-1 may be provided in the third first pixel circuit. A first end of the anode connection block 131c-1 is connected to the anode 131c, and a second end extends away from the anode 131c along the second direction Y. The anode connection block 131c-1 may be electrically connected to the second anode connection electrode 63c through the thirty-seventh via hole V37. The anode connection block 131c-1 and the anode 131c may be an integral structure connected to each other.

[0304] (2-10) A pixel definition layer, an organic light-emitting layer, a cathode layer, and an encapsulation layer are sequentially formed. The preparation process of the pixel definition layer, the organic light-emitting layer, the cathode layer, and the encapsulation layer in this example can be referred to the description of the previous embodiment, so it will not be repeated here.

[0305] The first signal lines and the second signal lines of the display substrate of this embodiment are both made of metal, which can reduce the material cost and mask cost of the transparent conductive layer, reduce the horizontal and vertical display defects caused by the high resistance of the first and second signal lines, and simplify the process, avoiding excessive hole opening. Moreover, in this example, the multiple first signal lines (for example, including the first scan connection line, the second scan connection line, the light control connection line, and the first initial connection line) are straight lines extending along the first direction X, and the multiple second signal lines (for example, including the first power connection line and the data connection line) are straight lines extending along the second direction Y. This can save space, help increase the light transmittance of the light-transmitting area, and reduce the diffraction effect of light.

[0306] The display substrate of this embodiment can reduce the number of isolated islands and slits by concentrating multiple first pixel circuits and multiple first light-emitting elements in the display island area, effectively reduce the light diffraction effect, and facilitate smoothing the edges of the display island area.

[0307] Figure 26 is another schematic partial top view of region S2 in Figure 17A. Figure 26 illustrates four display islands A11 arranged in a 2×2 array. Figure 27 is a schematic diagram of the display substrate in Figure 26 after the second conductive layer is formed. Figure 28A is a schematic diagram of the display substrate in Figure 26 after the third conductive layer is formed. Figure 28B is a schematic diagram of the third conductive layer in Figure 28A. Figure 29 is a schematic diagram of the display substrate in Figure 26 after the fifth insulating layer is formed. Figure 30A is a schematic diagram of the display substrate in Figure 26 after the fourth conductive layer is formed. Figure 30B is a schematic diagram of the fourth conductive layer in Figure 30A.

[0308] In some examples, in a direction perpendicular to the display substrate, the circuit structure layer of the first display area may include: a semiconductor layer, a first conductive layer, a second conductive layer, a third conductive layer, and a fourth conductive layer sequentially arranged on the substrate. A first insulating layer may be provided between the semiconductor layer and the first conductive layer, a second insulating layer may be provided between the first conductive layer and the second conductive layer, a third insulating layer may be provided between the second conductive layer and the third conductive layer, a fourth insulating layer and a fifth insulating layer may be provided between the third conductive layer and the fourth conductive layer, and a sixth insulating layer may be provided on the side of the fourth conductive layer away from the substrate. The patterns of the semiconductor layer, the first conductive layer, the second conductive layer, and the third insulating layer in this example can be described with reference to the embodiment shown in FIG. 18 , and therefore will not be repeated here.

[0309] In some examples, as shown in Figures 28A and 28B, the third conductive layer of a single display island region in the first display area may include at least a first connection electrode 41, a second connection electrode 42, a third connection electrode 43, a fourth connection electrode 44, a fifth connection electrode 45, a sixth connection electrode 46, a seventh connection electrode 47, and a data line (e.g., data line 51a). The number of the first connection electrode 41, the second connection electrode 42, the fourth connection electrode 44, the fifth connection electrode 45, and the sixth connection electrode 46 is three, and the number of the third connection electrode 43 is two. The third conductive layer of a single second wiring region between adjacent display island regions in the second direction Y may include at least one data connection line (e.g., data connection line 75a). The description of the first connection electrode 41, the second connection electrode 42, the third connection electrode 43, the fifth connection electrode 45, and the sixth connection electrode 46 in this example can be referred to the description of the previous embodiment, and thus will not be repeated here.

[0310] In some examples, as shown in Figures 27, 28A, and 28B, the three fourth connection electrodes 44 of a single display island area can all be connected to the seventh connection electrode 47. The shape of the seventh connection electrode 47 can be roughly E-shaped. The seventh connection electrode 47 can be located on the same side of the three fourth connection electrodes 44 in the second direction Y. The first end of the seventh connection electrode 47 can be electrically connected to the first fourth connection electrode 44 to achieve electrical connection with the fifth transistor and storage capacitor of the first first pixel circuit, the second end of the seventh connection electrode 47 can be electrically connected to the second fourth connection electrode 44 to achieve electrical connection with the fifth transistor and storage capacitor of the second first pixel circuit, and the third end of the seventh connection electrode 47 can be electrically connected to the third fourth connection electrode 44 to achieve electrical connection with the fifth transistor and storage capacitor of the third first pixel circuit. The seventh connection electrode 47 and the three fourth connection electrodes 44 can be an integrated structure connected to each other.

[0311] In some examples, as shown in Figures 28A and 28B, the shape of the data line 51a can be a broken line segment with a main portion extending along the second direction Y. The data line 51a can be electrically connected to the first area of ​​the fourth active layer of the fourth transistor of the first first pixel circuit through a via hole opened in the third insulating layer, the second insulating layer, and the first insulating layer. The shape of the data connection line 75a can be roughly a straight line extending along the second direction Y. The data lines 51a in adjacent display island areas in the second direction Y can be connected by the data connection line 75a. For example, the first end of the data connection line 75a in the second routing area between the display island area of ​​the mth column and the display island area of ​​the m-1th column can be connected to the data line 51a in the display island area of ​​the mth column and the kth row, and the second end can be connected to the data line 51a in the display island area of ​​the mth column and the k+1th row. The data line 51a and the data connection line 75a can be an integrated structure connected to each other.

[0312] In some examples, as shown in FIG29 , the plurality of vias in the fifth insulating layer of a single display island region may include at least a 31st via hole V31, a 32nd via hole V32, a 33rd via hole V33, a 34th via hole V34, and a 41st via hole V41. For the description of the 31st via hole V31, the 32nd via hole V32, the 33rd via hole V33, and the 34th via hole V34, reference can be made to the description of the previous embodiment and are not repeated here.

[0313] In some examples, as shown in Figures 29 and 28A, the orthographic projection of the forty-first via hole V41 on the substrate can be located within the range of the orthographic projection of the data line 51a on the substrate. The fifth insulating layer and the fourth insulating layer within the forty-first via hole V41 can be removed to expose a portion of the surface of the data line 51a. The forty-first via hole V31 can be configured to connect a subsequently formed third conductive block to the data line 51a through this via hole.

[0314] In some examples, as shown in Figures 30A and 30B, the fourth conductive layer of a single display island area may include at least: two data lines (for example, including data lines 51b and 51c), three second power connection lines (for example, including second power connection lines 61a, 61b and 61c), three second anode connection electrodes (for example, including second anode connection electrodes 63a, 63b and 63c), and a third conductive block 64.

[0315] In some examples, as shown in Figures 26 to 30B, the shape of the third conductive block 64 can be roughly rectangular, such as a rounded rectangle. The third conductive block 64 can be electrically connected to the data line 51a through the forty-first via V41. The third conductive block 64 is connected in parallel with the data line 51a, which helps reduce the resistance of the data line 51a. Moreover, the provision of the third conductive block helps to uniformly form the film pattern.

[0316] In some examples, as shown in Figures 26 to 30B, the second power connection lines 61a, 61b, and 61c can all be shaped like a broken line with a main portion extending along the second direction Y. The second power connection line 61a can be electrically connected to the fourth connection electrode 44 through the thirty-second via hole V32 located in the first first pixel circuit, and can also be electrically connected to the sixth connection electrode 46 through the thirty-fourth via hole V34 located in the first first pixel circuit. The second power connection line 61a can be electrically connected to the fourth connection electrode and the sixth connection electrode in the second first pixel circuit. The second power connection line 61c can be electrically connected to the fourth connection electrode and the sixth connection electrode in the third first pixel circuit.

[0317] In some examples, as shown in Figures 30A and 30B , the second power connection line 61a may be provided with a fourth power extension portion 61a-1 on a side proximal to the data line 51a. The fourth power extension portion 61a-1 may extend along the first direction X toward the data line 51a. The fourth power extension portion 61a-1 and the second power connection line 61a may be connected as a single unit. The second power connection line 61c may be provided with a third power extension portion 61c-1 on a side distal to the data line 51c. The third power extension portion 61c-1 may extend along the first direction X toward a side distal to the data line 51c. The third power extension portion 61c-1 and the second power connection line 61c may be connected as a single unit.

[0318] In some examples, as shown in Figures 30A and 30B , the fourth conductive layer of a single second wiring area between adjacent display island areas along the second direction Y may include at least one first power connection line (e.g., first power connection line 76) and two data connection lines (e.g., data connection lines 75b and 75c). The first power connection line 76 and the data connection lines 75b and 75c may be substantially straight lines extending along the second direction Y.

[0319] In some examples, as shown in Figures 26, 30A, and 30B, the second routing area between the mth column display island area and the m+1th column display island area may include: a data connection line 75c electrically connected to the third column first pixel circuit in the mth column display island area, a data connection line 75b electrically connected to the second column first pixel circuit in the m+1th column display island area, a data connection line 75a electrically connected to the first column first pixel circuit in the m+1th column display island area, and a first power connection line 76. The data connection line 75c, the first power connection line 76, the data connection line 75a, and the data connection line 75b may be arranged sequentially along the first direction X. The first power connection line 76 may be connected to the third power extension portion 61c-1 of the second power connection line 61c in the mth column display island area, and may also be connected to the fourth power extension portion 61a-1 of the second power connection line 61a in the m+1th column display island area. The first power connection line 76 and the adjacent second power connection lines 61 c and 61 a may be an integral structure connected to each other.

[0320] In some examples, within a single display island, the fourth connection electrode 44 and the seventh connection electrode 47 are used to achieve horizontal transmission of the first voltage signal. The first power connection line 76, the adjacent second power connection line 61a, and the second power connection line 61c are used to achieve horizontal transmission of the first voltage signal between adjacent display islands. The first power connection line 76 is used to achieve vertical transmission of the first voltage signal between adjacent display islands. The first power connection line, the second power connection line, the fourth connection electrode, and the seventh connection electrode in this example can form a mesh-like structure for transmitting the first voltage signal, which not only reduces the voltage drop of the first voltage signal, but also effectively improves the uniformity of the first voltage signal in the display substrate, effectively improves the display uniformity, and improves the display quality and display quality. Moreover, the second wiring area of ​​this example can be provided with only three data connection lines and one first power connection line, which can reduce the number of connection lines, thereby reducing the space occupied by the second wiring area, which is conducive to improving the light transmittance of the first light-transmitting area.

[0321] The remaining structures of the display substrate of this example can be referred to the description of the aforementioned embodiment, and thus will not be described again here.

[0322] This embodiment also provides a display substrate, comprising: a first display area. The first display area comprises: a plurality of display island areas arranged in an array, and a light-transmitting area located between adjacent display island areas. The light-transmitting area comprises a first light-transmitting area, and the first light-transmitting area is located between adjacent display island areas along the second direction. At least one display island area among the plurality of display island areas and the first light-transmitting area are alternately arranged along the second direction. The display island area comprises: a plurality of first pixel circuits and a plurality of first light-emitting elements arranged on a substrate. At least one first pixel circuit among the plurality of first pixel circuits is electrically connected to at least one first light-emitting element among the plurality of first light-emitting elements. At least one first pixel circuit is configured to drive the at least one first light-emitting element to emit light. The first pixel circuits in adjacent display island areas are connected in the first direction by a plurality of first signal lines, and the first pixel circuits in adjacent display island areas are connected in the second direction by a plurality of second signal lines; the first direction intersects with the second direction.

[0323] In some exemplary embodiments, the first light-transmitting region is located between a plurality of second signal lines along the first direction. For example, the plurality of second signal lines may include: a first power connection line and a data connection line.

[0324] In some exemplary embodiments, the light-transmitting region may further include a second light-transmitting region. The second light-transmitting region is located between adjacent display island regions along the first direction. The area of ​​the first light-transmitting region may be larger than that of the second light-transmitting region.

[0325] In some exemplary embodiments, the second light-transmitting region is located between the plurality of first signal lines. For example, the plurality of first signal lines may include: a first scan connection line, a second scan connection line, a light-emitting control connection line, and a first initial connection line.

[0326] In some exemplary embodiments, at least one display island region among the plurality of display island regions includes: three first pixel circuits and three first light-emitting elements. The three first pixel circuits are electrically connected to the three first light-emitting elements in a one-to-one correspondence, and the three first pixel circuits are arranged sequentially along the first direction. The three first light-emitting elements include: a first light-emitting element that emits a first color light, a first light-emitting element that emits a second color light, and a first light-emitting element that emits a third color light. The light-emitting region of the first light-emitting element that emits the first color light at least partially overlaps with the orthographic projection of the substrate on the substrate of the first pixel circuit connected to the first light-emitting element that emits the first color light. The light-emitting region of the first light-emitting element that emits the second color light at least partially overlaps with the orthographic projection of the substrate on the substrate of the first pixel circuit connected to the first light-emitting element that emits the second color light. The light-emitting region of the first light-emitting element that emits the third color light at least partially overlaps with the orthographic projection of the substrate on the substrate of the first pixel circuit connected to the first light-emitting element that emits the third color light.

[0327] The structure of the display substrate of this embodiment can be referred to the description of the above embodiments, and thus will not be described again here.

[0328] Figure 31 is a schematic diagram of a display device according to at least one embodiment of the present disclosure. As shown in Figure 31 , this embodiment provides a display device comprising: a display substrate 91; and a sensor 92 located on the light-emitting side of the light-emitting structure layer, away from the display substrate 91. Sensor 92 may be located on the non-display surface of the display substrate 91. The orthographic projection of sensor 92 on the display substrate 91 may overlap with the first display area A1.

[0329] In some exemplary embodiments, the display substrate 91 may be a flexible OLED display substrate, a QLED display substrate, a Micro-LED display substrate, or a Mini-LED display substrate. The display device may be a product having an image (including a static image or a dynamic image, wherein the dynamic image may be a video) display function. For example, the display device may be: a display, a television, a billboard, a digital photo frame, a laser printer with a display function, a telephone, a mobile phone, a painting screen, a personal digital assistant (PDA), a digital camera, a portable camcorder, a viewfinder, a navigator, a vehicle, a large-area wall, an information query device (such as business query equipment for e-government, banks, hospitals, power departments, etc.), a monitor, and the like. For another example, the display device may also be a microdisplay, a VR device or an AR device containing a microdisplay, and the like.

[0330] The drawings in this disclosure only relate to the structures involved in this disclosure, and other structures may refer to the general design. In the absence of conflict, the embodiments of this disclosure, that is, the features in the embodiments, can be combined with each other to obtain new embodiments. It should be understood by those skilled in the art that the technical solutions of this disclosure can be modified or replaced by equivalents without departing from the spirit and scope of the technical solutions of this disclosure, and should be included in the scope of the claims of this disclosure.

Claims

1. A display substrate, comprising: A first display area, comprising: a plurality of display island areas arranged in an array, and a light-transmitting area located between adjacent display island areas; The display island region includes: a plurality of first pixel circuits and a plurality of first light-emitting elements provided on a substrate, at least one first pixel circuit among the plurality of first pixel circuits is electrically connected to at least one first light-emitting element among the plurality of first light-emitting elements, and the at least one first pixel circuit is configured to drive the at least one first light-emitting element to emit light; The first pixel circuits in adjacent display island regions are connected in a first direction via a plurality of first signal lines, and the first pixel circuits in adjacent display island regions are connected in a second direction via a plurality of second signal lines; the first direction intersects the second direction; The material of the plurality of second signal lines includes a transparent conductive material, or the materials of the plurality of first signal lines and the plurality of second signal lines both include a metal material.

2. The display substrate according to claim 1, wherein The film layer where the plurality of second signal lines are located is located on a side of the film layer where the plurality of first signal lines are located away from the substrate.

3. The display substrate according to claim 1, wherein The material of the plurality of first signal lines includes a metal material, the material of the plurality of second signal lines includes a transparent conductive material, and the plurality of second signal lines are in a same-layer structure.

4. The display substrate according to claim 3, wherein: At least part of the plurality of second signal traces is located in the light-transmitting area.

5. The display substrate according to claim 3 or 4, wherein: The light-transmitting area includes: a first light-transmitting area located between display island areas adjacent to each other along the second direction, and a second light-transmitting area located between display island areas adjacent to each other along the first direction; the area of ​​the first light-transmitting area is larger than that of the second light-transmitting area. The display substrate according to claim 1 , wherein: Materials of the plurality of first signal lines and the plurality of second signal lines both include metal materials; The plurality of second signal lines are in a same-layer structure, or at least one second signal line among the plurality of second signal lines and the remaining second signal lines are in a different-layer structure.

7. The display substrate according to claim 6, wherein: The light-transmitting area at least includes: a first light-transmitting area located between display island areas adjacent to each other along the second direction; the display substrate further includes: a first routing area located between adjacent first light-transmitting areas, the first routing area being connected to the display island areas; the plurality of second signal routing lines are located in the first routing area.

8. The display substrate according to claim 6 or 7, wherein: The plurality of second signal lines include: a plurality of data connection lines for transmitting data signals to the plurality of first pixel circuits in the display island area respectively, and at least one first power connection line for transmitting a first voltage signal to the plurality of first pixel circuits in the display island area.

9. The display substrate according to claim 8, wherein: The plurality of first pixel circuits in the display island area are electrically connected to the same first power connection line.

10. The display substrate according to claim 8, wherein The plurality of first pixel circuits in the display island area are electrically connected to the plurality of first power connection lines respectively, and the plurality of data connection lines and the plurality of first power connection lines are arranged at intervals.

11. The display substrate according to any one of claims 8 to 10, wherein: The plurality of first pixel circuits in the display island area are sequentially arranged along the first direction, and the data connection line connected to the first first pixel circuit among the plurality of first pixel circuits and the data connection lines connected to the remaining first pixel circuits are in a different-layer structure.

12. The display substrate according to any one of claims 1 to 11, wherein At least one first signal line among the plurality of first signal lines is in a different layer structure than the other first signal lines.

13. The display substrate according to claim 12, wherein: The plurality of first signal lines include: a first initial connection line for transmitting a first initial signal, a first scanning connection line for transmitting a first scanning signal, a second scanning connection line for transmitting a second scanning signal, and a light-emitting control connection line for transmitting a light-emitting control signal; The first scanning connection line, the second scanning connection line and the light emitting control connection line are in the same layer structure.

14. The display substrate according to any one of claims 1 to 13, wherein: At least one display island area among the multiple display island areas includes: three first pixel circuits and three first light-emitting elements, the three first pixel circuits and the three first light-emitting elements are electrically connected in a one-to-one correspondence, and the three first pixel circuits are arranged in sequence along the first direction.

15. The display substrate according to claim 14, wherein: The three first light-emitting elements include: a first light-emitting element emitting a first color light, a first light-emitting element emitting a second color light, and a first light-emitting element emitting a third color light; The first light-emitting element emitting the first color light and the first light-emitting element emitting the second color light are arranged in the same column, the first light-emitting element emitting the third color light and the first light-emitting element emitting the first color light are arranged in different columns, and the first light-emitting element emitting the first color light, the first light-emitting element emitting the second color light and the first light-emitting element emitting the third color light are arranged in different rows.

16. The display substrate according to claim 15, wherein: The area of ​​the light-emitting region of the first light-emitting element that emits the second color light is larger than the area of ​​the light-emitting region of the first light-emitting element that emits the first color light, and the area of ​​the light-emitting region of the first light-emitting element that emits the third color light is larger than the area of ​​the light-emitting region of the first light-emitting element that emits the first color light.

17. The display substrate according to claim 15 or 16, wherein: The orthographic projection of the light emitting region of the first light emitting element emitting the first color light on the substrate at least partially overlaps with the orthographic projection of the first pixel circuit connected to the first light emitting element emitting the first color light on the substrate; The orthographic projection of the light emitting region of the first light emitting element emitting the second color light on the substrate does not overlap with the orthographic projection of the first pixel circuit connected to the first light emitting element emitting the second color light on the substrate; The orthographic projection of the light emitting region of the first light emitting element emitting the third color light on the substrate at least partially overlaps with the orthographic projection of the first pixel circuit connected to the first light emitting element emitting the third color light on the substrate.

18. The display substrate according to claim 17, wherein: The overlapping area between the light-emitting area of ​​the first light-emitting element emitting the third color light and the first pixel circuit connected to the first light-emitting element emitting the third color light is greater than the overlapping area between the light-emitting area of ​​the first light-emitting element emitting the first color light and the first pixel circuit connected to the first light-emitting element emitting the first color light.

19. The display substrate according to any one of claims 1 to 18, further comprising: a second display area located on at least one side of the first display area; The second display area includes: a plurality of second pixel circuits and a plurality of second light-emitting elements arranged on the substrate, at least one second pixel circuit among the plurality of second pixel circuits is electrically connected to at least one second light-emitting element among the plurality of second light-emitting elements, and the at least one second pixel circuit is configured to drive the at least one second light-emitting element to emit light.

20. A display device comprising the display substrate according to any one of claims 1 to 19, and a sensor located on a non-display surface side of the display substrate, wherein an orthographic projection of the sensor on the display substrate overlaps with a first display area of ​​the display substrate.

21. A display substrate, comprising: a first display area, the first display area comprising: a plurality of display island areas arranged in an array, and light-transmitting areas located between adjacent display island areas, the light-transmitting area comprising a first light-transmitting area, the first light-transmitting area being located between adjacent display island areas along a second direction, and at least one display island area of ​​the plurality of display island areas and the first light-transmitting area being alternately arranged along the second direction; The display island region includes: a plurality of first pixel circuits and a plurality of first light-emitting elements provided on a substrate, at least one first pixel circuit among the plurality of first pixel circuits is electrically connected to at least one first light-emitting element among the plurality of first light-emitting elements, and the at least one first pixel circuit is configured to drive the at least one first light-emitting element to emit light; The first pixel circuits in adjacent display island areas are connected in a first direction through multiple first signal lines, and the first pixel circuits in adjacent display island areas are connected in the second direction through multiple second signal lines; the first direction intersects the second direction.

22. The display substrate according to claim 21, wherein The first light-transmissive region is located between the plurality of second signal traces along the first direction.

23. The display substrate according to claim 21, wherein The light-transmitting area further includes a second light-transmitting area, the second light-transmitting area is located between adjacent display island areas along the first direction, and the area of ​​the first light-transmitting area is larger than that of the second light-transmitting area.

24. The display substrate according to claim 23, wherein: The second light-transmitting area is located between the plurality of first signal traces.

25. The display substrate according to any one of claims 21 to 24, wherein: At least one of the plurality of display island regions comprises: three first pixel circuits and three first light-emitting elements, the three first pixel circuits being electrically connected to the three first light-emitting elements in a one-to-one correspondence, and the three first pixel circuits being sequentially arranged along the first direction; the three first light-emitting elements comprising: a first light-emitting element emitting a first color light, a first light-emitting element emitting a second color light, and a first light-emitting element emitting a third color light; The orthographic projection of the light emitting region of the first light emitting element emitting the first color light on the substrate at least partially overlaps with the orthographic projection of the first pixel circuit connected to the first light emitting element emitting the first color light on the substrate; The orthographic projection of the light emitting region of the first light emitting element emitting the second color light on the substrate does not overlap with the orthographic projection of the first pixel circuit connected to the first light emitting element emitting the second color light on the substrate; The orthographic projection of the light emitting region of the first light emitting element emitting the third color light on the substrate at least partially overlaps with the orthographic projection of the first pixel circuit connected to the first light emitting element emitting the third color light on the substrate.

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